P320DB70VI [AMD]
32 Megabit (2 M x 16-Bit/1 M x 32-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory; 32兆位（2M ×16位/ 1的M× 32位） CMOS 3.0伏只高性能页模式闪存
| 型号： | P320DB70VI |
| 厂家： | 
AMD |
| 描述： | 32 Megabit (2 M x 16-Bit/1 M x 32-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory |
| 文件： | 总49页 (文件大小：946K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Am29PL320D
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not recommended for designs. For new and current designs,
S29GL032M supersedes Am29PL320D and is the factory-recommended migration path. Please refer
to the S29GL032M datasheet for specifications and ordering information. Availability of this docu-
ment is retained for reference and historical purposes only.
June 2005
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that
originally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appro-
priate, and changes will be noted in a revision summary.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 24075 Revision C Amendment +3 Issue Date June 13, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29PL320D
32 Megabit (2 M x 16-Bit/1 M x 32-Bit)
CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
This product has been retired and is not recommended for designs. For new and current designs, S29GL032M supersedes Am29PL320D and is the factory-recommended migration path.
Please refer to the S29GL032M datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
— Standby mode current: 2 µA
■ 32 Mbit Page Mode device
SOFTWARE FEATURES
— Word (16-bit) or double word (32-bit) mode
selectable via WORD# input
■ Software command-set compatible with JEDEC
standard
— Page size of 8 words/4 double words: Fast page
read access from random locations within the
page
— Backward compatible with Am29F and Am29LV
families
■ CFI (Common Flash Interface) compliant
■ Single power supply operation
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■ Flexible sector architecture
■ Erase Suspend/Erase Resume
— Sector sizes (x16 configuration): One 16 Kword,
two 8 Kword, one 96 Kword and fifteen 128
Kword sectors
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
— Supports full chip erase
HARDWARE FEATURES
■ SecSi™ (Secured Silicon) Sector region
■ Sector Protection
— Current version of device has 512 words (256
double words); future versions will have 128
words (64 double words)
— A hardware method of locking a sector to prevent
any program or erase operations within that
sector
■ Top or bottom boot block configuration
■ Manufactured on 0.23 µm process technology
■ 20-year data retention at 125°C
— Sectors can be locked via programming
equipment
— Temporary Sector Unprotect command
sequence allows code changes in previously
locked sectors
■ Minimum 1 million erase cycles guarantee
per sector
■ ACC (Acceleration) input provides faster
PERFORMANCE CHARACTERISTICS
programming times
■ High performance read access times
— Page access times as fast as 20 ns
— Random access times as fast as 60 ns
■ WP# (Write Protect) input
— At V , protects the first or last 32 Kword sector,
IL
regardless of sector protect/unprotect status
■ Power consumption (typical values)
— At V , allows removal of sector protection
IH
— Initial page read current: 4 mA (1 MHz),
40 mA (10 MHz)
— An internal pull up to V is provided
CC
■ Package Options
— Intra-page read current: 15 mA (10 MHz),
50 mA (33 MHz)
— 84-ball FBGA
— Program/erase current: 25 mA
Publication# 24075 Rev: C Amendment/+3
Issue Date: June 13, 2005
Refer to AMD’s Website (www.amd.com/flash) for the latest information.
GENERAL DESCRIPTION
The Am29PL320D is a 32 Mbit, 3.0 Volt-only page
mode Flash memory device organized as 2,097,152
words or 1,048,576 double words. The device is of-
fered in an 84-ball FBGA package. The word-wide
data (x16) appears on DQ15–DQ0; the double word-
wide (x32) data appears on DQ31–DQ0. The device is
available in both top and bottom boot versions. This
device can be programmed in-system or with in stan-
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7
(Data# Polling) and DQ6 (toggle) status bits. After a
program or erase cycle has been completed, the device
is ready to read array data or accept another command.
dard EPROM programmers. A 12.0 V V or 5.0 V
PP
CC
are not required for write or erase operations.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
The device offers fast page access times of 20, 25,
and 35 ns, with corresponding random access times of
60, 70, 90 ns, respectively, allowing high speed micro-
processors to operate without wait states. To eliminate
bus contention the device has separate chip enable
(CE#), write enable (WE#), and output enable (OE#)
controls.
Hardware data protection measures include a low
V
detector that automatically inhibits write opera-
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via
programming equipment.
Page Mode Features
The device is AC timing, input, output, and package
compatible with 16 Mbit x 16 page mode Mask
ROM. The page size is 8 words or 4 double words.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
After initial page access is accomplished, the page
mode operation provides fast read access speed of
random locations within that page.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
Standard Flash Memory Features
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The SecSi™ Sector (Secured Silicon) is an extra sec-
tor capable of being permanently locked by AMD or
customers. The SecSi Indicator Bit (DQ7) is perma-
nently set to a 1 if the part is factory locked, and set
to a 0 if customer lockable. This way, customer lock-
able parts can never be used to replace a factory
locked part. Current version of device has 512
words (256 double words); future versions will
have only 128 words (64 double words). This
should be considered during system design. Fac-
tory locked parts can store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may be programmed
after being shipped from AMD.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that
automatically times the program pulse widths and
verifies proper cell margin. The Unlock Bypass mode
facilitates faster programming times by requiring only
two write cycles to program data instead of four.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
2
Am29PL320D
June 13, 2005
TABLE OF CONTENTS
Figure 3. Erase Operation.............................................................. 23
Temporary Sector Unprotect Enable/Disable
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Standard Products .................................................................... 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29PL320D Device Bus Operations ................................9
Word/Double Word Configuration ............................................. 9
Requirements for Reading Array Data .....................................9
Read Mode ............................................................................... 9
Random Read (Non-Page Mode Read) ............................................9
Page Mode Read ....................................................................10
Table 2. Double Word Mode ...........................................................10
Table 3. Word Mode ........................................................................10
Writing Commands/Command Sequences ............................11
Accelerated Program Operation ......................................................11
Program and Erase Operation Status .................................... 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ...........................................................11
Output Disable Mode .............................................................. 11
Table 4. Sector Address Table, Top Boot (Am29PL320DT) ...........12
Table 5. SecSi™ Sector Addresses for Top Boot Devices .............12
Table 6. Sector Address Table, Bottom Boot (Am29PL320DB) ......13
Table 7. SecSi™ Sector Addresses for
Bottom Boot Devices .......................................................................13
Autoselect Mode .....................................................................14
Table 8. Am29PL320D Autoselect Codes (High Voltage Method) ..14
Sector Protection/Unprotection ...............................................14
Common Flash Memory Interface (CFI) . . . . . . . 15
Table 9. CFI Query Identification String ..........................................15
Table 10. System Interface String ...................................................16
Table 11. Device Geometry Definition ............................................16
Table 12. Primary Vendor-Specific Extended Query ......................17
SecSi™ (Secured Silicon) Sector Flash Memory Region .......18
Factory Locked: SecSi Sector Programmed and
Command Sequence .............................................................. 24
Figure 4. Temporary Sector Unprotect Algorithm .......................... 24
Command Definitions ............................................................. 25
Table 13. Command Definitions (Double Word Mode) .................. 25
Table 14. Command Definitions (Word Mode) ............................... 26
Write Operation Status. . . . . . . . . . . . . . . . . . . . . 27
DQ7: Data# Polling .................................................................27
Figure 5. Data# Polling Algorithm .................................................. 27
DQ6: Toggle Bit ......................................................................28
DQ2: Toggle Bit ......................................................................28
Reading Toggle Bits DQ6/DQ2 ...............................................28
DQ5: Exceeded Timing Limits ................................................ 28
Figure 6. Toggle Bit Algorithm........................................................ 29
DQ3: Sector Erase Timer ....................................................... 29
Table 15. Write Operation Status ................................................... 30
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 31
Figure 7. Maximum Negative Overshoot Waveform ...................... 31
Figure 8. Maximum Positive Overshoot Waveform........................ 31
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 31
Commercial (C) Devices ......................................................... 31
Industrial (I) Devices ............................................................... 31
V
Supply Voltages .............................................................. 31
CC
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32
CMOS Compatible .................................................................. 32
Zero Power Flash ................................................................... 33
Figure 9. I Current vs. Time (Showing Active and Automatic Sleep
CC1
Currents) ........................................................................................ 33
Figure 10. Typical I vs. Frequency ........................................... 33
CC1
Figure 11. Test Setup..................................................................... 34
Table 16. Test Specifications ......................................................... 34
Key to Switching Waveforms. . . . . . . . . . . . . . . . 34
Figure 12. Input Waveforms and Measurement Levels ................. 34
Read Operations .................................................................... 35
Figure 13. Conventional Read Operations Timings ....................... 36
Figure 14. Page Read Timings ...................................................... 36
Double Word/Word Configuration (WORD#) ........................ 37
Figure 15. WORD# Timings for Read Operations.......................... 37
Figure 16. WORD# Timings for Write Operations.......................... 37
Program/Erase Operations .................................................... 38
Figure 17. Program Operation Timings.......................................... 39
Figure 18. AC Waveforms for Chip/Sector Erase Operations........ 40
Figure 19. Data# Polling Timings (During Embedded Algorithms). 40
Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 41
Figure 21. DQ2 vs. DQ6 for Erase and
Protected At the Factory .................................................................18
Customer Lockable: SecSi Sector NOT Programmed or Locked
At the Factory .................................................................................18
Figure 1. SecSi Sector Protect Verify.............................................. 19
Write Protect (WP#) ................................................................19
Hardware Data Protection ......................................................19
Low V Write Inhibit ......................................................................19
CC
Write Pulse “Glitch” Protection ........................................................19
Logical Inhibit ..................................................................................19
Power-Up Write Inhibit ....................................................................19
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 19
Reading Array Data ................................................................19
Reset Command .....................................................................20
Autoselect Command Sequence ............................................20
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 20
Word/Double Word Program Command Sequence ............... 20
Unlock Bypass Command Sequence ..............................................21
Figure 2. Program Operation .......................................................... 21
Chip Erase Command Sequence ........................................... 22
Sector Erase Command Sequence ........................................22
Erase Suspend/Erase Resume Commands ........................... 22
Erase Suspend Operations ............................................................ 41
Alternate CE# Controlled
Erase/Program Operations ..................................................... 42
Figure 22. Alternate CE# Controlled Write Operation Timings ...... 43
Erase and Programming Performance . . . . . . . 44
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
BGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 46
FBF084—84-Ball Fine Pitch Ball Grid Array (FBGA) 11 x 12 mm ..... 46
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 47
Revision A (March 7, 2001) .................................................... 47
June 13, 2005
Am29PL320D
3
Revision B (June 12, 2001) ....................................................47
Revision B+1 (August 30, 2001) .............................................47
Revision C (October 22, 2002) ...............................................47
Revision C+1 (July 21, 2003) .................................................47
Revision C+2 (October 2, 2003) ............................................. 47
4
Am29PL320D
June 13, 2005
PRODUCT SELECTOR GUIDE
Family Part Number
Am29PL320D
Regulated Voltage Range: V =3.0–3.6 V
60R
70R
70
CC
Speed Option
Max access time, ns (t
Full Voltage Range: V = 2.7–3.6 V
90
90
90
30
30
CC
)
60
60
20
20
70
ACC
Max CE# access time, ns (t
)
70
CE
Max page access time, ns (t
)
25
PACC
Max OE# access time, ns (t
)
25
OE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ31–DQ0
V
CC
V
SS
Erase Voltage
Generator
Input/Output
Buffers
State
WE#
WORD#
ACC
Control
Command
Register
PGM Voltage
Generator
WP#
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
X-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
A19–A0
A1, A0,
A-1
June 13, 2005
Am29PL320D
5
CONNECTION DIAGRAMS
84-Ball FBGA
Top View, Balls Facing Down
B9
C9
D9
E9
F9
G9
H9
J9
VCC
DQ30
VCC
DQ13
DQ12
DQ27
DQ26
DQ9
A8
B8
C8
D8
E8
F8
G8
H8
J8
K8
DQ24
A19
CE#
VSS
DQ15
DQ29
DQ28
DQ11
VSS
VCC
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
NC
WORD#
OE#
DQ14
VSS
DQ10
DQ25
A18
A17
A16
A6
B6
C6
D6
E6
F6
G6
H6
J6
K6
A15
A13
WE#
NC
NC
DQ31/A-1
NC
NC
DQ8
A14
A5
B5
C5
D5
E5
F5
G5
NC
H5
J5
K5
NC
ACC
WP#
NC
NC
NC
NC
NC
NC
A4
A1
B4
A2
C4
A3
D4
A0
E4
F4
G4
H4
J4
K4
DQ2
NC
A12
A11
A9
A10
A3
A4
B3
A5
C3
D3
E3
F3
G3
H3
A8
J3
K3
A7
DQ0
DQ16
DQ18
DQ5
DQ21
A6
B2
C2
D2
E2
F2
G2
H2
J2
K2
VCC
DQ1
VSS
DQ19
DQ4
DQ6
DQ7
DQ23
VSS
C1
D1
E1
F1
G1
H1
J1
VCC
DQ17
VCC
DQ3
DQ20
VSS
DQ22
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
Special Handling Instructions for FBGA
Package
Special handling is required for Flash Memory products
in FBGA packages.
6
Am29PL320D
June 13, 2005
INPUT CONFIGURATION
LOGIC SYMBOL
A19–A0
= 20 address inputs
20
DQ30–DQ0 = 31 data inputs/outputs
A19–A0
16 or 32
DQ31/A-1
WORD#
=
=
In double word mode, functions as
DQ31. In word mode, functions
as A-1 (LSB address input)
DQ31–DQ0
(A-1)
CE#
OE#
Word enable input
When low, enables word mode
When high, enables double word mode
WE#
WP#
ACC
CE#
OE#
WE#
= Hardware Write Protect input
= Acceleration input
WORD#
WP#
=
Chip Enable input
Output Enable input
Write Enable input
ACC
=
=
=
V
3.0 volt-only single power supply
CC
(see Product Selector Guide for speed
options and voltage supply tolerances)
V
=
=
Device ground
SS
NC
input not connected internally
June 13, 2005
Am29PL320D
7
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29PL320D
B
60R
WP
I
TEMPERATURE RANGE
Industrial (–40°C to +85°C)
I
=
PACKAGE TYPE
WP 84-Ball Fine Pitch Ball Grid Array (FBGA) 0.8 mm pitch (FBF084)
=
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
B
=
=
Top Boot Sector
Bottom Boot Sector
DEVICE NUMBER/DESCRIPTION
Am29PL320D
32 Megabit (2 M x 16-Bit/1 M x 32-Bit)
CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
Valid Combinations
Package Marking
Voltage Range
AM29PL320DT60R,
AM29PL320DB60R
P320DT60RI,
P320DB60RI
V
V
= 3.0–3.6 V
= 2.7–3.6 V
CC
CC
AM29PL320DT70R,
AM29PL320DB70R
P320DT70RI,
P320DB70RI
WPI
AM29PL320DT70,
AM29PL320DB70
P320DT70VI,
P320DB70VI
AM29PL320DT90,
AM29PL320DB90
P320DT90VI,
P320DB90VI
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to
confirm availability of specific valid combinations and to check on newly released combinations.
8
Am29PL320D
June 13, 2005
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory
location. The register is composed of latches that store
the commands, along with the address and data infor-
mation needed to execute the command. The contents
of the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29PL320D Device Bus Operations
DQ31–DQ8
WORD#
= V
Addresses
(Note 1)
DQ7–
DQ0
WORD#
Operation
CE#
L
OE# WE# WP#
= V
IH
IL
Read
Write
L
H
L
X
X
A
D
D
DQ30–DQ16 = High-Z,
DQ31 = A-1
IN
OUT
OUT
L
H
A
D
D
IN
IN
IN
V
0.3 V
±
CC
Standby
X
H
X
H
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
Output Disable
L
X
High-Z
Legend:
L = Logic Low = V , H = Logic High = V , V = 12.0 ± ±0.5 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out
IL
IH
ID
IN
IN
OUT
Notes:
1. Addresses are A19–A0 in double word mode (WORD# = V ), A19–A-1 in word mode (WORD# = V ).
IH
IL
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
address inputs produce valid data on the device data
outputs. The device remains enabled for read access
until the command register contents are altered.
Word/Double Word Configuration
The WORD# input controls whether the device data
I/Os DQ31–DQ0 operate in the word or double word
configuration. If the WORD# input is set at V , the de-
vice is in double word configuration; DQ31–DQ0 are
active and controlled by CE# and OE#.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
IH
tions and to Figure 13 for the timing diagram. I
in
CC1
the DC Characteristics table represents the active cur-
rent specification for reading array data.
If the WORD# input is set at logic ‘0’, the device is in
word configuration, and only data I/Os DQ15–DQ0 are
active and controlled by CE# and OE#. The data I/Os
DQ30–DQ16 are tri-stated, and the DQ31 input is
used as an input for the LSB (A-1) address function.
Read Mode
Random Read (Non-Page Mode Read)
The device has two control functions which must be
satisfied in order to obtain data at the outputs. CE# is
the power control and should be used for device selec-
tion. OE# is the output control and should be used to
gate data to the output inputs if the device is selected.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# inputs to V . CE# is the power
IL
control and selects the device. OE# is the output control
and gates array data to the output inputs. WE# should
Address access time (t
) is equal to the delay from
ACC
remain at V . The WORD# input determines whether
IH
stable addresses to valid output data. The chip enable
the device outputs array data in words or bytes.
access time (t ) is the delay from the stable ad-
CE
dresses and stable CE# to valid data at the output
inputs. The output enable access time is the delay
from the falling edge of OE# to valid data at the output
inputs (assuming the addresses have been stable for
The internal state machine is set for reading array data
upon device power-up. This ensures that no spurious
alteration of the memory content occurs during the
power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device
at least t
–t time).
ACC OE
June 13, 2005
Am29PL320D
9
The following tables determine the specific word and
double word within the selected page:
Page Mode Read
The Am29PL320D is capable of fast page mode read
and is compatible with the page mode Mask ROM read
operation. This mode provides faster read access
speed for random locations within a page. The page
size of the Am29PL320D device is 8 words, or 4 dou-
ble words, with the appropriate page being selected by
the higher address bits A19–A2 and the LSB bits A1–
A0 (in the double word mode) and A1 to A-1 (in the
word mode) determining the specific word/double word
within that page. This is an asynchronous operation
with the microprocessor supplying the specific word or
double word location.
Table 2. Double Word Mode
Word
A1
0
A0
0
Double Word 0
Double Word 1
Double Word 2
Double Word 3
0
1
1
0
1
1
Table 3. Word Mode
The random or initial page access is equal to t
or
Word
A1
0
A0
0
A-1
ACC
t
and subsequent page read accesses (as long as
CE
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
0
1
0
1
0
1
0
1
the locations specified by the microprocessor falls
within that page) is equivalent to t . When CE# is
0
0
PACC
deasserted and reasserted for a subsequent access,
the access time is t or t . Here again, CE# selects
0
1
ACC
CE
the device and OE# is the output control and should be
used to gate data to the output inputs if the device is
selected. Fast page mode accesses are obtained by
keeping A19–A2 constant and changing A1 to A0 to
select the specific double word, or changing A1 to A-1
to select the specific word, within that page.
0
1
1
0
1
0
1
1
1
1
10
Am29PL320D
June 13, 2005
device to normal operation. Note that the ACC pin
must not be at V for operations other than acceler-
ated programming, or device damage may result. In
addition, the ACC pin must not be left floating or un-
connected; inconsistent behavior of the device may re-
sult.
Writing Commands/Command Sequences
HH
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V , and OE# to V .
IL
IH
For program operations, the WORD# input determines
whether the device accepts program data in double
words or words. Refer to “Word/Double Word Configu-
ration” for more information.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required
to program a word or double word, instead of four. The
“Word/Double Word Program Command Sequence”
section has details on programming data to the device
using both standard and Unlock Bypass command
sequences.
I
read specifications apply. Refer to “Write Operation
CC
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 4 indicates the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Command Definitions” section has de-
tails on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
The device enters the CMOS standby mode when the
CE# input is both held at VCC ± 0.3 V. (Note that this is
a more restricted voltage range than V .) If CE# is
IH
held at V , but not within VCC ± 0.3 V, the device will
IH
be in the standby mode, but the standby current will be
greater. The device requires standard access time
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
(t ) for read access when the device is in either of
CE
these standby modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
in the DC Characteristics table represents the ac-
CC2
Automatic Sleep Mode
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables this
mode when addresses remain stable for t
+ 30 ns.
ACC
Accelerated Program Operation
The automatic sleep mode is independent of the CE#,
WE#, and OE# control signals. Standard address access
timings provide new data when addresses are changed.
While in sleep mode, output data is latched and always
available to the system. Note that during Automatic Sleep
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput dur-
ing system production.
mode, OE# must be at V before the device reduces cur-
IH
If the system asserts V
(11.5 to 12.5 V) on this in-
HH
rent to the stated sleep mode specification.
put, the device automatically enters the aforemen-
tioned Unlock Bypass mode, temporarily unprotects
any protected sectors, and uses the higher voltage on
the pin to reduce the time required for program opera-
tions. The system would use a two-cycle program
command sequence as required by the Unlock Bypass
Output Disable Mode
When the OE# input is at V , output from the device is
IH
disabled. The output inputs are placed in the high im-
pedance state.
mode. Removing V
from the ACC pin returns the
HH
June 13, 2005
Am29PL320D
11
Table 4. Sector Address Table, Top Boot (Am29PL320DT)
Sector Size
(Kwords/
Kdouble
words)
Address Range (in hexadecimal)
Word Mode
(x16)
Double Word Mode
(x32)
Sector A19 A18 A17 A16 A15 A14 A13 A12
SA0
SA1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
96/48
000000–01FFFF
020000–03FFFF
040000–05FFFF
060000–07FFFF
080000–09FFFF
0A0000–0BFFFF
0C0000–0DFFFF
0E0000–0FFFFF
100000–11FFFF
120000–13FFFF
140000–15FFFF
160000–17FFFF
180000–19FFFF
1A0000–1BFFFF
1C0000–1DFFFF
1E0000–1F7FFF
1F8000–1F9FFF
1FA000–1FBFFF
1FC000–1FFFFF
00000–0FFFF
10000–1FFFF
20000–2FFFF
30000–3FFFF
40000–4FFFF
50000–5FFFF
60000–6FFFF
70000–7FFFF
80000–8FFFF
90000–9FFFF
A0000–AFFFF
B0000–BFFFF
C0000–CFFFF
D0000–DFFFF
E0000–EFFFF
F0000–FBFFF
FC000–FCFFF
FD000–FDFFF
FE000–FFFFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
0000–1011
1
1
1
1
1
1
0
0
1
0
1
X
8/4
8/4
16/8
Note: Address range is A19–A-1 if device is in word mode (WORD# = V ). Address range is A19–A0 if device is in double word
IL
mode (WORD# = V ).
IH
Table 5. SecSi™ Sector Addresses for Top Boot Devices
Sector Address
(x16)
(x32)
Device
A7–A0
Sector Size
Address Range
Address Range
Am29PL320DT
00000000
512 words/256 double words
000000h–0001FFh
00000h–000FFh
12
Am29PL320D
June 13, 2005
Table 6. Sector Address Table, Bottom Boot (Am29PL320DB)
Sector Size
(Kwords/
Kdouble
words)
Address Range (in hexadecimal)
Word Mode
(x16)
Double Word Mode
(x32)
Sector A19 A18 A17 A16 A15 A14 A13 A12
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
X
0
1
16/8
000000–003FFF
004000–005FFF
006000–007FFF
008000–01FFFF
020000–03FFFF
040000–05FFFF
060000–07FFFF
080000–09FFFF
0A0000–0BFFFF
0C0000–0DFFFF
0E0000–0FFFFF
100000–11FFFF
120000–13FFFF
140000–15FFFF
160000–17FFFF
180000–19FFFF
1A0000–1BFFFF
1C0000–1DFFFF
1E0000–1FFFFF
00000–001FF
02000–02FFF
03000–03FFF
04000–0FFFF
10000–1FFFF
20000–2FFFF
30000–3FFFF
40000–4FFFF
50000–5FFFF
60000–6FFFF
70000–7FFFF
80000–8FFFF
90000–9FFFF
A0000–AFFFF
B0000–BFFFF
C0000–CFFFF
D0000–DFFFF
E0000–EFFFF
F0000–FFFFF
8/4
SA2
8/4
SA3
01000–11111
96/48
SA4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
Note: Address range is A19–A-1 if device is in word mode (WORD# = V ). Address range is A19–A0 if device is in double word
IL
mode (WORD# = V ).
IH
Table 7. SecSi™ Sector Addresses for
Bottom Boot Devices
Sector Address
A7–A0
(x16)
Address Range
(x32)
Address Range
Device
Sector Size
Am29PL320DB
00000000
512 words/256 double words
000000h–0001FFh
00000h–000FFh
June 13, 2005
Am29PL320D
13
dition, when verifying sector protection, the sector
address must appear on the appropriate highest order
address bits (Table 4). Table 8 shows the remaining
address bits that are don’t care. When all necessary
bits have been set as required, the programming
equipment may then read the corresponding identifier
code on DQ7-DQ0.
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed
with its corresponding programming algorithm. How-
ever, the autoselect codes can also be accessed in-
system through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 13. This method
When using programming equipment, the autoselect
does not require V . See “Command Definitions” for
ID
mode requires V (11.5 V to 12.5 V) on address input
ID
details on using the autoselect mode.
A9. Address inputs must be as shown in Table 8. In ad-
Table 8. Am29PL320D Autoselect Codes (High Voltage Method)
DQ31–
DQ8
Description
Mode
DQ7–DQ0
Manufacturer ID: AMD
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
X
X
X
X
V
V
X
X
L
L
X
X
X
L
X
L
L
L
L
X
01h
ID
Word
Read
22h
H
7Eh
03h
ID
Cycle 1
Dbl. Word
222222h
22h
Word
Read
X
X
X
X
V
X
X
L
L
X
X
H
H
H
H
H
H
L
ID
ID
Cycle 2
Dbl. Word
222222h
22h
Word
Read
00h (bottom boot)
01h (top boot)
V
H
Cycle 3
Dbl. Word
222222h
SecSi™ Sector Indicator
Bit
80h (factory locked)
00h (not factory locked)
L
L
L
L
H
H
X
X
X
V
V
X
X
L
L
X
X
L
L
L
L
H
H
H
L
X
X
ID
01h (protected)
Sector Protection
Verification
SA
ID
00h (unprotected)
L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.
IL
IH
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 13.
Sector protection and unprotection must be imple-
mented via programming equipment. The procedure
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector.
The hardware sector unprotection feature re-enables
both program and erase operations in previously
protected sectors.
requires high voltage (V ) to be placed on address
ID
input A9 and control input OE#. This method is com-
patible with programmer routines written for earlier
AMD 3.0 volt devices. Publication number 24136 con-
tains further details; contact an AMD representative to
request a copy. For sector unprotect, all unprotected
sectors must first be protected prior to the first sector
unprotect write cycle. Note that after the sector unpro-
tect operation, all previously protected sectors must be
re-protected using the sector protect algorithm.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
The device features a temporary unprotect command
sequence to allow changing array data in-system. See
“Temporary Sector Unprotect Enable/Disable
Command Sequence” for more information.
14
Am29PL320D
June 13, 2005
The system can read CFI information at the addresses
given in Tables 9–12. To terminate reading CFI data,
the system must write the reset command.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of de-
vices. Software support can then be device-
independent, JEDEC ID-independent, and forward-
and backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 9–12. The
system must write the reset command to return the de-
vice to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi. Alterna-
tively, contact an AMD representative for copies of
these documents.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h in double word mode (or address AAh in word
mode), any time the device is ready to read array data.
Table 9. CFI Query Identification String
Addresses
(Double
Addresses
Word Mode)
(Word Mode)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
June 13, 2005
Am29PL320D
15
Table 10. System Interface String
Data
Addresses
(Double Word
Mode)
Addresses
(Word Mode)
Description
V
Min. (write/erase)
CC
1Bh
36h
0027h
D7–D4: volt, D3–D0: 100 millivolt
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0036h
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0006h
0000h
V
V
V
Max. (write/erase), D7–D4: volt, D3–D0: 100 millivolt
CC
PP
PP
Min. voltage (00h = no V input present)
PP
Max. voltage (00h = no V input present)
PP
N
Typical timeout per single word/double word write 2 µs
N
Typical timeout for Min. size buffer write 2 µs (00h = not supported)
N
Typical timeout per individual block erase 2 ms
N
Typical timeout for full chip erase 2 ms (00h = not supported)
N
Max. timeout for word/ double word write 2 times typical
N
Max. timeout for buffer write 2 times typical
N
Max. timeout per individual block erase 2 times typical
N
Max. timeout for full chip erase 2 times typical (00h = not supported)
Table 11. Device Geometry Definition
Addresses
(Double Word
Mode)
Addresses
(Word Mode)
Data
Description
N
27h
4Eh
0016h
Device Size = 2 byte
28h
29h
50h
52h
0005h
0000h
Flash Device Interface description (refer to CFI publication 100)
N
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of bytes in multi-byte write = 2
(00h = not supported)
2Ch
58h
0004h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0000h
0000h
0080h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
0001h
0000h
0040h
0000h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0003h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
000Eh
0000h
0000h
0004h
16
Am29PL320D
June 13, 2005
Table 12. Primary Vendor-Specific Extended Query
Addresses
(Double Word
Mode)
Addresses
(Word Mode)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0032h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required, 1 = Not Required
45h
46h
47h
48h
8Ah
8Ch
8Eh
90h
0000h
0002h
0001h
0001h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
49h
4Ah
4Bh
4Ch
4Dh
92h
94h
96h
98h
9Ah
0001h
0000h
0000h
0002h
00B5h
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
Simultaneous Operation
00 = Not Supported, 01 = Supported
Burst Mode Type
00 = Not Supported, 01 = 4 Word Linear Burst, 02 = 8 Word Linear Burst,
03 = 32 Linear Burst, 04 = 4 Word Interleave Burst
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply
Minimum 00h = not supported,
D7–D4: volt; D3–D0: 100 millivolt.
ACC (Acceleration) Supply
4Eh
50h
9Ch
A0h
00C5h
0000h
Maximum 00h = not supported,
D7–D4: volt; D3–D0: 100 millivolt.
Program Suspend
00h = not supported, 01h = supported
128 words. This should be considered during sys-
tem design.
SecSi™ (Secured Silicon) Sector Flash
Memory Region
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The factory-
locked version is always protected when shipped from
the factory, and has the SecSi (Secured Silicon) Sec-
tor Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi
Sector unprotected, allowing customers to utilize the
that sector in any manner they choose. The customer-
lockable version has the SecSi (Secured Silicon) Sec-
tor Indicator Bit permanently set to a “0.” Thus, the
SecSi Sector Indicator Bit prevents customer-lockable
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is a minimum of 128 words
(64 double words) in length, and uses a SecSi Sector
Indicator Bit (DQ7) to indicate whether or not the
SecSi Sector is locked when shipped from the factory.
This bit is permanently set at the factory and cannot
be changed, which prevents cloning of a factory locked
part. This ensures the security of the ESN once the
product is shipped to the field. Current version of de-
vice has 512 words; future versions will have only
June 13, 2005
Am29PL320D
17
devices from being used to replace devices that are
factory locked.
bypass functions are not available when programming
the SecSi Sector.
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi™ Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresses normally occupied by the boot sectors. This
mode of operation continues until the system issues
the Exit SecSi Sector command sequence, or until
power is removed from the device. On power-up the
device reverts to sending commands to the boot sec-
tors.
The SecSi Sector can be locked in-system by perform-
ing the following steps:
■ Write the three-cycle Enter SecSi Sector Region
command sequence.
■ Write 60h to any address (protect command).
■ Wait 150 µs, and then write 40h to address 01h (ver-
ify command).
■ Read from address 02h. The data should be 01h.
■ Write the reset command (F0h to any address).
■ Write the four-cycle Exit SecSi Sector command se-
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
quence to return to reading from the array.
To verify the protect/unprotect status of the SecSi
Sector, follow the algorithm shown in Figure 1.
In a factory locked device, the SecSi Sector is pro-
tected when the device is shipped from the factory.
The SecSi Sector cannot be modified in any way. The
device is available preprogrammed with one of the fol-
lowing:
The SecSi Sector lock must be used with caution
since, once locked, there is no procedure available for
unlocking the SecSi Sector area and none of the bits
in the SecSi Sector memory space can be modified in
any way.
■ A random, secure ESN only
■ Customer code through the ExpressFlash service
■ Both a random, secure ESN and customer code
START
through the ExpressFlash service.
If data = 00h,
RESET# =
In devices that have an ESN, a Bottom Boot device will
have the 8-word (4-double word) ESN in the lowest ad-
dressable memory area at addresses 000000h–
000003h in double word mode (or 000000h–000007h
in word mode). In the Top Boot device the starting ad-
dress of the ESN will be at the bottom of the lowest 8
Kbyte boot sector at addresses 1F8000h–1F8003h in
double word mode (or addresses FC0000h–FC0007h
in word mode).
SecSi Sector is
VIH or VID
unprotected.
If data = 01h,
SecSi Sector is
protected.
Wait 1 μs
Write 60h to
any address
Remove VIH or VID
from RESET#
Write 40h to SecSi
Sector address
with A6 = 0,
command
A1 = 1, A0 = 0
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. AMD
programs the customer’s code, with or without the ran-
dom ESN. The devices are then shipped from AMD’s
factory with the SecSi Sector permanently locked.
Contact an AMD representative for details on using
AMD’s ExpressFlash service.
Write reset
SecSi Sector
Read from SecSi
Protect Verify
Sector address
complete
with A6 = 0,
A1 = 1, A0 = 0
Customer Lockable: SecSi Sector NOT
Programmed or Locked At the Factory
Figure 1. SecSi Sector Protect Verify
If the security feature is not required, the SecSi Sector
can be treated as an additional Flash memory space,
expanding the size of the available Flash array. Cur-
rent version of device has 512 words; future ver-
sions will have only 128 words. This should be
considered during system design. The SecSi Sec-
tor can be read, programmed, and erased as often as
required. (In upcoming versions of this device, the
SecSi Sector erase function will not be available.) Note
that the accelerated programming (ACC) and unlock
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting certain boot sectors without
using V .
ID
If the system asserts V on the WP# input, the device
IL
disables program and erase functions in Sector 0 (for
bottom boot) or Sector 18 (for top boot) independently
of whether those sectors were protected or unpro-
18
Am29PL320D
June 13, 2005
tected using the method described in “Sector Protec-
tion/Unprotection”.
Low V
Write Inhibit
CC
When V
is less than V
, the device does not ac-
LKO
CC
cept any write cycles. This protects data during V
If the system asserts V on the WP# input, the device
CC
IH
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored
reverts to whether Sector 0 or 18 was last set to be
protected or unprotected. That is, sector protection or
unprotection for that sector depends on whether they
were last protected or unprotected using the method
described in “Sector Protection/Unprotection”.
until V
is greater than V
. The system must pro-
CC
LKO
vide the proper signals to the control inputs to prevent
unintentional writes when V is greater than V
.
CC
LKO
Note that the WP# input must not be left floating or un-
connected; inconsistent behavior of the device may re-
sult.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Hardware Data Protection
Logical Inhibit
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 13 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
Write cycles are inhibited by holding any one of OE# =
V , CE# = V or WE# = V . To initiate a write cycle,
IL
IH
IH
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
spurious system level signals during V
power-up
CC
If WE# = CE# = V and OE# = V during power up,
IL
IH
and power-down transitions, or from system noise.
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device
operations. Table 13 defines the valid register com-
mand sequences. Note that writing incorrect address
and data values or writing them in the improper se-
quence may place the device in an unknown state. A
reset command is required to return the device to nor-
mal operation.
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 13 shows the timing diagram.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
The reset command may be written between the se-
quence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
June 13, 2005
Am29PL320D
19
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
controls or timings. The device automatically gener-
ates the program pulses and verifies the programmed
cell margin. Table 13 shows the address and data re-
quirements for the program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can
determine the status of the program operation by using
DQ7 or DQ6. See “Write Operation Status” for informa-
tion on these status bits.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 13 shows the address and data requirements.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. The Program
command sequence should be reinitiated once the de-
vice has reset to reading array data, to ensure data
integrity.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect mode,
and the system may read any number of autoselect
codes without reinitiating the command sequence.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may
halt the operation and set DQ5 to “1,” or cause the
Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read will show that
the data is still “0”. Only erase operations can convert
a “0” to a “1”.
Tables 13 and 14 show the address and data require-
ments for the command sequence. To determine sec-
tor protection information, the system must write to the
appropriate sector address (SA). Tables 4 and 6 show
the address range associated with each sector.
Unlock Bypass Command Sequence
The system must write the reset command to exit the
autoselect mode and return to reading array data.
The unlock bypass feature allows the system to pro-
gram bytes or words to the device faster than using the
standard program command sequence. The unlock by-
pass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The de-
vice then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the pro-
gram address and data. Additional data is
programmed in the same manner. This mode dis-
penses with the initial two unlock cycles required in the
standard program command sequence, resulting in
faster total programming time. Table 13 shows the re-
quirements for the command sequence.
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing a random, eight-word (or four double word)
electronic serial number (ESN). The system can ac-
cess the SecSi Sector region by issuing the three-
cycle Enter SecSi Sector command sequence. The
device continues to access the SecSi Sector region
until the system issues the four-cycle Exit SecSi Sec-
tor command sequence. The Exit SecSi Sector com-
mand sequence returns the device to normal
operation. Table 13 shows the address and data re-
quirements for both command sequences. See also
“SecSi™ (Secured Silicon) Sector Flash
Memory Region” for further information.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to
reading array data.
Word/Double Word Program
Command Sequence
The system may program the device by word or double
word, depending on the state of the WORD# input.
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
Figure 2 illustrates the algorithm for the program oper-
ation. See the Program/Erase Operations table in “AC
Characteristics” for parameters, and to Figure 17 for
timing diagrams.
20
Am29PL320D
June 13, 2005
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Table 13 for program command sequence
Figure 2. Program Operation
June 13, 2005
Am29PL320D
21
this time to ensure all commands are accepted. The in-
terrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase Sus-
pend during the time-out period resets the device
to reading array data. The system must rewrite the
command sequence and any additional sector ad-
dresses and commands.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 13
shows the address and data requirements for the chip
erase command sequence.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, or DQ2.
(Refer to “Write Operation Status” for information on
these status bits.)
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Program/Erase Operations tables in “AC
Characteristics” for parameters, and to Figure 18 for
timing diagrams.
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Program/Erase Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 18 for timing diagrams.
Sector Erase Command Sequence
Erase Suspend/Erase Resume Commands
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 13 shows the address and data
requirements for the sector erase command sequence.
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase
Suspend command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector
for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maxi-
mum of 20 µs to suspend the erase operation.
However, when the Erase Suspend command is writ-
ten during the sector erase time-out, the device
immediately terminates the time-out period and sus-
pends the erase operation.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
22
Am29PL320D
June 13, 2005
suspends” all sectors selected for erasure.) Note that
unlock bypass programming is not allowed when the
device is erase-suspended.
Another Erase Suspend command can be written after
the device has resumed erasing.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
START
Write Erase
Command Sequence
After an erase-suspended program operation is com-
plete, the system can once again read array data
within non-suspended sectors. The system can deter-
mine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard
program operation. See “Write Operation Status” for
more information.
Data Poll
from System
Embedded
Erase
algorithm
in progress
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
No
Data = FFh?
Yes
Erasure Completed
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase sus-
pend mode and continue the sector erase operation.
Further writes of the Resume command are ignored.
Notes:
1. See Table 13 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
June 13, 2005
Am29PL320D
23
Temporary Sector Unprotect Enable/Dis-
able Command Sequence
The temporary unprotect command sequence is a
four-bus-cycle operation. The sequence is initiated by
writing two unlock write cycles. A third write cycle sets
up the command. The fourth and final write cycle en-
ables or disables the temporary unprotect feature. If
the temporary unprotect feature is enabled, all sectors
are temporarily unprotected. The system may program
or erase data as needed. When the system writes the
temporary unprotect disable command sequence, all
sectors return to their previous protected or unpro-
tected settings. See Table 13 and Figure 4 for more
information.
START
Write Temporary Sector
Unprotect Enable
Command Sequence
(Note 1)
Perform Erase or
Program Operations
Write Temporary Sector
Unprotect Disable
Command Sequence
(Note 2)
Procedure Complete
Notes:
1. All protected sectors are unprotected. If WP# = V , the
IL
first or last 64 KByte sector will remain protected.
2. All previously protected sectors are protected once again.
Figure 4. Temporary Sector Unprotect Algorithm
24
Am29PL320D
June 13, 2005
Command Definitions
Table 13. Command Definitions (Double Word Mode)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Data
Addr Data Addr Data Addr Data Addr
Data
Addr Data Addr
Read (Note 6)
Reset (Note 7)
1
RA
XXX
555
555
RD
F0
1
4
6
Manufacturer ID
AA
AA
2AA
2AA
55
55
555
555
90
90
00
01
01
Device ID (Note 9)
227E
0E
2203
0F
2200 2201
SecSi™ Sector Factory
Protect (Note 10)
(BA)
555
(BA)
X03
4
4
555
555
AA
AA
2AA
2AA
55
55
90
90
(Note 10)
(Note 11)
Sector Protect Verify
(Note 11)
(SA)
X02
555
Enter SecSi Sector Region
Exit SecSi Sector Region
CFI Query (Note 12)
Program
3
4
1
4
3
555
555
55
AA
AA
98
2AA
2AA
55
55
555
555
88
90
XXX
PA
00
555
555
AA
AA
2AA
2AA
55
55
555
555
A0
20
PD
Unlock Bypass
Unlock Bypass Program
(Note 13)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 14)
Chip Erase
2
6
6
1
1
XXX
555
90
AA
AA
B0
30
XXX
2AA
2AA
00
55
55
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
555
Erase Suspend (Note 15)
Erase Resume (Note 16)
XXX
XXX
Temporary Sector Unprotect
Enable
4
4
555
555
AA
AA
2AA
2AA
55
55
555
555
E0
E0
XXX
XXX
01
00
Temporary Sector Unprotect
Disable
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
SA = Address of the sector to be verified (in autoselect mode) or erased.
Address bits A19–A12 uniquely select any sector.
PA = Address of the memory location to be programmed. Addresses latch
on the falling edge of the WE# or CE# pulse, whichever happens later.
11. The data is 00h for an unprotected sector and 01h for a protected
sector. See “Autoselect Command Sequence” for more information.
Notes:
1. See Table 1 for description of bus operations.
12. Command is valid when device is ready to read array data or when
device is in autoselect mode.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
13. The Unlock Bypass command is required prior to the Unlock Bypass
Program command.
4. Data bits DQ31–DQ8 are don’t cares for unlock and command
cycles.
14. The Unlock Bypass Reset command is required to return to reading
array data when the device is in the unlock bypass mode.
15. The system may read and program in non-erasing sectors, or enter
the autoselect mode, when in the Erase Suspend mode. The Erase
Suspend command is valid only during a sector erase operation.
16. The Erase Resume command is valid only during the Erase Suspend
mode.
5. Address bits A19–A11 are don’t cares for unlock and command
cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when
device is in the autoselect mode, or if DQ5 goes high (while the
device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read
cycle.
9. DQ31–DQ16 output 2222h for device ID reads. The device ID must
be read across the fourth, fifth, and sixth cycles. The sixth cycle
specifies 22222200h for bottom boot devices and 22222201h for top
boot devices.
10. The data is 80h for factory locked and 00h for not factory locked.
June 13, 2005
Am29PL320D
25
Table 14. Command Definitions (Word Mode)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Data
Addr Data Addr Data Addr Data Addr
Data
Addr Data Addr
Read (Note 6)
Reset (Note 7)
Manufacturer ID
1
1
4
6
RA
RD
F0
XXX
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
90
90
00
02
01
Device ID (Note 9)
227E
1C
2203
1E
2200 2201
SecSi™ Sector Factory
Protect (Note 10)
(BA)
AAA
(BA)
X06
4
4
AAA
AAA
AA
AA
555
555
55
55
90
90
(Note 10)
(Note 11)
Sector Protect Verify
(Note 11)
(SA)
X04
AAA
Enter SecSi Sector Region
Exit SecSi Sector Region
CFI Query (Note 12)
Program
3
4
1
4
3
2
2
6
6
1
1
AAA
AAA
55
AA
AA
98
555
555
55
55
AAA
AAA
88
90
XXX
PA
00
AAA
AAA
XXX
XXX
AAA
AAA
XXX
XXX
AA
AA
A0
90
555
555
PA
55
55
PD
00
55
55
AAA
AAA
A0
20
PD
Unlock Bypass
Unlock Bypass Program (Note 13)
Unlock Bypass Reset (Note 14)
Chip Erase
XXX
555
555
AA
AA
B0
30
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Erase Suspend (Note 15)
Erase Resume (Note 16)
Temporary Sector Unprotect
Enable
4
4
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
E0
E0
XXX
XXX
01
00
Temporary Sector Unprotect
Disable
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
SA = Address of the sector to be verified (in autoselect mode) or erased.
Address bits A19–A12 uniquely select any sector.
PA = Address of the memory location to be programmed. Addresses latch
on the falling edge of the WE# or CE# pulse, whichever happens later.
10. The data is 80h for factory locked and 00h for not factory locked.
11. The data is 00h for an unprotected sector and 01h for a protected
sector. See “Autoselect Command Sequence” for more information.
12. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
13. The Unlock Bypass command is required prior to the Unlock Bypass
Program command.
4. Data bits DQ31–DQ8 are don’t cares for unlock and command
cycles.
14. The Unlock Bypass Reset command is required to return to reading
array data when the device is in the unlock bypass mode.
5. Address bits A19–A11 are don’t cares for unlock and command
cycles, unless SA or PA required.
15. The system may read and program in non-erasing sectors, or enter
the autoselect mode, when in the Erase Suspend mode. The Erase
Suspend command is valid only during a sector erase operation.
16. The Erase Resume command is valid only during the Erase Suspend
mode.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when
device is in the autoselect mode, or if DQ5 goes high (while the
device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read
cycle.
9. The device ID must be read across the fourth, fifth, and sixth cycles.
The sixth cycle specifies 2200h for bottom boot devices and 2201h
for top boot devices.
26
Am29PL320D
June 13, 2005
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 15 and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
DQ6 while Output Enable (OE#) is asserted low. See
Figure 18 in the “AC Characteristics” section.
Table 15 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge
of the final WE# pulse in the program or erase com-
mand sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 1 µs, then the device returns to reading
array data.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum out-
put described for the Embedded Program algorithm:
the erase function changes all the bits in a sector to
“1”; prior to this, the device outputs the “complement,”
or “0.” The system must provide an address within any
of the sectors selected for erasure to read valid status
information on DQ7.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ7–DQ0 on the following read cycles. This is be-
cause DQ7 may change asynchronously with DQ0–
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5
Figure 5. Data# Polling Algorithm
June 13, 2005
Am29PL320D
27
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for
erasure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 15 to compare outputs
for DQ2 and DQ6.
DQ6: Toggle Bit
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. See also the DQ6: Toggle Bit
subsection. Figure 20 shows the toggle bit timing dia-
gram. Figure 21 shows the differences between DQ2
and DQ6 in graphical form.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system
must write the reset command to return to reading
array data.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 15 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. Figure 20 in the “AC Character-
istics” section shows the toggle bit timing diagrams.
Figure 21 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
“DQ2: Toggle Bit”.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 6).
DQ2: Toggle Bit
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
28
Am29PL320D
June 13, 2005
condition that indicates the program or erase cycle
was not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
START
Read DQ7–DQ0
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
Read DQ7–DQ0
(Note 1)
No
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3 if
the system can guarantee that the time between addi-
tional sector erase commands will always be less than
50 μs. See also the “Write Operation Status” section.
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read
DQ3. If DQ3 is “1”, the internally controlled erase cycle
has begun; all further commands (other than Erase
Suspend) are ignored until the erase operation is com-
plete. If DQ3 is “0”, the device will accept additional
sector erase commands. To ensure the command has
been accepted, the system software should check the
status of DQ3 prior to and following each subsequent
sector erase command. If DQ3 is high on the second
status check, the last command might not have been
accepted. Table 15 shows the outputs for DQ3.
Read DQ7–DQ0
Twice
(Notes
1, 2)
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 6. Toggle Bit Algorithm
June 13, 2005
Am29PL320D
29
Table 15. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 2)
DQ7#
0
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
0
0
No toggle
Toggle
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Erase
Suspend
Mode
Reading within Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
30
Am29PL320D
June 13, 2005
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . -65°C to +150°C
20 ns
20 ns
+0.8 V
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . -65°C to +125°C
–0.5 V
–2.0 V
Voltage with Respect to Ground
V
(Note 1). . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
CC
A9, OE#, ACC (Note 2) . . . . . . . .–0.5 V to +13.0 V
All other inputs (Note 1) . . . . . . . . .–0.5 V to +5.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
20 ns
Figure 7. Maximum Negative
Overshoot Waveform
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During
voltage transitions, voltages on inputs or I/Os may
overshoot V to –2.0 V for periods of up to 20 ns.
SS
Maximum DC voltage on output and I/Os is V + 0.5 V.
CC
20 ns
During voltage transitions I/Os may overshoot to V
2.0 V for periods up to 20 ns.
+
CC
V
CC
+2.0 V
2. Minimum DC input voltage on inputs A9, OE#, and ACC
is –0.5 V. During voltage transitions, A9 and OE# may
V
CC
+0.5 V
overshoot V to -2.0 V for periods of up to 20 ns.
SS
Maximum DC input voltage on input A9, OE#, and ACC is
+13.0 V which may overshoot to 14.0 V for periods up to
20 ns.
2.0 V
20 ns
20 ns
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Figure 8. Maximum Positive Overshoot Waveform
4. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the de-
vice at these or any other conditions above those indi-
cated in the operational sections of this data sheet is not
implied. Exposure of the device to absolute maximum rat-
ing conditions for extended periods may affect device re-
liability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T ) . . . . . . . . . . . 0°C to +70°C
A
Industrial (I) Devices
Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C
A
V
V
V
Supply Voltages
CC
CC
CC
for regulated voltage range. . . . . . .3.0 V to 3.6 V
for full voltage range . . . . . . . . . . . .2.7 V to 3.6 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
June 13, 2005
Am29PL320D
31
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Description
Test Conditions
= V to V
Min
Typ
Max
± 1.0
35
Unit
µA
V
V
,
CC
IN
SS
I
Input Load Current
LI
= V
CC
CC max
I
A9 Input Load Current
Output Leakage Current
V
= V
; A9 = 12.5 V
µA
LIT
CC
CC max
V
V
= V to V
,
CC
OUT
SS
I
± 1.0
µA
LO
= V
CC
CC max
1 MHz
4
50
80
mA
mA
V
Active Inter-Page Read
CC
I
CE# = V OE# = V
IL,
CC1
IH
IH
Current (Notes 1, 2)
10 MHz
40
V
Active Write Current
CC
I
I
CE# = V OE# = V
25
80
mA
µA
CC2
IL,
(Notes 2, 4)
V
Standby Current (Note 2)
CE# = V ± 0.3 V
2
1
5
5
CC3
CC
CC
OE# = V
OE# = V
IH
IL
Automatic Sleep Mode
(Notes 2, 3, 6)
V
V
= V ± 0.3 V;
IH
IL
CC
I
µA
CC4
CC5
= V ± ±0.3 V
SS
2
20
50
80
0.8
10 MHz
33 MHz
15
50
mA
mA
V
V
Active Intra-Page Read
CC
I
CE# = V OE# = V
IL,
IH
Current (Note 2)
V
Input Low Voltage
Input High Voltage
–0.5
2.0
IL
V
V
+ 0.3
CC
V
IH
Voltage for Accelerated
Programming on ACC
V
11.5
11.5
12.5
V
HH
Voltage for Autoselect and
Temporary Sector Unprotect
V
V
= 3.0 ± 0.3 V
CC
12.5
0.45
V
V
ID
V
Output Low Voltage
I
I
I
= 4.0 mA, V = V
CC CC min
OL
OL
OH
OH
V
V
= –2.0 mA, V = V
0.85 x V
CC
OH1
OH2
CC
CC min
CC min
Output High Voltage
V
V
= –100 µA, V = V
V
–0.4
CC
CC
Low V Lock-Out Voltage
CC
V
2.3
2.5
LKO
(Note 6)
Notes:
1. The I current listed is typically less than 4 mA/MHz, with OE# at V . Typical V is 3.0 V.
CC
IH
CC
2. Maximum I specifications are tested with V = V max.
CC
CC
CC
3. The Automatic Sleep Mode current is dependent on the state of OE#.
4. I active while Embedded Erase or Embedded Program is in progress.
CC
5. Automatic sleep mode enables the low power mode when addresses remain stable for t
6. Not 100% tested.
+ 30 ns.
ACC
32
Am29PL320D
June 13, 2005
DC CHARACTERISTICS (Continued)
Zero Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz.
Figure 9.
I
Current vs. Time (Showing Active and Automatic Sleep Currents)
CC1
20
16
12
8
3.6 V
2.7 V
4
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical I
vs. Frequency
CC1
June 13, 2005
Am29PL320D
33
TEST CONDITIONS
Table 16. Test Specifications
3.3 V
Test Condition
All speeds
1 TTL gate
Unit
Output Load
2.7 kΩ
Device
Under
Test
Output Load Capacitance, C
(including jig capacitance)
L
30
pF
C
L
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
6.2 kΩ
0.0–3.0
Input timing measurement
reference levels
1.5
1.5
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 12. Input Waveforms and Measurement Levels
34
Am29PL320D
June 13, 2005
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
60R
70R, 70
90
Unit
t
t
Read Cycle Time
Min
60
60
70
90
ns
AVAV
RC
CE#=V ,
IL
t
t
Address Access Time
Max
70
90
ns
AVQV
ELQV
ACC
OE#=V
IL
t
t
Chip Enable to Output Delay
Page Access Time
OE#=V
Max
Max
Max
Max
Max
60
20
20
70
25
25
16
16
0
90
35
35
ns
ns
ns
ns
ns
ns
CE
IL
t
PACC
t
t
t
Output Enable to Output Valid
Chip Enable to Output High Z
Output Enable to Output High Z
GLQV
EHQZ
GHQZ
OE
t
t
DF
DF
t
Read
Output Enable
Hold Time (Note 1)
t
OEH
Toggle and
Data# Polling
10
0
ns
ns
Output Hold Time From Addresses, OE#
or CE#, Whichever Occurs First (Note 1)
t
t
Min
AXQX
OH
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 16 for test specifications.
June 13, 2005
Am29PL320D
35
AC CHARACTERISTICS
tRC
Addresses Stable
Addresses
CE#
tACC
tDF
tOE
OE#
WE#
tOEH
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
0 V
Figure 13. Conventional Read Operations Timings
Same Page
A19-A3
A2-A-1
Ad
Aa
tACC
Ab
tPACC
Ac
tPACC
tPACC
Data Bus
CE#
Qa
Qb
Qc
Qd
Note: Double Word Configuration: Toggle A2, A1, A0. Word Configuration: Toggle A2, A1, A0, A-1.
Figure 14. Page Read Timings
36
Am29PL320D
June 13, 2005
AC CHARACTERISTICS
Double Word/Word Configuration (WORD#)
Parameter
Speed Options
JEDEC
Std
Description
60R
70R, 70
90
Unit
ns
t
t
t
t
CE# to WORD# Switching Low or High
WORD# Switching Low to Output HIGH Z
WORD# Switching High to Output Active
Max
Max
Min
5
ELFL/ ELFH
16
70
ns
FLQZ
FHQV
60
90
ns
CE#
OE#
WORD#
t
ELFL
Data Output
(DQ30–DQ0)
Data Output
(DQ15–DQ0)
WORD#
Switching
from double
word to word
mode
DQ30–DQ0
DQ31/A-1
Address
Input
DQ31
Output
t
FLQZ
t
ELFH
WORD#
WORD#
Switching
from word to
double word
mode
Data Output
(DQ15–DQ0)
Data Output
(DQ30–DQ0)
DQ30–DQ0
DQ31/A-1
Address
Input
DQ15
Output
t
FHQV
Figure 15. WORD# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
WORD#
t
SET
(t
)
AS
t
(t
)
HOLD AH
Note: Refer to the Erase/Program Operations table for t and t specifications.
AS
AH
Figure 16. WORD# Timings for Write Operations
June 13, 2005
Am29PL320D
37
AC CHARACTERISTICS
Program/Erase Operations
Parameter
Speed Options
Unit
JEDEC
Std
Description
60R
70R, 70
90
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
60
70
0
90
ns
ns
ns
ns
ns
ns
AVAV
WC
t
t
t
AVWL
WLAX
DVWH
WHDX
AS
AH
DS
DH
t
35
30
45
35
0
45
45
t
t
t
t
Data Hold Time
t
Output Enable Setup Time
0
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
Min
0
ns
GHWL
GHWL
t
t
CE# Setup Time
Min
Min
Min
Min
Typ
0
0
ns
ns
ns
ns
µs
ELWL
WHEH
WLWH
WHWL
CS
t
t
t
CE# Hold Time
CH
t
Write Pulse Width
Write Pulse Width High
35
25
35
30
14.3
35
30
WP
t
t
WPH
Word
t
t
t
t
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
WHWH1
WHWH2
WHWH1
Double
Word
Typ
18.3
Typ
Min
5
sec
µs
WHWH2
t
V
Setup Time (Note 1)
CC
50
VCS
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
38
Am29PL320D
June 13, 2005
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tGHWL
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
VCC
tVCS
Notes:
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode.
Figure 17. Program Operation Timings
June 13, 2005
Am29PL320D
39
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tGHWL
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
VCC
Complete
55h
30h
Progress
10 for Chip Erase
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
Figure 18. AC Waveforms for Chip/Sector Erase Operations
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ6–DQ0
Status Data
True
Valid Data
Status Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle
Figure 19. Data# Polling Timings (During Embedded Algorithms)
40
Am29PL320D
June 13, 2005
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 21. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations
June 13, 2005
Am29PL320D
41
AC CHARACTERISTICS
Alternate CE# Controlled
Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
60R
70R, 70
90
Unit
ns
t
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
60
70
0
90
AVAV
AVEL
ELAX
DVEH
EHDX
WC
t
ns
AS
AH
DS
DH
t
t
35
30
45
35
0
45
45
ns
t
t
ns
t
t
Data Hold Time
ns
t
Output Enable Setup Time
0
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
WLEL
GHEL
t
t
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
0
0
ns
ns
ns
ns
WS
t
EHWH
WH
t
t
CE# Pulse Width
CE# Pulse Width High
25
30
30
14.3
35
ELEH
EHEL
CP
t
t
CPH
Word
Programming Operation
(Note 2)
t
t
t
t
µs
WHWH1
WHWH1
Double
Word
Typ
Typ
18.3
5
Sector Erase Operation (Note 2)
sec
WHWH2
WHWH2
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
42
Am29PL320D
June 13, 2005
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tDH
DQ7#
DOUT
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D
device.
= data written to the
OUT
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
Figure 22. Alternate CE# Controlled Write Operation Timings
June 13, 2005
Am29PL320D
43
ERASE AND PROGRAMMING PERFORMANCE
Typ
Max
Parameter
(Note 1) (Note 2)
Unit
Comments
Sector Erase Time, 96 and 128 KByte
sector
2
60
60
s
Excludes 00h programming
prior to erasure (Note 4)
Sector Erase Time, 8 and 16 KByte sector
Chip Erase Time
0.5
33.5
14.3
18.3
28
s
µs
µs
s
Word Programming Time
300
360
84
Double Word Programming Time
Excludes system level
overhead (Note 5)
Word Mode
Chip Programming Time
Double Word
(Note 3)
18
54
s
Mode
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 1,000,000 cycles. Additionally,
CC
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 13 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to V on all inputs except I/O inputs
(including A9 and OE#)
SS
–1.0 V
12.5 V
Input voltage with respect to V on all I/O inputs
–1.0 V
V
+ 1.0 V
CC
SS
V
Current
–100 mA
+100 mA
CC
Includes all inputs except V . Test conditions: V = 3.0 V, one input at a time.
CC
CC
DATA RETENTION
Parameter
Test Conditions
Min
10
Unit
150°C
125°C
Years
Years
Minimum Pattern Data Retention Time
20
* For reference only. BSC is an ANSI standard for Basic Space Centering.
BGA PACKAGE CAPACITANCE
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
Typ
4.2
5.4
3.9
Max
5.0
Unit
C
V
= 0
IN
pF
pF
pF
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
6.5
OUT
OUT
C
V
= 0
IN
4.7
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
44
Am29PL320D
June 13, 2005
PHYSICAL DIMENSIONS
FBF084—84-Ball Fine Pitch Ball Grid Array (FBGA) 11 x 12 mm
Dwg. Rev. AB-01; 7/00
June 13, 2005
Am29PL320D
45
REVISION SUMMARY
Distinctive Characteristics
Revision A (March 7, 2001)
Clarified endurance specification from “write cycles” to
“erase cycles.”
Initial release.
Revision B (June 12, 2001)
SecSi™ (Secured Silicon) Sector Flash
Global
Memory Region
Added 70R speed option.
Added text and figure on SecSi Sector Protect Verify
function.
Changed data sheet status from Advance Information
to Preliminary.
Command Definitions
Modified first paragraph to indicate device behavior
when incorrect data or commands are written.
Distinctive Characteristics
SecSi Sector: Added note to future compatibility.
DC Characteristics
Power Consumption: Replaced stated maximum val-
ues with typical values.
Changed V maximum specification. Changed V
IL CC
test condition for V parameter.
ID
General Description
BGA Ball Capacitance
Added section on SecSi Sector.
Added table.
SecSi™ (Secured Silicon) Sector Flash
Memory Region
Revision C+1 (July 21, 2003)
Common Flash Interface (CFI)
Changed URL for CFI publications.
Added note to indicate sector size and erase function-
ality for future devices.
DC Characteristics
Command Definitions
Added typical values for I
–I
to table. Corrected
CC1 CC5
V
test condition specification to V
.
Added the phrase “in the improper sequence” to cau-
tionary text in first paragraph.
IN
CC
Figure 10, Typical I
vs. Frequency
CC1
Erase and Programming Performance
Changed scale on Y-axis to 4 mA divisions.
Changed typical sector erase time and typical chip
erase time. Added typical and maximum sector erase
times pertaining to 8 and 16 Kword sectors.
Revision B+1 (August 30, 2001)
Autoselect Command Sequence
Modified section to point to appropriate tables for au-
toselect functions.
Revision C+2 (October 2, 2003)
Erase Suspend/Erase Resume Commands
Accelerated Program Operation
Modified text to “Note that unlock bypass programming
is not allowed when the device is erase-suspended” in
the third paragraph.
Specified a voltage range for V
.
HH
Table 13, Command Definitions
Corrected the autoselect device ID command se-
quence. The device ID is read in cycles 4, 5, and 6 of a
single command sequence, not as three separate
command sequences as previously shown. Separated
the word and double word command sequences into
two tables for easier reference.
AC Characteristics - Double Word/Word
Configuration (WORD#) diagram
Modified all instances of DQ14 to DQ30, DQ7 to
DQ15, and DQ15 to DQ31.
Revision C+3 (June 13, 2005)
DC Characteristics
Cover Page / Title Page
Added V parameter to table.
HH
Added Spansion EOL cover page and added EOL
disclaimer to title page.
Revision C (October 22, 2002)
Global
Deleted preliminary status from data sheet.
46
Am29PL320D
June 13, 2005
Trademarks
Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
June 13, 2005
Am29PL320D
47
相关型号：
P320DB90VI
32 Megabit (2 M x 16-Bit/1 M x 32-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
AMD
P320DT60RI
32 Megabit (2 M x 16-Bit/1 M x 32-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
AMD
P320DT70RI
32 Megabit (2 M x 16-Bit/1 M x 32-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
AMD
P320DT70VI
32 Megabit (2 M x 16-Bit/1 M x 32-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
AMD
P320DT90VI
32 Megabit (2 M x 16-Bit/1 M x 32-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
AMD
©2020 ICPDF网 联系我们和版权申明