PAL16L8-7 [AMD]
20-Pin TTL Programmable Array Logic; 20引脚TTL可编程阵列逻辑
| 型号： | PAL16L8-7 |
| 厂家： | 
AMD |
| 描述： | 20-Pin TTL Programmable Array Logic |
| 文件： | 总33页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
COM’L: -4/5/7/B/B-2/A, D/2
Advanced
Micro
PAL16R8 Family
20-Pin TTL Programmable Array Logic
Devices
DISTINCTIVE CHARACTERISTICS
■ As fast as 4.5 ns maximum propagation delay
■ Power-up reset for initialization
■ Popular 20-pin architectures: 16L8, 16R8, 16R6,
■ Extensive third-party software and programmer
16R4
support through FusionPLD partners
■ Programmable replacement for high-speed TTL
■ 20-Pin DIP and PLCC packages save space
logic
■ 28-Pin PLCC-4 package provides ultra-clean
■ Register preload for testability
high-speed signals
GENERAL DESCRIPTION
The PAL16R8 Family (PAL16L8, PAL16R8, PAL16R6,
PAL16R4) includes the PAL16R8-5/4 Series which pro-
vides the highest speed in the 20-pin TTL PAL device
family, making the series ideal for high-performance ap-
plications. The PAL16R8 Family is provided with stan-
dard 20-pin DIP and PLCC pinouts and a 28-pin PLCC
pinout. The 28-pin PLCC pinout contains seven extra
ground pins interleaved between the outputs to reduce
noise and increase speed.
The AND array is programmed to create custom product
terms, while the OR array sums selected terms at the
outputs.
In addition, the PAL device provides the following
options:
— Variable input/output pin ratio
— Programmable three-state outputs
— Registers with feedback
The devices provide user-programmable logic for re-
placing conventional SSI/MSI gates and flip-flops at a
reduced chip count.
Product terms with all connections opened assume the
logicalHIGHstate;producttermsconnectedtobothtrue
and complement of any single input assume the logical
LOW state. Registers consist of D-type flip-flops that are
loaded on the LOW-to-HIGH transition of the clock. Un-
used input pins should be tied to VCC or GND.
The family allows the systems engineer to implement
the design on-chip, by opening fuse links to configure
AND and OR gates within the device, according to the
desired logic function. Complex interconnections be-
tween gates, which previously required time-consuming
layout, are lifted from the PC board and placed on sili-
con, where they can be easily modified during proto-
typing or production.
The entire PAL device family is supported by the
FusionPLD partners. The PAL family is programmed on
conventionalPALdeviceprogrammerswithappropriate
personality and socket adapter modules. Once the PAL
device is programmed and verified, an additional con-
nection may be opened to prevent pattern readout. This
feature secures proprietary circuits.
The PAL device implements the familiar Boolean logic
transfer function, the sum of products. The PAL device
is a programmable AND array driving a fixed OR array.
PRODUCT SELECTOR GUIDE
Dedicated
Product Terms/
Device
Inputs
Outputs
Output
Feedback
Enable
PAL16L8
10
6 comb.
2 comb.
7
7
I/O
–
prog.
prog.
PAL16R8
PAL16R6
8
8
8 reg.
8
reg.
pin
6 reg.
2 comb.
8
7
reg.
I/O
pin
prog.
PAL16R4
8
4 reg.
4 comb.
8
7
reg.
I/O
pin
prog.
Publication# 16492 Rev. D Amendment/0
Issue Date: February 1996
2-3
AMD
BLOCK DIAGRAMS
PAL16L8
INPUTS
10
Programmable
AND Array
(32 x 64)
7
7
7
7
7
7
7
7
O8
16492D-1
O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
PAL16R8
INPUTS
OE
CLK
8
Programmable
AND Array
(32 x 64)
8
8
8
8
8
8
8
8
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
O1
O2
O3
O4
O5
O6
O7
O8
16492D-2
2-4
PAL16R8 Family
AMD
BLOCK DIAGRAMS
PAL16R6
CLK
INPUTS
OE
8
Programmable
AND Array
(32 x 64)
7
8
8
8
8
8
8
7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
Q
Q
Q
Q
Q
Q
I/O1
O2
O3
O4
O5
O6
O7
I/O8
16492D-3
PAL16R4
CLK
OE
8
Programmable
AND Array
(32 x 64)
7
7
8
8
8
8
7
7
D
Q
D
Q
D
Q
D
Q
Q
Q
Q
Q
I/O1
O5
I/O2
O3
O4
O6
I/O7
I/O8
16492D-4
2-5
PAL16R8 Family
AMD
CONNECTION DIAGRAMS
Top View
DIP
20-Pin PLCC
1
20
19
18
17
16
(Note 1)
VCC
(Note 10)
(Note 9)
I1
I2
I3
2
3
3
2
1
20
19
4
5
6
(Note 8)
(Note 7)
(Note 6)
(Note 5)
(Note 4)
(Note 3)
(Note 2)
I4
I5
I6
(Note 9)
(Note 8)
(Note 7)
(Note 6)
18
17
16
15
4
5
6
7
I3
I4
I5
I6
15
14
13
7
8
I7
I8
9
12
11
14
(Note 5)
I7
8
GND
10
9
10 11 12 13
16492D-5
16492D-6
28-Pin PLCC
4
3
2
1
28 27 26
PIN DESIGNATIONS
I1
I8
5
6
7
8
9
25
24
23
22
21
20
CLK
GND
I
=
=
=
=
=
=
=
Clock
Ground
Input
(Note 1)
VCC
GND
(Note 2)
(Note 3)
GND
I/O
O
Input/Output
Output
(Note 10)
GND
OE
Output Enable
(Note 9)
10
11
(Note 4)
VCC
Supply Voltage
GND
GND
19
Note:
17 18
12 13 14 15 16
Pin 1 is marked for orientation.
16492D-7
Note
1
16L8
I0
16R8
CLK
OE
O1
16R6
CLK
OE
I/O1
O2
16R4
CLK
OE
I/O1
I/O2
O3
2
I9
3
O1
4
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
O8
O2
5
O3
O3
6
O4
O4
O4
7
O5
O5
O5
8
O6
O6
O6
9
O7
O7
I/O7
I/O8
10
O8
I/O8
2-6
PAL16R8 Family
AMD
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
PAL 16
R
8
-5
P C
OPTIONAL PROCESSING
Blank = Standard Processing
FAMILY TYPE
PAL = Programmable Array Logic
OPERATING CONDITIONS
NUMBER OF
ARRAY INPUTS
C = Commercial (0°C to +75°C)
OUTPUT TYPE
R = Registered
PACKAGE TYPE
P = 20-Pin Plastic DIP (PD 020)
J = 20-Pin Plastic Leaded Chip
Carrier (PL 020)
28-Pin Plastic Leaded Chip
Carrier for -4 (PL 028)
D = 20-Pin Ceramic DIP (CD 020)
L
= Active-Low Combinatorial
NUMBER OF OUTPUTS
SPEED
-4 = 4.5 ns tPD
-5 = 5 ns tPD
-7 = 7.5 ns tPD
D = 10 ns tPD
VERSION
Blank = First Revision
/2 = Second Revision
Valid Combinations
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
PAL16L8
PAL16R8
-5PC, -5JC, -4JC
PC, JC, DC
PAL16R6
PAL16R4
PAL16L8-7
PAL16R8-7
PAL16R6-7
PAL16R4-7
PAL16L8D/2
PAL16R8D/2
PAL16R6D/2
PAL16R4D/2
PC, JC
2-7
PAL16R8-4/5/7, D/2 (Com’l)
AMD
ORDERING INFORMATION
Commercial Products (MMI Marking Only)
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
PAL 16
R 8 B -2 C N
FAMILY TYPE
OPTIONAL PROCESSING
PAL = Programmable Array Logic
Blank = Standard Processing
PACKAGE TYPE
NUMBER OF
ARRAY INPUTS
N
= 20-Pin Plastic DIP
(PD 020)
OUTPUT TYPE
NL = 20-Pin Plastic Leaded
Chip Carrier (PL 020)
R = Registered
L = Active-Low Combinatorial
J
= 20-Pin Ceramic DIP
(CD 020)
NUMBER OF OUTPUTS
OPERATING CONDITIONS
= Commercial (0°C to +75°C)
SPEED
C
B = Very High Speed (15 ns–35 ns tPD
)
A = High Speed (25 ns–35 ns tPD
)
POWER
Blank = Full Power (155 mA–180 mA ICC
)
-2
-4
= Half Power (80 mA–90 mA ICC)
= Quarter Power (55 mA ICC
)
Valid Combinations
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
PAL16L8
PAL16R8
PAL16R6
PAL16R4
B, B-2, A,
CN, CNL, CJ
B-4
Note: Marked with MMI logo.
2-8
PAL16R8/B/B-2/A/B-4 (Com’l)
AMD
FUNCTIONAL DESCRIPTION
Standard 20-Pin PAL Family
Registers with Feedback
Registered outputs are provided for data storage and
synchronization. Registers are composed of D-type
flip-flops that are loaded on the LOW-to-HIGH transition
of the clock input.
The standard bipolar 20-pin PAL family devices have
common electrical characteristics and programming
procedures. Four different devices are available, includ-
ing both registered and combinatorial devices. All parts
are produced with a fuse link at each input to the AND
gate array, and connections may be selectively re-
moved by applying appropriate voltages to the circuit.
Utilizing an easily-implemented programming algo-
rithm, these products can be rapidly programmed to
any customized pattern. Extra test words are pre-
programmed during manufacturing to ensure extremely
high field programming yields, and provide extra test
paths to achieve excellent parametric correlation.
Register Preload
TheregisterontheAMDmarked16R8, 16R6, and16R4
devices can be preloaded from the output pins to facili-
tate functional testing of complex state machine de-
signs. This feature allows direct loading of arbitrary
states, making it unnecessary to cycle through long test
vector sequences to reach a desired state. In addition,
transitions from illegal states can be verified by loading
illegal states and observing proper recovery.
Power-Up Reset
Pinouts
All flip-flops power-up to a logic LOW for predictable
system initialization. Outputs of the PAL16R8 Family
will be HIGH due to the active-low outputs. The VCC rise
must be monotonic and the reset delay time is 1000 ns
maximum.
The PAL16R8 Family is available in the standard 20-pin
DIP and PLCC pinouts and the PAL16R8-4 Series is
available in the new 28-pin PLCC pinout. The 28-pin
PLCC pinout gives the designer the cleanest possible
signal with only 4.5 ns delay.
The PAL16R8-4 pinout has been designed to minimize
the noise that can be generated by high-speed signals.
Because of its inherently shorter leads, the PLCC pack-
age is the best package for use in high-speed designs.
The short leads and multiple ground signals reduce the
effective lead inductance, minimizing ground bounce.
Placing the ground pins between the outputs optimizes
the ground bounce protection, and also isolates the out-
puts from each other, eliminating cross-talk. This pinout
can reduce the effective propagation delay by as much
as 20% from a standard DIP pinout. Design files for
PAL16R8-4 Series devices are written as if the device
had a standard 20-pin DIP pinout for most design soft-
ware packages.
Security Fuse
After programming and verification, a PAL16R8 Family
design can be secured by programming the security
fuse. Once programmed, this fuse defeats readback of
the internal programmed pattern by a device program-
mer, securing proprietary designs from competitors.
When the security fuse is programmed, the array will
read as if every fuse is programmed.
Quality and Testability
The PAL16R8 Family offers a very high level of built-in
quality. Extra programmable fuses provide a means of
verifying performance of all AC and DC parameters. In
addition, this verifies complete programmability and
functionality of the device to provide the highest pro-
gramming yields and post-programming functional
yields in the industry.
Variable Input/Output Pin Ratio
The registered devices have eight dedicated input lines,
and each combinatorial output is an I/O pin. The
PAL16L8 has ten dedicated input lines and six of the
eight combinatorial outputs are I/O pins. Buffers for de-
vice inputs have complementary outputs to provide
user-programmable input signal polarity. Unused input
pins should be tied to VCC or GND.
Technology
The PAL16R8-5, -7 and D/2 are fabricated with AMD’s
oxide isolated bipolar process. The array connections
are formed with highly reliable PtSi fuses. The
PAL16R8B, B-2, A and B-4 series are fabricated with
AMD’s advanced trench-isolated bipolar process. The
array connections are formed with proven TiW fuses for
reliable operation. These processes reduce parasitic
capacitances and minimum geometries to provide
higher performance.
Programmable Three-State Outputs
Each output has a three-state output buffer with three-
state control. On combinatorial outputs, a product term
controls the buffer, allowing enable and disable to be a
function of any product of device inputs or output feed-
back. The combinatorial output provides a bidirectional
I/O pin and may be configured as a dedicated input if the
output buffer is always disabled. On registered outputs,
an input pin controls the enabling of the three-state
outputs.
2-9
PAL16R8 Family
AMD
LOGIC DIAGRAM
DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts
16L8 (-4)
V
20
CC
1
I
0
(23)
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
(24)
0
O
19
8
(22)
7
8
2
I
I
I
I
1
2
3
4
GND
(25)
(21)
I/O
7
18
(20)
15
16
3
GND
(26)
(19)
17 I/O
(18)
6
23
24
4
GND
(27)
(17)
16 I/O
(16)
5
31
32
5
GND
(28)
(15)
15 I/O
(14)
V
4
CC
(1)
39
40
6
I
5
GND
(2)
(13)
I/O
3
14
(12)
47
48
7
I
6
GND
(3)
(11)
13 I/O
2
(10)
55
56
I
8
7
GND
(4)
(9)
12 O
1
(8)
63
11
(7)
I
9
I
9
8
(5)
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
10
(6)
GND
16492D-8
2-10
PAL16R8 Family
AMD
LOGIC DIAGRAM
DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts
16R8(-4)
20
V
CC
CLK
1
(23)
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
(24)
0
O
D
Q
Q
19
8
(22)
7
8
I
GND
2
(25)
1
(21)
O
7
D
Q
Q
18
(20)
15
16
GND
I
3
2
(19)
(26)
17
(18)
D
D
D
D
D
D
Q
Q
O
6
23
24
GND
I
4
3
(17)
(27)
O
5
Q
Q
16
(16)
31
32
GND
I
5
4
(15)
(28)
O
4
15
(14)
Q
Q
V
CC
(1)
39
40
GND
I
6
5
(13)
(2)
O
3
14
Q
Q
(12)
47
48
GND
I
7
6
(11)
(3)
O
2
Q
Q
13
(10)
55
56
GND
I
8
7
(9)
(4)
O
1
12
(8)
Q
Q
63
I
9
(5)
OE
11
(7)
8
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
10
(6)
GND
16492D-9
2-11
PAL16R8 Family
AMD
LOGIC DIAGRAM
DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts
16R6 (-4)
20
V
CC
CLK
1
(24)
(23)
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
0
I/O
19
8
(22)
7
8
I
2
GND
1
(25)
(21)
O
7
D
D
D
D
D
D
Q
Q
18
(20)
15
16
I
3
GND
2
(26)
(19)
17
Q
Q
O
6
(18)
23
24
GND
I
4
3
(17)
(27)
O
5
Q
Q
16
(16)
31
32
I
GND
5
4
(15)
(28)
V
O
4
15
CC
Q
Q
(1)
(14)
39
40
GND
I
6
5
(13)
(2)
O
3
14
(12)
Q
Q
47
48
I
GND
7
(3)
6
(11)
O
2
Q
Q
13
(10)
55
56
I
8
7
GND
(4)
(9)
I/O
1
12
(8)
63
I
9
OE
11
(7)
8
(5)
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
10
(6)
GND
16492D-10
2-12
PAL16R8 Family
AMD
LOGIC DIAGRAM
DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts
16R4 (-4)
20
V
CC
1
CLK
(23)
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
(24)
0
I/O
8
19
(22)
7
8
2
I
1
GND
(25)
(21)
18 I/O
(20)
7
15
16
I
3
GND
2
(19)
(26)
D
Q
Q
17
O
6
(18)
23
24
GND
4
I
3
(17)
(27)
D
Q
Q
16
O
5
(16)
31
32
GND
5
(28)
I
4
(15)
D
Q
Q
15
(14)
O
4
V
CC
(1)
39
40
GND
6
I
5
(13)
(2)
D
Q
Q
14
(12)
O
3
47
48
7
I
GND
6
(3)
(11)
13
(10)
I/O
2
55
56
8
(4)
I
GND
7
(9)
12 I/O
(8)
1
63
9
11
(7)
OE
I
8
(5)
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
GND 10
(6)
16492D-11
2-13
PAL16R8 Family
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Ambient Temperature with
Commercial (C) Devices
Power Applied . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature (TA)
Storage Temperature . . . . . . . . . . –55°C to +125°C
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to + 7.0 V
Supply Voltage (VCC
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
)
DC Input Voltage . . . . . . . . . . –1.2 V to VCC + 0.5 V
DC Input Current . . . . . . . . . . . . . –30 mA to + 5 mA
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC Output or I/O Pin
Voltage . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . 2001 V
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VIN = VIH or VIL
VCC = Min
2.4
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 24 mA
VIN = VIH or VIL
VCC = Min
0.5
V
V
V
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
VI
IIH
IIL
Input Clamp Voltage
Input HIGH Current
Input LOW Current
Maximum Input Current
IIN = –18 mA, VCC = Min
–1.2
25
V
VIN = 2.7 V, VCC = Max (Note 2)
VIN = 0.4 V, VCC = Max (Note 2)
VIN = 5.5 V, VCC = Max
µA
µA
mA
µA
–250
1
II
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 2.7 V, VCC = Max
VIN = VIH or VIL (Note 2)
100
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0.4 V, VCC = Max
–100
µA
VIN = VIH or VIL (Note 2)
ISC
ICC
Output Short-Circuit Current
Supply Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30
–130
210
mA
mA
VIN = 0 V, Outputs Open (IOUT = 0 mA)
V
CC = Max
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2-14
PAL16R8-4/5 (Com’l)
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CLK, OE
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V
8
I1–I8
5
TA = 25°C
pF
COUT
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
-5
-4
Parameter
Symbol
Min
Min
Parameter Description
(Note 3) Max (Note 3) Max Unit
tPD
Input or Feedback to Combinatorial Output
1
5
1
4.5
ns
16L8, 16R8,
16R4
tS
tH
Setup Time from Input or Feedback to Clock
Hold Time
4.5
0
4.5
0
ns
ns
tCO
Clock to Output
1
4.0
1
1
3.5
0.5
ns
tSKEWR
tWL
Skew Between Registered Outputs (Note 4)
ns
16R8, 16R6,
16R4
LOW
Clock Width
HIGH
4
4
ns
tWH
4
4
ns
External Feedback
Internal Feedback
1/(tS + tCO
)
117
125
125
125
MHz
MHz
Maximum
Frequency
(Note 5)
fMAX
1/(tS + tCF
(Note 6)
)
(fCNT
)
No Feedback
1/(tWH + tWL
)
125
1
125
1
MHz
ns
tPZX
tPXZ
tEA
OE to Output Enable
OE to Output Disable
6.5
5
6.5
5
1
1
ns
Input to Output Enable Using
Product Term Control
2
6.5
2
6.5
ns
16L8, 16R6,
16R4
tER
Input to Output Disable Using
Product Term Control
2
5
2
5
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improve-
ments may alter these values; therefore, minimum values are recommended for simulation purposes only.
4. Skew testing takes into account pattern and switching direction differences between outputs.
5. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where the frequency may be affected.
6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
2-15
PAL16R8-4/5 (Com’l)
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Ambient Temperature (TA)
Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to + 7.0 V
Supply Voltage (VCC
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
)
DC Input Voltage . . . . . . . . . . . . . . . –1.2 V to + 7.0 V
DC Input Current . . . . . . . . . . . . . . –30 mA to + 5 mA
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC Output or I/O Pin
Voltage . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VIN = VIH or VIL
CC = Min
2.4
V
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 24 mA
VIN = VIH or VIL
CC = Min
0.5
V
V
V
V
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
VI
IIH
IIL
Input Clamp Voltage
Input HIGH Current
Input LOW Current
Maximum Input Current
IIN = –18 mA, VCC = Min
–1.2
25
V
VIN = 2.7 V, VCC = Max (Note 2)
VIN = 0.4 V, VCC = Max (Note 2)
VIN = 5.5 V, VCC = Max
µA
µA
mA
µA
–250
1
II
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 2.7 V, VCC = Max
VIN = VIH or VIL (Note 2)
100
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0.4 V, VCC = Max
–100
µA
VIN = VIH or VIL (Note 2)
ISC
ICC
Output Short-Circuit Current
Supply Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30
–130
180
mA
mA
VIN = 0 V, Outputs Open (IOUT = 0 mA)
VCC = Max
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2-16
PAL16R8-7 (Com’l)
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
VIN = 2.0 V
Typ
5
Unit
pF
CIN
Input Capacitance
Output Capacitance
VCC = 5.0 V
TA = 25°C
f = 1 MHz
COUT
VOUT = 2.0 V
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Min
Parameter Description
(Note 3)
Max
7.5
7
Unit
16L8, 16R6,
16R4
3
3
Input or Feedback to
Combinatorial Output
tPD
ns
1 Output Switching
tS
tH
Setup Time from Input or Feedback to Clock
Hold Time
7
0
1
ns
ns
tCO
tSKEW
tWL
tWH
Clock to Output
6.5
1
ns
Skew Between Registered Outputs (Note 4)
16R8, 16R6,
16R4
ns
LOW
5
5
ns
Clock Width
HIGH
ns
External Feedback
1/(tS + tCO
)
74
100
MHz
MHz
Maximum
Frequency
(Note 5)
fMAX
Internal Feedback
1/(tS + tCF
(Note 6)
)
(fCNT
)
No Feedback
1/(tWH + tWL
)
100
1
MHz
ns
tPZX
tPXZ
tEA
OE to Output Enable
OE to Output Disable
8
8
1
ns
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
16L8, 16R6,
16R4
3
10
10
ns
tER
3
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improve-
ments may alter these values; therefore, minimum values are recommended for simulation purposes only.
4. Skew is measured with all outputs switching in the same direction.
5. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where the frequency may be affected.
6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
2-17
PAL16R8-7 (Com’l)
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Ambient Temperature (TA)
Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to + 7.0 V
Supply Voltage (VCC
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
)
DC Input Voltage . . . . . . . . . . . . . . . –1.5 V to + 5.5 V
DC Output or I/O Pin Voltage . . . . . –0.5 V to + 5.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VIN = VIH or VIL
VCC = Min
2.4
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 24 mA
VIN = VIH or VIL
0.5
V
V
V
VCC = Min
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
VI
IIH
IIL
Input Clamp Voltage
Input HIGH Current
Input LOW Current
Maximum Input Current
IIN = –18 mA, VCC = Min
–1.5
25
V
VIN = 2.4 V, VCC = Max (Note 2)
VIN = 0.4 V, VCC = Max (Note 2)
VIN = 5.5 V, VCC = Max
µA
µA
µA
µA
–250
100
100
II
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 2.4 V, VCC = Max
V
IN = VIH or VIL (Note 2)
VOUT = 0.4 V, VCC = Max
IN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
–100
µA
V
ISC
ICC
Output Short-Circuit Current
Supply Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30
–130
180
mA
mA
VIN = 0 V, Outputs Open (IOUT = 0 mA)
V
CC = Max
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-18
PAL16R8D/2 (Com’l)
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V
TA = 25°C
f = 1 MHz
5
8
pF
COUT
Output Capacitance
VOUT = 2.0 V
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Min
(Note 3)
Parameter Description
Max
Unit
tPD
Input or Feedback to Combinatorial Output
16L8, 16R6,
16R4
3
10
ns
tS
tH
Setup Time from Input or Feedback to Clock
Hold Time
10
0
ns
ns
tCO
tWL
tWH
Clock to Output
3
7
ns
Clock Width
LOW
8
ns
HIGH
16R8, 16R6,
16R4
8
ns
External Feedback
1/(tS + tCO
)
58.8
60
MHz
MHz
Maximum
Frequency
(Note 4)
fMAX
Internal Feedback
1/(tS + tCF
(Note 5)
)
(fCNT
)
No Feedback
1/(tWH + tWL
)
62.5
MHz
ns
tPZX
tPXZ
OE to Output Enable
OE to Output Disable
2
2
3
3
10
10
10
10
ns
tEA
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
16L8, 16R6,
16R4
ns
tER
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improve-
ments may alter these values; therefore, minimum values are recommended for simulation purposes only.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where the frequency may be affected.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
2-19
PAL16R8D/2 (Com’l)
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Ambient Temperature (TA)
Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
)
DC Input Voltage . . . . . . . . . . . –1.5 V to VCC + 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC Output or I/O Pin
Voltage . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VIN = VIH or VIL
VCC = Min
2.4
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 24 mA
VIN = VIH or VIL
0.5
V
V
V
VCC = Min
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
VI
IIH
IIL
Input Clamp Voltage
Input HIGH Current
Input LOW Current
Maximum Input Current
IIN = –18 mA, VCC = Min
–1.2
V
25
VIN = 2.4 V, VCC = Max (Note 2)
VIN = 0.4 V, VCC = Max (Note 2)
VIN = 5.5 V, VCC = Max
µA
µA
µA
µA
–250
100
100
II
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 2.4 V, VCC = Max
V
IN = VIH or VIL (Note 2)
VOUT = 0.4 V, VCC = Max
IN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
–100
µA
V
ISC
ICC
Output Short-Circuit Current
Supply Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30
–130
180
mA
mA
VIN = 0 V, Outputs Open (IOUT = 0 mA)
V
CC = Max
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-20
PAL16R8B (Com’l)
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V
TA = 25°C
f = 1 MHz
8
pF
COUT
Output Capacitance
VOUT = 2.0 V
9
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
Max
Unit
tPD
Input or Feedback to Combinatorial Output
16L8, 16R6,
16R4
15
ns
tS
tH
Setup Time from Input or Feedback to Clock
Hold Time
15
0
ns
ns
tCO
tWL
tWH
Clock to Output or Feedback
12
ns
Clock Width
LOW
10
10
37
ns
16R8, 16R6,
16R4
HIGH
ns
Maximum
Frequency
(Note 3)
External Feedback
1/(tS + tCO
)
MHz
fMAX
No Feedback
1/(tWH + tWL
)
50
MHz
ns
tPZX
tPXZ
tEA
OE to Output Enable
OE to Output Disable
15
15
15
15
ns
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
ns
16R8, 16R6,
16R4
tER
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2-21
PAL16R8B (Com’l)
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Ambient Temperature (TA)
Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
)
DC Input Voltage . . . . . . . . . . . –1.5 V to VCC + 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC Output or I/O Pin
Voltage . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VIN = VIH or VIL
CC = Min
2.4
V
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 24 mA
VIN = VIH or VIL
CC = Min
0.5
V
V
V
V
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
VI
IIH
IIL
Input Clamp Voltage
Input HIGH Current
Input LOW Current
Maximum Input Current
IIN = –18 mA, VCC = Min
–1.2
25
V
VIN = 2.7 V, VCC = Max (Note 2)
VIN = 0.4 V, VCC = Max (Note 2)
VIN = 5.5 V, VCC = Max
µA
µA
µA
µA
–100
100
100
II
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 2.7 V, VCC = Max
VIN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0.4 V, VCC = Max
VIN = VIH or VIL (Note 2)
–100
µA
ISC
ICC
Output Short-Circuit Current
Supply Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30
–130
90
mA
mA
VIN = 0 V, Outputs Open (IOUT = 0 mA)
VCC = Max
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2-22
PAL16R8B-2 (Com’l)
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V
7
TA = 25°C
pF
COUT
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
7
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
Max
Unit
tPD
Input or Feedback to Combinatorial Output
16L8, 16R6,
16R4
25
ns
tS
tH
Setup Time from Input or Feedback to Clock
Hold Time
25
0
ns
ns
ns
ns
tCO
tWL
tWH
Clock to Output
15
Clock Width
LOW
15
16R8, 16R6,
16R4
HIGH
15
25
ns
External Feedback
1/(tS + tCO
)
MHz
MHz
Maximum
Frequency
(Note 4)
fMAX
Internal Feedback
1/(tS + tCF
(Note 5)
)
28.5
(fCNT
)
No Feedback
1/(tWH + tWL
)
33
MHz
ns
tPZX
tPXZ
tEA
OE to Output Enable
OE to Output Disable
20
20
25
25
ns
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
ns
16R8, 16R6,
16R4
tER
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. Calculated from measured fMAX internal.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
2-23
PAL16R8B-2 (Com’l)
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Ambient Temperature (TA)
Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to + 7.0 V
Supply Voltage (VCC
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
)
DC Input Voltage . . . . . . . . . . . –1.5 V to VCC + 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC Output or I/O Pin
Voltage . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VIN = VIH or VIL
VCC = Min
2.4
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 24 mA
VIN = VIH or VIL
0.5
V
V
V
VCC = Min
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
VI
IIH
IIL
Input Clamp Voltage
Input HIGH Current
Input LOW Current
Maximum Input Current
IIN = –18 mA, VCC = Min
–1.2
25
V
VIN = 2.7 V, VCC = Max (Note 2)
VIN = 0.4 V, VCC = Max (Note 2)
VIN = 5.5 V, VCC = Max
µA
µA
µA
µA
–250
100
100
II
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 2.7 V, VCC = Max
VIN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0.4 V, VCC = Max
VIN = VIH or VIL (Note 2)
–100
–130
µA
ISC
ICC
Notes:
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30
mA
mA
16L8
16R8/6/4
VIN = 0 V, Outputs Open (IOUT = 0 mA)
VCC = Max
155
180
Supply Current
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VCC = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2-24
PAL16R8A (Com’l)
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
pF
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V
TA = 25°C
f = 1 MHz
7
COUT
Output Capacitance
VOUT = 2.0 V
7
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
Max
Unit
tPD
Input or Feedback to Combinatorial Output
16L8, 16R6,
16R4
25
ns
tS
tH
Setup Time from Input or Feedback to Clock
Hold Time
25
0
ns
ns
tCO
tWL
tWH
Clock to Output
15
ns
Clock Width
LOW
15
15
ns
HIGH
ns
16R8, 16R6,
16R4
External Feedback
1/(tS + tCO
)
25
MHz
MHz
Maximum
Frequency
(Note 4)
fMAX
Internal Feedback
1/(tS + tCF
(Note 5)
)
28.5
(fCNT
)
No Feedback
1/(tWH + tWL
)
33
MHz
ns
tPZX
tPXZ
tEA
OE to Output Enable
OE to Output Disable
20
20
25
25
ns
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
ns
16R8, 16R6,
16R4
tER
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. Calculated from measured fMAX internal.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
2-25
PAL16R8A (Com’l)
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Ambient Temperature (TA)
Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
)
DC Input Voltage . . . . . . . . . . . . . . . –1.5 V to +5.5 V
DC Output or I/O Pin Voltage . . . . . . . . . . . . . . 5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –1 mA
VIN = VIH or VIL
CC = Min
2.4
V
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 8 mA
VIN = VIH or VIL
CC = Min
0.5
V
V
V
V
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
VI
IIH
IIL
Input Clamp Voltage
Input HIGH Current
Input LOW Current
Maximum Input Current
IIN = –18 mA, VCC = Min
–1.5
25
V
VIN = 2.4 V, VCC = Max (Note 2)
VIN = 0.4 V, VCC = Max (Note 2)
VIN = 5.5 V, VCC = Max
µA
µA
µA
µA
–250
100
100
II
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 2.4 V, VCC = Max
VIN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0.4 V, VCC = Max
VIN = VIH or VIL (Note 2)
–100
µA
ISC
ICC
Output Short-Circuit Current
Supply Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30
–250
55
mA
mA
VIN = 0 V, Outputs Open (IOUT = 0 mA)
V
CC = Max
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V as been chosen to avoid test problems caused by tester ground degradation.
2-26
PAL16R8B-4 (Com’l)
AMD
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
Parameter
Symbol
Parameter Description
Min
Max
Unit
tPD
Input or Feedback to Combinatorial Output
16L8, 16R6,
16R4
35
ns
tS
tH
Setup Time from Input or Feedback to Clock
Hold Time
35
0
ns
ns
tCO
tWL
tWH
Clock to Output or Feedback
16R8, 16R6,
16R4
25
ns
Clock Width
LOW
25
25
16
ns
HIGH
ns
Maximum
Frequency
(Note 2)
External Feedback
1/(tS + tCO
)
MHz
fMAX
No Feedback
1/(tWH + tWL
)
20
MHz
ns
tPZX
tPXZ
tEA
OE to Output Enable
OE to Output Disable
25
25
35
35
ns
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
16L8, 16R6,
16R4
ns
tER
ns
Notes:
1. See Switching Test Circuit for test conditions.
2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
2-27
PAL16R8B-4 (Com’l)
AMD
SWITCHING WAVEFORMS
Input or
Feedback
VT
tH
tS
Input or
Feedback
VT
VT
tCO
Clock
tPD
Combinatorial
Output
Registered
Output
VT
VT
16492D-13
16492D-12
Combinatorial Output
Registered Output
Clock
Registered
Output 1
VT
tWH
tSKEWR
VT
Clock
Registered
Output 2
VT
tWL
16492D-14
16492D-15
Registered Output Skew
Clock Width
VT
VT
Input
OE
tER
tEA
tPXZ
tPZX
VT
VOH – 0.5V
VT
VOH – 0.5V
VOL + 0.5V
Output
Output
VOL + 0.5V
16492D-16
16492D-17
Input to Output Disable/Enable
OE to Output Disable/Enable
Notes:
1. VT = 1.5 V
2. Input pulse amplitude 0 V to 3.0 V
3. Input rise and fall times 2 ns–3 ns typical.
2-28
PAL16R8 Family
AMD
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
5 V
S1
R1
Output
Test Point
R2
CL
16492D-18
Commercial
Measured
Specification
PD, tCO
PZX, tEA
S1
CL
R1
R2
Output Value
t
Closed
All but B-4:
Allbut B-4:
1.5 V
t
Z → H: Open
Z → L: Closed
50 pF
5 pF
200 Ω
390 Ω
1.5 V
tPXZ, tER
H → Z: Open
L → Z: Closed
B-4:
B-4:
H → Z: VOH – 0.5 V
L → Z: VOL + 0.5 V
800 Ω
1.56 kΩ
2-29
PAL16R8 Family
AMD
MEASURED SWITCHING CHARACTERISTICS for the PAL16R8-5
VCC = 4.75 V, TA = 75°C (Note 1)
5.0
–5
4.5
4.0
tPD, ns
3.5
3.0
1
2
3
4
5
6
7
8
Number of Outputs Switching
16492D-19
tPD vs. Number of Outputs Switching
10
8
6
4
2
tPD, ns
–5
0
50
100
150
200
250
CL, pF
16492D-20
tPD vs. Load Capacitance
CC = 5.25 V, TA = 25°C
V
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where tPD may be affected.
2-30
PAL16R8-5
AMD
CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS for the PAL16R8-4/5
VCC = 5.0 V, TA = 25°C
IOL, mA
15
10
5
V
OL, V
–0.6 –0.4 –0.2
–5
0.2 0.4 0.6
–10
–15
16492D-21
Output, LOW
IOH, mA
20
VOH, V
–3 –2 –1
1
2
3
–20
–40
–60
–80
–90
16492D-22
Output, HIGH
II, µA
20
1
2
3
VI, V
–3 –2 –1
–50
–100
–150
–200
16492D-23
Input
2-31
PAL16R8-5
AMD
MEASURED SWITCHING CHARACTERISTICS for the PAL16R8-7
VCC = 4.75 V, TA = 75°C (Note 1)
7.5
7
tPD, ns
6.5
6
1
2
3
4
5
6
7
8
NUMBER OF OUTPUTS SWITCHING
16492D-24
tPD vs. Number of Outputs Switching
8
7
tPD, ns
6
5
10
30
50
70
90
110
CL, pF
16492D-25
tPD vs. Load Capacitance
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where tPD may be affected.
2-32
PAL16R8-7
AMD
CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS for the PAL16R8-7
VCC = 5.0 V, TA = 25°C
IOL, mA
15
10
5
V
OL, V
–0.6 –0.4 –0.2
–5
0.2 0.4 0.6
–10
–15
16492D-26
Output, LOW
IOH, mA
20
VOH, V
–3 –2 –1
1
2
3
–20
–40
–60
–80
16492D-27
Output, HIGH
II, µA
20
1
2
3
VI, V
–3 –2 –1
–20
–40
–60
–80
16492D-28
Input
2-33
PAL16R8-7
AMD
INPUT/OUTPUT EQUIVALENT SCHEMATICS
V
CC
Input
Program/Verify
Circuitry
16492D-29
Typical Input
V
CC
40 Ω NOM
Output
Input,
I/O
Pins
Program/Verify/
Test Circuitry
Preload
Circuitry
16492D-30
Typical Output
PAL16R8-5
2-34
AMD
VCC can rise to its steady state, two conditions are
required to ensure a valid power-up reset. These condi-
tions are:
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
The output state will be HIGH due to the inverting output
buffer. This feature is valuable in simplifying state
machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous opera-
tion of the power-up reset and the wide range of ways
■ The VCC rise must be monotonic.
■ Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and feed-
back setup times are met.
Parameter
Symbol
Parameter Description
Max
Unit
tPR
Power-Up Reset Time
1000
ns
tS
Input or Feedback Setup Time
Clock Width LOW
See Switching
Characteristics
tWL
VCC
4 V
Power
tPR
Registered
Active-Low
Output
tS
Clock
tWL
16492D-31
Power-Up Reset Waveform
2-35
PAL16R8 Family
相关型号：
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