PALCE20V8Q-10JI4 [AMD]
EE CMOS 24-Pin Universal Programmable Array Logic; EE CMOS 24引脚通用可编程阵列逻辑
| 型号： | PALCE20V8Q-10JI4 |
| 厂家： | 
AMD |
| 描述： | EE CMOS 24-Pin Universal Programmable Array Logic |
| 文件： | 总16页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-15/25, Q-20/25
Advanced
Micro
PALCE20V8 Family
EE CMOS 24-Pin Universal Programmable Array Logic
Devices
DISTINCTIVE CHARACTERISTICS
■ Pin and function compatible with all GAL
20V8/As
■ Peripheral Component Interconnect (PCI)
compliant
■ Electrically erasable CMOS technology pro-
vides reconfigurable logic and full testability
■ High-speed CMOS technology
— 5-ns propagation delay for “-5” version
■ Preloadable output registers for testability
■ Automatic register reset on power-up
■ Cost-effective 24-pin plastic SKINNYDIP and
28-pin PLCC packages
■ Extensive third-party software and programmer
support through FusionPLD partners
■ Fully tested for 100% programming and func-
tional yields and high reliability
■ Programmable output polarity
■ 5-ns version utilizes a split leadframe for
improved performance
— 7.5-ns propagation delay for “-7” version
■ Direct plug-in replacement for a wide range of
24-pin PAL devices
■ Programmable enable/disable control
■ Outputs individually programmable as
registered or combinatorial
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. Its macrocells provide a universal device
architecture. The PALCE20V8 is fully compatible with
the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa-
tions are programmed into the device through floating-
gate cells in the AND logic array that can be erased
electrically.
Devicelogicisautomaticallyconfiguredaccordingtothe
user’s design specification. A design is implemented
using any of a number of popular design software pack-
ages, allowing automatic creation of a programming file
based on Boolean or state equations. Design software
also verifies the design and can provide test vectors for
the finished device. Programming can be accomplished
on standard PAL device programmers.
The fixed OR array allows up to eight data product terms
per output for logic functions. The sum ofthese products
feeds the output macrocell. Each macrocell can be
programmed as registered or combinatorial with an
active-high or active-low output. The output configura-
tion is determined by two global bits and one local bit
controlling four multiplexers in each macrocell.
The PALCE20V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
I1 – I10
CLK/I0
BLOCK DIAGRAM
10
Programmable AND Array
40 x 64
Input
Mux.
Input
Mux.
MACRO
MC0
MACRO
MC1
MACRO
MC2
MACRO
MC3
MACRO
MC4
MACRO
MC5
MACRO
MC6
MACRO
MC7
I/O6
OE/I11 I12
I/O0
I/O1
I/O2
I/O4
I/O4
I/O7
I13
I/O5
16491D-1
Publication# 16491 Rev. D Amendment/0
Issue Date: February 1996
2-155
AMD
CONNECTION DIAGRAMS
(Top View)
SKINNYDIP
PLCC/LCC
1
2
3
4
5
6
24
23
22
21
20
19
CLK/I0
VCC
I1
I2
I13
4
3 2 1 28 27 26
I/O7
I/O
I/O
I/O
I
I
I
5
6
7
25
24
6
5
4
3
4
5
I3
I4
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
I12
23
22
NC
NC
I5
I6
8
I
I/O
21
20
19
9
6
3
7
8
18
17
I/O
I
10
2
1
7
I7
I8
I/O
I
11
8
9
16
15
14
13
12
13 14 15 16
18
17
10
11
12
I9
I10
GND
OE/I11
16491D-3
16491D-2
Note:
Pin 1 is marked for orientation.
PIN DESIGNATIONS
CLK = Clock
GND = Ground
I
= Input
I/O
NC
OE
VCC
= Input/Output
= No Connect
= Output Enable
= Supply Voltage
2-156
PALCE20V8 Family
AMD
ORDERING INFORMATION
Commercial and Industrial Products
AMD programmable logic products for commercial and industrial applications are available with several ordering options. The
order number (Valid Combination) is formed by a combination of:
PAL CE 20 V 8 H -5 P C /5
FAMILY TYPE
PAL = Programmable Array Logic
PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
TECHNOLOGY
CE = CMOS Electrically Erasable
/4
/5
= First Revision
Second Revision
(Same algorithm as /4)
NUMBER OF ARRAY INPUTS
OPERATING CONDITIONS
C = Commercial (0°C to +75°C)
OUTPUT TYPE
V = Versatile
I
= Industrial (–40°C to +85°C)
NUMBER OF FLIP-FLOPS
POWER
H = Half Power (90-125 mA ICC
Q = Quarter Power (55 mA ICC
PACKAGE TYPE
P = 24-Pin 300 mil Plastic
SKINNYDIP (PD3024)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)
)
)
SPEED
-5 = 5 ns tPD
-7 = 7.5 ns tPD
-10 = 10 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
-25 = 25 ns tPD
Valid Combinations
Valid Combinations
Valid Combinations lists configurations planned to
be supported in volume for this device. Consult the
local AMD sales office to confirm availability of spe-
cific valid combinations and to check on newly re-
leased combinations.
PALCE20V8H-5
JC
/5
PALCE20V8H-7
PALCE20V8H-10
PALCE20V8Q-10
PALCE20V8H-15
PALCE20V8Q-15
PALCE20V8Q-20
PALCE20V8H-25
PALCE20V8Q-25
Blank, /4
/5
PC, JC
PC, JC, PI, JI
PC, JC
Blank,
/4
PI, JI
PC, JC, PI, JI
PALCE20V8H-5/7/10/15/25, Q-10/15/25 (Com’l)
PALCE20V8H-15/25, Q-20/25 (Ind)
2-157
AMD
specification is processed by development software to
verify the design and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user’s desired function.
FUNCTIONAL DESCRIPTION
The PALCE20V8 is a universal PAL device. It has eight
independently configurable macrocells (MC0..MC7).
Each macrocell can be configured as a registered out-
put, combinatorial output, combinatorial I/O, or dedi-
cated input. The programming matrix implements a
programmable AND logic array, which drives a fixed OR
logic array. Buffers for device inputs have complemen-
tary outputs to provide user-programmable input signal
polarity. Pins 1 and 13 serve either as array inputs or as
clock (CLK) and output enable (OE) for all flip-flops.
The user is given two design options with the
PALCE20V8. First, it can be programmed as an emu-
lated PAL device. This includes the PAL20R8 series
and most 24-pin combinatorial PAL devices. The PAL
device programmer manufacturer will supply device
codes for the standard PAL architectures to be used
with the PALCE20V8. The programmer will program the
PALCE20V8 to the corresponding PAL device architec-
ture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to
them. Alternatively, the device can be programmed
directly as a PALCE20V8. Here the user must use the
PALCE20V8 device code. This option provides full utili-
zation of the macrocells, allowing non-standard archi-
tectures to be built.
Unused input pins should be tied directly to VCC or GND.
Product terms with all bits unprogrammed (discon-
nected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical LOW state.
The programmable functions on the PALCE20V8 are
automatically configured from the user’s design specifi-
cation, which can be in a number of formats. The design
To
Adjacent
Macrocell
1 1
OE
VCC
1 0
0 0
0 1
1 1
0 X
1 0
SL0X
SG1
1 1
0 X
I/OX
D
Q
1 0
SL1X
CLK
Q
1 0
1 1
0 X
From
Adjacent
Pin
SL0X
*SG1
16491D-4
* In Macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.
Figure 1. PALCE20V8 Macrocell
2-158
PALCE20V8 Family
AMD
Configuration Options
Dedicated Output in a Non-Registered
Device
Each macrocell can be configured as one of the follow-
ing: registered output, combinatorial output, combinato-
rial I/O or dedicated input. In the registered output
configuration, theoutputbufferisenabledbytheOE pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, the buffer is always dis-
abled. A macrocell configured as a dedicated input de-
rives the input signal from an adjacent I/O.
The control settings are SG0 = 1, SG1 = 0, and SL0x = 0.
All eight product terms are available to the OR gate. Al-
though the macrocell is a dedicated output, the feed-
back is used, with the exception of pins 18(21) and
19(23). Pins 18(21) and 19(23) do not use feedback in
this mode.
Dedicated Input in a Non-Registered
Device
The macrocell configurations are controlled by the con-
figuration control word. It contains 2 global bits (SG0
andSG1)and16localbits(SL00 throughSL07 andSL10
through SL17). SG0 determines whether registers will
be allowed. SG1 determines whether the PALCE20V8
will emulate a PAL20R8 family or a combinatorial de-
vice. Within each macrocell, SL0x, in conjunction with
SG1, selects the configuration of the macrocell and
SL1x sets the output as either active low or active high.
The control bit settings are SG0 = 1, SG1 = 0 and SL0x =
1. The output buffer is disabled. The feedback signal is
an adjacent I/O pin.
Combinatorial I/O in a Non-Registered
Device
The control settings are SG0 = 1, SG1 = 1, and SL0x = 1.
Only seven product terms are available to the OR gate.
The eighth product term is used to enable the output
buffer. The signal at the I/O pin is fed back to the AND
array via the feedback multiplexer. This allows the pin to
be used as an input.
The configuration bits work by acting as control inputs
for the multiplexers in the macrocell. There are four mul-
tiplexers: a product term input, an enable select, an out-
put select, and a feedback select multiplexer. SG1 and
SL0x are the control signals for all four multiplexers. In
MC0 and MC7, SG0 replaces SG1 on the feedback
multiplexer.
Combinatorial I/O in a Registered Device
The control bit settings are SG0=0,SG1=1 and SL0x =1.
Only seven product terms are available to the OR gate.
The eighth product term is used as the output enable.
The feedback signal is the corresponding I/O signal.
These configurations are summarized in table 1 and il-
lustrated in figure 2.
If the PALCE20V8 is configured as a combinatorial de-
vice, the CLK and OE pins may be available as inputs to
the array. If the device is configured with registers, the
CLK and OE pins cannot be used as data inputs.
Table 1. Macrocell Configurations
SG0 SG1 SL0x Cell Configuration Devices Emulated
Device has registers
Registered Output Configuration
0
1
0
Registered
Output
Combinatorial I/O PAL20R6, 20R4
PAL20R8, 20R6,
20R4
The control bit settings are SG0 = 0, SG1 = 1 and SL0x =
0. There is only one registered configuration. All eight
product terms are available as inputs to the OR gate.
Data polarity is determined by SL1x. SL1x is an input to
the exclusive-OR gate which is the D input to the flip-
flop. SL1x is programmed as 1 for inverted output or 0
for non-inverted output. The flip-flop is loaded on the
LOW-to-HIGH transition of CLK. The feedback path is
from Q on the register. The output buffer is enabled by
OE.
0
1
1
Device has no registers
1
1
1
0
0
1
0
1
1
Combinatorial
Output
Dedicated Input
PAL20L2,
18L4,16L6,14L8
PAL20L2,18L4,
16L6
Combinatorial I/O PAL20L8
Programmable Output Polarity
Combinatorial Configurations
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
The PALCE20V8 has three combinatorial output con-
figurations: dedicated output in a non-registered device,
I/O in a non-registered device and I/O in a registered
device.
Selection is made through a programmable bit SL1x
which controls an exclusive-OR gate at the output of the
AND/OR logic. The output is active high if SL1x is a 0
and active low if SL1x is a 1.
PALCE20V8 Family
2-159
AMD
OE
OE
D
Q
D
Q
Q
Q
CLK
CLK
Registered Active Low
Registered Active High
Combinatorial I/O Active Low
Combinatorial I/O Active High
VCC
VCC
Note 1
Note 1
Combinatorial Output Active Low
Combinatorial Output Active High
Notes:
Note 2
1. Feedback is not available on pins 18 (21)
and 19 (23) in the combinatorial output mode.
2. This macrocell configuration is not available on
pins 18 (21) and 19 (23).
Adjacent I/O pin
Dedicated Input
16491D-5
Figure 2. Macrocell Configurations
PALCE20V8 Family
2-160
AMD
Power-Up Reset
Programming and Erasing
All flip-flops power up to a logic LOW for predictable sys-
teminitialization. OutputsofthePALCE20V8dependon
whether they are selected as registered or combinato-
rial. If registered is selected, the output will be HIGH. If
combinatorial is selected, the output will be a function of
the logic.
The PALCE20V8 can be programmed on standard logic
programmers. It also may be erased to reset a previ-
ously configured device back to its virgin state. Erasure
is automatically performed by the programming hard-
ware. No special erase operation is required.
Quality and Testability
Register Preload
The PALCE20V8 offers a very high level of built-in qual-
ity. The erasability of the device provides a direct means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest pro-
gramming and post-programming functional yields in
the industry.
The register on the PALCE20V8 can be preloaded from
the output pins to facilitate functional testing of complex
state machine designs. This feature allows direct load-
ing of arbitrary states, making it unnecessary to cycle
through long test vector sequences to reach a desired
state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper
recovery.
Technology
The high-speed PALCE20V8H is fabricated with AMD’s
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
Security Bit
A security bit is provided on the PALCE20V8 as a deter-
rent to unauthorized copying of the array configuration
patterns. Once programmed, this bit defeats readback
and verification of the programmed pattern by a device
programmer, securing proprietary designs from com-
petitors. The bit can only be erased in conjunction with
the array during an erase cycle.
PCI Compliance
The PALCE20V8H-7/10 is fully compliant with the PCI
Local Bus Specification published by the PCI Special In-
terestGroup. ThePALCE20V8H-7/10’spredictabletim-
ing ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD
and FPGA architectures without predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
Electronic Signature Word
An electronic signature word is provided in the
PALCE20V8. It consists of 64 bits of programmable
memory that can contain any user-defined data. The
signature data is always available to the user independ-
ent of the security bit.
PALCE20V8 Family
2-161
AMD
LOGIC DIAGRAM
SKINNYDIP (PLCC and LCC) Pinouts
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31 32 35 36 39
24
V
CC
CLK/I
1
(2)
(28)
0
1
0
23
(27)
I
I
13
2
(3)
1
SG0
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL0
SL0
SL0
7
0
7
SG1
1 1
0 X
I/O
22
(26)
7
D
Q
Q
1 0
1 0
1 1
0 X
I
3
(4)
2
3
4
SG0
SL0
SL0
SL0
7
6
5
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
6
8
SG1
1 1
0 X
21 I/O
(25)
6
D
Q
Q
1 0
15
1 0
1 1
0 X
I
4
(5)
SG1
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
5
16
23
SG1
1 1
0 X
I/O
5
20
(24)
D
Q
Q
1 0
1 0
1 1
0 X
I
5
(6)
SG1
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL0
4
24
31
SG1
1 1
0 X
I/O
(23)
19
4
D
Q
Q
1 0
1 0
1 1
0 X
I
6
(7)
5
SG1
SL0
4
0
3
4
7
8
11 12 15 16 19 20
24 27 28 31 32 35 36 39
23
CLK OE
16491D-6
2-162
PALCE20V8 Family
AMD
LOGIC DIAGRAM (continued)
SKINNYDIP (PLCC and LCC) Pinouts
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31 32 35 36 39
CLK OE
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL0
3
32
39
SG1
1 1
0 X
18
(21)
I/O
3
2
1
D
Q
Q
1 0
1 0
1 1
0 X
I
7
(9)
6
SG1
SL0
3
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL0
2
40
47
SG1
1 1
0 X
I/O
17
(20)
D
Q
Q
1 0
1 0
1 1
0 X
I
8
(10)
7
SG1
SL0
2
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL0
1
48
55
SG1
1 1
0 X
I/O
16
(19)
D
Q
Q
1 0
1 0
1 1
0 X
I
8
9
(11)
SL0
SG1
1
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL0
0
56
63
SG1
1 1
0 X
I/O
(18)
15
0
D
Q
Q
1 0
1 0
1 1
0 X
I
10
(12)
9
SL0
0
SG0
14
(17)
I
0
1
12
11
(13)
10
SG0
13 OE/I
(16)
11
39
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31 32 35 36
16491D-6
(concluded)
PALCE20V8 Family
2-163
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
Temperature (TA) Operating
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
)
DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = 0°C to +75°C) . . . . . . . . . . . . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VCC = Min
VIN = VIH or VIL
2.4
V
VOL
Output LOW Voltage
IOL = 24 mA
VCC = Min
VIN = VIH or VIL
0.5
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
V
V
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
IIH
IIL
Input HIGH Leakage Current
Input LOW Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
VIN = 0 V, VCC = Max (Note 2)
10
–100
10
µA
µA
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–100
–150
µA
ISC
ICC
Output Short-Circuit Current
Supply Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30
mA
mA
Outputs Open (IOUT = 0 mA)
VCC = Max, f = 15 MHz
90
55
H
Q
Notes:
1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-172
PALCE20V8H-15/25 Q-15/25 (Com’l)
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
5
Unit
CIN
Input Capacitance
Output Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C,
pF
pF
COUT
VOUT = 2.0 V f = 1 MHz
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
-15
-25
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Unit
tPD
tS
Input or Feedback to Combinatorial Output
15
25
ns
Setup Time from Input or Feedback to Clock
Hold Time
12
0
15
0
ns
ns
ns
ns
tH
tCO
tWL
tWH
Clock to Output
10
12
LOW
Clock Width
HIGH
8
12
8
12
37
ns
External Feedback
1/(tS + tCO)
45.5
50
MHz
MHz
MHz
Maximum
Frequency
(Note 3)
fMAX
Internal Feedback (fCNT) 1/(tS + tCF) (Note 4)
40
No Feedback
1/(tWH + tWL)
62.5
41.6
tPZX
tPXZ
tEA
OE to Output Enable
OE to Output Disable
15
15
15
15
20
20
25
25
ns
ns
ns
ns
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
tER
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
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PALCE20V8H-15/25 Q-15/25 (Com’l)
AMD
SWITCHING WAVEFORMS
Input or
Feedback
VT
tS
tH
Input or
Feedback
VT
VT
tCO
Clock
tPD
Registered
Output
Combinatorial
Output
VT
16491D-7
VT
16491D-8
Combinatorial Output
Registered Output
tWH
VT
Input
VT
tER
tEA
VT
16491D-10
Clock
VOH - 0.5V
VOL + 0.5V
Output
tWL
16491D-9
Clock Width
Input to Output Disable/Enable
VT
OE
tPXZ
tPZX
VT
VOH - 0.5V
VOL + 0.5V
Output
16491D-11
OE to Output Disable/Enable
Notes:
1. VT = 1.5 V
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns – 5 ns typical.
2-176
PALCE20V8 Family
AMD
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
5 V
S1
R1
Output
R2
CL
16491D-12
Switching Test Circuit
Commercial
Measured
Specification
PD, tCO
PZX, tEA
S1
CL
R1
R2
Output Value
t
Closed
1.5 V
t
Z → H: Open
Z → L: Closed
50 pF
5 pF
200 Ω
390 Ω
1.5 V
tPXZ, tER
H → Z: Open
L → Z: Closed
H-5:
H → Z: VOH – 0.5 V
L → Z: VOL + 0.5 V
200 Ω
PALCE20V8 Family
2-177
AMD
TYPICAL ICC CHARACTERISTICS
VCC = 5.0 V, TA = 25°C
150
125
100
20V8H-5
20V8H-7
ICC (mA)
75
50
25
0
20V8H-10
20V8H-15/25
20V8Q-10
20V8Q-15/25
0
10
20
30
40
50
16491D-13
Frequency (MHz)
ICC vs. Frequency
The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and
the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any
vector, half of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to
estimate the ICC requirements for a particular design.
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PALCE20V8 Family
AMD
uses an EE cell to replace the fuse link used in bipolar
parts. As a result, the device can be erased and
reprogrammed—a feature which allows 100% testing at
the factory.
ENDURANCE CHARACTERISTICS
The PALCE20V8 is manufactured using AMD’s ad-
vanced electrically erasable process. This technology
Endurance Characteristics
Symbol Parameter
tDR Min Pattern Data Retention Time
Test Conditions
Min
Unit
Max Storage Temperature
10
20
Years
Years
Cycles
Max Operating Temperature
Normal Programming Conditions
N
Min Reprogramming Cycles
100
PALCE20V8 Family
2-179
AMD
Due to the synchronous operation of the power-up reset
and the wide range of ways VCC can rise to its steady
state, two conditions are required to insure a valid
power-up reset. These conditions are:
POWER-UP RESET
The PALCE20V8 has been designed with the capability
to reset during system power-up. Following power-up,
all flip-flops will be reset to LOW. The output state will be
HIGH independent of the logic polarity. This feature pro-
vides extra flexibility to the designer and is especially
valuable in simplifying state machine initialization. A
timing diagram and parameter table are shown below.
■ The VCC rise must be monotonic.
■ Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter
Symbol
Parameter Description
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
Min
Max
Unit
tPR
1000
ns
tS
See Switching
Characteristics
tWL
VCC
4 V
Power
tPR
Registered
Output
tS
Clock
tWL
16491D-16
Power-Up Reset Waveforms
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PALCE20V8 Family
相关型号：
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