PALCE26V12H-10JI [AMD]
28-Pin EE CMOS Versatile PAL Device; 28引脚EE CMOS通用PAL器件
| 型号： | PALCE26V12H-10JI |
| 厂家： | 
AMD |
| 描述： | 28-Pin EE CMOS Versatile PAL Device |
| 文件： | 总21页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
COM’L: H-7/10/15/20
IND: H-10/15/20
PALCE26V12 Family
28-Pin EE CMOS Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
■ 28-pin versatile PAL programmable logic
■ Two clock inputs for independent functions
device architecture
■ Global asynchronous reset and synchronous
■ Electrically erasable CMOS technology
provides half power (only 115 mA) at high
speed (7.5 ns propagation delay)
preset for initialization
■ Register preload for testability and built-in
register reset on power-up
■ 14 dedicated inputs and 12 input/output
■ Space-efficient 28-pin SKINNYDIP and PLCC
macrocells for architectural flexibility
packages
■ Macrocells can be registered or combinatorial,
■ Center VCC and GND pins to improve signal
and active high or active low
characteristics
■ Varied product term distribution allows up to
■ Extensive third-party software and programmer
16 product terms per output
support through FusionPLD partners
GENERAL DESCRIPTION
The PALCE26V12 is a 28-pin version of the popular
PAL22V10 architecture. Built with low-power, high-
speed, electrically-erasable CMOS technology, the
PALCE26V12 offers many unique advantages.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to 16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial, active high or
active low, with registered I/O possible. The flip-flop can
be clocked by one of two clock inputs. The output
configuration is determined by four bits controlling three
multiplexers in each macrocell.
Device logic is automatically configured according to
the user’s design specification. Design is simplified by
design software, allowing automatic creation of a
programming file based on Boolean or state equations.
The software can also be used to verify the design and
can provide test vectors for the programmed device.
AMD’s FusionPLD program allows PALCE26V12
designs to be implemented using a wide variety of
popular industry-standard design tools. By working
closely with the FusionPLD partners, AMD certifies that
the tools provide accurate, quality support. By ensuring
that third-party tools are available, costs are lowered
because a designer does not have to buy a complete set
of new tools for each device. The FusionPLD program
also greatly reduces design time since a designer can
use a tool that is already installed and familiar. Please
refer to the PLD Software Reference Guide for certified
development systems and the Programmer Reference
Guide for approved programmers.
The PALCE26V12 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced
to sum-of-products form, taking advantage of the
very wide input gates available in PAL devices. The
functions are programmed into the device through
electrically-erasable floating-gate cells in the AND logic
array and the macrocells. In the unprogrammed state,
all AND product terms float HIGH. If both true and
complement of any input are connected, the term will be
permanently LOW.
Publication# 16072 Rev. E Amendment/0
Issue Date: February 1996
2-306
AMD
BLOCK DIAGRAM
I
CLK/I
2
12
PROGRAMMABLE
AND ARRAY
(52x150)
SYNC.
PRESET
ASYNC.
RESET
8
8
10
12
14
16
16
14
12
10
8
8
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
16072E-1
CONNECTION DIAGRAMS
Top View
DIP
PLCC
1
2
3
4
5
6
28
27
26
25
24
23
CLK1/I0
I13
I1
I/O11
I/O10
I/O9
I/O8
I/O7
I/O6
GND
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
I2
4
3
2
1
26
CLK2/I3
I4
28 27
I
I/O
5
6
25
4
9
8
7
6
I5
I
I/O
I/O
I/O
5
24
23
22
21
20
VCC
I6
7
8
22
21
V
7
CC
I
8
6
9
20
19
18
17
I7
I
GND
9
7
10
11
12
I8
I
I/O
5
10
8
I9
I
I/O
4
11
9
19
I10
I11
I12
17 18
12 13 14 15 16
13
14
16
15
16072E-2
Note:
16072E-3
Pin 1 is marked for orientation.
PIN DESCRIPTION
CLK
GND
I
I/O
VCC
=
=
=
=
=
Clock
Ground
Input
Input/Output
Supply Voltage
PALCE26V12 Family
2–307
AMD
ORDERING INFORMATION
Commercial and Industrial Products
AMD commercial and industrial programmable logic products are available with several ordering options. The order
number (Valid Combination) is formed by a combination of:
PAL CE 26 V 12 H -7 P C /4
OPTIONAL PROCESSING
Blank = Standard Processing
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
CE = CMOS Electrically Erasable
PROGRAMMING DESIGNATOR
/4 = First Revision
(May require programmer
update)
NUMBER OF
ARRAY INPUTS
OPERATING CONDITIONS
OUTPUT TYPE
V= Versatile
C = Commercial (0°C to +75°C)
I
= Industrial (–40°C to +85°C)
NUMBER OF OUTPUTS
PACKAGE TYPE
P= 28-Pin 300 mil Plastic
SKINNYDIP (PD3028)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)
POWER
H= Half Power (115 mA ICC
)
SPEED
-7 = 7.5 ns tPD
-10= 10 ns tPD
-15= 15 ns tPD
-20= 20 ns tPD
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
PALCE26V12H-7
JC
PALCE26V12H-10
PALCE26V12H-15
PALCE26V12H-20
/4
PC, JC, PI, JI
2–308
PALCE26V12H-7/10/15/20 (Com’l), H-10/15/20 (Ind)
AMD
OE
P1
FUNCTIONAL DESCRIPTION
AR CLK
1
The PALCE26V12 has fourteen dedicated input lines,
two of which can be used as clock inputs. Unused inputs
should be tied directly to ground or VCC. Buffers for
device inputs and feedbacks have both true and
complementary outputs to provide user-selectable
signal polarity. The inputs drive a programmable AND
logic array, which feeds a fixed OR logic array.
1
1
0
1
AR
D
Q
0
0
0
1
1
0
Q
SP
Pn
S
2
S
0
n = 8,8,10,12,14,16
CLK
2
S
0
1
1
SP
The OR gates feed the twelve I/O macrocells (see
Figure 1). The macrocell allows one of eight potential
output configurations; registered or combinatorial, ac-
tive high or active low, with register or I/O pin feedback
(seeFigure2). Inaddition, registeredconfigurationscan
be clocked by either of the two clock inputs.
*
S
3
*When S = 1 (unprogrammed) the feedback is selected by S .
When S = 0 (programmed), the feedback is the opposite of
3
3
1
that selected by S .
1
16072E-4
Figure 1. PALCE26V12 Macrocell
The configuration choice is made according to the
user’sdesignspecificationandcorrespondingprogram-
ming of the configuration bits S0–S3 (see Table 1).
Multiplexer controls initially float to VCC (1) through a
programmable cell, selecting the “1” path through the
multiplexer. Programming the cell connects the control
line to GND (0), selecting the “0” path.
Registered or Combinatorial
Each macrocell of the PALCE26V12 includes a D-type
flip-flop for data storage and synchronization. The
flip-flop is loaded on the LOW-to-HIGH edge of the
selected clock input. Any macrocell can be configured
as combinatorial by selecting a multiplexer path that
bypasses the flip-flop. Bypass is controlled by bit S1.
Table 1. Macrocell Configuration Table
Programmable Clock
The clock input for any flip-flop can be selected to be
from either pin 1 or pin 4. A 2:1 multiplexer controlled by
bit S2 determines the clock input.
S3 S1 S0
Output Configuration
1
0
0
Registered Output and Feedback,
Active Low
1
0
1
Registered Output and Feedback,
Active High
Programmable Feedback
A 2:1 multiplexer allows the user to determine whether
the macrocell feedback comes from the flip-flop or
from the I/O pin, independent of whether the output is
registered or combinatorial. Thus, registered outputs
may have internal register feedback for higher speed
(fMAX internal), or I/O feedback for use of the pin as a
direct input (fMAX external). Combinatorial outputs may
have I/O feedback, either for use of the signal in other
equations or for use as another direct input, or register
feedback.
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
Combinatorial I/O, Active Low
Combinatorial I/O, Active High
Registered I/O, Active Low
Registered I/O, Active High
Combinatorial Output, Registered
Feedback, Active Low
0
1
1
Combinatorial Output, Registered
Feedback, Active High
1 = Unprogrammed EE bit
0 = Programmed EE bit
S2 Clock Input
1
0
CLK1/I0
CLK2/I3
PALCE26V12 Family
2–309
AMD
The feedback multiplexer is controlled by the same bit
(S1) that controls whether the output is registered or
combinatorial, as on the 22V10, with an additional
control bit (S3) that allows the alternative feedback path
to be selected. When S3 = 1, S1 selects register
feedback for registered outputs (S1 = 0) and I/O
feedback for combinatorial outputs (S1 = 1). When S3 =
0, the opposite is selected: I/O feedback for registered
outputsandregisterfeedbackforcombinatorialoutputs.
Power-Up Reset
All flip-flops power up to a logic LOW for predictable
system initialization. Outputs of the PALCE26V12 will
be HIGH or LOW depending on whether the output is
activeloworactivehigh, respectively. TheVCC risemust
be monotonic, and the reset delay time is 1000 ns
maximum.
Register Preload
The register on the PALCE26V12 can be preloaded
from the output pins to facilitate functional testing of
complex state machine designs. This feature allows
direct loading of arbitrary states, thereby making it
unnecessary to cycle through long test vector se-
quences to reach a desired state. In addition, transitions
from illegal states can be verified by loading illegal
states and observing proper recovery.
Programmable Enable and I/O
Each macrocell has a three-state output buffer con-
trolled by an individual product term. Enable and disable
can be a function of any combination of device inputs or
feedback. The macrocell provides a bidirectional I/O pin
if I/O feedback is selected, and may be configured as a
dedicated input if the buffer is always disabled. This is
accomplished by connecting all inputs to the enable
term, forcing the AND of the complemented inputs to be
always LOW. To permanently enable the outputs, all
inputs are left disconnected from the term (the
unprogrammed state).
Security Bit
After programming and verification, a PALCE26V12
design can be secured by programming the security bit.
Once programmed, this bit defeats readback of the
internal programmed pattern by a device programmer,
securing proprietary designs from competitors. Pro-
gramming the security bit disables preload, and the
array will read as if every bit is disconnected. The
security bit can only be erased in conjunction with
erasure of the entire pattern.
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Programming and Erasing
The PALCE26V12 can be programmed on standard
logic programmers. It also may be erased to reset a
previously configured device back to its virgin state.
Erasure is automatically performed by the programming
hardware. No special erase operation is required.
Selection is controlled by programmable bit S0 in the
output macrocell, and affects both registered and
combinatorial outputs. Selection is automatic, based on
the design specification and pin definitions. If the pin
definition and output equation have the same polarity,
the output is programmed to be active high.
Quality and Testability
The PALCE26V12 offers a very high level of built-in
quality. The erasability of the device provides a means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest
programming yields and post-programming functional
yields in the industry.
Preset/Reset
For initialization, the PALCE26V12 has additional
Preset and Reset product terms. These terms are
connected to all registered outputs. When the Synchro-
nous Preset (SP) product term is asserted high, the
output registers will be loaded with a HIGH or the next
LOW-to-HIGHclocktransition. WhentheAsynchronous
Reset (AR) product term is asserted high, the output
registers will be immediately loaded with a LOW
independent of the clock.
Technology
The high-speed PALCE26V12 is fabricated with AMD’s
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
Note that preset and reset control the flip-flop, not the
output pin. The output level is determined by the output
polarity selected.
2–310
PALCE26V12 Family
AMD
AR
SP
AR
SP
D
Q
Q
D
Q
Q
CLK
CLK
Registered Active-Low Output,
Register Feedback
Registered Active-High Output,
Register Feedback
AR
AR
D
Q
Q
D
Q
Q
CLK
CLK
SP
SP
Registered Active-Low I/O
Registered Active-High I/O
Registered Outputs
Combinatorial Active-Low I/O
Combinatorial Active-High I/O
AR
AR
D
Q
Q
D
Q
Q
CLK
CLK
SP
SP
Combinatorial Active-Low Output,
Register Feedback
Combinatorial Active-High Output,
Register Feedback
16072E-5
Combinatorial Outputs
Figure 2. PALCE26V12 Macrocell Configuration Options
PALCE26V12 Family
2–311
AMD
LOGIC DIAGRAM
PALCE26V12
8
12
16
20
24
28
32
44
48
0
4
36
40
ASYNCH.
RESET
0
1
28
I13
1
10
11
00
01
CLK1/I0
AR
SP
27
I/O11
Q
Q
D
1
0
9
S0
S2
S1
R
0
11
*
2
I1
1
S3
10
18
10
11
00
01
AR
SP
26
I/O 10
D
Q
1
0
Q
S0
S1
S2
R
0
10
*
3
I2
1
S3
19
10
11
00
01
25
I/O9
AR
SP
D
Q
1
0
Q
S0
S1
29
S2
R
9
*
4
0
1
CLK2/I 3
S3
30
10
11
00
01
AR
SP
24
I/O8
D
Q
1
0
Q
S0
S1
S2
42
R
8
0
5
I4
1
*
S3
43
10
11
00
01
AR
SP
23
I/O 7
D
Q
1
0
Q
S0
S1
S2
57
R
7
*
0
6
I5
1
S3
58
10
11
00
01
22
I/O6
AR
D
Q
1
0
Q
SP
S0
S1
S2
74
R
6
*
0
8
1
I6
8
12
16
20
24
28
32
44
48
0
4
36
40
AR CLK1
SP
S3
21
CLK 2
GND
*
When S3 = 1 (unprogrammed) the feedback is selected by S1.
When S3 = 0 (programmed), the feedback is the opposite of
16072E-6
that selected by S .
1
2–312
PALCE26V12 Family
AMD
LOGIC DIAGRAM (continued)
PALCE26V12
AR CLK1
SP
8
12
16
20
24
28
32
44
48
0
4
36
40
CLK2
75
10
11
00
01
20
I/O5
AR
SP
D
Q
Q
1
0
S0
S1
S2
91
92
R
*
5
0
9
I7
1
S3
10
11
00
01
19
I/O4
AR
SP
D
Q
1
0
Q
S0
S1
S2
106
107
R
*
4
0
10
I8
1
S3
10
11
00
01
AR
SP
18
I/O3
D
Q
1
0
Q
S0
S1
S2
119
120
R
0
3
11
I9
1
*
S3
10
11
00
01
AR
SP
17
I/O2
D
Q
1
0
Q
S0
S1
130
S2
R
2
0
12
I10
1
*
S3
131
139
10
11
00
01
16
I/O1
AR
SP
D
Q
1
0
Q
S0
S1
S2
R
1
0
13
I11
1
*
S3
140
10
11
00
01
15
I/O0
AR
SP
D
Q
1
0
Q
148
149
S0
S1
S2
R
0
0
14
I12
1
SYNCH
PRESET
*
S3
8
12
16
20
24
28
32
44
48
0
4
36
40
*
When S3 = 1 (unprogrammed) the feedback is selected by S1.
When S3 = 0 (programmed), the feedback is the opposite of
that selected by S1.
16072E-6
(concluded)
PALCE26V12 Family
2–313
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Ambient Temperature (TA)
Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
)
DC Input Voltage . . . . . . . . . . . . . . . –0.6 V to +7.0 V
Industrial (I) Devices
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . –40°C to +85°C
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Supply Voltage (VCC
)
with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless
otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VIN = VIH or VIL
CC = Min
2.4
V
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 16 mA
VIN = VIH or VIL
VCC = Min
0.4
V
V
V
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
IIH
IIL
Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2)
Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2)
10
–10
10
µA
µA
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3)
–30
–170
115
mA
mA
ICC
VIN = 0 V, Outputs Open (IOUT = 0 mA) H-7/10
(Static)
VCC = Max, f = 0 MHz
Commercial Supply Current
Industrial Supply Current
ICC
(Dynamic)
H-7/10
H-10
140
150
mA
mA
VIN = 0 V, Outputs Open (IOUT = 0 mA)
VCC = Max, f = 15 MHz
ICC
(Dynamic)
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2–314
PALCE26V12H-7/10 (Com’l), H-10 (Ind)
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 0 V
VCC = 5.0 V
5
TA = +25°C
pF
COUT
Output Capacitance
VOUT = 0 V
f = 1 MHz
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
(Note 2)
-7
-10
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Unit
tPD
tS1
Input or Feedback to Combinatorial Output
7.5
10
ns
Setup Time from Input or Feedback
Setup Time from SP to Clock
Hold Time
3.5
4.5
0
5
5
0
ns
ns
tS2
tH
ns
tCO
tAR
Clock to Output
6
9
ns
Asynchronous Reset to Registered Output
Asynchronous Reset Width
Asynchronous Reset Recovery Time
Synchronous Preset Recovery Time
11
13
ns
tARW
tARR
tSPR
tWL
tWH
fMAX
6
5
8
8
ns
ns
5
8
ns
LOW
3.5
3.5
105.3
125
4
ns
Clock Width
HIGH
4
ns
Maximum
Frequency
(Notes 3 and 4)
External Feedback
1/(tS + tCO)
71.4
105
MHz
MHz
ns
Internal Feedback (fCNT) 1/(tS + tCF)
tEA
tER
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
8
10
10
7.5
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
PALCE26V12H-7/10 (Com’l), H-10 (Ind)
2–315
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Ambient Temperature (TA)
Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
)
DC Input Voltage . . . . . . . . . . . . . . . –0.6 V to +7.0 V
lndustrial (I) Devices
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . –40°C to +85°C
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Supply Voltage (VCC
)
with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless
otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VIN = VIH or VIL
CC = Min
2.4
V
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 16 mA
VIN = VIH or VIL
VCC = Min
0.4
V
V
V
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
IIH
IIL
Input HIGH Leakage Current
Input LOW Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
VIN = 0 V, VCC = Max (Note 2)
10
–10
10
µA
µA
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
Output Short-Circuit Current
Commerical Supply Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30
–160
105
mA
mA
ICC
(Static)
VIN = 0 V, Outputs Open (IOUT = 0 mA) H-15/20
VCC = Max, f = 0 MHz
ICC
(Dynamic)
VIN = 0 V, Outputs Open (IOUT = 0 mA) H-15
VCC = Max, f = 15 MHz
150
130
150
mA
mA
mA
ICC
(Static)
VIN = 0 V, Outputs Open (IOUT = 0 mA) H-20
VCC = Max
Industrial Supply Current
ICC
VIN = 0 V, Outputs Open (IOUT = 0 mA) H-20
(Dynamic)
VCC = Max, f = 15 MHz
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2–316
PALCE26V12H-15/20 (Com’l, Ind)
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 0 V
VCC = 5.0 V
TA = +25°C
f = 1 MHz
5
pF
COUT
Output Capacitance
VOUT = 0 V
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
(Note 2)
-15
-20
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Unit
tPD
tS
Input or Feedback to Combinatorial Output
15
20
ns
Setup Time from Input, Feedback, or SP to Clock
Hold Time
10
0
13
0
ns
ns
tH
tCO
tAR
Clock to Output
10
20
12
25
ns
Asynchronous Reset to Registered Output
Asynchronous Reset Width
ns
tARW
tARR
tSPR
tWL
tWH
15
15
10
8
20
20
13
10
10
40
43
ns
Asynchronous Reset Recovery Time
Synchronous Preset Recovery Time
ns
ns
LOW
ns
Clock Width
HIGH
8
ns
Maximum
Frequency
(Notes 3 and 4)
External Feedback
1/(tS + tCO
)
50
58.8
MHz
MHz
ns
fMAX
Internal Feedback (fCNT
)
1/(tS + tCF)
tEA
tER
Notes:
2. See Switching Test Circuit for test conditions.
Input to Output Enable Using Product Term Control
15
15
20
20
Input to Output Disable Using Product Term Control
ns
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
PALCE26V12H-15/20 (Com’l, Ind)
2–317
AMD
SWITCHING WAVEFORMS
Input or
Feedback
VT
tS
tH
Input or
Feedback
VT
VT
tCO
Clock
tPD
Registered
Output
Combinatorial
Output
VT
VT
16072E-8
16072E-7
Combinatorial Output
Registered Output
VT
Input
tWH
tER
tEA
VOH - 0.5V
VOL + 0.5V
Clock
VT
VT
Output
tWL
16072E-10
Input to Output Disable/Enable
Clock Width
16072E-9
tARW
Input Asserting
Asynchronous
Reset
Input Asserting
Synchronous
Preset
VT
VT
tAR
tS
tH
tSPR
Registered
Outputs
Clock
VT
VT
tARR
tCO
Registered
Outputs
Clock
VT
VT
16072E-11
16072E-12
Asynchronous Reset
Synchronous Preset
Notes:
1. VT = 1.5 V
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–5 ns typical.
2–318
PALCE26V12 Family
AMD
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
5 V
S1
R1
R2
Output
Test Point
CL
16072E-13
Measured
R2
Specification
tPD, tCO
S1
CL
R1
Output Value
Closed
1.5 V
Com’l: H-15/20
Ind: H-20
390 Ω
tEA
Z → H: Open
Z → L: Closed
50 pF
5 pF
1.5 V
300 Ω
Com’l: H-7/10
Ind: H-10/15
300 Ω
tER
H → Z: Open
L → Z: Closed
H → Z: VOH – 0.5 V
L → Z: VOL + 0.5 V
PALCE26V12 Family
2–319
AMD
TYPICAL ICC CHARACTERISTICS FOR THE PALCE26V12H-7/10
VCC = 5.0 V, TA = 25°C
150
125
100
75
50
25
ICC (mA)
0
0
10
20
30
40
50
Frequency (MHz)
16072E-14
The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the
other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector,
half of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to
estimate the ICC requirements for a particular design.
2–320
PALCE26V12 Family
AMD
parts. As a result, the device can be erased and
reprogrammed—a feature which allows 100% testing at
the factory.
ENDURANCE CHARACTERISTICS
The PALCE26V12 is manufactured using AMD’s ad-
vanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
Symbol
Parameter
Test Conditions
Min
Unit
tDR
Min Pattern Data Retention Time
Max Storage Temperature
10
20
Years
Years
Cycles
Max Operating Temperature
Normal Programming Conditions
N
Min Reprogramming Cycles
100
PALCE26V12 Family
2–321
AMD
the state of the input and pulls the voltage away from the
input threshold voltage where noise can cause oscilla-
tions. For an illustration of this configuration, see below.
Bus-Friendly Inputs
The PALCE26V12H-7/10 (Com’l) and H-10/15 (Ind)
inputs and I/O loop back to the input after the second
stage of the input buffer. This configuration reinforces
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR REV. C VERSION*
VCC
VCC
100 kΩ
ESD
Protection
Input
VCC
VCC
VCC
100 kΩ
Preload Feedback
Circuitry
Input
16072E-15
Output
*
Device
Rev. Letter
Topside Marking:
AMD CMOS PLD’s are marked on top of the package in the
following manner:
PALCE26V12H-7
PALCE26V12H-10
PALCE26V12H-15
C
PALCE xxxx
Datecode (4 numbers) LOT ID (3 characters) – – (Rev. Letter)
The Lot ID and Rev. letter are separated by two spaces.
2–322
PALCE26V12 Family
AMD
false clocking caused by subsequent ringing. A special
noise filter makes the programming circuitry completely
insensitive to any positive overshoot that has a pulse
width of less than about 100 ns.
ROBUSTNESS FEATURES
The PALCE26V12 has some unique features that make
it extremely robust, especially when operating in high
speed design environments. Input clamping circuitry
limits negative overshoot, eliminating the possibility of
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR REV. B VERSION*
VCC
VCC
> 50 kΩ
ESD
Protection
and
Programming
Pins only
Programming
Voltage
Detection
Positive
Overshoot
Filter
Programming
Circuitry
Clamping
Typical Input
VCC
VCC
> 50 kΩ
Provides ESD
Protection and
Clamping
Preload Feedback
Circuitry
Input
16072E-16
Typical Output
Topside Marking:
*
Device
Rev. Letter
AMD CMOS PLD’s are marked on top of the package in the
following manner:
PALCE xxxx
PALCE26V12-15
PALCE26V12-20
B
Datecode (4 numbers) LOT ID (3 characters) – – (Rev. Letter)
The Lot ID and Rev. letter are separated by two spaces.
PALCE26V12 Family
2–323
AMD
range of ways VCC can rise to its steady state, two
conditions are required to ensure a valid power-up
reset. These conditions are:
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
The output state will depend on the programmed
configuration. This feature is valuable in simplifying
state machine initialization. A timing diagram and
parameter table are shown below. Due to the synchro-
nous operation of the power-up reset and the wide
The VCC rise must be monotonic.
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter
Symbol
Parameter Description
Max
Unit
tPR
Power-Up Reset Time
1000
ns
See Switching
Characteristics
tS
Input or Feedback Setup Time
Clock Width LOW
tWL
VCC
4 V
Power
tPR
Registered
Active-Low
Output
tS
Clock
16072E-17
tWL
Power-Up Reset Waveform
2–324
PALCE26V12 Family
AMD
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
PALCE26V12
Typ
SKINNYDIP
Parameter
Symbol
Parameter Description
PLCC
Unit
θjc
Thermal impedance, junction to case
19
65
18
°C/W
θja
Thermal impedance, junction to ambient
55
°C/W
θjma
Thermal impedance, junction to ambient with air flow 200 lfpm air
59
54
50
50
48
44
39
37
°C/W
°C/W
°C/W
°C/W
400 lfpm air
600 lfpm air
800 lfpm air
Plastic θjc Considerations
The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of
the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at
a constant temperature. Therefore, the measurements can only be used in a similar environment.
2–325
PALCE26V12H-15/20
AMD
internal delay from the flip-flop outputs through the inter-
nal feedback and logic to the flip-flop inputs. This fMAX is
designated “fMAX internal”. A simple internal counter is a
good example of this type of design, therefore, this pa-
rameter is sometimes called “fCNT.”
fMAX Parameters
The parameter fMAX is the maximum clock rate at which
the device is guaranteed to operate. Because the flexi-
bility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, fMAX is specified for
three types of synchronous designs.
The third type of design is a simple data path applica-
tion. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (tS + tH). How-
ever, a lower limit for the period of each fMAX type is the
minimum clock period (tWH + tWL). Usually, this minimum
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the in-
put setup time for the external signals (tS + tCO). The re-
ciprocal, fMAX, is the maximum frequency with external
feedback or in conjunction with an equivalent speed de-
vice. This fMAX is designated “fMAX external.”
clock period determines the period for the third fMAX
,
designated “fMAX no feedback.”
f
MAX external and fMAX no feedback are calculated pa-
rameters. fMAX external is calculated from tS and tCO, and
MAX no feedback is calculated from tWL and tWH. fMAX in-
ternal is measured.
The second type of design is a single-chip state ma-
chine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop out-
puts. Under these conditions, the period is limited by the
f
CLK
(SECOND
CHIP)
LOGIC
REGISTER
tS
tS
tCO
fMAX External; 1/(tS + tCO
)
CLK
CLK
LOGIC
REGISTER
LOGIC
REGISTER
tS
fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL
16072E-18
fMAX Internal (fCNT
)
)
2–326
PALCE26V12 Family
相关型号：
PALCE26V12H-10PC/4
EE PLD, 10ns, PAL-Type, CMOS, PDIP28, 0.300 INCH, SKINNY, PLASTIC, DIP-28
LATTICE
PALCE26V12H-10PI/4
EE PLD, 10ns, PAL-Type, CMOS, PDIP28, 0.300 INCH, SKINNY, PLASTIC, DIP-28
LATTICE
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