A25L010 [AMICC]
16Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors; 16Mbit的低电压，串行闪存的100MHz统一4KB扇区
| 型号： | A25L010 |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 16Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors |
| 文件： | 总41页 (文件大小：546K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A25L016 Series
16Mbit Low Voltage, Serial Flash Memory
With 100MHz Uniform 4KB Sectors
Document Title
16Mbit, Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors
Revision History
Rev. No. History
Issue Date
Remark
0.0
Initial issue
April 2, 2008
Final
(April, 2008, Version 0.0)
AMIC Technology Corp.
A25L016 Series
16Mbit Low Voltage, Serial Flash Memory
With 100MHz Uniform 4KB Sectors
FEATURES
Family of Serial Flash Memories
16Mbit Flash memory
- Uniform 4-Kbyte sectors
- Uniform 64-Kbyte blocks
Electronic Signatures
- A25L016: 16M-bit /2M-byte
Flexible Sector Architecture with 4KB sectors
- Sector Erase (4K-bytes) in 60ms (typical)
- Block Erase (64K-bytes) in 0.5s (typical)
Page Program (up to 256 Bytes) in 0.8ms (typical)
2.7 to 3.6V Single Supply Voltage
- JEDEC Standard Two-Byte Signature
A25L016: (3015h)
- RES Instruction, One-Byte, Signature, for backward
compatibility
Dual input / output instructions resulting in an equivalent
clock frequency of 200MHz:
A25L016 (14h)
Package options
-
-
Dual Output Fast Read Instruction
Dual Input and Output Fast Read Instruction
- 8-pin SOP (209mil), 16-pin SOP (300mil), 8-pin DIP
(300mil)
- All Pb-free (Lead-free) products are RoHS compliant
SPI Bus Compatible Serial Interface
100MHz Clock Rate (maximum)
Deep Power-down Mode 5µA (Max)
GENERAL DESCRIPTION
The A25L016 is 16M bit Serial Flash Memory, with advanced
write protection mechanisms, accessed by a high speed
SPI-compatible bus.
sectors. Each sector is composed of 16 pages. Each page is
256 bytes wide. Thus, the whole memory can be viewed as
consisting of 8,192 pages, or 2,097,152 bytes.
The whole memory can be erased using the Chip Erase
instruction, a block at a time, using Block Erase instruction, or a
sector at a time, using the Sector Erase instruction.
The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The memory is organized as 32 blocks, each containing 16
Pin Configurations
SOP8 Connections
SOP16 Connections
DIP8 Connections
A25L016
A25L016
A25L016
HOLD
VCC
DU
DU
DU
DU
S
C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DIO
DU
DU
DU
DU
VSS
VCC
S
DO
1
2
3
4
8
7
6
5
VCC
S
DO
1
2
3
4
8
7
6
5
HOLD
C
DIO
HOLD
C
DIO
W
VSS
W
VSS
DO
W
Note:
DU = Do not Use
(April, 2008, Version 0.0)
1
AMIC Technology Corp.
A25L016 Series
Block Diagram
HOLD
High Voltage
Generator
W
Control Logic
S
C
DIO
DO
I/O Shift Register
Address register
and Counter
256 Byte
Data Buffer
Status
Register
1FFFFF
Size of the
memory area
00000h
000FFh
256 Byte (Page Size)
X Decoder
Pin Descriptions
Logic Symbol
Pin No.
Description
VCC
C
Serial Clock
DIO
DO
Serial Data Input 1
Serial Data Output 2
Chip Select
DIO
DO
C
S
S
A25L016
Write Protect
Hold
W
W
HOLD
HOLD
VCC
Supply Voltage
Ground
VSS
VSS
Notes:
1. The DIO is also used as an output pin when the Fast
Read Dual Output instruction and the Fast Read Dual
Input-Output instruction are executed.
2. The DO is also used as an input pin when the Fast
Read Dual Input-Output instruction.
(April, 2008, Version 0.0)
2
AMIC Technology Corp.
A25L016 Series
impedance. Unless an internal Program, Erase or Write
Status Register cycle is in progress, the device will be in the
Standby mode (this is not the Deep Power-down mode).
SIGNAL DESCRIPTION
Serial Data Output (DO). This output signal is used to
transfer data serially out of the device. Data is shifted out on
the falling edge of Serial Clock (C).
The DO pin is also used as an input pin when the Fast Read
Dual Input-Output instruction and Dual Input Fast Program is
executed.
Driving Chip Select ( ) Low enables the device, placing it in
S
the active power mode.
After Power-up, a falling edge on Chip Select ( ) is required
S
prior to the start of any instruction.
Serial Data Input (DIO). This input signal is used to transfer
data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are
latched on the rising edge of Serial Clock (C).
The DIO pin is also used as an output pin when the Fast
Read Dual Output instruction and the Fast Read Dual
Input-Output instruction are executed.
Serial Clock (C). This input signal provides the timing of the
serial interface. Instructions, addresses, or data present at
Serial Data Input (DIO) are latched on the rising edge of
Serial Clock (C). Data on Serial Data Output (DO) changes
after the falling edge of Serial Clock (C).
Hold (
). The Hold (
) signal is used to pause
HOLD
HOLD
any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (DO) is
high impedance, and Serial Data Input (DIO) and Serial
Clock (C) are Don’t Care. To start the Hold condition, the
device must be selected, with Chip Select ( ) driven Low.
S
Write Protect ( ). The main purpose of this input signal is
W
to freeze the size of the area of memory that is protected
against program or erase instructions (as specified by the
values in the BP2, BP1, and BP0 bits of the Status Register).
Chip Select ( ). When this input signal is High, the device
S
is deselected and Serial Data Output (DO) is at high
(April, 2008, Version 0.0)
3
AMIC Technology Corp.
A25L016 Series
SPI MODES
falling edge of Serial Clock (C).
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from the
The difference between the two modes, as shown in Figure 2,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
Figure 1. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA)
SDI
SCK
= (0, 0) or (1, 1)
C
DO DIO
C
DO DIO
C
DO DIO
Bus Master
(ST6, ST7, ST9,
ST10, Other)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
W HOLD
S
W HOLD
S
W HOLD
Note: The Write Protect ( ) and Hold (
W
) signals should be driven, High or Low as appropriate.
HOLD
Figure 2. SPI Modes Supported
CPOL CPHA
0
1
0
1
C
C
DIO
DO
MSB
MSB
(April, 2008, Version 0.0)
4
AMIC Technology Corp.
A25L016 Series
OPERATING FEATURES
Page Programming
WIP bit. The Write In Progress (WIP) bit indicates whether
the memory is busy with a Write Status Register, Program or
Erase cycle.
To program one data byte, two instructions are required: Write
Enable (WREN), which is one byte, and a Page Program (PP)
sequence, which consists of four bytes plus data. This is
followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction
allows up to 256 bytes to be programmed at a time (changing
bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
WEL bit. The Write Enable Latch (WEL) bit indicates the
status of the internal Write Enable Latch.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits
are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions.
Sector Erase, Block Erase, and Chip Erase
SRWD bit. The Status Register Write Disable (SRWD) bit is
The Page Program (PP) instruction and Dual Input Fast
Program (DIFP) instruction allow bits to be reset from 1 to 0.
Before this can be applied, the bytes of memory need to have
been erased to all 1s (FFh). This can be achieved, a sector at
a time, using the Sector Erase (SE) instruction, a block at a
time, using the Block Erase (BE) instruction, or throughout the
entire memory, using the Chip Erase (CE) instruction. This
starts an internal Erase cycle (of duration tSE, tBE, or tCE).
The Erase instruction must be preceded by a Write Enable
(WREN) instruction.
operated in conjunction with the Write Protect ( ) signal.
W
The Status Register Write Disable (SRWD) bit and Write
Protect ( ) signal allow the device to be put in the Hardware
W
Protected mode. In this mode, the non-volatile bits of the
Status Register (SRWD, TB, BP2, BP1, BP0) become
read-only bits.
Protection Modes
The environments where non-volatile memory devices are
used can be very noisy. No SPI device can operate correctly
in the presence of excessive noise. To help combat this, the
A25L016 boasts the following data protection mechanisms:
Power-On Reset and an internal timer (tPUW) can provide
protection against inadvertent changes while the power
supply is outside the operating specification.
Program, Erase and Write Status Register instructions are
checked that they consist of a number of clock pulses that
is a multiple of eight, before they are accepted for
execution.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register
(WRSR), Program (PP) or Erase (SE, BE, or CE) can be
achieved by not waiting for the worst case delay (tW, tPP, tSE
,
t
BE, tCE). The Write In Progress (WIP) bit is provided in the
Status Register so that the application program can monitor
its value, polling it to establish when the previous Write cycle,
Program cycle or Erase cycle is complete.
All instructions that modify data must be preceded by a
Write Enable (WREN) instruction to set the Write Enable
Latch (WEL) bit. This bit is returned to its reset state by
the following events:
Active Power, Stand-by Power and Deep
Power-Down Modes
When Chip Select ( ) is Low, the device is enabled, and in
S
the Active Power mode.
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
When Chip Select ( ) is High, the device is disabled, but
S
could remain in the Active Power mode until all internal cycles
have completed (Program, Erase, Write Status Register). The
device then goes in to the Stand-by Power mode. The device
consumption drops to ICC1.
The Deep Power-down mode is entered when the specific
instruction (the Deep Power-down Mode (DP) instruction) is
executed. The device consumption drops further to ICC2. The
device remains in this mode until another specific instruction
(the Release from Deep Power-down Mode and Read
Electronic Signature (RES) instruction) is executed.
All other instructions are ignored while the device is in the
Deep Power-down mode. This can be used as an extra
software protection mechanism, when the device is not in
active use, to protect the device from inadvertent Write,
Program or Erase instructions.
- Chip Erase (CE) instruction completion
The Block Protect (BP2, BP1, BP0) bits allow part of the
memory to be configured as read-only. This is the
Software Protected Mode (SPM).
The Write Protect ( ) signal allows the Block Protect
W
(BP2, BP1, BP0) bits and Status Register Write Disable
(SRWD) bit to be protected. This is the Hardware
Protected Mode (HPM).
In addition to the low power consumption feature, the
Deep Power-down mode offers extra software protection
from inadvertent Write, Program and Erase instructions, as
all instructions are ignored except one particular instruction
(the Release from Deep Power-down instruction).
Status Register
The Status Register contains a number of status and control
bits that can be read or set (as appropriate) by specific
instructions.
(April, 2008, Version 0.0)
5
AMIC Technology Corp.
A25L016 Series
Table 1. Protected Area Sizes
Status Register Content
Memory Protection
Addresses
BP2
0
BP1
0
BP0
0
Block(s)
None
Density
None
Portion
None
None
0
0
1
31
1F0000h – 1FFFFFh
1E0000h – 1FFFFFh
1C0000h – 1FFFFFh
180000h – 1FFFFFh
100000h – 1FFFFFh
000000h – 1FFFFFh
64KB
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
All
0
1
0
30 – 31
28 – 31
24 – 31
16 – 31
0 – 31
128KB
256KB
512KB
1MB
0
1
1
1
0
0
1
0
1
1
1
X
2MB
Note:
1. X = don’t care
2. The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
(April, 2008, Version 0.0)
6
AMIC Technology Corp.
A25L016 Series
Hold Condition
The Hold (
communications with the device without resetting the clocking
sequence. However, taking this signal Low does not
terminate any Write Status Register, Program or Erase cycle
that is currently in progress.
Serial Clock (C) next goes Low. This is shown in Figure 3.
During the Hold condition, the Serial Data Output (DO) is high
impedance, and Serial Data Input (DIO) and Serial Clock (C)
are Don’t Care.
) signal is used to pause any serial
HOLD
Normally, the device is kept selected, with Chip Select (
)
S
To enter the Hold condition, the device must be selected, with
driven Low, for the whole duration of the Hold condition. This
is to ensure that the state of the internal logic remains
unchanged from the moment of entering the Hold condition.
Chip Select ( ) Low.
S
The Hold condition starts on the falling edge of the Hold
If Chip Select ( ) goes High while the device is in the Hold
S
condition, this has the effect of resetting the internal logic of
the device. To restart communication with the device, it is
(
) signal, provided that this coincides with Serial Clock
HOLD
(C) being Low (as shown in Figure 3.).
The Hold condition ends on the rising edge of the Hold
necessary to drive Hold (
) High, and then to drive
HOLD
(
) signal, provided that this coincides with Serial Clock
HOLD
Chip Select ( ) Low. This prevents the device from going
S
(C) being Low.
If the falling edge does not coincide with Serial Clock (C)
being Low, the Hold condition starts after Serial Clock (C)
next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after
back to the Hold condition.
Figure 3. Hold Condition Activation
C
HOLD
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
(April, 2008, Version 0.0)
7
AMIC Technology Corp.
A25L016 Series
MEMORY ORGANIZATION
Each page can be individually programmed (bits are
programmed from 1 to 0). The device is Sector, Block, or Chip
Erasable (bits are erased from 0 to 1) but not Page Erasable.
The memory is organized as:
2,097,152 bytes (8 bits each)
32 blocks (64 Kbytes each)
512 sectors (4 Kbytes each)
8192 pages (256 bytes each)
Table 2. Memory Organization
A25L016 Address Table
Block
Sector
Address range
Block
Sector
Address range
335
14F000h
14FFFFh
511
1FF000h
1FFFFFh
20
31
320
319
140000h
13F000h
140FFFh
13FFFFh
496
495
1F0000h
1EF000h
1F0FFFh
1EFFFFh
19
30
304
303
130000h
12F000h
130FFFh
12FFFFh
480
479
1E0000h
1DF000h
1E0FFFh
1DFFFFh
18
17
16
15
14
13
12
11
10
29
288
287
120000h
11F000h
120FFFh
11FFFFh
464
463
1D0000h
1CF000h
1D0FFFh
1CFFFFh
28
27
26
25
24
23
22
21
272
271
110000h
10F000h
110FFFh
10FFFFh
448
447
1C0000h
1BF000h
1C0FFFh
1BFFFFh
256
255
100000h
FF000h
100FFFh
FFFFFh
432
431
1B0000h
1AF000h
1B0FFFh
1AFFFFh
240
239
F0000h
EF000h
F0FFFh
EFFFFh
416
415
1A0000h
19F000h
1A0FFFh
19FFFFh
224
223
E0000h
DF000h
E0FFFh
DFFFFh
400
399
190000h
18F000h
190FFFh
18FFFFh
208
207
D0000h
CF000h
D0FFFh
CFFFFh
384
383
180000h
17F000h
180FFFh
17FFFFh
192
191
C0000h
BF000h
C0FFFh
BFFFFh
368
367
170000h
16F000h
170FFFh
16FFFFh
176
175
B0000h
AF000h
B0FFFh
AFFFFh
352
351
160000h
15F000h
160FFFh
15FFFFh
160
A0000h
A0FFFh
336
150000h
150FFFh
(April, 2008, Version 0.0)
8
AMIC Technology Corp.
A25L016 Series
Memory Organization (continued)
Block
Sector
Address range
Block
Sector
Address range
63
3F000h
3FFFFh
159
9F000h
9FFFFh
3
9
48
47
30000h
2F000h
30FFFh
2FFFFh
144
143
90000h
8F000h
90FFFh
8FFFFh
8
2
1
32
31
20000h
1F000h
20FFFh
1FFFFh
128
127
80000h
7F000h
80FFFh
7FFFFh
7
6
16
15
10000h
0F000h
10FFFh
0FFFFh
112
111
70000h
6F000h
70FFFh
6FFFFh
4
3
04000h
03000h
04FFFh
03FFFh
96
95
60000h
5F000h
60FFFh
5FFFFh
0
5
4
2
02000h
02FFFh
80
79
50000h
4F000h
50FFFh
4FFFFh
1
0
01000h
00000h
01FFFh
00FFFh
64
40000h
40FFFh
(April, 2008, Version 0.0)
9
AMIC Technology Corp.
A25L016 Series
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input (DIO) is sampled on the first rising edge of
the shifted-in instruction sequence is followed by a data-out
sequence. Chip Select ( ) can be driven High after any bit of
S
the data-out sequence is being shifted out.
Serial Clock (C) after Chip Select ( ) is driven Low. Then, the
S
In the case of a Page Program (PP), Sector Erase (SE), Block
Erase (BE), Chip Erase (CE), Write Status Register (WRSR),
Write Enable (WREN), Write Disable (WRDI) or Deep
one-byte instruction code must be shifted in to the device,
most significant bit first, on Serial Data Input (DIO), each bit
being latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 3.
Power-down (DP) instruction, Chip Select ( ) must be driven
S
High exactly at a byte boundary, otherwise the instruction is
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at
Higher Speed (Fast_Read), Read Identification (RDID), Read
Electronic Manufacturer and Device Identification (REMS),
Read Status Register (RDSR) or Release from Deep
Power-down, Read Device Identification and Read Electronic
Signature (RES) instruction,
rejected, and is not executed. That is, Chip Select ( ) must
S
driven High when the number of clock pulses after Chip Select
(
) being driven Low is an exact multiple of eight.
S
All attempts to access the memory array during a Write Status
Register cycle, Program cycle or Erase cycle are ignored, and
the internal Write Status Register cycle, Program cycle or
Erase cycle continues unaffected.
Table 3. Instruction Set
One-byte
Instruction Code
Address
Bytes
Dummy
Bytes
Data
Bytes
Instruction
WREN
Description
Write Enable
Write Disable
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 1011
06h
04h
05h
01h
03h
0Bh
0
0
0
0
3
3
0
0
0
0
0
1
0
WRDI
0
RDSR
Read Status Register
Write Status Register
1 to ∞
1
WRSR
READ
Read Data Bytes
1 to ∞
1 to ∞
FAST_READ
Read Data Bytes at Higher Speed
FAST_READ_DUAL
_OUTPUT
Read Data Bytes at Higher Speed by
Dual Output (1)
00111011
10111011
3Bh
BBh
3
1
1 to ∞
1 to ∞
FAST_READ_DUAL
_INPUT-OUTPUT
Read Data Bytes at Higher Speed by
Dual Input and Dual Output (1)
3(2)
1(2)
PP
Page Program
Sector Erase
0000 0010
0010 0000
1101 1000
1100 0111
1011 1001
1001 1111
02h
20h
D8h
C7h
B9h
9Fh
3
3
3
0
0
0
0
0
0
0
0
0
1 to 256
SE
0
BE
Block Erase
0
0
CE
Chip Erase
DP
Deep Power-down
Read Device Identification
0
RDID
1 to ∞
Read Electronic Manufacturer & Device
Identification
REMS
1001 0000
90h
1(3)
2
1 to ∞
Release from Deep Power-down, and
Read Electronic Signature
0
0
3
0
1 to ∞
RES
1010 1011
ABh
Release from Deep Power-down
0
Note: (1) DIO = (D6, D4, D2, D0)
DO = (D7, D5, D3, D1)
(2) Dual Input, DIO = (A22, A20, A18, ………, A6, A4, A2, A0)
DO = (A23, A21, A19, …….., A7, A5, A3, A1)
(3) ADD= (00h) will output manufacturer’s ID first and ADD=(01h) will output device ID first
(April, 2008, Version 0.0)
10
AMIC Technology Corp.
A25L016 Series
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 4.) sets the
Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every
Page Program (PP), Sector Erase (SE), Block Erase (BE),
Chip Erase (CE) and Write Status Register (WRSR)
instruction.
The Write Enable (WREN) instruction is entered by driving
Chip Select ( ) Low, sending the instruction code, and then
S
driving Chip Select ( ) High.
S
Figure 4. Write Enable (WREN) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
DIO
High Impedance
DO
Write Disable (WRDI)
﹣ Power-up
﹣ Write Disable (WRDI) instruction completion
﹣ Write Status Register (WRSR) instruction completion
﹣ Page Program (PP) instruction completion
﹣ Sector Erase (SE) instruction completion
﹣ Block Erase (BE) instruction completion
﹣ Chip Erase (CE) instruction completion
The Write Disable (WRDI) instruction (Figure 5.) resets the
Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip
S
Select ( ) Low, sending the instruction code, and then driving
Chip The Write Enable Latch (WEL) bit is reset under the
following conditions:
Figure 5. Write Disable (WRDI) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
DIO
High Impedance
DO
(April, 2008, Version 0.0)
11
AMIC Technology Corp.
A25L016 Series
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the
Status Register to be read. The Status Register may be read
at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in
progress, it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as
shown in Figure 6.
WEL bit. The Write Enable Latch (WEL) bit indicates the
status of the internal Write Enable Latch. When set to 1 the
internal Write Enable Latch is set, when set to 0 the internal
Write Enable Latch is reset and no Write Status Register,
Program or Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits
are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions.
These bits are written with the Write Status Register (WRSR)
instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as
defined in Table 1.) becomes protected against Page
Program (PP), Sector Erase (SE), and Block Erase (BE)
instructions. The Block Protect (BP2, BP1, BP0) bits can be
written provided that the Hardware Protected mode has not
been set. The Chip Erase (CE) instruction is executed if, and
only if, all Block Protect (BP2, BP1, BP0) bits are 0.
Table 4. Status Register Format
b7
SRWD
b6
0
b5
0
b4
b3
b2
b1
b0
BP2 BP1 BP0 WEL WIP
Status Register
Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
SRWD bit. The Status Register Write Disable (SRWD) bit is
operated in conjunction with the Write Protect ( ) signal.
W
The Status Register Write Disable (SRWD) bit and Write
Protect (
) signal allow the device to be put in the
W
Hardware Protected mode (when the Status Register Write
The status and control bits of the Status Register are as
follows:
WIP bit. The Write In Progress (WIP) bit indicates whether
the memory is busy with a Write Status Register, Program or
Erase cycle. When set to 1, such a cycle is in progress, when
reset to 0 no such cycle is in progress.
Disable (SRWD) bit is set to 1, and Write Protect ( ) is
W
driven Low). In this mode, the non-volatile bits of the Status
Register (SRWD, TB, BP2, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no
longer accepted for execution.
Figure 6. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12
14 15
13
C
Instruction
DIO
Status Register Out
Status Register Out
High Impedance
DO
5
7
6
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
(April, 2008, Version 0.0)
12
AMIC Technology Corp.
A25L016 Series
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new
values to be written to the Status Register. Before it can be
Write Status Register cycle is in progress, the Status
Register may still be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0
when it is completed. When the cycle is completed, the
Write Enable Latch (WEL) is reset.
accepted,
a Write Enable (WREN) instruction must
previously have been executed. After the Write Enable
(WREN) instruction has been decoded and executed, the
device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by
The Write Status Register (WRSR) instruction allows the
user to change the values of the Block Protect (BP2, BP1,
BP0) bits, to define the size of the area that is to be treated
as read-only, as defined in Table 1. The Write Status
Register (WRSR) instruction also allows the user to set or
reset the Status Register Write Disable (SRWD) bit in
S
driving Chip Select ( ) Low, followed by the instruction
code and the data byte on Serial Data Input (DIO).
The instruction sequence is shown in Figure 7. The Write
Status Register (WRSR) instruction has no effect on b6, b5,
b1 and b0 of the Status Register. b6 and b5 are always read
as 0.
accordance with the Write Protect ( ) signal. The Status
W
Register Write Disable (SRWD) bit and Write Protect (
)
W
S
Chip Select ( ) must be driven High after the eighth bit of
signal allow the device to be put in the Hardware Protected
Mode (HPM). The Write Status Register (WRSR) instruction
is not executed once the Hardware Protected Mode (HPM)
is entered.
the data byte has been latched in. If not, the Write Status
Register (WRSR) instruction is not executed. As soon as
S
Chip Select ( ) is driven High, the self-timed Write Status
Register cycle (whose duration is tW) is initiated. While the
Figure 7. Write Status Register (WRSR) Instruction Sequence
S
6
0
1
2
3
4
5
7
8
9 10 11 12
14 15
13
C
Status
Instruction
Register In
5
7
6
4
3
2
1
0
DIO
DO
High Impedance
MSB
(April, 2008, Version 0.0)
13
AMIC Technology Corp.
A25L016 Series
Table 5. Protection Modes
Memory Content
SRWD
Bit
Write Protection of the
Status Register
W
Signal
Mode
Protected Area1
Unprotected Area1
1
0
1
0
0
1
Status Register is Writable (if the
Software WREN instruction has set the
Protected WEL bit) The values in the
Protected against Page
Program, Dual Input Fast
Program, Sector Erase,
Block Erase, and Chip
Erase
Ready to accept Page
Program, Dual Input Fast
Program, Sector Erase,
and Block Erase
(SPM)
SRWD, TB, BP2, BP1, and BP0
bits can be changed
instructions
Protected against Page
Program, Dual Input Fast
Program, Sector Erase,
Block Erase, and Chip
Erase
Ready to accept Page
Program, Dual Input Fast
Program, Sector Erase,
and Block Erase
Status Register is Hardware write
protected The values in the
SRWD, TB, BP2, BP1, and BP0
bits cannot be changed
Hardware
Protected
(HPM)
0
1
instructions
Note: 1. As defined by the values in the Block Protect (TB, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
Register are rejected, and are not accepted for execution).
As a consequence, all the data bytes in the memory area
that are software protected (SPM) by the Block Protect
(BP2, BP1, BP0) bits of the Status Register, are also
hardware protected against data modification.
The protection features of the device are summarized in Table
5.
When the Status Register Write Disable (SRWD) bit of the
Status Register is 0 (its initial delivery state), it is possible to
write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction, regardless of the whether Write Protect
Regardless of the order of the two events, the Hardware
Protected Mode (HPM) can be entered:
by setting the Status Register Write Disable (SRWD) bit
after driving Write Protect ( ) Low
(
) is driven High or Low.
W
W
When the Status Register Write Disable (SRWD) bit of the
Status Register is set to 1, two cases need to be considered,
or by driving Write Protect (
) Low after setting the
W
Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM)
once entered is to pull Write Protect ( ) High.
depending on the state of Write Protect ( ):
W
If Write Protect ( ) is driven High, it is possible to write
W
W
to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
If Write Protect ( ) is permanently tied High, the Hardware
W
Protected Mode (HPM) can never be activated, and only the
Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
If Write Protect (W) is driven Low, it is not possible to
write to the Status Register even if the Write Enable Latch
(WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status
(April, 2008, Version 0.0)
14
AMIC Technology Corp.
A25L016 Series
Read Data Bytes (READ)
therefore, be read with a single Read Data Bytes (READ)
instruction. When the highest address is reached, the
address counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
S
The device is first selected by driving Chip Select ( ) Low.
The instruction code for the Read Data Bytes (READ)
instruction is followed by a 3-byte address (A23-A0), each bit
being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on
Serial Data Output (DO), each bit being shifted out, at a
maximum frequency fR, during the falling edge of Serial Clock
(C).
The Read Data Bytes (READ) instruction is terminated by
S
S
driving Chip Select ( ) High. Chip Select ( ) can be driven
High at any time during data output. Any Read Data Bytes
(READ) instruction, while an Erase, Program or Write cycle is
in progress, is rejected without having any effects on the
cycle that is in progress.
The instruction sequence is shown in Figure 8. The first byte
addressed can be at any location. The address is
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
Figure 8. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
33 34 35 36 37 38 39
32
C
DIO
DO
Instruction
24-Bit Address
21
23
2
1
0
22
3
MSB
Data Out 2
Data Out 1
High Impedance
5
4
1
0
6
3
2
7
7
MSB
Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0)
15
AMIC Technology Corp.
A25L016 Series
Read Data Bytes at Higher Speed (FAST_READ)
Speed (FAST_READ) instruction. When the highest address
is reached, the address counter rolls over to 000000h,
allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ)
S
The device is first selected by driving Chip Select ( ) Low.
The instruction code for the Read Data Bytes at Higher
Speed (FAST_READ) instruction is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being
latched-in during the rising edge of Serial Clock (C). Then the
memory contents, at that address, is shifted out on Serial
Data Output (DO), each bit being shifted out, at a maximum
frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 9. The first byte
addressed can be at any location. The address is
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher
S
instruction is terminated by driving Chip Select ( ) High.
S
Chip Select ( ) can be driven High at any time during data
output. Any Read Data Bytes at Higher Speed (FAST_READ)
instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle
that is in progress.
Figure 9. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31
C
DIO
DO
Instruction
24-Bit Address
21
23
2
1
0
22
3
MSB
High Impedance
S
C
33 34 35 36 37 38 39 40
Dummy Byte
32
7
41 42 43 44 45 46 47
6
5
4
3
2
0
1
DIO
DO
Data Out 2
Data Out 1
0
5
4
1
5
4
1
6
3
2
0
6
3
2
7
7
7
MSB
MSB
MSB
Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0)
16
AMIC Technology Corp.
A25L016 Series
Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the
Fast Read (0Bh) instruction except the data is output on two
pins, DO and DIO, instead of just DO. This allows data to be
transferred from the A25L016 at twice the rate of standard
SPI devices.
Similar to the Fast Read instruction, the Fast Read Dual
Output instruction can operate at the highest possible
frequency of fC (See AC Characteristics). This is
accomplished by adding eight “dummy” clocks after the
24-bit address as shown in figure 10. The dummy clocks
allow the device’s internal circuits additional time for setting
up the initial address. The input data during the dummy
clocks is “don’t care”. However, the DIO pin should be
high-impedance prior to the falling edge of the first data out
clock.
Figure 10. FAST_READ_DUAL_OUTPUT Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
C
DIO
DO
Instruction
24-Bit Address
21
23
2
1
0
22
3
MSB
High Impedance
S
C
33 34 35 36 37 38 39 40
Dummy Byte
32
7
41 42 43 44 45 46 47
DIO switches from input to output
6
5
4
3
2
0
6
4
2
0
6
4
2
0
6
4
2
3
0
1
6
7
4
5
2
3
0
1
1
DIO
DO
3
1
3
5
7
5
1
5
7
7
7
MSB
MSB
MSB
Data Out 1
Data Out 2
Data Out 3
Data Out 4
Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0)
17
AMIC Technology Corp.
A25L016 Series
Fast Read Dual Input-Output (BBh)
The Fast Read Dual Input-Output (BBh) instruction is similar
to the Fast_Read (0Bh) instruction except the data is input
and output on two pins, DO and DIO, instead of just DO. This
allows data to be transferred from the A25L016 at twice the
rate of standard SPI devices.
Similar to the Fast Read instruction, the Fast Read Dual
Output instruction can operate at the highest possible
frequency of fC (See AC Characteristics). This is
accomplished by adding four “dummy” clocks after the 24-bit
address as shown in figure 11. The dummy clocks allow the
device’s internal circuits additional time for setting up the
initial address. The input data during the dummy clocks is
“don’t care”. However, the DIO and DO pins should be
high-impedance prior to the falling edge of the first data out
clock.
Figure 11. FAST_READ_DUAL_INPUT-OUTPUT Instruction Sequence and Data-Out Sequence
S
6
0
1
2
3
4
5
7
8
9 10
16 17 18 19
C
DIO
DO
Instruction
24-Bit Address
22
18
4
2
3
0
1
20
6
MSB
High Impedance
23
19
5
7
21
S
C
20 21 22 23 24 25 26 27 28
Dummy
29 30 31 32 33 34 35
DIO switches from input to output
Byte
3
2
1
0
6
4
2
0
6
4
2
0
6
4
2
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
DIO
DO
3
1
3
7
5
3
1
5
7
5
7
7
MSB
MSB
MSB
MSB
Data Out 2
Data Out 3
Data Out 4
Data Out 5
Data Out 1
Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0)
18
AMIC Technology Corp.
A25L016 Series
Page Program (PP)
The Page Program (PP) instruction allows bytes to be
programmed in the memory (changing bits from 1 to 0).
Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
programmed correctly within the same page. If less than 256
Data bytes are sent to device, they are correctly programmed
at the requested addresses without having any effects on the
other bytes of the same page.
S
Chip Select ( ) must be driven High after the eighth bit of the
last data byte has been latched in, otherwise the Page
Program (PP) instruction is not executed.
The Page Program (PP) instruction is entered by driving Chip
S
Select ( ) Low, followed by the instruction code, three
S
As soon as Chip Select ( ) is driven High, the self-timed
address bytes and at least one data byte on Serial Data Input
(DIO). If the 8 least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the
same page (from the address whose 8 least significant bits
Page Program cycle (whose duration is tPP) is initiated. While
the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed
Page Program cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
S
(A7-A0) are all zero). Chip Select ( ) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in Figure 12. If more than
256 bytes are sent to the device, previously latched data are
discarded and the last 256 data bytes are guaranteed to be
A Page Program (PP) instruction applied to a page which is
protected by the Block Protect (BP2, BP1, BP0) bits (see
table 1 and table 2) is not executed.
Figure 12. Page Program (PP) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
33 34 35 36 37 38 39
Data Byte 1
32
7
C
Instruction
24-Bit Address
23
21
2
1
0
22
3
5
4
1
0
6
3
2
DIO
MSB
MSB
S
C
40 41 42 43 44 45 46
Data Byte 2
48 49 50 51 52 53 54 55
Data Byte 3
47
Data Byte 256
DIO
0
5
4
1
5
4
1
6
3
2
0
6
7
3
2
5
4
1
6
3
2
0
7
7
MSB
MSB
MSB
Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0)
19
AMIC Technology Corp.
A25L016 Series
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits
inside the chosen sector. Before it can be accepted, a Write
Enable (WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip
S
instruction is not executed. As soon as Chip Select ( ) is
driven High, the self-timed Sector Erase cycle (whose
duration is tSE) is initiated. While the Sector Erase cycle is in
progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Sector Erase cycle, and is
0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is
protected by the Block Protect (TB, BP2, BP1, BP0) bits (see
table 1 and table 2) is not executed.
S
Select ( ) Low, followed by the instruction code on Serial
S
Data Input (DIO). Chip Select ( ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 13. Chip Select
S
(
) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Sector Erase
Figure 13. Sector Erase (SE) Instruction Sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31
C
Instruction
24-Bit Address
3
1
22
0
23
21
2
DIO
MSB
Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0)
20
AMIC Technology Corp.
A25L016 Series
Block Erase (BE)
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside
the chosen block. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded,
the device sets the Write Enable Latch (WEL).
S
instruction is not executed. As soon as Chip Select ( ) is
driven High, the self-timed Block Erase cycle (whose duration
is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit
is 1 during the self-timed Block Erase cycle, and is 0 when it
is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a page which is
protected by the Block Protect (TB, BP2, BP1, BP0) bits (see
table 1and table 2) is not executed.
The Block Erase (BE) instruction is entered by driving Chip
S
Select ( ) Low, followed by the instruction code on Serial
S
Data Input (DIO). Chip Select ( ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 14. Chip Select
S
(
) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Block Erase
Figure 14. Block Erase (BE) Instruction Sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31
C
Instruction
24-Bit Address
22
3
23
21
2
1
0
DIO
MSB
Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0)
21
AMIC Technology Corp.
A25L016 Series
Chip Erase (CE)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before
it can be accepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
S
instruction is not executed. As soon as Chip Select ( ) is
driven High, the self-timed Chip Erase cycle (whose duration
is tCE) is initiated. While the Chip Erase cycle is in progress,
the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is
1 during the self-timed Chip Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is executed only if all Block
Protect (TB, BP2, BP1, BP0) bits are 0. The Chip Erase (CE)
instruction is ignored if one, or more, blocks are protected.
The Chip Erase (CE) instruction is entered by driving Chip
S
Select ( ) Low, followed by the instruction code on Serial
S
Data Input (DIO). Chip Select ( ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 15. Chip Select
S
(
) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Block Erase
Figure 15. Chip Erase (CE) Instruction Sequence
S
0
1
3
2
4 5
6
7
C
Instruction
DIO
Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0)
22
AMIC Technology Corp.
A25L016 Series
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only
way to put the device in the lowest consumption mode (the
Deep Power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in
active use, since in this mode, the device ignores all Write,
Program and Erase instructions.
The Deep Power-down mode automatically stops at
Power-down, and the device always Powers-up in the
Standby mode.
The Deep Power-down (DP) instruction is entered by driving
S
Chip Select ( ) Low, followed by the instruction code on
S
Serial Data Input (DIO). Chip Select ( ) must be driven Low
S
Driving Chip Select ( ) High deselects the device, and puts
for the entire duration of the sequence. The instruction
sequence is shown in Figure 16.
the device in the Standby mode (if there is no internal cycle
currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only be
entered by executing the Deep Power-down (DP) instruction,
to reduce the standby current (from ICC1 to ICC2, as specified in
DC Characteristics Table.).
S
Chip Select ( ) must be driven High after the eighth bit of the
instruction code has been latched in, otherwise the Deep
Power-down (DP) instruction is not executed. As soon as
S
Chip Select ( ) is driven High, it requires a delay of tDP
before the supply current is reduced to ICC2 and the Deep
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase,
Program or Write cycle is in progress, is rejected without
having any effects on the cycle that is in progress.
Once the device has entered the Deep Power-down mode, all
instructions are ignored except the Release from Deep
Power-down and Read Electronic Signature (RES) instruction.
This releases the device from this mode. The Release from
Deep Power-down and Read Electronic Signature (RES)
instruction also allows the Electronic Signature of the device
to be output on Serial Data Output (DO).
Figure 16. Deep Power-down (DP) Instruction Sequence
S
tDP
0
1
3
2
4
5
6
7
C
Instruction
DIO
Stand-by Mode
Deep Power-down Mode
(April, 2008, Version 0.0)
23
AMIC Technology Corp.
A25L016 Series
Read Device Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit
manufacturer identification code to be read, followed by two
bytes of device identification. The manufacturer identification
is assigned by JEDEC, and has the value 37h. The device
identification is assigned by the device manufacturer, and
indicates the memory in the first bytes (30h), and the memory
capacity of the device in the second byte (16h for A25L032,
15h for A25L016).
This is followed by the 24-bit device identification, stored in
the memory, being shifted out on Serial Data Output (DO),
each bit being shifted out during the falling edge of Serial
Clock (C).
The instruction sequence is shown in Figure 17. The Read
Identification (RDID) instruction is terminated by driving Chip
S
Select ( ) High at any time during data output.
Any Read Identification (RDID) instruction while an Erase, or
Program cycle is in progress, is not decoded, and has no
effect on the cycle that is in progress.
S
When Chip Select ( ) is driven High, the device is put in the
Stand-by Power mode. Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode
and execute instructions.
S
The device is first selected by driving Chip Select ( ) Low.
Then, the 8-bit instruction code for the instruction is shifted in.
Table 6. Read Identification (READ_ID) Data-Out Sequence
Manufacture Identification
Device Identification
Memory Capacity
15h
Manufacture ID
37h
Memory Type
30h
Figure 17. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9
10
13 14 15 16 17 18
21 22 23 24 25 26
29 30 31
C
Instruction
DIO
DO
23
21
18
16 15
13
14
10
8
7
6
5
2
1
0
22
17
9
High Impedance
Manufacture ID
Memory Type
Memory Capacity
(April, 2008, Version 0.0)
24
AMIC Technology Corp.
A25L016 Series
Read Electronic Manufacturer ID & Device ID (REMS)
The Read Electronic Manufacturer ID & Device ID (REMS)
instruction allows the 8-bit manufacturer identification code to
be read, followed by one byte of device identification. The
manufacturer identification is assigned by JEDEC, and has
the value 37h for AMIC. The device identification is assigned
by the device manufacturer, and has the value 15h for
A25L032, 14h for A25L016.
If the one-byte address is set to 01h, then the device ID will
be read first and then followed by the Manufacturer ID. On
the other hand, if the one-byte address is set to 00h, then the
Manufacturer ID will be read first and then followed by the
device ID.
The instruction sequence is shown in Figure 18. The Read
Electronic Manufacturer ID & Device ID (REMS) instruction is
Any Read Electronic Manufacturer ID & Device ID (REMS)
instruction while an Erase, or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in
progress.
S
terminated by driving Chip Select ( ) High at any time during
data output.
S
When Chip Select ( ) is driven High, the device is put in the
Stand-by Power mode. Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode
and execute instructions.
S
The device is first selected by driving Chip Select ( ) Low.
The 8-bit instruction code is followd by 2 dummy bytes and
one byte address(A7~A0), each bit being latched-in on Serial
Data Input (DIO) during the rising edge of Serial Clock (C).
Table 7. Read Electronic Manufacturer ID & Device ID (REMS) Data-Out Sequence
Manufacture Identification
Device Identification
37h
14h
Figure 18. Read Electronic Manufacturer ID & Device ID (REMS) Instruction Sequence and Data-Out Sequence
S
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23
C
DIO
DO
Instruction
2 Dummy Bytes
13 2 1
15
0
14
3
MSB
High Impedance
S
C
25 26 27 28 29 30 31 32
ADD(1)
24
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
7 6 5 4
3
2
0
1
DIO
Manufacturer ID
5 4
Device ID
5 4
3 2
0
1
1
DO
6
3 2
0
6
7
7
MSB
MSB
MSB
Notes:
(1) ADD=00h will output the manufacturer ID first and ADD=01h will output device ID first
(April, 2008, Version 0.0)
25
AMIC Technology Corp.
A25L016 Series
edge of Serial Clock (C). Then, the 8-bit Electronic Signature,
stored in the memory, is shifted out on Serial Data Output
(DO), each bit being shifted out during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 19.
The Release from Deep Power-down and Read Electronic
Signature (RES) instruction is terminated by driving Chip
Release from Deep Power-down and Read
Electronic Signature (RES)
Once the device has entered the Deep Power-down mode,
all instructions are ignored except the Release from Deep
Power-down and Read Electronic Signature (RES)
instruction. Executing this instruction takes the device out of
the Deep Power-down mode.
S
Select ( ) High after the Electronic Signature has been read
The instruction can also be used to read, on Serial Data
Output (DO), the 8-bit Electronic Signature, whose value for
the A25L032 is 15h, and for A25L016 is 14h.
at least once. Sending additional clock cycles on Serial Clock
S
(C), while Chip Select ( ) is driven Low, cause the
Electronic Signature to be output repeatedly.
Except while an Erase, Program or Write Status Register
cycle is in progress, the Release from Deep Power-down and
Read Electronic Signature (RES) instruction always provides
access to the 8-bit Electronic Signature of the device, and
can be applied even if the Deep Power-down mode has not
been entered.
S
When Chip Select ( ) is driven High, the device is put in the
Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by
Power mode is immediate. If the device was previously in the
Deep Power-down mode, though, the transition to the Stand-
Any Release from Deep Power-down and Read Electronic
Signature (RES) instruction while an Erase, Program or Write
Status Register cycle is in progress, is not decoded, and has
no effect on the cycle that is in progress.
S
by Power mode is delayed by tRES2, and Chip Select (
)
must remain High for at least tRES2 (max), as specified in AC
Characteristics Table . Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode
and execute instructions.
S
The device is first selected by driving Chip Select ( ) Low.
The instruction code is followed by 3 dummy bytes, each bit
being latched-in on Serial Data Input (DIO) during the rising
Figure 19. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and
Data-Out Sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
C
DIO
DO
tRES2
Instruction
3 Dummy Bytes
21
23
2
1
0
22
3
MSB
High Impedance
5
4
1
0
6
3
2
7
MSB
Deep Power-down Mode
Stand-by Mode
Note: The value of the 8-bit Electronic Signature is 14h.
(April, 2008, Version 0.0)
26
AMIC Technology Corp.
A25L016 Series
Figure 20. Release from Deep Power-down (RES) Instruction Sequence
S
tRES1
1
3
0
2
4
5
6
7
C
Instruction
DIO
High Impedance
DO
Deep Power-down Mode Stand-by Mode
previously in the Deep Power-down mode, though, the
transition to the Stand-by Power mode is delayed by tRES1
S
Driving Chip Select ( ) High after the 8-bit instruction byte
has been received by the device, but before the whole of the
8-bit Electronic Signature has been transmitted for the first
time (as shown in Figure 20.), still insures that the device is
put into Stand-by Power mode. If the device was not pre-
viously in the Deep Power-down mode, the transition to the
Stand-by Power mode is immediate. If the device was
,
S
and Chip Select ( ) must remain High for at least tRES1 (max),
as specified in AC Characteristics Table. Once in the
Stand-by Power mode, the device waits to be selected, so
that it can receive, decode and execute instructions.
(April, 2008, Version 0.0)
27
AMIC Technology Corp.
A25L016 Series
POWER-UP AND POWER-DOWN
-
tPUW after VCC passed the VWI threshold
tVSL afterVCC passed the VCC(min) level
At Power-up and Power-down, the device must not be
S
selected (that is Chip Select ( ) must follow the voltage
These values are specified in Table 8.
If the delay, tVSL, has elapsed, after VCC has risen above
applied on VCC) until VCC reaches the correct value:
VCC (min) at Power-up, and then for a further delay of tVSL
VSS at Power-down
V
CC(min), the device can be selected for READ instructions
even if the tPUW delay is not yet fully elapsed.
At Power-up, the device is in the following state:
S
Usually a simple pull-up resistor on Chip Select ( ) can be
used to insure safe and proper Power-up and Power-down.
To avoid data corruption and inadvertent write operations
during power up, a Power On Reset (POR) circuit is included.
The logic inside the device is held reset while VCC is less than
the POR threshold value, VWI – all operations are disabled,
and the device does not respond to any instruction.
The device is in the Standby mode (not the Deep
Power-down mode).
The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail decoupling,
to stabilize the VCC feed. Each device in a system should
have the VCC rail decoupled by a suitable capacitor close to
the package pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when VCC drops from the operating voltage,
to below the POR threshold value, VWI, all operations are
disabled and the device does not respond to any instruction.
(The designer needs to be aware that if a Power-down occurs
while a Write, Program or Erase cycle is in progress, some
data corruption can result.)
Moreover, the device ignores all Write Enable (WREN), Page
Program (PP), Sector Erase (SE), Block Erase (BE), Chip
Erase (CE) and Write Status Register (WRSR) instructions
until a time delay of tPUW has elapsed after the moment that
VCC rises above the VWI threshold. However, the correct
operation of the device is not guaranteed if, by this time, VCC
is still below VCC(min). No Write Status Register, Program or
Erase instructions should be sent until the later of:
Figure 21. Power-up Timing
VCC
VCC(max)
VCC(min)
tPU
Full Device Access
time
(April, 2008, Version 0.0)
28
AMIC Technology Corp.
A25L016 Series
Table 8. Power-Up Timing
Symbol
Parameter
Min.
2.7
5
Max.
Unit
V
VCC(min)
tPU
VCC (minimum)
VCC (min) to device operation
ms
Note: These parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains
00h (all Status Register bits are 0).
(April, 2008, Version 0.0)
29
AMIC Technology Corp.
A25L016 Series
Absolute Maximum Ratings*
*Comments
Stressing the device above the rating listed in the Absolute
Maximum Ratings" table may cause permanent damage to
the device. These are stress ratings only and operation of
the device at these or any other conditions above those
indicated in the Operating sections of this specification is not
implied. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability. Refer also
to the AMIC SURE Program and other relevant quality docu-
ments.
Storage Temperature (TSTG) . . . . . . . . . . -65°C to + 150°C
Lead Temperature during Soldering (Note 1)
D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to VCC+0.6V
Transient Voltage (<20ns) on Any Pin to Ground Potential . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VCC+2.0V
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . -0.6V to +4.0V
Electrostatic Discharge Voltage (Human Body model)
(VESD) (Note 2) . . . . . . . . . . . . . . . . . . . -2000V to 2000V
Notes:
1. Compliant with JEDEC Std J-STD-020B (for small body,
Sn-Pb or Pb assembly).
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500Ω,
R2=500Ω)
DC AND AC PARAMETERS
This section summarizes the operating and measurement
conditions, and the DC and AC characteristics of the device.
The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the
Measurement Conditions summarized in the relevant tables.
Designers should check that the operating conditions in their
circuit match the measurement conditions when relying on
the quoted parameters.
Table 9. Operating Conditions
Symbol
VCC
Parameter
Min.
2.7
Max.
3.6
Unit
V
Supply Voltage
Ambient Operating Temperature
TA
–40
85
°C
Table 10. Data Retention and Endurance
Parameter
Condition
Min.
Max.
Unit
Erase/Program Cycles
At 85°C
At 85°C
100,000
Cycles per Sector
Years
Data Retention
20
Note: 1. This is preliminary data
Table 11. Capacitance
Symbol
COUT
Parameter
Test Condition
Min.
Max.
Unit
pF
Output Capacitance (DO)
VOUT = 0V
VIN = 0V
8
6
CIN
Input Capacitance (other pins)
pF
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 33 MHz.
(April, 2008, Version 0.0)
30
AMIC Technology Corp.
A25L016 Series
Table 12. DC Characteristics
Symbol
Parameter
Test Condition
Min.
Max.
Unit
ILI
Input Leakage Current
Output Leakage Current
Standby Current
± 2
± 2
5
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
V
ILO
ICC1
ICC2
S
S
= VCC, VIN = VSS or VCC
= VCC, VIN = VSS or VCC
Deep Power-down Current
5
C= 0.1VCC / 0.9.VCC at 50MHz, DO = open
C= 0.1VCC / 0.9.VCC at 33MHz, DO = open
30
ICC3
Operating Current (READ)
25
ICC4
ICC5
ICC6
ICC7
VIL
Operating Current (PP)
Operating Current (WRSR)
Operating Current (SE)
Operating Current (BE)
Input Low Voltage
15
S
S
S
S
= VCC
= VCC
= VCC
= VCC
15
15
15
–0.5
0.3VCC
VIH
Input High Voltage
0.7VCC
VCC+0.4
0.4
V
V
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 1.6mA
IOH = –100µA
VCC–0.2
Note: 1. This is preliminary data at 85°C
Table 13. Instruction Times
Symbol
Alt.
Parameter
Write Status Register Cycle Time
Page Program Cycle Time
Sector Erase Cycle Time
Min.
Typ.
5
Max.
15
Unit
ms
ms
s
tW
tPP
0.8
0.06
0.5
16
2.4
0.24
2
tSE
tBE
Block Erase Cycle Time
s
tCE
Chip Erase Cycle Time
64
s
Note: 1. At 85°C
2. This is preliminary data
Table 14. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
CL
Load Capacitance
30
Input Rise and Fall Times
Input Pulse Voltages
5
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
VCC / 2
Input Timing Reference Voltages
Output Timing Reference Voltages
V
V
Note: Output Hi-Z is defined as the point where data out is no longer driven.
(April, 2008, Version 0.0)
31
AMIC Technology Corp.
A25L016 Series
Figure 22. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.2VCC
0.7VCC
0.5VCC
0.3VCC
(April, 2008, Version 0.0)
32
AMIC Technology Corp.
A25L016 Series
Table 15. AC Characteristics
Alt.
Parameter
Min.
Typ.
Max.
Unit
Symbol
fC
fC
Clock Frequency for the following instructions: FAST_READ,
PP, SE, BE, DP, RES, RDID, WREN, WRDI, RDSR, WRSR
D.C.
100
MHz
fR
tCH
tCL
Clock Frequency for READ instructions
Clock High Time
D.C.
6
50
MHz
ns
1
1
tCLH
tCLL
Clock Low Time
5
ns
2
2
tCLCH
tCHCL
tSLCH
Clock Rise Time3 (peak to peak)
Clock Fall Time3 (peak to peak)
0.1
0.1
5
V/ns
V/ns
ns
tCSS
S
S
Active Setup Time (relative to C)
Not Active Hold Time (relative to C)
tCHSL
5
ns
tDVCH
tCHDX
tCHSH
tDSU
tDH
Data In Setup Time
Data In Hold Time
5
5
5
ns
ns
ns
S
S
S
Active Hold Time (relative to C)
Not Active Setup Time (relative to C)
Deselect Time
tSHCH
tSHSL
5
ns
ns
tCSH
100
2
tSHQZ
tCLQV
tCLQX
tHLCH
tDIS
tV
Output Disable Time
Clock Low to Output Valid
Output Hold Time
8
8
ns
ns
ns
ns
tHO
0
5
Setup Time (relative to C)
HOLD
HOLD
tCHHH
5
ns
Hold Time (relative to C)
tHHCH
tCHHL
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD to Output Low-Z
5
5
ns
ns
ns
ns
2
tHHQX
tLZ
8
8
2
tHLQZ
tHZ
to Output High-Z
HOLD
4
4
tWHSL
tSHWL
Write Protect Setup Time
Write Protect Hold Time
20
ns
ns
µs
100
2
tDP
3
S
S
S
High to Deep Power-down Mode
2
2
tRES1
tRES2
30
30
µs
µs
High to Standby Mode without Electronic Signature Read
High to Standby Mode with Electronic Signature Read
tW
tpp
tSE
tBE
tCE
Write Status Register Cycle Time
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase Cycle Time
Chip Erase Cycle Time
5
15
2.4
0.24
2
ms
ms
s
0.8
0.06
0.5
16
s
64
s
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
(April, 2008, Version 0.0)
33
AMIC Technology Corp.
A25L016 Series
Figure 23. Serial Input Timing
tSHSL
tSHCH
S
tCHSL
tSLCH
tCHSH
C
tCHCL
tDVCH
tCLCH
tCHDX
DIO
DO
MSB IN
LSB IN
High Impedance
Figure 24. Write Protect Setup and Hold Timing during WRSR when SRWD=1
W
tSHWL
tWHSL
S
C
DIO
High Impedance
DO
(April, 2008, Version 0.0)
34
AMIC Technology Corp.
A25L016 Series
Figure 25. Hold Timing
S
tHLCH
tCHHH
tCHHL
tHHCH
C
DIO
tHLQZ
tHHQX
DO
HOLD
Figure 26. Output Timing
S
C
tCH
ADDR.LSB IN
DIO
tCL
tSHQZ
tCLQV
tCLQV
tCLQX
DO
tCLQX
LSB OUT
tQLQH
tQHQL
(April, 2008, Version 0.0)
35
AMIC Technology Corp.
A25L016 Series
Part Numbering Scheme
X XXX X X X
X
A25
Package Material
Blank: normal
F: PB free
Temperature*
Blank = 0°C ~ +70°C
U = -40°C ~ +85°C
Package Type
Blank = DIP8
M = 209 mil SOP 8
N = 300 mil SOP 16
Device Version*
Blank = The first version
Device Density
512 = 512 Kbit (4KB uniform sectors)
010 = 1 Mbit (4KB uniform sectors)
020 = 2 Mbit (4KB uniform sectors)
040 = 4 Mbit (4KB uniform sectors)
080 = 8 Mbit (4KB uniform sectors)
016 = 16 Mbit (4KB uniform sectors)
032 = 32 Mbit (4KB uniform sectors)
Device Voltage
L = 2.7-3.6V
Device Type
A25 = AMIC Serial Flash
* Optional
(April, 2008, Version 0.0)
36
AMIC Technology Corp.
A25L016 Series
Ordering Information
Part No.
Speed (MHz)
Active Read
Current
Program/Erase Standby Current
Package
Current
Typ. (μA)
Typ. (mA)
Typ. (mA)
A25L016-F
8 Pin Pb-Free DIP (300 mil)
8 Pin Pb-Free DIP (300 mil)
8 Pb-Free Pin SOP (209mil)
8 Pb-Free Pin SOP (209mil)
16 Pb-Free Pin SOP (300mil)
16 Pb-Free Pin SOP (300mil)
A25L016-UF
A25L016M-F
A25L016M-UF
A25L016N-F
A25L016N-UF
100
30
15
5
Blank is for commercial operating temperature range: 0°C ~ +70°C
-U is for industrial operating temperature range: -40°C ~ +85°C
(April, 2008, Version 0.0)
37
AMIC Technology Corp.
A25L016 Series
Package Information
P-DIP 8L Outline Dimensions
unit: inches/mm
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
0.180
-
Min
Nom
Max
A
-
-
-
-
-
4.57
-
A1
A2
0.015
0.128
0.38
3.25
0.130
0.136
3.30
3.45
B
0.014
0.050
0.032
0.018
0.060
0.039
0.022
0.070
0.046
0.36
1.27
0.81
0.46
1.52
0.99
0.56
1.78
1.17
B1
B2
C
D
0.008
0.350
0.010
0.360
0.013
0.370
0.20
8.89
0.25
9.14
0.33
9.40
E
E1
e1
L
0.290
0.254
-
0.300
0.260
0.100
-
0.315
0.266
-
7.37
6.45
-
7.62
6.60
2.54
-
8.00
6.76
-
0.125
0.345
0.016
-
3.18
8.76
0.41
-
EA
S
-
0.385
0.026
-
9.78
0.66
0.021
0.53
Notes:
1. Dimension D and E1 do not include mold flash or protrusions.
2. Dimension B1 does not include dambar protrusion.
3. Tolerance: ±0.010” (0.25mm) unless otherwise specified.
(April, 2008, Version 0.0)
38
AMIC Technology Corp.
A25L016 Series
Package Information
SOP 8L (209mil) Outline Dimensions
unit: mm
8
5
1
4
C
D
GAGE PLANE
SEATING PLANE
θ
e
b
L
Dimensions in mm
Symbol
Min
1.75
0.05
1.70
0.35
0.19
5.13
7.70
5.18
Nom
1.95
0.15
1.80
0.42
0.20
5.23
7.90
5.28
1.27 BSC
0.65
-
Max
2.16
A
A1
A2
b
0.25
1.91
0.48
0.25
5.33
8.10
5.38
C
D
E
E1
e
L
0.50
0°
0.80
8°
θ
Notes:
Maximum allowable mold flash is 0.15mm at the package
ends and 0.25mm between leads
(April, 2008, Version 0.0)
39
AMIC Technology Corp.
A25L016 Series
Package Information
SOP 16L (300mil) Outline Dimensions
unit: inches/mm
D
C
9
16
o
1
8
e
b
SEATING PLANE
θ
0.10
C
L
Dimensions in inch
Dimensions in mm
Symbol
Min
Max
Min
Max
2.65
A
A1
b
0.104
2.36
0.093
0.004
0.012
0.10
0.30
0.016 Typ.
0.008 Typ.
0.41 Typ.
0.20 Typ.
C
D
E
e
0.398
0.413
0.299
10.10
10.50
7.60
0.291
7.39
0.050 Typ.
1.27 Typ.
H
L
0.394
0.016
0°
0.419
0.050
8°
10.01
0.40
0°
10.64
1.27
8°
θ
Notes:
1. Dimensions “D” does not include mold flash, protrusions or
gate burrs.
2. Dimensions “E” does not include interlead flash, or protrusions.
(April, 2008, Version 0.0)
40
AMIC Technology Corp.
相关型号：
©2020 ICPDF网 联系我们和版权申明