A29DL322UG-90IF_技术文档

A29DL32x Series

32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only,

Simultaneous Operation Flash Memory

Document Title

4M X 8 Bit / 2M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory

Revision History

Rev. No. History

Issue Date

May 25, 2005

June 5, 2006

July 6, 2006

Remark

0.0

0.1

0.2

Initial issue

Preliminary

Error Correction: Page 4 Block, Page 13 Table-17

Change Table 1 &Program/Erasure time

Add Pb-Free package type

1.0

1.1

1.2

Final revision release

January 5, 2007

April 11, 2007

Final

Modify toggle bit mechanism

Modify symbol “L” outline dimensions in TSOP 48L package

November 16, 2007

(November, 2007, Version 1.2)

AMIC Technology, Corp.

A29DL32x Series

32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only,

Simultaneous Operation Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

Simultaneous Read/Write operations

- Regulated voltage range: 2.7 to 3.6 volt read and write

operations for compatibility with high performance 3 volt

microprocessors

SOFTWARE FEATURES

Supports Common Flash Memory Interface (CFI)

Erase Suspend/Erase Resume

- Suspends erase operations to allow programming in

same bank

- Data can be continuously read from one bank while

executing erase/program functions in other bank

- Zero latency between read and write operations

Multiple bank architectures

- Three devices available with different bank sizes (refer to

Table 2)

Package options

Software temporary sector block unprotect command

Software sector protect/unprotect command

Polling and Toggle Bits

Data

- Provides a software method of detecting the status of

program or erase cycles

Unlock Bypass Program command

- Reduces overall programming time when issuing

multiple program command sequences

- 48-ball TFBGA

- 48-pin TSOP

- All Pb-free (Lead-free) products are RoHS compliant

Top or bottom boot block

HARDWARE FEATURES

Any combination of sectors can be erased

Manufactured on 0.18 µm process technology

- Compatible with AMD AM29DL32xD device

Compatible with JEDEC standards

- Pinout and software compatible with single-power-supply

flash standard

Ready/

output (RY/

)

BY

Busy

- Hardware method for detecting program or erase cycle

completion

Hardware reset pin (

)

RESET

- Hardware method of resetting the internal state machine

to reading array data

PERFORMANCE CHARACTERISTICS

High performance

/ACC input pin

WP

- Access time as fast as 70ns

- Program time: 6µs/word typical utilizing Accelerate

function

- Write protect (

) function allows protection of two

WP

outermost boot sectors, regardless of sector protect

status

Ultra low power consumption (typical values)

- 2mA active read current at 1MHz

- 10mA active read current at 5MHz

- 500nA in standby or automatic sleep mode

Typical 100,000 write cycles guaranteed per sector

20 Year data retention at 125°C

- Reliable operation for the life of the system

- Acceleration (ACC) function accelerates program timing

Sector protection

- Hardware method of locking a sector, either in-system or

using programming equipment, to prevent any program

or erase operation within that sector

- Temporary Sector Unprotect allows changing data in

protected sectors in-system

(November, 2007, Version 1.2)

1

AMIC Technology, Corp.

A29DL32x Series

GENERAL DESCRIPTION

A29DL32x Features

The A29DL32x family consists of 32 megabit, 3.0 volt-only

flash memory devices, organized as 2,097,152 words of 16

bits each or 4,194,304 bytes of 8 bits each. Word mode data

appears on I/O⁰–I/O15; byte mode data appears on I/O0–I/O7.

The device is designed to be programmed in-system with the

standard 3.0 volt VCC supply, and can also be programmed

in standard EPROM programmers.

The device offers complete compatibility with the JEDEC

single-power-supply Flash command set standard.

Commands are written to the command register using

standard microprocessor write timings. Reading data out of

the device is similar to reading from other Flash or EPROM

devices.

The device is available with an access time of 70, 80, 90, or

120 ns. The devices are offered in 48-pin TSOP and 48-ball

The host system can detect whether a program or erase

operation is complete by using the device status bits:

Fine-pitch TFBGA. Standard control pins—chip enable (

),

RY/

pin, I/O7 (

BY

Polling) and I/O6/I/O2 (toggle bits).

Data

CE

After a program or erase cycle has been completed, the

device automatically returns to reading array data.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data

contents of other sectors. The device is fully erased when

shipped from the factory.

Hardware data protection measures include a low VCC

detector that automatically inhibits write operations during

power transitions. The hardware sector protection feature

disables both program and erase operations in any

combination of the sectors of memory. This can be achieved

write enable (

), and output enable (

OE

)—control

WE

normal read and write operations, and avoid bus contention

issues.

The device requires only a single 3.0 volt power supply for

both read and write functions. Internally generated and

regulated voltages are provided for the program and erase

operations.

Simultaneous Read/Write Operations with Zero

Latency

The Simultaneous Read/Write architecture provides

in-s y s t e m or via programming equipment.

simultaneous operation by dividing the memory space into

The device offers two power-saving features. When

addresses have been stable for a specified amount of time,

the device enters the automatic sleep mode. The system

can also place the device into the standby mode. Power

consumption is greatly reduced in both modes.

two banks. The device can improve overall system

performance by allowing a host system to program or erase

in one bank, then immediately and simultaneously read from

the other bank, with zero latency. This releases the system

from waiting for the completion of program or erase

operations.

The A29DL32x devices use multiple bank architectures to

provide flexibility for different applications. Three devices are

available with these bank sizes:

Device

DL322

DL323

DL324

Bank 1

4 Mb

Bank 2

28 Mb

24 Mb

16 Mb

8 Mb

16 Mb

(November, 2007, Version 1.2)

2

AMIC Technology, Corp.

A29DL32x Series

Pin Configurations

TSOP (I)

A15

A14

A13

A12

A11

A10

A9

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

A16

2

BYTE

VSS

I/O¹⁵(A-1)

3

4

5

I/O⁷

I/O¹⁴

I/O₆

I/O¹³

I/O⁵

6

7

A8

8

9

A19

A20

10

11

12

13

14

15

16

17

I/O₁₂

I/O⁴

VCC

I/O₁₁

I/O³

I/O¹⁰

I/O₂

I/O⁹

WE

RESET

NC

A29DL32xV

WP/ACC

RY/BY

A18

A17

A7

18

19

31

30

I/O¹

I/O⁸

I/O₀

A6

A5

A4

A3

A2

A1

20

21

22

23

24

29

28

27

26

25

OE

VSS

CE

A0

TFBGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16

BYTE

I/O15(A-1) VSS

G5

A5

B5

C5

D5

E5

F5

H5

A9

A8

A10

A11

I/O⁷

I/O14

I/O13

I/O6

A4

B4

C4

D4

E4

F4

G4

H4

WE

RESET

NC

A19

I/O5

I/O12

VCC

I/O4

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY WP/ACC

A18

A20

I/O2

I/O10

I/O11

I/O3

A2

B2

C2

A6

D2

A5

E2

F2

G2

H2

A7

A17

I/O0

I/O8

I/O9

I/O1

A1

B1

C1

A2

D1

A1

E1

F1

G1

H1

A3

A4

A0

VSS

CE

OE

(November, 2007, Version 1.2)

3

AMIC Technology, Corp.

A29DL32x Series

Block Diagram

VCC

VSS

OE BYTE

Upper Bank Address

A0-A20

Upper Bank

X-Decoder

RY/BY

A0-A20

STATE

CONTROL

&

COMMAND

REGISTER

RESET

WE

CE

BYTE

WP/ACC

Status

I/O0-I/O15

Control

I/O0-I/O15

X-Decoder

Lower Bank

Lower Bank Address

A0-A20

OE BYTE

Pin Descriptions

Logic Symbol

Pin No.

A0 – A20

I/O0 - I/O14

Description

Address Inputs

21

Data Inputs/Outputs

A0-A20

Data Input/Output, Word Mode

I/O15

16 or 8

I/O15 (A-1)

A-1 LSB Address Input, Byte Mode

Chip Enable

I/O0-I/O15(A-1)

CE

WE

OE

Write Enable

Output Enable

CE

OE

Hardware Write Protect/Acceleration Pin

Hardware Reset Pin, Active Low

/ACC

WP

WE

RESET

BYTE

RY/BY

WP/ACC

RESET

BYTE

Selects 8-bit or 16-bit Mode

Ready/

Ground

Output

BUSY

RY/

BY

VSS

VCC

NC

3.0 volt-only single power supply

Pin Not Connected Internally

(November, 2007, Version 1.2)

4

AMIC Technology, Corp.

A29DL32x Series

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register itself does

not occupy any addressable memory location. The register is

composed of latches that store the commands, along with

the address and data information needed to execute the

command. The contents of the register serve as inputs to the

internal state machine. The state machine outputs dictate the

function of the device. The appropriate device bus operations

table lists the inputs and control levels required, and the

resulting output. The following subsections describe each of

these operations in further detail.

Table 1. A29DL32x Device Bus Operations

Operation

A0 – A20

(Note 1)

I/O0 - I/O7

I/O⁸- I/O15

=VIH

/ACC

WP

WE

CE

OE

RESET

=VIL

BYTE

Read

L

H

L

H

L/H

AIN

DOUT

DIN

DOUT

DIN

I/O8~I/O15=High-Z

I/O8~I/O14=High-Z

I/O¹⁵=A-1

Write

H

(Note 3)

Standby

X

H

X

High-Z

VCC ±

0.3 V

VCC ±

0.3 V

Output Disable

Reset

L

X

L

H

X

H

X

L

H

L

L/H

X

High-Z

D^IN

High-Z

X

High-Z

X

Sector Protect

(See Note 2)

V^ID

SA, A6=L,

A1=H, A0=L

Sector Unprotect

(See Note 2)

L

H

X

L

V^ID

L/H

SA, A6=H,

A1=H, A0=L

D^IN

X

Temporary Sector

Unprotect

X

AIN

DIN

High-Z

Legend:

L = Logic Low = V^IL, H = Logic High = VIH, VID = 8.5V-10.5V, VHH = 8.5V-10.5V, X = Don’t Care, SA = Sector Address, AIN =

Address In, D^IN= Data In, DOUT = Data Out

Notes:

1. Addresses are A20:A0 in word mode (

=VIH), A20: A-1 in byte mode (

=VIL).

BYTE

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the

“Sector/Sector Block Protection and Unprotection” section.

3. If

/ACC = VIL, the two outermost boot sectors remain protected. If

/ACC = VIH, the two outermost boot sector

WP

protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block

Protection and Unprotection”. If

/ACC = VHH all sectors will be unprotected.

WP

(November, 2007, Version 1.2)

5

AMIC Technology, Corp.

A29DL32x Series

Accelerated Program Operation

Word/Byte Configuration

The device offers accelerated program operations through

the ACC function. This is one of two functions provided by

The

pin determines whether the I/O pins I/O15-I/O0

BYTE

operate in the byte or word configuration. If the

pin is

BYTE

set at logic ”1”, the device is in word configuration, I/O¹⁵-I/O0

are active and controlled by and

the

/ACC pin. This function is primarily intended to allow

WP

faster manufacturing throughput at the factory.

.

OE

CE

If the system asserts VHH on this pin, the device automatically

enters the aforementioned Unlock Bypass mode, temporarily

unprotects any protected sectors, and uses the higher

voltage on the pin to reduce the time required for program

operations. The system would use a two-cycle program

command sequence as required by the Unlock Bypass

If the

pin is set at logic “0”, the device is in byte

BYTE

configuration, and only I/O⁰-I/O7 are active and controlled by

and . I/O8-I/O14 are tri-stated, and I/O15 pin is used

CE

OE

as an input for the LSB(A-1) address function.

mode. Removing V^HHfrom the

/ACC pin returns the

WP

Requirements for Reading Array Data

device to normal operation. Note that the

not be at V^HHfor operations other than accelerated program-

ming, or device damage may result. In addition, the

/ACC pin must

WP

To read array data from the outputs, the system must drive

the

and

pins to VIL.

is the power control and

CE

OE

CE

/ACC pin must not be left floating or unconnected;

inconsistent behavior of the device may result.

WP

selects the device.

OE

data to the output pins.

is the output control and gates array

should remain at VIH. The

WE

Autoselect Functions

pin determines whether the device outputs array data

in words or bytes.

BYTE

If the system writes the autoselect command sequence, the

device enters the autoselect mode. The system can then

read autoselect codes from the internal register (which is

separate from the memory array) on I/O⁷-I/O0. Standard read

cycle timings apply in this mode. Refer to the Autoselect

Mode and Autoselect Command Sequence sections for more

information.

The internal state machine is set for reading array data upon

device power-up, or after a hardware reset. This ensures that

no spurious alteration of the memory content occurs during

the power transition. No command is necessary in this mode

to obtain array data. Standard microprocessor read cycles

that assert valid addresses on the device address inputs

produce valid data on the device data outputs. Each bank

remains enabled for read access until the command register

contents are altered.

Simultaneous Read/Write Operations with Zero

Latency

See "Requirements for Reading Array Data" for more

information. Refer to the AC Read-Only Operations table for

timing specifications and to Figure 11 for the timing

waveform, l^CC1in the DC Characteristics table represents the

active current specification for reading array data.

This device is capable of reading data from one bank of

memory while programming or erasing in the other bank of

memory. An erase operation may also be suspended to read

from or program to another location within the same bank

(except the sector being erased). Figure 18 shows how read

and write cycles may be initiated for simultaneous operation

with zero latency. I^CC6and ICC7 in the DC Characteristics

table represent the current specifications for read-while-pro-

gram and read-while-erase, respectively.

Writing Commands/Command Sequences

To write a command or command sequence (which includes

programming data to the device and erasing sectors of

memory), the system must drive

and

to VIL, and

CE

WE

Standby Mode

to VIH.

OE

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode,

current consumption is greatly reduced, and the outputs are

For program operations, the

the device accepts program data in bytes or words, Refer to

“Word/Byte Configuration” for more information.

pin determines whether

BYTE

placed in the high impedance state, independent of the

input.

OE

The device features an Unlock Bypass mode to facilitate

faster programming. Once a bank enters the Unlock Bypass

mode, only two write cycles are required to program a word

or byte, instead of four. The “Word / Byte Program Command

Sequence” section has details on programming data to the

device using both standard and Unlock Bypass command

sequence.

An erase operation can erase one sector, multiple sectors, or

the entire device. The Sector Address Tables 3-4 indicate the

address range that each sector occupies. The device

address space is divided into two banks: Bank 1 contains the

boot/parameter sectors, and Bank 2 contains the larger, code

sectors of uniform size. A “bank address” is the address bits

required to uniquely select a bank. Similarly, a “sector

address” is the address bits required to uniquely select a

sector.

The device enters the CMOS standby mode when the

&

CE

pins are both held at VCC ± 0.3V. (Note that this is a

RESET

more restricted voltage range than V^IH.) If

and

CE

RESET

are held at V^IH, but not within VCC ± 0.3V, the device will be

in the standby mode, but the standby current will be greater.

The device requires the standard access time (tCE) for read

access when the device is in either of these standby modes,

before it is ready to read data.

If the device is deselected during erasure or programming,

the device draws active current until the operation is

completed.

ICC3 in the DC Characteristics tables represent the standby

current specification.

I^CC2in the DC Characteristics table represents the active

current specification for the write mode. The "AC

Characteristics" section contains timing specification tables

and timing diagrams for write operations.

(November, 2007, Version 1.2)

6

AMIC Technology, Corp.

A29DL32x Series

The

pin may be tied to the system reset circuitry. A

RESET

Automatic Sleep Mode

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from the

Flash memory.

The automatic sleep mode minimizes Flash device energy

consumption. The device automatically enables this mode

when addresses remain stable for t^ACC+30ns. The automatic

If

is asserted during a program or erase operation,

RESET

sleep mode is independent of the

,

and

control

OE

WE

CE

the RY/

pin remains a “0” (busy) until the internal reset

BY

signals. Standard address access timings provide new data

when addresses are changed. While in sleep mode, output

data is latched and always available to the system. I^CC4in the

DC Characteristics table represents the automatic sleep

mode current specification.

operation is complete, which requires a time t^READY(during

Embedded Algorithms). The system can thus monitor

RY/

BY

complete. If

to determine whether the reset operation is

is asserted when a program or erase

RESET

operation is not executing (RY/

operation is completed within a time of t^READY(not during

Embedded Algorithms). The system can read data t^RHafter

pin is “1”), the reset

BY

: Hardware Reset Pin

RESET

The

pin provides a hardware method of resetting

RESET

the device to reading array data. When the system drives the

pin low for at least a period of tRP, the device

the

pin return to VIH.

RESET

Refer to the AC Characteristics tables for

parameters and diagram.

RESET

immediately terminates any operation in progress, tristates

all data output pins, and ignores all read/write attempts for

Output Disable Mode

the duration of the

pulse. The device also resets the

RESET

When the

input is at VIH, output from the device is

OE

internal state machine to reading array data. The operation

that was interrupted should be reinitiated once the device is

ready to accept another command sequence, to ensure data

integrity.

disabled. The output pins are placed in the high impedance

state.

Current is reduced for the duration of the

pulse.

RESET

When

is held at VSS ± 0.3V, the device draws

RESET

CMOS standby current (I^CC4). If

is held at VIL but not

RESET

within VSS ± 0.3V, the standby current will be greater.

Table 2. A29DL32x Device Bank Divisions

Device

Part Number

Bank 1

Sector Sizes

Bank 2

Sector Sizes

Megabits

Eight 8 Kbyte/4 Kword,

seven 64 Kbyte/32 Kword

Fifty-six

64 Kbyte/32 Kword

A29DL322

4 Mbit

28 Mbit

Eight 8 Kbyte/4 Kword,

fifteen 64 Kbyte/32 Kword

Forty-eight

64 Kbyte/32 Kword

A29DL323

A29DL324

8 Mbit

24 Mbit

16 Mbit

Eight 8 Kbyte/4 Kword,

Thirty one 64 Kbyte/32 Kword

Thirty-two

64 Kbyte/32 Kword

16 Mbit

(November, 2007, Version 1.2)

7

AMIC Technology, Corp.

A29DL32x Series

Table 3 Sector Addresses for Top Boot Sector Devices

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Sector

Address Range

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

000000XXX

000001XXX

000010XXX

000011XXX

000100XXX

000101XXX

000110XXX

000111XXX

001000XXX

001001XXX

001010XXX

001011XXX

001100XXX

001101XXX

001110XXX

001111XXX

010000XXX

010001XXX

010010XXX

010011XXX

010100XXX

010101XXX

010110XXX

010111XXX

011000XXX

011001XXX

011010XXX

011011XXX

011100XXX

011101XXX

011110XXX

011111XXX

100000XXX

100001XXX

100010XXX

100011XXX

100100XXX

100101XXX

100110XXX

100111XXX

101000XXX

101001XXX

101010XXX

101011XXX

101100XXX

101101XXX

101110XXX

101111XXX

64/32

000000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

260000h-26FFFFh

270000h-27FFFFh

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

000000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–1FFFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

(November, 2007, Version 1.2)

8

AMIC Technology, Corp.

A29DL32x Series

Table 3 Sector Addresses for Top Boot Sector Devices

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Sector

Address Range

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

110000XXX

110001XXX

110010XXX

110011XXX

110100XXX

110101XXX

110110XXX

110111XXX

111000XXX

111001XXX

111010XXX

111011XXX

111100XXX

111101XXX

111110XXX

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

64/32

8/4

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

3F2000h-3F3FFFh

3F4000h-3F5FFFh

3F6000h-3F7FFFh

3F8000h-3F9FFFh

3FA000h-3FBFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1F8FFFh

1F9000h–1F9FFFh

1FA000h–1FAFFFh

1FB000h–1FBFFFh

1FC000h–1FCFFFh

1FD000h–1FDFFFh

3FC000h-3FDFFFh 1FE000h–1FEFFFh

3FE000h-3FFFFFh 1FF000h–1FFFFFh

The address range is A20: A-1in byte mode (

A18 for A29DL322T, A20 and A19 for A29DL323T, and A20 for A29DL324T.

=VIL) or A20:A0 in word mode (

=VIH). The bank address bits are A20-

BYTE

(November, 2007, Version 1.2)

9

AMIC Technology, Corp.

A29DL32x Series

Table 4. Sector Addresses for Bottom Boot Sector Devices

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Sector

Address Range

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

000000000

000000001

000000010

000000011

000000100

000000101

000000110

000000111

000001XXX

000010XXX

000011XXX

000100XXX

000101XXX

000110XXX

000111XXX

001000XXX

001001XXX

001010XXX

001011XXX

001100XXX

001101XXX

001110XXX

001111XXX

010000XXX

010001XXX

010010XXX

010011XXX

010100XXX

010101XXX

010110XXX

010111XXX

011000XXX

011001XXX

011010XXX

011011XXX

011100XXX

011101XXX

011110XXX

011111XXX

100000XXX

100001XXX

100010XXX

100011XXX

100100XXX

100101XXX

100110XXX

100111XXX

101000XXX

8/4

000000h-001FFFh

002000h-003FFFh

004000h-005FFFh

006000h-007FFFh

008000h-009FFFh

00A000h-00BFFFh

00C000h-00DFFFh

00E000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

260000h-26FFFFh

270000h-27FFFFh

280000h-28FFFFh

000000h-000FFFh

001000h-001FFFh

002000h-002FFFh

003000h-003FFFh

004000h-004FFFh

005000h-005FFFh

006000h-006FFFh

007000h-007FFFh

008000h-00FFFFh

010000h-017FFFh

018000h-01FFFFh

020000h-027FFFh

028000h-02FFFFh

030000h-037FFFh

038000h-03FFFFh

040000h-047FFFh

048000h-04FFFFh

050000h-057FFFh

058000h-05FFFFh

060000h-067FFFh

068000h-06FFFFh

070000h-077FFFh

078000h-07FFFFh

080000h-087FFFh

088000h-08FFFFh

090000h-097FFFh

098000h-09FFFFh

0A0000h-0A7FFFh

0A8000h-0AFFFFh

0B0000h-0B7FFFh

0B8000h-0BFFFFh

0C0000h-0C7FFFh

0C8000h-0CFFFFh

0D0000h-0D7FFFh

0D8000h-0DFFFFh

0E0000h-0E7FFFh

0E8000h-0EFFFFh

0F0000h-0F7FFFh

0F8000h-0FFFFFh

100000h-107FFFh

108000h-10FFFFh

110000h-117FFFh

118000h-11FFFFh

120000h-127FFFh

128000h-12FFFFh

130000h-137FFFh

138000h-13FFFFh

140000h-147FFFh

64/32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

(November, 2007, Version 1.2)

10

AMIC Technology, Corp.

A29DL32x Series

Table 4. Sector Addresses for Bottom Boot Sector Devices

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Sector

Address Range

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

101001XXX

101010XXX

101011XXX

101100XXX

101101XXX

101110XXX

101111XXX

110000XXX

110001XXX

110010XXX

110011XXX

110100XXX

110101XXX

110110XXX

110111XXX

111000XXX

111001XXX

111010XXX

111011XXX

111100XXX

111101XXX

111110XXX

111111XXX

64/32

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

148000h-14FFFFh

150000h-157FFFh

158000h-15FFFFh

160000h-167FFFh

168000h-16FFFFh

170000h-177FFFh

178000h-17FFFFh

180000h-187FFFh

188000h-18FFFFh

190000h-197FFFh

198000h-19FFFFh

1A0000h-1A7FFFh

1A8000h-1AFFFFh

1B0000h-1B7FFFh

1B8000h-1BFFFFh

1C0000h-1C7FFFh

1C8000h-1CFFFFh

1D0000h-1D7FFFh

1D8000h-1DFFFFh

1E0000h-1E7FFFh

1E8000h-1EFFFFh

1F0000h-1F7FFFh

1F8000h-1FFFFFh

Note:

The address range is A20: A-1in byte mode (

A18 for A29DL322U, A20 and A19 for A29DL323U, and A20 for A29DL324U.

=VIL) or A20:A0 in word mode (

=VIH). The bank address bits are A20-

BYTE

(November, 2007, Version 1.2)

11

AMIC Technology, Corp.

A29DL32x Series

Autoselect Mode

The autoselect mode provides manufacturer and device

identification, and sector protection verification, through

identifier codes output on I/O7 - I/O0. This mode is primarily

intended for programming equipment to automatically match

must appear on the appropriate highest order address bits.

(see Table 3-4). Table 5 shows the remaining address bits

that are don't care. When all necessary bits have been set as

required, the programming equipment may then read the

corresponding identifier code on I/O⁷- I/O0.

a

device to be programmed with its corresponding

programming algorithm. However, the autoselect codes can

also be accessed in-system through the command register.

When using programming equipment, the autoselect mode

requires V^ID(8.5V to 10.5 V) on address pin A9. Address

pins A6, A1, and A0 must be as shown in Table 5. In

addition, when verifying sector protection, the sector address

To access the autoselect codes in-system, the host system

can issue the autoselect command via the command

register, as shown in Table 12. This method does not require

VID. Refer to the Autoselect Command Sequence section for

more information.

Table 5. A29DL32x Autoselect Codes (High Voltage Method)

I/O8 to I/O15

A20

to

A12

A11

to

A10

A8

to

A7

A5

to

A4

I/O7

to

I/O0

Description

OE

A9

A6

A3 A2 A1 A0

CE

WE

BYTE BYTE

= VIH

= VIL

Manufacturer ID:

AMIC

L

H

BA

X

VID

X

L

X

L

X

L

X

L

H

X

37h

Device ID: A29DL322

Device ID: A29DL323

Device ID: A29DL324

22h

55h (T), 56h (U)

50h (T), 53h (U)

5Ch (T), 5Fh (U)

Continuation ID

L

H

X

VID

X

L

X

L

X

L

H

L

X

7Fh

01h (protected),

00h (unprotected)

Read Sector Status

SA

L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care, BA=Bank Address

Note: The autoselect codes may also be accessed in-system via command sequences.

(November, 2007, Version 1.2)

12

AMIC Technology, Corp.

A29DL32x Series

Sector/Sector Block Protection and Unprotection

(Note: For the following discussion, the term “sector” applies

to both sectors and sector blocks. A sector block consists of

two or more adjacent sectors that are protected or

unprotected at the same time (see Tables 6 and 7).

Table 7. Bottom Boot Sector/Sector Block Addresses for

Protection/Unprotection

Table 6. Top Boot Sector/Sector Block Addresses for

Protection/Unprotection

Sector /

Sector Block

Sector /

Sector Block

A20–A12

Sector / Sector Block Size

A20–A12

Sector / Sector Block Size

SA70

111111XXX

64 Kbytes

SA0

000000XXX

64 Kbytes

111110XXX

111101XXX

111100XXX

000001XXX

000010XXX

000011XXX

SA69- SA67

192 (3x64) Kbytes

SA1-SA3

192 (3x64) Kbytes

SA66- SA63

SA62- SA59

SA58- SA55

SA54- SA51

1110XXXXX

1101XXXXX

1100XXXXX

1011XXXXX

256 (4x64) Kbytes

SA4-SA7

SA8-SA11

0001XXXXX

0010XXXXX

0011XXXXX

0100XXXXX

0101XXXXX

0110XXXXX

0111XXXXX

1000XXXXX

1001XXXXX

1010XXXXX

1011XXXXX

1100XXXXX

1101XXXXX

1110XXXXX

256 (4x64) Kbytes

SA12-SA15

SA16-SA19

SA20-SA23

SA24-SA27

SA28-SA31

SA32-SA35

SA36-SA39

SA40-SA43

SA44-SA47

SA48-SA51

SA52-SA55

SA56-SA59

SA50- SA47

1010XXXXX

256 (4x64) Kbytes

SA46-SA43

SA42-SA39

SA38-SA35

SA34-SA31

SA30-SA27

SA26-SA23

SA22-SA19

SA18-SA15

SA14-SA11

1001XXXXX

1000XXXXX

0111XXXXX

0110XXXXX

0101XXXXX

0100XXXXX

0011XXXXX

0010XXXXX

0001XXXXX

256 (4x64) Kbytes

111100XXX

111101XXX

111110XXX

000001XXX

000010XXX

000011XXX

SA60-SA62

192 (3x64) Kbytes

SA10-SA8

192 (3x64) Kbytes

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

8 Kbytes

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

000000111

000000110

000000101

000000100

000000011

000000010

000000001

000000000

8 Kbytes

(November, 2007, Version 1.2)

13

AMIC Technology, Corp.

A29DL32x Series

The hardware sector protection feature disables both

program and erase operations in any sector. The hardware

sector unprotection feature re-enables both program and

erase operations in previously protected sectors. Sector

protection and unprotection can be implemented via two

methods.

“Sector/Sector Block Protection and Unprotection”. The two

outermost 8 Kbyte boot sectors are the two sectors

containing the lowest addresses in a bottom-boot-configured

device, or the two sectors containing the highest addresses

in a top-boot-configured device.

If the system asserts V^IHon the

/ACC pin, the device

WP

The primary method requires V^IDon the

pin only,

reverts to whether the two outermost 8 Kbyte boot sectors

were last set to be protected or unprotected. That is, sector

protection or unprotection for these two sectors depends on

whether they were last protected or unprotected using the

method described in “Sector/Sector Block Protection and

Unprotection”.

RESET

and can be implemented either in-system or via

programming equipment. Figure 2 shows the algorithms and

Figure 23 shows the timing diagram. This method uses

standard microprocessor bus cycle timing. For sector

unprotect, all unprotected sectors must first be protected

prior to the first sector unprotect write cycle.

The sector unprotect algorithm unprotects all sectors in

parallel. All previously protected sectors must be individually

re-protected. To change data in protected sectors efficiently,

the temporary sector unprotect function is available. See

“Temporary Sector/Sector Block Unprotect”.

The alternate method for protection and unprotection is by

software sector /sector block protect unprotect command.

See Figure 2 for Command Flow.

The device is shipped with all sectors unprotected.

It is possible to determine whether a sector is protected or

unprotected. See the Autoselect Mode section for details.

Note that the

/ACC pin must not be left floating or

WP

unconnected; inconsistent behavior of the device may result.

Temporary Sector/Sector Block Unprotect

(Note: For the following discussion, the term “sector” applies

to both sectors and sector blocks. A sector block consists of

two or more adjacent sectors that are protected or

unprotected at the same time (see Tables 6 and 7).

This feature allows temporary unprotection of previously

protected sectors to change data in-system. The Sector

Unprotect mode is activated by setting the

pin to VID

RESET

(8.5V-10.5V). During this mode, formerly protected sectors

can be programmed or erased by selecting the sector

Write Protect (

)

WP

addresses. Once VID is removed from the

pin, all the

RESET

The Write Protect function provides a hardware method of

protecting certain boot sectors without using V^ID. This

previously protected sectors are protected again. Figure 1

shows the algorithm, and Figure 22 shows the timing

diagrams, for this feature.

function is one of two provided by the

/ACC pin.

WP

If the system asserts V^ILon the

/ACC pin, the device

WP

disables program and erase functions in the two “outermost”

8 Kbyte boot sectors independently of whether those sectors

were protected or unprotected using the method described in

(November, 2007, Version 1.2)

14

AMIC Technology, Corp.

A29DL32x Series

START

555/AA + 2AA/55 + 555/77

(Note 1)

RESET = VID

(Note 1)

Perform Erase or

Program Operations

Perform Erase or

Program Operations

XXX/F0

(Reset Command)

RESET = VIH

Soft-ware Temporary

Sector Unprotect

Completed

(Note 2)

Temporary Sector

Unprotect

Completed (Note 2)

Notes:

1. All protected sectors unprotected (If WP/ACC=V^IL,

outermost boot sectors will remain protected).

2. All previously protected sectors are protected once again.

Notes:

1. All protected sectors unprotected (If WP/ACC=V^IL,

outermost boot sectors will remain protected).

2. All previously protected sectors are protected once again.

Figure 1-2. Temporary Sector Unprotect Operation by Software Mode

Figure 1-1. Temporary Sector Unprotect Operation by RESET Mode

(November, 2007, Version 1.2)

15

AMIC Technology, Corp.

A29DL32x Series

START

Protect all sectors:

The indicated portion of

the sector protect

PLSCNT=1

algorithm must be

performed for all

RESET=VID

unprotected sectors prior

to issuing the first sector

unprotect address

Wait 1 us

No

Temporary Sector

Unprotect Mode

First Write

Cycle=60h?

First Write

Cycle=60h?

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

All sectors

protected?

Sector Protect:

Write 60h to sector

address with A6=0,

A1=1, A0=0

Yes

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with A6=1,

A1=1, A0=0

Wait 150 us

Verify Sector

Protect: Write 40h

to sector address

with A6=0, A1=1,

A0=0

Reset

PLSCNT=1

Increment

PLSCNT

Wait 15 ms

Verify Sector

Unprotect : Write

40h to sector

address with A6=1,

A1=1, A0=0

Read from

sector address

with A6=0,

Increment

PLSCNT

A1=1, A0=0

No

Read from sector

address with A6=1,

A1=1, A0=0

No

PLSCNT

=25?

Data=01h?**

Yes

No

Set up

next sector

address

Yes

No

PLSCNT=

1000?

Yes

Data=00h?**

Yes

Protect another

sector?

Device failed

Yes

No

Remove VID

from RESET

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove VID

from RESET

Sector Protect

complete

Sector Protect

Algorithm

Sector Unprotect

Algorithm

Write reset

Command

Note: The term “sector” in the figure applies to both sectors and sector blocks

* No other command is allowed during this process

** Read access time is 200ns-300ns

Sector Unprotect

complete

Figure 2-1. High Voltage Sector/Sector Block Protection and Unprotection Algorithms

(November, 2007, Version 1.2)

16

AMIC Technology, Corp.

A29DL32x Series

START

PLSCNT=1

Protect all sectors:

The indicated portion of

the sector protect

555/AA + 2AA/55 +

555/77

555/AA + 2AA/55 +

555/77

algorithm must be

performed for all

unprotected sectors prior

to issuing the first sector

unprotect address

Wait 1 us

No

Temporary Sector

Unprotect Mode

First Write

Cycle=60h?

First Write

Cycle=60h?

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

All sectors

protected?

Sector Protect:

Write 60h to sector

address with A6=0,

A1=1, A0=0

Yes

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with A6=1,

A1=1, A0=0

Wait 150 us

Verify Sector

Protect: Write 40h

to sector address

with A6=0, A1=1,

A0=0

Reset

PLSCNT=1

Increment

PLSCNT

Wait 15 ms

Verify Sector

Unprotect : Write

40h to sector

address with A6=1,

A1=1, A0=0

Read from

sector address

with A6=0,

Increment

PLSCNT

A1=1, A0=0

No

Read from sector

address with A6=1,

A1=1, A0=0

No

PLSCNT

=25?

Data=01h?**

Yes

No

Set up

next sector

address

Yes

No

PLSCNT=

1000?

Yes

Data=00h?**

Yes

Protect another

sector?

Device failed

Yes

No

Write reset

command

No

Last sector

verified?

Device failed

Sector Protect

complete

Yes

Sector Protect

Algorithm

Write reset

Command

Sector Unprotect

Algorithm

Sector Unprotect

complete

Note: The term “sector” in the figure applies to both sectors and sector blocks

* No other command is allowed during this process

** Read access time is 200ns-300ns

Figure 2-2. Software Sector/Sector Block Protection and Unprotection Algorithms

(November, 2007, Version 1.2)

17

AMIC Technology, Corp.

A29DL32x Series

Hardware Data Protection

Power-Up Write Inhibit

If = VIL and = VIH during power up, the

OE

The command sequence requirement of unlock cycles for

programming or erasing provides data protection against

inadvertent writes (refer to Table 12 for command definitions).

In addition, the following hardware data protection measures

prevent accidental erasure or programming, which might

otherwise be caused by spurious system level signals during

VCC power-up and power-down transitions, or from system

noise.

=

WE

CE

device does not accept commands on the rising edge of

.

WE

The internal state machine is automatically reset to reading

array data on power-up.

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification outlines

device and host system software interrogation handshake,

which allows specific vendor-specified software algorithms to

be used for entire families of devices. Software support can

then be device-independent, JEDEC ID-independent, and

forward- and backward-compatible for the specified flash

device families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

Low VCC Write Inhibit

When VCC is less than V^LKO, the device does not accept any

write cycles. This protects data during VCC power-up and

power-down. The command register and all internal

program/erase circuits are disabled, and the device resets to

reading array data. Subsequent writes are ignored until VCC

is greater than V^LKO. The system must provide the proper

signals to the control pins to prevent unintentional writes

when VCC is greater than VLKO.

This device enters the CFI Query mode when the system

writes the CFI Query command, 98h, to address 55h in word

mode (or address AAh in byte mode), any time the device is

ready to read array data. The system can read CFI

information at the addresses given in Tables 8-11. To

terminate reading CFI data, the system must write the reset

command.

The system can also write the CFI query command when the

device is in the autoselect mode. The device enters the CFI

query mode, and the system can read CFI data at the

addresses given in Tables 8-11. The system must write the

reset command to return the device to the autoselect mode.

Write Pulse “Glitch” Protection

Noise pulses of less than 5ns (typical) on

do not initiate a write cycle.

,

or

OE CE

WE

Logical Inhibit

Write cycles are inhibited by holding any one of

= VIL,

OE

= VIH or

= VIH. To initiate a write cycle,

and

CE

WE

CE

is a logical one.

OE

must be a logical zero while

WE

Table 8. CFI Query Identification String

Addresses

Data

Description

(Word Mode)

(Byte Mode)

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

0051h

0052h

0059h

0002h

0000h

0040h

0000h

Query Unique ASCII string “QRY”

Primary OEM Command Set

Address for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

(November, 2007, Version 1.2)

18

AMIC Technology, Corp.

A29DL32x Series

Table 9. System Interface String

Addresses

(Word Mode)

1Bh

Addresses

(Byte Mode)

36h

Data

Description

0027h

0036h

VCC Min. (write/erase)

I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt

VCC Max. (write/erase)

1Ch

38h

I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0003h

0000h

0009h

0000h

0005h

0000h

0004h

0000h

Vpp Min. voltage (00h = no Vpp pin present)

Vpp Max. voltage (00h = no Vpp pin present)

Typical timeout per single byte/word write 2^Nμs

Typical timeout for Min. size buffer write 2^Nμs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 10 Device Geometry Definition

Addresses

(Word Mode)

27h

Addresses

(Byte Mode)

4Eh

Data

Description

Device Size = 2^Nbyte

0016h

0002h

0000h

0002h

0007h

0000h

0020h

0000h

003Eh

0000h

0001h

0000h

28h

50h

Flash Device Interface description

29h

52h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ah

54h

2Bh

56h

Number of Erase Block Regions within device

2Ch

58h

2Dh

5Ah

Erase Block Region 1 Information

(refer to the CFI specification)

2Eh

5Ch

2Fh

5Eh

30h

60h

31h

62h

32h

64h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

33h

66h

34h

68h

35h

6Ah

36h

6Ch

37h

6Eh

38h

70h

39h

72h

3Ah

74h

3Bh

76h

3Ch

78h

(November, 2007, Version 1.2)

19

AMIC Technology, Corp.

A29DL32x Series

Table 11. Primary Vendor-Specific Extended Query

Addresses

(Byte Mode)

80h

Data

Description

(Word Mode)

40h

41h

42h

43h

44h

45h

0050h

0052h

0049h

0031h

0033h

0004h

Query-unique ASCII string “PRI”

82h

84h

86h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock

0 = Required, 1 = Not Required

Erase Suspend

88h

8Ah

46h

47h

48h

49h

4Ah

8Ch

8Eh

90h

92h

94h

0002h

0001h

0004h

00XXh

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in the smallest group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

04 = A29L800 mode

Number of Sectors (Excluding Bank 1)

XX = 38 (A29DL322)

XX = 30 (A29DL323)

XX = 20 (A29DL324)

4Bh

4Ch

96h

98h

0000h

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt,

D3-D0: 100 mV

4Dh

9Ah

0085h

ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt,

D3-D0: 100 mV

4Eh

4Fh

9Ch

9Eh

0095h

000Xh

Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot

Device

Program Suspend

50h

57h

A0h

AEh

0000h

0002h

0 = Not Supported, 1 = Supported

Bank Organization

X = 2 (2 banks, all models)

Bank 1 Region Information – Number of Sectors on Bank 1

XX = 0F (A29DL322)

58h

59h

B0h

B2h

00XXh

XX = 17 (A29DL323)

XX = 27 (A29DL324)

Bank 2 Region Information – Number of Sectors in Bank 2

XX = 38 (A29DL322)

XX = 30 (A29DL323)

XX = 20 (A29DL324)

5Ah

5Bh

B4h

B6h

0000

Bank 3 Region Information – Number of Sector in Bank 3

Bank 4 Region Information – Number of Sector in Bank 4

(November, 2007, Version 1.2)

20

AMIC Technology, Corp.

A29DL32x Series

(or erase-suspend-read mode if that bank was in Erase

Suspend).

COMMAND DEFINITIONS

Writing specific address and data commands or sequences

into the command register initiates device operations. Table

12 defines the valid register command sequences. Writing

incorrect address and data values or writing them in the

improper sequence may place the device in an unknown

state. A reset command is then required to return the device

to reading array data.

Autoselect Command Sequence

The autoselect command sequence allows the host system

to access the manufacturer and device codes, and determine

whether or not a sector is protected. Table 12 shows the

address and data requirements. This method is an

alternative to that shown in Table 5, which is intended for

PROM programmers and requires V^IDon address pin A9.

The autoselect command sequence may be written to an

address wit h in a bank that is either in t he read or erase-

suspend-read mode. The autoselect command may not be

written while the device is actively programming or erasing in

the other bank.

All addresses are latched on the falling edge of

or

,

CE

WE

whichever happens later. All data is latched on the rising

edge of or , whichever happens first. Refer to the

WE

CE

AC Characteristics section for timing diagrams.

Reading Array Data

The autoselect command sequence is initiated by first writing

two unlock cycles. This is followed by a third write cycle that

contains the bank address and the autoselect command. T he

bank then enter s the autoselect mode. The system may read

at any address within the same bank any number of times

without initiating another autoselect command sequence:

A read cycle at address (BA)XX00h (where BA is the bank

address) returns the manufacturer code.

The device is automatically set to reading array data after

device power-up. No commands are required to retrieve

data. The device is also ready to read array data after

completing an Embedded Program or Embedded Erase

algorithm.

After the device accepts an Erase Suspend command, the

corresponding bank enters the erase-suspend-read mode,

after which the system can read data from any non-erase-

suspended sector within the same bank. After completing a

programming operation in the Erase Suspend mode, the

system may once again read array data with the same

exception. See the Erase Suspend/Erase Resume

Commands section for more information.

The system must issue the reset command to return a bank

to the read (or erase-suspend-read) mode if I/O⁵goes high

during an active program or erase operation, or if the bank is

in the autoselect mode. See the next section, Reset

Command, for more information.

See also Requirements for Reading Array Data in the Device

Bus Operations section for more information. The Read-Only

Operations table provides the read parameters, and Figure

11 shows the timing diagram.

A read cycle at address (BA)XX01h in word mode (or

(BA)XX02h in byte mode) returns the device code.

A read cycle to an address containing a sector address

(SA) within the same bank, and the address 02h on A7-A0

in word mode (or the address 04h on A6-A-1 in byte mode)

returns 01h if the sector is protected, or 00h if it is

unprotected. (Refer to Tables 3-4 for valid sector

addresses).

The system must write the reset command to return to

reading array data (or erase-suspend-read mode if the bank

was previously in Erase Suspend).

Byte/Word Program Command Sequence

The system may program the device by word or byte,

depending on the state of the

pin. Programming is a

BYTE

Reset Command

four-bus-cycle operation. The program command sequence

is initiated by writing two unlock write cycles, followed by the

program set-up command. The program address and data

are written next, which in turn initiate the Embedded Program

algorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 12 shows the address and

data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, that

bank then returns to reading array data and addresses are

no longer latched. The system can determine the status of

Writing the reset command resets the banks to the read or

erase-suspend-read mode. Address bits are don’t cares for

this command.

The reset command may be written between the sequence

cycles in an erase command sequence before erasing

begins. This resets the bank to which the system was writing

to reading array data. Once erasure begins, however, the

device ignores reset commands until the operation is

complete.

The reset command may be written between the sequence

cycles in

a

program command sequence before

programming begins. This resets the bank to which the

system was writing to reading array data. If the program

command sequence is written to a bank that is in the Erase

Suspend mode, writing the reset command returns that bank

to the erase-suspend-read mode. Once programming begins,

however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the sequence

cycles in an autoselect command sequence. Once in the

autoselect mode, the reset command must be written to

return to reading array data. If a bank entered the autoselect

mode while in the Erase Suspend mode, writing the reset

command returns that bank to the erase-suspend-read mode.

If I/O⁵goes high during a program or erase operation, writing

the reset command returns the banks to reading array data

the program operation by using I/O⁷, I/O6, or RY/

to the Write Operation Status section for information on these

status bits.

. Refer

BY

Any commands written to the device during the Embedded

Program Algorithm are ignored. Note that a hardware reset

immediately terminates the program operation. The program

command sequence should be reinitiated once that bank has

returned to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across sector

boundaries. A bit cannot be programmed from “0” back to a

“1.” Attempting to do so may cause that bank to set I/O⁵= 1,

or cause the I/O⁷and I/O6 status bits to indicate the operation

was successful. However, a succeeding read will show that

the data is still “0.” Only erase operations can convert a “0” to

a “1.”

(November, 2007, Version 1.2)

21

AMIC Technology, Corp.

A29DL32x Series

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program

bytes or words to a bank faster than using the standard

program command sequence. The unlock bypass command

sequence is initiated by first writing two unlock cycles. This is

followed by a third write cycle containing the unlock bypass

command, 20h. The device then enters the unlock bypass

START

Write Program

Command

Sequence

mode.

A two-cycle unlock bypass program command

sequence is all that is required to program in this mode. The

first cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the program

address and data. Additional data is programmed in the

same manner. This mode dispenses with the initial two

unlock cycles required in the standard program command

sequence, resulting in faster total programming time. Table

12 shows the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass

Program and Unlock Bypass Reset commands are valid. To

exit the unlock bypass mode, the system must issue the two-

cycle unlock bypass reset command sequence. The device

then returns to reading array data.

Data Poll

from System

Embedded

Program

algorithm in

progress

Verify Data ?

No

The device offers accelerated program operations through

Yes

Last Address ?

Yes

the

/ACC pin. When the system asserts VHH on the

WP

/ACC pin, the device automatically enters the Unlock

WP

Bypass mode. The system may then write the two-cycle

Unlock Bypass program command sequence. The device

No

Increment Address

uses the higher voltage on the

/ACC pin to accelerate

WP

the operation. Note that the

/ACC pin must not be at VHH

WP

any operation other than accelerated programming, or device

damage may result. In addition, the /ACC pin must not

WP

be left floating or unconnected; inconsistent behavior of the

device may result.

Programming

Completed

Figure 3 illustrates the algorithm for the program operation.

Refer to the Erase and Program Operations table in the AC

Characteristics section for parameters, and Figure 15 for

timing diagrams.

Note : See Table 14 for program command sequnce.

Figure 3. Program Operation

(November, 2007, Version 1.2)

22

AMIC Technology, Corp.

A29DL32x Series

When the Embedded Erase algorithm is complete, the bank

returns to reading array data and addresses are no longer

latched. Note that while the Embedded Erase operation is in

progress, the system can read data from the non-erasing

bank. The system can determine the status of the erase

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the chip erase command, which

in turn invokes the Embedded Erase algorithm. The device

does not require the system to preprogram prior to erase.

The Embedded Erase algorithm automatically preprograms

and verifies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to provide

any controls or timings during these operations. Table 12

shows the address and data requirements for the chip erase

command sequence.

operation by reading I/O⁷, I/O6, I/O2, or RY/

bank.

in the erasing

BY

Refer to the Write Operation Status section for information on

these status bits.

Once the sector erase operation has begun, only the Erase

Suspend command is valid. All other commands are ignored.

However, note that a hardware reset immediately terminates

the erase operation. If that occurs, the sector erase

command sequence should be reinitiated once that bank has

returned to reading array data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase operation.

Refer to the Erase and Program Operations tables in the AC

Characteristics section for parameters, and Figure 17 section

for timing diagrams

When the Embedded Erase algorithm is complete, that bank

returns to reading array data and addresses are no longer

latched. The system can determine the status of the erase

operation by using I/O⁷, I/O6, I/O2, or RY/

Write Operation Status section for information on these

status bits.

. Refer to the

BY

Any commands written during the chip erase operation are

ignored. However, note that a hardware reset immediately

terminates the erase operation. If that occurs, the chip erase

command sequence should be reinitiated once that bank has

returned to reading array data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase operation.

Refer to the Erase and Program Operations tables in the AC

Characteristics section for parameters, and Figure 17 section

for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to

interrupt a sector erase operation and then read data from, or

program data to, any sector not selected for erasure. This

command is valid only during the sector erase operation,

including the 50 µs time-out period during the sector erase

command sequence. The Erase Suspend command is

ignored if written during the chip erase operation or

Embedded Program algorithm.

Sector Erase Command Sequence

When the Erase Suspend command is written during the

sector erase operation, the device requires a maximum of 20

µs to suspend the erase operation. However, when the Erase

Suspend command is written during the sector erase time-

out, the device immediately terminates the time-out period

and suspends the erase operation.

After the erase operation has been suspended, the bank

enters the erase-suspend-read mode. The system can read

data from or program data to any sector not selected for

erasure. (The device “erase suspends” all sectors selected

for erasure.) Reading at any address within erase-suspended

sectors produces status information on I/O⁷–I/O0. The system

can use I/O⁷, or I/O6 and I/O2 together, to determine if a

sector is actively erasing or is erase-suspended. Refer to the

Write Operation Status section for information on these

status bits.

After an erase-suspended program operation is complete,

the bank returns to the erase-suspend-read mode. The

system can determine the status of the program operation

using the I/O⁷or I/O6 status bits, just as in the standard Byte

Program operation. Refer to the Write Operation Status

section for more information.

In the erase-suspend-read mode, the system can also issue

the autoselect command sequence. Refer to the Autoselect

Mode and Autoselect Command Sequence sections for

details.

Sector erase is a six bus cycle operation. The sector erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock cycles

are written, and are then followed by the address of the

sector to be erased, and the sector erase command. Table

12 shows the address and data requirements for the sector

erase command sequence.

The device does not require the system to preprogram prior

to erase. The Embedded Erase algorithm automatically

programs and verifies the entire memory for an all zero data

pattern prior to electrical erase. The system is not required to

provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-

out of 50 µs occurs. During the time-out period, additional

sector addresses and sector erase commands within the

bank may be written. Loading the sector erase buffer may be

done in any sequence, and the number of sectors may be

from one sector to all sectors. The time between these

additional cycles must be less than 50µs, otherwise erasure

may begin. Any sector erase address and command

following the exceeded time-out may or may not be accepted.

It is recommended that processor interrupts be disabled

during this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector Erase

command is written. Any command other than Sector Erase

or Erase Suspend during the time-out period resets that bank

to reading array data. The system must rewrite the command

sequence and any additional addresses and commands.

The system can monitor I/O³to determine if the sector erase

timer has timed out (See the section on I/O³: Sector Erase

Timer.). The time-out begins from the rising edge of the final

To resume the sector erase operation, the system must write

the Erase Resume command. The bank address of the

erase-suspended bank is ignored when writing this command.

Further writes of the Resume command are ignored. Another

Erase Suspend command can be written after the chip has

resumed erasing.

pulse in the command sequence.

WE

(November, 2007, Version 1.2)

23

AMIC Technology, Corp.

A29DL32x Series

START

Write Erase

Command Sequence

(Notes 1,2)

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm in

progress

No

Data = FFh ?

Yes

Erasure Completed

Note :

1. See Table 14 for erase command sequence.

2. See the section on I/O³for information on the sector

erase timer.

Figure 4. Erase Operation

(November, 2007, Version 1.2)

24

AMIC Technology, Corp.

A29DL32x Series

Command Definitions

Table 12. A29DL32x Command Definitions

Bus Cycles (Notes 2–5)

Third Fourth

Addr

Command

Sequence

(Note 1)

First

Second

Fifth

Sixth

Addr Data Addr Data

Data

Addr

Data

Addr

Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

RD

F0

(BA)555

(BA)AAA

(BA)555

(BA)AAA

Word

Byte

Word

Byte

2AA

555

2AA

555

(BA)X00

Manufacturer ID

Device ID

4

3

4

3

AA

55

90

77

A0

20

37

AAA

555

(BA)X01

(BA)X02

(see

Table5)

AAA

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

555

AAA

555

AAA

555

AAA

555

AAA

555

AAA

XXX

555

AAA

555

AAA

XXX

55

2AA

555

2AA

555

2AA

555

2AA

555

2AA

555

PA

555

AAA

X03

X06

Continuation ID

7F

(BA)555

(BA)AAA

(SA)

Sector Protect Verify

(Note 9)

00/01

(SA)X04

555

AAA

555

Command Temporary

Sector Unprotect (Note15)

Program

PA

PD

AAA

555

Unlock Bypass

AAA

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

555

AAA

555

AA A

555

2AA

555

2AA

555

Chip Erase

Byte

6

AA

55

80

AA

55

10

30

AAA

Word

Sector Erase

Byte

SA

AAA

Erase Suspend (Note 12)

Erase Resume (Note 13)

1

B0

30

Word

CFI Query (Note 14)

1

98

Byte

AA

Legend:

X = Don't care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the

or

pulse,

CE

WE

whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of

or

pulse, whichever happens first.

CE

WE

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20 - A12 select a unique sector.

BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased.

Note:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.

4. Data bits I/O¹⁵-I/O8 are don’t care in command sequences. Except for RD and PD.

5. Unless otherwise noted, address bits A20-A11 are don’t cares.

6. No unlock or command cycles required when bank is reading array data.

7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase

Suspend) when a bank is in the autoselect mode, or if I/O5 goes high (while the bank is providing status information).

8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain

the manufacture ID, or device ID information. Data bits I/O¹⁵-I/O8 are don’t care. See the Autoselect Command Sequence

section for more information.

9. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.

10. The Unlock Bypass command is required prior to the Unlock Bypass Program Command.

11. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.

12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase operation, and require the bank address.

13. The Erase Resume command is valid only during the Erase.

14. Command is valid when device is ready to read array data or when device is in autoselect mode.

15. Once a reset command is applied, software temporary unprotect is exit to return to read array data. But under erase

suspend condition, this command is still effective even a reset command has been applied. The reset command which can

deactivate the software temporary unprotect command is useful only after the erase command is complete.

(November, 2007, Version 1.2)

25

AMIC Technology, Corp.

A29DL32x Series

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: I/O², I/O3, I/O5, I/O6, and I/O7.

Table 13 and the following subsections describe the function

of these bits. I/O7 and I/O6 each offer a method for

determining whether a program or erase operation is

complete or in progress. The device also provides a

START

Read I/O7-I/O0

Address = VA

hardware-based output signal, RY/

an Embedded Program or Erase operation is in progress or

has been completed.

, to determine whether

BY

I/O7:

Polling

Data

Yes

I/O7

= Data ?

No

The

Polling bit, I/O7, indicates to the host system

Data

whether an Embedded Algorithm is in progress or completed,

or whether the device is in Erase Suspend. Polling is

Data

pulse in the

valid after the rising edge of the final

program or erase command sequence.

WE

During the Embedded Program algorithm, the device outputs

on I/O⁷the complement of the datum programmed to I/O7.

This I/O⁷status also applies to programming during Erase

Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to I/O7.

The system must provide the program address to read valid

status information on I/O⁷. If a program address falls within a

No

I/O5 = 1?

Yes

protected sector,

Polling on I/O7 is active for

Data

Read I/O

7

- I/O0

Address = VA

approximately 1μs, then the device returns to reading array

data.

During the Embedded Erase algorithm,

Polling

Data

produces a "0" on I/O⁷. When the Embedded Erase algorithm

is complete, or if the device enters the Erase Suspend mode,

Yes

Polling produces a "1" on I/O7. The system must

Data

I/O7

= Data ?

provide an address within any of the sectors selected for

erasure to read valid status information on I/O⁷.

After an erase command sequence is written, if all sectors

selected for erasing are protected,

Polling on I/O7 is

Data

No

active for approximately 100μs, then the bank returns to

reading array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are protected.

However, if the system reads I/O⁷at an address within a

protected sector, the status may not be valid.

FAIL

PASS

Just prior to the completion of an Embedded Program or

Erase operation, I/O⁷may change asynchronously with I/O0–

Note :

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

I/O⁶while Output Enable (

) is asserted low. That is, the

OE

device may change from providing status information to valid

data on I/O⁷. Depending on when the system samples the

I/O⁷output, it may read the status or valid data. Even if the

device has completed the program or erase operation and

I/O7 has valid data, the data outputs on I/O0-I/O6 may be still

invalid. Valid data on I/O⁰-I/O7 will appear on successive read

cycles.

2. I/O

7

should be rechecked even if I/O

may change simultaneously with I/O

5 = "1" because

I/O7

5

.

Figure 5. Data Polling Algorithm

Table 13 shows the outputs for

Polling on I/O7. Figure

Data

5 shows the

Polling algorithm. Figure 19 in the AC

Data

Characteristics section shows the

diagram.

Polling timing

Data

(November, 2007, Version 1.2)

26

AMIC Technology, Corp.

A29DL32x Series

RY/

: Read/

Busy

BY

The RY/

is a dedicated, open-drain output pin that

BY

indicates whether an Embedded algorithm is in progress or

START

complete. The RY/ status is valid after the rising edge of

BY

pulse in the command sequence. Since RY/

the final

WE

BY

pins can be tied

is an open-drain output, several RY/

BY

together in parallel with a pull-up resistor to VCC.

Read I/O7-I/O0

If the output is low (Busy), the device is actively erasing or

programming. (This includes programming in the Erase

Suspend mode.) If the output is high (Ready), the device is

ready to read array data (including during the Erase Suspend

mode), or is in the standby mode.

(Note 1)

No

Table 13 shows the outputs for RY/

.

BY

I/O6: Toggle Bit I

Toggle Bit I on I/O6 indicates whether an Embedded Program

or Erase algorithm is in progress or complete, or whether the

device has entered the Erase Suspend mode. Toggle Bit I

may be read at any address, and is valid after the rising edge

Toggle Bit

= Toggle ?

of the final

pulse in the command sequence (prior to the

WE

Yes

I/O5 = 1?

Yes

program or erase operation), and during the sector erase

time-out.

During an Embedded Program or Erase algorithm operation,

successive read cycles to any address cause I/O⁶to toggle.

No

The system may use either

or

to control the read

CE

OE

cycles. When the operation is complete, I/O6 stops toggling.

After an erase command sequence is written, if all sectors

selected for erasing are protected, I/O6 toggles for

approximately 100μs, then returns to reading array data. If not

all selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores the

selected sectors that are protected.

Read I/O7 - I/O0

(Notes 1,2)

Twice

The system can use I/O⁶and I/O2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), I/O⁶toggles. When the device

enters the Erase Suspend mode, I/O⁶stops toggling.

However, the system must also use I/O²to determine which

sectors are erasing or erase-suspended. Alternatively, the

No

Toggle Bit

= Toggle ?

Yes

Program/Erase

Operation Not

Commplete, Write

Reset Command

system can use I/O⁷(see the subsection on " I/O7:

Polling").

Data

Program/Erase

Operation Complete

If a program address falls within a protected sector, I/O⁶

toggles for approximately 1μs after the program command

sequence is written, then returns to reading array data.

I/O⁶also toggles during the erase-suspend-program mode,

and stops toggling once the Embedded Program algorithm is

complete.

Table 13 shows the outputs for Toggle Bit I on I/O⁶. Figure 6

shows the toggle bit algorithm. Figure 20-1, 20-2, 20-3 in the

“AC Characteristics” section show the toggle bit timing

diagrams. Figure 23 shows the differences between I/O²and

I/O⁶in graphical form. See also the subsection on I/O2:

Toggle Bit II.

Note:

The system should recheck the toggle bit even if I/O⁵=”1"

because the toggle bit may stop toggling as I/O⁵changes to

“1”. See the subsections on I/O⁶and I/O2 for more information.

Figure 6. Toggle Bit Algorithm

(November, 2007, Version 1.2)

27

AMIC Technology, Corp.

A29DL32x Series

I/O2: Toggle Bit II

I/O5: Exceeded Timing Limits

The "Toggle Bit II" on I/O2, when used with I/O6, indicates

whether a particular sector is actively erasing (that is, the

Embedded Erase algorithm is in progress), or whether that

sector is erase-suspended. Toggle Bit II is valid after the

I/O5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions I/O5 produces a "1." This is a failure condition that

indicates the program or erase cycle was not successfully

completed.

The device may output a “1” on I/O⁵if the system tries to

program a “1” to a location that was previously programmed

to “0.” Only an erase operation can change a “0” back to a

“1.” Under this condition, the device halts the operation, and

when the timing limit has been exceeded, I/O⁵produces a

“1.” .

rising edge of the final

pulse in the command sequence.

WE

I/O²toggles when the system reads at addresses within those

sectors that have been selected for erasure. (The system may

use either

or

to control the read cycles.) But I/O2

CE

OE

cannot distinguish whether the sector is actively erasing or is

erase-suspended. I/O⁶, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but cannot

distinguish which sectors are selected for erasure. Thus, both

status bits are required for sector and mode information.

Refer to Table 8 to compare outputs for I/O²and I/O6.

Figure 6 shows the toggle bit algorithm in flowchart form, and

the section " I/O²: Toggle Bit II" explains the algorithm. See

also the " I/O⁶: Toggle Bit I" subsection. Figure 20-1, 20-2, 20-

3 show the toggle bit timing diagram. Figure 21 shows the

differences between I/O2 and I/O6 in graphical form.

Under both these conditions, the system must write the reset

command to return to reading array data (or to the erase-

suspend-read mode if a bank was previously in the erase-

suspend-program mode).

I/O3: Sector Erase Timer

After writing a sector erase command sequence, the system

may read I/O³to determine whether or not an erase

operation has begun. (The sector erase timer does not apply

to the chip erase command.) If additional sectors are

selected for erasure, the entire time-out also applies after

each additional sector erase command. When the time-out is

complete, I/O³switches from "0" to "1." The system may

ignore I/O³if the system can guarantee that the time

between additional sector erase commands will always be

less than 50μs. See also the "Sector Erase Command

Sequence" section.

Reading Toggle Bits I/O6, I/O2

Refer to Figure 6 for the following discussion. Whenever the

system initially begins reading toggle bit status, it must read

I/O7-I/O0 at least twice in a row to determine whether a toggle

bit is toggling. Typically, a system would note and store the

value of the toggle bit after the first read. After the second

read, the system would compare the new value of the toggle

bit with the first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system can

read array data on I/O⁷-I/O0 on the following read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the system also

should note whether the value of I/O⁵is high (see the section

on I/O⁵). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may

have stopped toggling just as I/O⁵went high. If the toggle bit

is no longer toggling, the device has successfully completed

the program or erase operation. If it is still toggling, the device

did not complete the operation successfully, and the system

must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines

that the toggle bit is toggling and I/O⁵has not gone high. The

system may continue to monitor the toggle bit and I/O⁵

through successive read cycles, determining the status as

described in the previous paragraph. Alternatively, it may

choose to perform other system tasks. In this case, the

system must start at the beginning of the algorithm when it

returns to determine the status of the operation (top of Figure

6).

After the sector erase command sequence is written, the

system should read the status on I/O⁷(

Polling) or I/O6

Data

(Toggle Bit 1) to ensure the device has accepted the

command sequence, and then read I/O³. If I/O3 is "1", the

internally controlled erase cycle has begun; all further

commands (Except Erase Suspend) are ignored until the

erase operation is complete. If I/O³is "0", the device will

accept additional sector erase commands. To ensure the

command has been accepted, the system software should

check the status of I/O³prior to and following each

subsequent sector erase command. If I/O³is high on the

second status check, the last command might not have been

accepted.

Table 13 shows the status of I/O³relative to the other status

bits.

(November, 2007, Version 1.2)

28

AMIC Technology, Corp.

A29DL32x Series

Table 13. Write Operation Status

I/O7

I/O6

I/O5

(Note 1)

0

I/O3

I/O2

RY/

BY

Status

(Note 2)

No toggle

Standard

Mode

Embedded Program Algorithm

Toggle

N/A

1

0

I/O7

0

Embedded Erase Algorithm

Erase

Erase-Suspend- Suspended Sector

0

Toggle

0

1

Erase

Suspend

Mode

1

No toggle

N/A

Read

Non-Erase

Data

I/O7

Data

0

Data

N/A

Data

N/A

1

0

Suspend Sector

Erase-Suspend-Program

Toggle

Notes:

1. I/O⁵switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on I/O⁵for more information.

2. I/O⁷and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

(November, 2007, Version 1.2)

29

AMIC Technology, Corp.

A29DL32x Series

ABSOLUTE MAXIMUM RATINGS*

*Comments

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to this device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

Storage Temperature Plastic Packages. . . -65°C to + 150°C

Ambient Temperature with Power Applied. -65°C to + 125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V

A9,

&

(Note 2) . . . . . . . . . . . . -0.5V to +10.5V

RESET

OE

/ACC . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +10.5V

WP

All other pins (Note 1) . . . . . . . . . . . . . -0.5V to VCC + 0.5V

Output Short Circuit Current (Note 3) . . . . . . . . . . . . 200mA

OPERATING RANGES

Industrial (I) Devices

Notes:

For –U series . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

For – I series . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C

1. Minimum DC voltage on input or I/O pins is -0.5V. During

voltage transitions, input or I/O pins may undershoot VSS

to -2.0V for periods of up to 20ns. Maximum DC voltage

on input and I/O pins is VCC +0.5V. See Figure 7. During

voltage transitions, input or I/O pins may overshoot to

VCC +2.0V for periods up to 20ns. See Figure 8.

VCC Supply Voltages

VCC for all devices . . . . . . . . . . . . . . . . . . . . +2.7V to +3.6V

Operating ranges define those limits between which the

functionally of the device is guaranteed.

2. Minimum DC input voltage on A9,

,

and

RESET

OE

/ACC is -0.5V. During voltage transitions, A9,

,

WP

OE

/ACC and

may overshoot VSS to -2.0V for

RESET

periods of up to 20ns. See Figure 7. Maximum DC input

voltage on A9 is +10.5V which may overshoot to 12.0V

for periods up to 20ns. Maximum DC input voltage on

/ACC is +10.5V which may overshoot to +12.0V for

period up to 20ns.

WP

3. No more than one output is shorted to ground at a time.

Duration of the short circuit should not be greater than

one second.

Figure 7. Maximum Negative Overshoot Waveform

20ns

+0.8V

-0.5V

-2.0V

20ns

Figure 8. Maximum Positive Overshoot Waveform

20ns

VCC+2.0V

VCC+0.5V

2.0V

20ns

(November, 2007, Version 1.2)

30

AMIC Technology, Corp.

A29DL32x Series

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Description

Min.

Typ.

Max.

Unit

ILI

Input Load Current

V^IN= VSS to VCC. VCC = VCC Max

VCC = VCC Max, A9 =12.5V

±1.0

35

μA

ILIT

ILO

A9 Input Load Current

Output Leakage Current

V^OUT= VSS to VCC. VCC = VCC Max

±1.0

5 MHz

10

2

16

= VIL,

= VIH

CE

Byte Mode

OE

1 MHz

5 MHz

1 MHz

4

VCC Active Read Current

(Notes 1, 2)

ICC1

ICC2

mA

10

2

16

4

= VIL,

CE

Word Mode

VCC Active Write Current

(Notes 2, 3)

20

30

5

= VIL,

=VIH

OE

CE

ICC3

ICC4

ICC5

VCC Standby Current (Note 2)

0.5

μA

=

= VCC ± 0.3V

CE RESET

VCC Reset Current (Note 2)

= VSS ± 0.3V

RESET

0.5

5

Automatic Sleep Mode

(Note 2, 4)

V^IH= VCC ± 0.3V; VIL = VSS ± 0.3V

μA

Byte

21

45

VCC Active Read-While-Program

Current (Notes 1, 2)

= VIL,

= VIH

CE

OE

ICC6

ICC7

mA

Word

Byte

VCC Active Read-While-Erase

Current (Notes 1, 2)

mA

Word

VCC Active

= VIL,

= VIH

CE

OE

Program-While-Erase-Suspended

Current (Notes 2, 5)

17

ICC8

IACC

35

10

ACC pin

VCC pin

5

ACC Accelerated Program Current,

Word or Byte

15

30

0.8

Input Low Level

Input High Level

VIL

VIH

-0.5

V

0.7 x VCC

VCC + 0.3

Voltage for

/ACC Sector

WP

VCC = 3.0 V ± 10%

8.5

10.5

V

Protect/Unprotect and Program

Acceleration

VHH

VID

Voltage for Autoselect and

Temporary Unprotect Sector

Output Low Voltage

VCC = 3.0 V ± 10%

10.5

0.45

V

VOL

VOH1

VOH2

VLKO

I^OL= 4.0mA, VCC = VCC Min

V

I^OH= -2.0 mA, VCC = VCC Min

0.85 x VCC

VCC - 0.4

2.3

Output High Voltage

IOH = -100 μA, VCC = VCC Min

Low VCC Lock-Out Voltage (Note 5)

2.5

Notes:

1. The ICC current listed is typically less than 2 mA/MHz, with

at VIH.

OE

2. Maximum ICC specifications are tested with VCC = VCC max.

3. I^CCactive while Embedded Algorithm (program or erase) is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t^ACC+ 30ns. Typical sleep mode current

is 500nA.

5. Not 100% tested.

(November, 2007, Version 1.2)

31

AMIC Technology, Corp.

A29DL32x Series

TEST CONDITIONS

Table 14. Test Specifications

Test Condition

-70, -80

-90, -120

Unit

Output Load

1 TTL gate

Output Load Capacitance, CL(including jig capacitance)

Input Rise and Fall Times

30

5

100

5

pF

ns

V

Input Pulse Levels

0.0 - 3.0

1.5

0.0 - 3.0

1.5

Input timing measurement reference levels

Output timing measurement reference levels

V

1.5

V

Figure 9. Test Setup

3.3 V

2.7 KΩ

Device

Under

Test

Diodes = IN3064 or Equivalent

CL

6.2 KΩ

Figure 10. Input Waveforms and Measurement Levels

3.0V

Measurement Level

Input

1.5V

Output

0.0V

(November, 2007, Version 1.2)

32

AMIC Technology, Corp.

A29DL32x Series

AC CHARACTERISTICS

Read Only Operations

Parameter

Description

Test Setup

Speed

Unit

JEDEC Std

-70

-80

-90

-120

Read Cycle Time (Note 1)

Address to Output Delay

tAVAV

tRC

Min.

70

80

90

120

ns

= VIL

CE

OE

tAVQV

tACC

Max.

70

80

90

120

Chip Enable to Output Delay

Output Enable to Output Delay

tELQV

tGLQV

t^CE

Max.

70

30

80

30

90

40

120

50

ns

= VIL

OE

tOE

Chip Enable to Output High Z

(Notes 1,3)

tEHQZ

tGHQZ

t^DF

Max.

16

ns

Output Enable to Output High Z

(Notes 1,3)

Output Hold Time from Addresses,

tAXQX

tOH

Min.

0

ns

or

CE OE

, Whichever Occurs First

Read

tOEH

Output Enable Hold

Time (Note 1)

Toggle and

Polling

10

Data

Notes:

1. Not 100% tested.

2. See Figure 9 and Table 14 for test specifications.

3. Measurements performed by placing a 50-ohm termination on the data pin with a bias of VCC/2. The time from

the data bus driven to VCC/2 is taken as t^DF.

high to

OE

Figure 11. Read Operation Timings

tRC

Addresses

CE

Addresses Stable

tACC

tRH

tDF

tOE

OE

tOEH

WE

tCE

t^OH

High-Z

Output

Output Valid

RESET

RY/BY

0V

(November, 2007, Version 1.2)

33

AMIC Technology, Corp.

A29DL32x Series

AC CHARACTERISTICS

Hardware Reset (

Parameter

)

RESET

Description

Test Setup

All Speed Options

Unit

JEDEC

Std

Pin Low (During Embedded

Algorithms) to Read or Write (See Note)

RESET

t^READY

Max

20

μs

Pin Low (Not During Embedded

RESET

Algorithms) to Read or Write (See Note)

t^READY

Max

500

ns

tRP

tRH

Min

500

50

0

ns

μs

Pulse Width

RESET

High Time Before Read (See Note)

Recovery Time

tRB

RY/

BY

tRPD

20

Low to Standby Mode

RESET

Note: Not 100% tested.

Figure 12.

Timings

RESET

RY/BY

0V

CE, OE

tRH

RESET

tRP

tReady

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

tReady

RY/BY

tRB

CE, OE

RESET

tRP

(November, 2007, Version 1.2)

34

AMIC Technology, Corp.

A29DL32x Series

AC CHARACTERISTICS

Word/Byte Configuration (

Parameter

)

BYTE

Description

All Speed Options

Unit

JEDEC

Std

-70

-80

-90

-120

t^ELFL/tELFH

Max

5

ns

to

Switching Low or High

BYTE

CE

Switching Low to Output High-Z

Switching High to Output Active

BYTE

t^FLQZ

t^HQV

Max

Min

25

70

25

80

30

90

30

ns

120

Figure 13.

Timings for Read Operations

BYTE

CE

OE

BYTE

t

ELFL

Data Output

(I/O -I/O

BYTE

I/O -I/O14

0

(I/O

0

-I/O14

)

0

7)

Switching

from word to

byte mode

I/O15

Output

Address Input

I/O15 (A-1)

t

FLQZ

t

ELFH

BYTE

Data Output

(I/O -I/O

Data Output

(I/O0-I/O14)

I/O -I/O14

0

7

)

BYTE

Switching

from byte to

word mode

I/O15

Output

Address Input

I/O15 (A-1)

t

FHQV

Figure 14.

Timings for Write Operations

BYTE

CE

The falling edge of the last WE signal

WE

BYTE

tSET

(tAS)

tHOLD(tAH)

Note:

Refer to the Erase/Program Operations table for tAS and tAH specifications.

(November, 2007, Version 1.2)

35

AMIC Technology, Corp.

A29DL32x Series

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Description

Speed

Unit

JEDEC

tAVAV

Std

t^WC

t^AS

-70

-80

-90

-120

Write Cycle Time (Note 1)

Min.

70

80

90

120

ns

Address Setup Time

tAVWL

0

t^ASO

Address Setup Time to

polling

low during toggle bit

OE

12

40

12

45

12

45

12

50

ns

Address Hold Time

tWLAX

t^AH

Min.

Address Hold Time From

toggle bit polling

or

high during

OE

CE

t^AHT

0

ns

tDVWH

tWHDX

t^DS

t^DH

Data Setup Time

Data Hold Time

Min.

40

20

45

20

45

20

50

20

ns

Output Enable High during toggle bit polling

Read Recover Time Before Write

t^OEPH

tGHWL

t^GHWL

Min.

ns

0

(

high to

low)

WE

OE

tELWL

tWHEH

tWLWH

tWHDL

tCS

t^CH

Min.

ns

Setup Time

Hold Time

0

CE

Write Pulse Width

t^WP

t^WPH

30

35

30

35

30

50

30

Write Pulse Width High

Latency Between Read and Write Operations

Min.

Typ.

0

6

9

6

t^SR/W

Byte

Byte Programming Operation

tWHWH1

μs

(Note 2)

Word

Accelerated Programming Operation,

Word or Byte (Note 2)

tWHWH1

tWHWH2

tWHWH1

sec

tWHWH2 Sector Erase Operation (Note 2)

VCC Set Up Time (Note 1)

Typ.

Min.

Min

0.7

50

0

t^vcs

t^RB

μs

ns

Recovery Time from RY/

BY

t^BUSY

90

Program/Erase Valid to RY/

Delay

BY

Notes:

1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

(November, 2007, Version 1.2)

36

AMIC Technology, Corp.

A29DL32x Series

AC CHARACTERISTICS

Figure 15. Program Operation Timings

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

tWC

tAS

Addresses

CE

PA

555h

PA

tAH

tCH

tWP

OE

tWHWH1

WE

tCS

tWPH

tDS

tDH

Data

A0h

PD

D^OUT

Status

tRB

tBUSY

RY/BY

VCC

tVCS

Note :

1. PA = program address, PD = program data, Dout is the true data at the program address.

2. Illustration shows device in word mode.

Figure 16. Accelerated Program Timing Diagram

VHH

VIL or VIH

WP/ACC

tVHH

(November, 2007, Version 1.2)

37

AMIC Technology, Corp.

A29DL32x Series

AC CHARACTERISTICS

Figure 17. Chip/Sector Erase Operation Timings

Erase Command Sequence (last two cycles)

Read Status Data

VA

tAS

tWC

SA

Addresses

CE

2AAh

555h for chip erase

tAH

OE

tCH

tWP

WE

tWPH

tDH

tWHWH2

tCS

tDS

In

Data

55h

30h

10h for chip erase

Complete

Progress

tRB

tBUSY

RY/BY

tVCS

VCC

Note :

1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").

2. Illustration shows device in word mode.

(November, 2007, Version 1.2)

38

AMIC Technology, Corp.

A29DL32x Series

AC CHARACTERISTICS

Figure 18. Back-to-back Read/Write Cycle Timings

tWC

tRC

tWC

Addresses

Valid PA

Valid RA

Valid PA

tAH

tACC

tCE

tCPH

CE

tCP

tOE

OE

tGHWL

tOEH

tWP

WE

tDF

tWPH

tDS

tOH

tDH

Valid

In

Valid

In

Valid

Out

Valid

In

Data

tSR/W

WE Controlled Write Cycle

Read Cycle

CE Controlled Write Cycles

Figure 19.

Polling Timings (During Embedded Algorithms)

Data

tRC

Addresses

CE

VA

tACC

tCE

tCH

tOE

OE

tDF

tOEH

WE

tOH

High-Z

Valid Data

I/O7

Complement

Status Data

Complement

Status Data

True

I/O⁰- I/O6

High-Z

tBUSY

RY/BY

Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

(November, 2007, Version 1.2)

39

AMIC Technology, Corp.

A29DL32x Series

AC CHARACTERISTICS

Figure 20-1. Toggle Bit Timings (During Embedded Algorithms)

tAHT

tAS

Addresses

tAHT

tASO

tCEPH

CE

tOEH

tOEPH

WE

OE

tDH

tOE

I/O6 , I/O2

Valid Status

(stop togging)

Valid Status

(first read)

Valid Status

Valid Data

Valid Status

(second read)

RY/BY

Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

Figure 20-2. Toggle Bit I and Toggle Bit II Mechanism, Chip Enable Controlled

Address Outside the Bank

Being Programmed or Erased

Address in the Bank

Being Programmed or Erased

Address Outside the Bank

Being Programmed or Erased

A0-A20

tAXCL

CE

OE

tCE

Toggle Bit I/

Toggle Bit II

Toggle Bit I/

Toggle Bit II

I/O6,I/O2

Data

Read Operation Outside the Bank

Being Programmed or Erased

Read Operation in the Bank

Being Programmed or Erased

Read Operation Outside the Bank

Being Programmed or Erased

Note: 1. The Toggle Bit I is output on I/O⁶,

2. The Toggle Bit II is output on I/O².

3. t^AXCLminimum value is 10ns.

(November, 2007, Version 1.2)

40

AMIC Technology, Corp.

A29DL32x Series

Figure 20-3. Toggle Bit I and Toggle Bit II Mechanism, Output Enable Controlled

Note: 1. The Toggle Bit I is output on I/O6,

2. The Toggle Bit II is output on I/O².

3. t^AXELminimum value is 10ns

Figure 21. I/O2 vs. I/O6

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

WE

I/O6

I/O2

Erase

Suspend

Program

Erase

Erase Suspend

Read

Erase Suspend

Read

Erase

Complete

I/O2 and I/O6 toggle with OE and CE

Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Status" for

more information.

(November, 2007, Version 1.2)

41

AMIC Technology, Corp.

A29DL32x Series

AC CHARACTERISTICS

Temporary Sector/Sector Block Unprotect

Parameter

Description

All Speed Options

Unit

JEDEC

Std

t^VIDR

VID Rise and Fall Time (See Note)

VHH Rise and Fall Time (See Note)

Min

500

ns

tVHH

Min

250

4

μs

Setup Time for Temporary

RESET

Sector/Sector Block Unprotect

Hold Time from RY/

t^RSP

High for

BY

RESET

Temporary Sector/Sector Block Unprotect

t^RRB

Min

4

μs

Note: Not 100% tested.

Figure 22. Temporary Sector/Sector Block Unprotect Timing Diagram

VID

VSS, VIL,

or V^IH

RESET

tVIDR

Program or Erase Command Sequence

CE

WE

tRSP

tRRB

RY/BY

Program/Erase Command Sequence

CE

WE

555

AA

2AA

55

555

77

XXX

FQ

Address

I/O⁰- I/O7

RY/BY

(November, 2007, Version 1.2)

42

AMIC Technology, Corp.

A29DL32x Series

AC CHARACTERISTICS

Figure 23. Sector/Sector Block Protect and Unprotect Timing Diagram

VID

VIH

RESET

SA, A6,

A1, A0

Valid*

Sector Protect/Unprotect

Verify

40h

60h

Data

CE

Status

Sector Protect:150us

Sector Unprotect:15ms

1us

WE

OE

Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0

200ns-300ns

(November, 2007, Version 1.2)

43

AMIC Technology, Corp.

A29DL32x Series

AC CHARACTERISTICS

Alternate

Controlled Erase and Program Operations

CE

Parameter

JEDEC

Description

Speed

Unit

Std

tWC

tAS

tAH

tDS

tDH

-70

-80

-90

-120

tAVAV

tAVEL

tELAX

tDVEH

tEHDX

Write Cycle Time (Note 1)

Min.

70

80

90

120

ns

Address Setup Time

Address Hold Time

Data Setup Time

0

40

45

50

Data Hold Time

0

Read Recover Time Before Write

tGHEL

Min.

ns

(

High to

Low)

WE

OE

tWLEL

tEHWH

tELEH

tEHEL

tWS

tWH

tCP

Min.

0

ns

Setup Time

Hold Time

WE

CE

30

35

30

45

30

50

30

Pulse Width

tCPH

Pulse Width High

Programming Operation

(Note 2)

Byte

Typ.

6

9

μs

tWHWH1

Word

Accelerated Programming Operation,

Word or Byte (Note 2)

Typ.

6

μs

tWHWH1

tWHWH2

tWHWH1

tWHWH2

Sector Erase Operation (Note 2)

0.7

sec

Notes:

1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

(November, 2007, Version 1.2)

44

AMIC Technology, Corp.

A29DL32x Series

AC CHARACTERISTICS

Figure 24. Alternate

Controlled Write (Erase/Program) Operation Timings

CE

PA for program

SA for sector erase

555 for chip erase

555 for program

2AA for erase

Data Polling

PA

Addresses

tWC

tAS

tAH

tWH

WE

tGHEL

OE

CE

tCP

tWHWH1 or 2

tBUSY

tCPH

tDH

tWS

tDS

Data

D^OUT

I/O7

tRH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET

RY/BY

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3.

is the complement of the data written to the device. DOUT is the data written to the device.

I/O7

4. Waveforms are for the word mode.

(November, 2007, Version 1.2)

45

AMIC Technology, Corp.

A29DL32x Series

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Sector Erase Time

Typ. (Note 1)

Unit

sec

μs

Comments

0.7

45

6

Excludes 00h programming prior to erasure

(Note 3)

Chip Erase Time

Byte Programming Time

Word Programming Time

Accelerated Word/Byte Programming Time

9

μs

Excludes system-level overhead (Note 4)

6

μs

Chip Programming Time

(Note 2)

Byte Mode

Word Mode

32

20

sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 100,000 cycles. Additionally,

programming typically assumes checkerboard pattern.

2. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed.

3. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

4. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 12

for further information on command definitions.

5. The device has a minimum erase and program cycle endurance of 100,000 cycles.

LATCH-UP CHARACTERISTICS

Description

Min.

-1.0V

Max.

VCC+1.0V

+100 mA

12.5V

Input Voltage with respect to VSS on all I/O pins

VCC Current

-100 mA

-1.0V

Input voltage with respect to VSS on all pins except I/O pins

(including A9,

and

)

RESET

OE

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at time.

PACKAGE AND PIN CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

TSOP

Typ.

Max.

Unit

6

7.5

5

pF

CIN

Input Capacitance

V^IN=0

V^OUT=0

V^IN=0

TFBGA

TSOP

4.2

8.5

5.4

7.5

3.9

12

6.5

9

COUT

Output Capacitance

TFBGA

TSOP

CIN2

Control Pin Capacitance

TFBGA

4.7

Notes:

1. Sampled, not 100% tested.

2. Test conditions T^A= 25°C, f = 1.0MHz

DATA RETENTION

Parameter

Test Conditions

150°C

Min

Unit

Years

10

20

Minimum Pattern Data Retention Time

125°C

(November, 2007, Version 1.2)

46

AMIC Technology, Corp.

A29DL32x Series

Ordering Information

Top Boot Sector Flash

Standby

Current

Typ. (μA)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Access Time

Part No.

Package

(ns)

Typ. (mA)

A29DL322TV-70

A29DL322TV-70U

A29DL322TV-70I

A29DL322TV-70F

A29DL322TV-70UF

A29DL322TV-70IF

A29DL322TG-70

A29DL322TG-70U

A29DL322TG-70I

A29DL322TG-70F

A29DL322TG-70UF

A29DL322TG-70IF

A29DL323TV-70

A29DL323TV-70U

A29DL323TV-70I

A29DL323TV-70F

A29DL323TV-70UF

A29DL323TV-70IF

A29DL323TG-70

A29DL323TG-70U

A29DL323TG-70I

A29DL323TG-70F

A29DL323TG-70UF

A29DL323TG-70IF

A29DL324TV-70

A29DL324TV-70U

A29DL324TV-70I

A29DL324TV-70F

A29DL324TV-70UF

A29DL324TV-70IF

A29DL324TG-70

A29DL324TG-70U

A29DL324TG-70I

A29DL324TG-70F

A29DL324TG-70UF

A29DL324TG-70IF

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

70

10

20

0.5

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

70

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

70

48 pin TFBGA

48 pin Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C, -I is for industrial operating temperature range: -25°C to +85°C

(November, 2007, Version 1.2)

47

AMIC Technology, Corp.

A29DL32x Series

Ordering Information (continued)

Top Boot Sector Flash

Standby

Current

Typ. (μA)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Access Time

Part No.

(ns)

Package

Typ. (mA)

A29DL322TV-80

A29DL322TV-80U

A29DL322TV-80I

A29DL322TV-80F

A29DL322TV-80UF

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL322TV-80IF

80

A29DL322TG-80

10

20

0.5

A29DL322TG-80U

A29DL322TG-80I

A29DL322TG-80F

A29DL322TG-80UF

A29DL322TG-80IF

A29DL323TV-80

A29DL323TV-80U

A29DL323TV-80I

A29DL323TV-80F

A29DL323TV-80UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL323TV-80IF

80

A29DL323TG-80

A29DL323TG-80U

A29DL323TG-80I

A29DL323TG-80F

A29DL323TG-80UF

A29DL323TG-80IF

A29DL324TV-80

A29DL324TV-80U

A29DL324TV-80I

A29DL324TV-80F

A29DL324TV-80UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL324TV-80IF

80

A29DL324TG-80

A29DL324TG-80U

A29DL324TG-80I

A29DL324TG-80F

A29DL324TG-80UF

A29DL324TG-80IF

48 pin TFBGA

48 pin Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C, -I is for industrial operating temperature range: -25°C to +85°C

(November, 2007, Version 1.2)

48

AMIC Technology, Corp.

A29DL32x Series

Ordering Information (continued)

Top Boot Sector Flash

Standby

Current

Typ. (μA)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Access Time

Part No.

(ns)

Package

Typ. (mA)

A29DL322TV-90

A29DL322TV-90U

A29DL322TV-90I

A29DL322TV-90F

A29DL322TV-90UF

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL322TV-90IF

90

A29DL322TG-90

10

20

0.5

A29DL322TG-90U

A29DL322TG-90I

A29DL322TG-90F

A29DL322TG-90UF

A29DL322TG-90IF

A29DL323TV-90

A29DL323TV-90U

A29DL323TV-90I

A29DL323TV-90F

A29DL323TV-90UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL323TV-90IF

90

A29DL323TG-90

A29DL323TG-90U

A29DL323TG-90I

A29DL323TG-90F

A29DL323TG-90UF

A29DL323TG-90IF

A29DL324TV-90

A29DL324TV-90U

A29DL324TV-90I

A29DL324TV-90F

A29DL324TV-90UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL324TV-90IF

90

A29DL324TG-90

A29DL324TG-90U

A29DL324TG-90I

A29DL324TG-90F

A29DL324TG-90UF

A29DL324TG-90IF

48 pin TFBGA

48 pin Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C, -I is for industrial operating temperature range: -25°C to +85°C

(November, 2007, Version 1.2)

49

AMIC Technology, Corp.

A29DL32x Series

Ordering Information (continued)

Top Boot Sector Flash

Standby

Current

Typ. (μA)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Access Time

Part No.

(ns)

Package

Typ. (mA)

A29DL322TV-120

A29DL322TV-120U

A29DL322TV-120I

A29DL322TV-120F

A29DL322TV-120UF

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL322TV-120IF

120

A29DL322TG-120

10

20

0.5

A29DL322TG-120U

A29DL322TG-120I

A29DL322TG-120F

A29DL322TG-120UF

A29DL322TG-120IF

A29DL323TV-120

A29DL323TV-120U

A29DL323TV-120I

A29DL323TV-120F

A29DL323TV-120UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL323TV-120IF

120

A29DL323TG-120

A29DL323TG-120U

A29DL323TG-120I

A29DL323TG-120F

A29DL323TG-120UF

A29DL323TG-120IF

A29DL324TV-120

A29DL324TV-120U

A29DL324TV-120I

A29DL324TV-120F

A29DL324TV-120UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL324TV-120IF

120

A29DL324TG-120

A29DL324TG-120U

A29DL324TG-120I

A29DL324TG-120F

A29DL324TG-120UF

A29DL324TG-120IF

48 pin TFBGA

48 pin Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C, -I is for industrial operating temperature range: -25°C to +85°C

(November, 2007, Version 1.2)

50

AMIC Technology, Corp.

A29DL32x Series

Ordering Information (continued)

Bottom Boot Sector Flash

Standby

Current

Typ. (μA)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Access Time

Part No.

(ns)

Package

Typ. (mA)

A29DL322UV-70

A29DL322UV-70U

A29DL322UV-70I

A29DL322UV-70F

A29DL322UV-70UF

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL322UV-70IF

70

A29DL322UG-70

10

20

0.5

A29DL322UG-70U

A29DL322UG-70I

A29DL322UG-70F

A29DL322UG-70UF

A29DL322UG-70IF

A29DL323UV-70

A29DL323UV-70U

A29DL323UV-70I

A29DL323UV-70F

A29DL323UV-70UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL323UV-70IF

70

A29DL323UG-70

A29DL323UG-70U

A29DL323UG-70I

A29DL323UG-70F

A29DL323UG-70UF

A29DL323UG-70IF

A29DL324UV-70

A29DL324UV-70U

A29DL324UV-70I

A29DL324UV-70F

A29DL324UV-70UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL324UV-70IF

70

A29DL324UG-70

A29DL324UG-70U

A29DL324UG-70I

A29DL324UG-70F

A29DL324UG-70UF

A29DL324UG-70IF

48 pin TFBGA

48 pin Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C, -I is for industrial operating temperature range: -25°C to +85°C

(November, 2007, Version 1.2)

51

AMIC Technology, Corp.

A29DL32x Series

Ordering Information (continued)

Bottom Boot Sector Flash

Standby

Current

Typ. (μA)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Access Time

Part No.

(ns)

Package

Typ. (mA)

A29DL322UV-80

A29DL322UV-80U

A29DL322UV-80I

A29DL322UV-80F

A29DL322UV-80UF

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL322UV-80IF

80

A29DL322UG-80

10

20

0.5

A29DL322UG-80U

A29DL322UG-80I

A29DL322UG-80F

A29DL322UG-80UF

A29DL322UG-80IF

A29DL323UV-80

A29DL323UV-80U

A29DL323UV-80I

A29DL323UV-80F

A29DL323UV-80UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL323UV-80IF

80

A29DL323UG-80

A29DL323UG-80U

A29DL323UG-80I

A29DL323UG-80F

A29DL323UG-80UF

A29DL323UG-80IF

A29DL324UV-80

A29DL324UV-80U

A29DL324UV-80I

A29DL324UV-80F

A29DL324UV-80UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL324UV-80IF

80

A29DL324UG-80

A29DL324UG-80U

A29DL324UG-80I

A29DL324UG-80F

A29DL324UG-80UF

A29DL324UG-80IF

48 pin TFBGA

48 pin Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C, -I is for industrial operating temperature range: -25°C to +85°C

(November, 2007, Version 1.2)

52

AMIC Technology, Corp.

A29DL32x Series

Ordering Information (continued)

Bottom Boot Sector Flash

Standby

Current

Typ. (μA)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Access Time

Part No.

(ns)

Package

Typ. (mA)

A29DL322UV-90

A29DL322UV-90U

A29DL322UV-90I

A29DL322UV-90F

A29DL322UV-90UF

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL322UV-90IF

90

A29DL322UG-90

10

20

0.5

A29DL322UG-90U

A29DL322UG-90I

A29DL322UG-90F

A29DL322UG-90UF

A29DL322UG-90IF

A29DL323UV-90

A29DL323UV-90U

A29DL323UV-90I

A29DL323UV-90F

A29DL323UV-90UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL323UV-90IF

90

A29DL323UG-90

A29DL323UG-90U

A29DL323UG-90I

A29DL323UG-90F

A29DL323UG-90UF

A29DL323UG-90IF

A29DL324UV-90

A29DL324UV-90U

A29DL324UV-90I

A29DL324UV-90F

A29DL324UV-90UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL324UV-90IF

90

A29DL324UG-90

A29DL324UG-90U

A29DL324UG-90I

A29DL324UG-90F

A29DL324UG-90UF

A29DL324UG-90IF

48 pin TFBGA

48 pin Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C, -I is for industrial operating temperature range: -25°C to +85°C

(November, 2007, Version 1.2)

53

AMIC Technology, Corp.

A29DL32x Series

Ordering Information (continued)

Bottom Boot Sector Flash

Standby

Current

Typ. (μA)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Access Time

Part No.

(ns)

Package

Typ. (mA)

A29DL322UV-120

A29DL322UV-120U

A29DL322UV-120I

A29DL322UV-120F

A29DL322UV-120UF

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL322UV-120IF

120

A29DL322UG-120

10

20

0.5

A29DL322UG-120U

A29DL322UG-120I

A29DL322UG-120F

A29DL322UG-120UF

A29DL322UG-120IF

A29DL323UV-120

A29DL323UV-120U

A29DL323UV-120I

A29DL323UV-120F

A29DL323UV-120UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL323UV-120IF

120

A29DL323UG-120

A29DL323UG-120U

A29DL323UG-120I

A29DL323UG-120F

A29DL323UG-120UF

A29DL323UG-120IF

A29DL324UV-120

A29DL324UV-120U

A29DL324UV-120I

A29DL324UV-120F

A29DL324UV-120UF

48 pin TFBGA

48 pin Pb-Free TFBGA

48 pin TSOP

48 pin Pb-Free TSOP

48 pin TFBGA

A29DL324UV-120IF

120

A29DL324UG-120

A29DL324UG-120U

A29DL324UG-120I

A29DL324UG-120F

A29DL324UG-120UF

A29DL324UG-120IF

48 pin TFBGA

48 pin Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C, -I is for industrial operating temperature range: -25°C to +85°C

(November, 2007, Version 1.2)

54

AMIC Technology, Corp.

A29DL32x Series

Package Information

TSOP 48L (Type I) Outline Dimensions

unit: inches/mm

D

D1

1

48

D

24

25

θ

L

Detail "A"

Dimensions in inches

Dimensions in mm

Symbol

Min

-

Nom

Max

Min

Nom

Max

A

A1

A2

b

-

0.047

0.006

0.042

0.011

0.008

0.795

0.728

0.476

-

1.20

0.15

0.002

0.037

0.007

0.004

0.779

0.720

-

0.05

0.94

0.18

0.12

19.80

18.30

-

1.00

0.039

0.009

-

1.06

0.22

0.27

c

-

0.20

D

D1

E

e

0.787

0.724

0.472

0.020 BASIC

20.00

18.40

12.00

0.50 BASIC

0.60

20.20

18.50

12.10

L

0.020

0.024 0.0275

0.011 Typ.

0.50

0.70

S

y

0.28 Typ.

-

0.004

8°

-

0.10

8°

0°

-

θ

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

(November, 2007, Version 1.2)

55

AMIC Technology, Corp.

A29DL32x Series

Package Information

48LD CSP (6 x 8 mm) Outline Dimensions

(48TFBGA)

unit: mm

TOP VIEW

BOTTOM VIEW

b

1

2

3

4

5

6

5

4

3

2

1

H

G

F

H

G

F

E

D

C

B

A

E

D

C

B

A

e

D¹

Ball*A1 CORNER

D

SIDE VIEW

C

SEATING PLANE

0.10

C

Dimensions in mm

Symbol

Min.

Nom.

Max.

A

A1

b

-

0.25

1.20

0.30

0.40

6.10

0.20

0.30

5.90

-

D

6.00

D1

e

4.00 BSC

0.80

-

E

7.90

8.00

8.10

E1

5.60 BSC

(November, 2007, Version 1.2)

56

AMIC Technology, Corp.


型号：	A29DL322UG-90IF
厂家：	AMIC TECHNOLOGY
描述：	Flash, 2MX16, 90ns, PBGA48
文件：	总57页 (文件大小：711K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A29DL322UG-90IF [AMICC]

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