A29L160BTG-70F/Q_技术文档

A29L160B Series

2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only,

Boot Sector Flash Memory

Document Title

2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory

Revision History

Rev. No. History

Issue Date

June 5, 2013

June 10, 2014

Remark

Preliminary

Final

0.0

1.0

Initial issue

Update I^CC1~ICC5, VID, Absolute Maximum Rating, Program/Erase Time,

Data Retention, Regulated Voltage Range

1.1

Page 6 “Writing Commands/Command Sequences” section :

Change

August 5, 2014

The “Word/Byte Program Command Sequence” section has details on

programming data to the device using both standard and Unlock Bypass

command sequence.

Into

The “Word/Byte Program Command Sequence” and “Unlock Bypass

Command Sequence” has detail descriptions on programming data to the

device using both standard and Unlock Bypass command sequence.

Page 17: Delete Note 8 and adjust the Notes in Table 9

1.2

August 12, 2014

(August, 2014, Version 1.2)

AMIC Technology, Corp.

A29L160B Series

2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only,

Boot Sector Flash Memory

Features

Single power supply operation

- Regulated voltage range: 2.7 to 3.6 volt read and write

operations for compatibility with high performance 3.3

volt microprocessors

Access times:

- 70ns (max.)

Current:

-

Embedded Program algorithm automatically writes and

verifies data at specified addresses

Minimum 100,000 program/erase cycles per sector

20-year data retention 125°C

- Reliable operation for the life of the system

CFI (Common Flash Interface) compliant

- Provides device-specific information to the system,

allowing host software to easily reconfigure for different

Flash devices

- 15mA typical active read current

- 30mA typical program/erase current

- 3μA typical CMOS standby

Compatible with JEDEC-standards

- Pinout and software compatible with single-power-supply

Flash memory standard

- Superior inadvertent write protection

- 3μA Automatic Sleep Mode current

Flexible sector architecture

- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors

- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors

- Any combination of sectors can be erased

- Supports full chip erase

Polling and toggle bits

Data

- Provides a software method of detecting completion of

program or erase operations

- Sector protection:

Ready /

pin (RY /

)

BY

BUSY

A hardware method of protecting sectors to prevent any

inadvertent program or erase operations within that

sector. Temporary Sector Unprotect feature allows code

changes in previously locked sectors

- Provides a hardware method of detecting completion of

program or erase operations

Erase Suspend/Erase Resume

- Suspends a sector erase operation to read data from, or

program data to, a non-erasing sector, then resumes the

erase operation

Unlock Bypass Program Command

- Reduces overall programming time when issuing

multiple program command sequence

Top or bottom boot block configurations available

Embedded Algorithms

Hardware reset pin (

)

RESET

- Hardware method to reset the device to reading array

data

Package options

- Embedded Erase algorithm will automatically erase the

entire chip or any combination of designated sectors and

verify the erased sectors

- 48-pin TSOP (I) or 48-ball TFBGA

- All Pb-free (Lead-free) products are RoHS2.0 compliant

General Description

The A29L160B is a 16Mbit, 3.3 volt-only Flash memory

organized as 2,097,152 bytes of 8 bits or 1,048,576 words of

16 bits each. The 8 bits of data appear on I/O⁰- I/O7; the 16

bits of data appear on I/O⁰~I/O15. The A29L160B is offered in

48-ball FBGA and 48-Pin TSOP packages. This device is

designed to be programmed in-system with the standard

system 3.3 volt VCC supply. Additional 12.0 volt VPP is not

required for in-system write or erase operations. However,

the A29L160B can also be programmed in standard EPROM

programmers.

The A29L160B has the first toggle bit, I/O⁶, which indicates

whether an Embedded Program or Erase is in progress, or it

is in the Erase Suspend. Besides the I/O6 toggle bit, the

A29L160B has a second toggle bit, I/O², to indicate whether

the addressed sector is being selected for erase. The

A29L160B also offers the ability to program in the Erase

Suspend mode. The standard A29L160B offers access times

of 70ns, allowing high-speed microprocessors to operate

without wait states. To eliminate bus contention the device

has separate chip enable (

), write enable (

) and

WE

CE

output enable (

) controls.

OE

The device requires only a single 3.3 volt power supply for

both read and write functions. Internally generated and

regulated voltages are provided for the program and erase

operations.

The A29L160B is entirely software command set compatible

with the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register contents

serve as input to an internal state-machine that controls the

erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and

erase operations. Reading data out of the device is similar to

reading from other Flash or EPROM devices.

Device programming occurs by writing the proper program

command sequence. This initiates the Embedded Program

algorithm - an internal algorithm that automatically times the

program pulse widths and verifies proper program margin.

(August, 2014, Version 1.2)

1

AMIC Technology, Corp.

A29L160B Series

Device erasure occurs by executing the proper erase

command sequence. This initiates the Embedded Erase

The hardware sector protection feature disables operations

for both program and erase in any combination of the

sectors of memory. This can be achieved via programming

equipment.

The Erase Suspend/Erase Resume feature enables the user

to put erase on hold for any period of time to read data from,

or program data to, any other sector that is not selected for

erasure. True background erase can thus be achieved.

algorithm

-

an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper erase margin. The Unlock Bypass mode

facilitates faster programming times by requiring only two

write cycles to program data instead of four.

The hardware

pin terminates any operation in

RESET

progress and resets the internal state machine to reading

array data. The pin may be tied to the system reset

The host system can detect whether a program or erase

operation is complete by observing the RY /

pin, or by

BY

RESET

reading the I/O⁷(

Polling) and I/O6 (toggle) status bits.

Data

circuitry. A system reset would thus also reset the device,

enabling the system microprocessor to read the boot-up

firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of time,

the device enters the automatic sleep mode. The system can

also place the device into the standby mode. Power

consumption is greatly reduced in both these modes.

After a program or erase cycle has been completed, the

device is ready to read array data or accept another

command.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data

contents of other sectors. The A29L160B is fully erased

when shipped from the factory.

(August, 2014, Version 1.2)

2

AMIC Technology, Corp.

A29L160B Series

Pin Configurations

TSOP (I)

A15

A14

A13

A12

A11

A10

A9

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

2

BYTE

VSS

I/O15(A-1)

I/O7

3

4

5

6

I/O14

I/O6

7

A8

8

I/O13

I/O5

9

A19

NC

WE

10

11

12

13

14

15

16

17

I/O12

I/O⁴

VCC

I/O11

I/O3

RESET

NC

A29L160BV

NC

I/O10

I/O²

I/O⁹

I/O1

I/O8

RY/BY

A18

A17

A7

A6

A5

A4

A3

A2

A1

18

19

20

21

22

23

24

I/O0

OE

VSS

CE

A0

TFBGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16

BYTE

I/O15(A-1)

VSS

G5

A5

B5

C5

D5

E5

F5

H5

A9

A8

A10

A11

I/O⁷

I/O14

I/O13

I/O6

A4

B4

C4

D4

E4

F4

G4

H4

WE

A3

RESET

NC

A19

I/O5

I/O12

VCC

I/O4

B3

C3

D3

E3

F3

G3

H3

RY/BY

NC

A18

NC

I/O2

I/O10

I/O11

I/O3

A2

B2

C2

A6

D2

A5

E2

F2

G2

H2

A7

A17

I/O0

I/O8

I/O9

I/O1

A1

B1

C1

A2

D1

A1

E1

F1

G1

H1

A3

A4

A0

CE

OE

VSS

(August, 2014, Version 1.2)

3

AMIC Technology, Corp.

A29L160B Series

Block Diagram

RY/BY

I/O0 - I/O15 (A-1)

VCC

VSS

Sector Switches

Input/Output

Buffers

Erase Voltage

Generator

RESET

State

Control

WE

BYTE

PGM Voltage

Generator

Command

Register

Chip Enable

Output Enable

Logic

STB

Data Latch

CE

OE

Y-Gating

Y-Decoder

STB

VCC Detector

Timer

A0-A19

X-decoder

Cell Matrix

Pin Descriptions

Pin No.

A0 - A19

I/O0 - I/O14

Description

Address Inputs

Data Inputs/Outputs

Data Input/Output, Word Mode

I/O15

I/O15 (A-1)

A-1

LSB Address Input, Byte Mode

Chip Enable

CE

WE

Write Enable

Output Enable

OE

Hardware Reset

RESET

BYTE

Selects Byte Mode or Word Mode

Ready/

- Output

BUSY

RY/

BY

VSS

Ground

VCC

NC

Power Supply

Pin not connected internally

(August, 2014, Version 1.2)

4

AMIC Technology, Corp.

A29L160B Series

Absolute Maximum Ratings*

*Comments

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to this device.

These are stress ratings only. Functional operation of

this device at these or any other conditions above

those indicated in the operational sections of these

specification is not implied or intended. Exposure to

the absolute maximum rating conditions for extended periods

may affect device reliability.

Storage Temperature Plastic Packages…… -65°C to +150°C

Ambient Temperature with Power Applied… -55°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) …………………………………... -0.5V to +4.0V

A9,

&

(Note 2)…………………… -0.5 to +11.5V

RESET

OE

All other pins (Note 1) ………………….. -0.5V to VCC + 0.5V

Output Short Circuit Current (Note 3)…………………. 200mA

Notes:

Operating Ranges

1. Minimum DC voltage on input or I/O pins is -0.5V. During

voltage transitions, input or I/O pins may undershoot VSS

to -2.0V for periods of up to 20ns. Maximum DC voltage

on input and I/O pins is VCC + 0.5V. During voltage

transitions, input or I/O pins may overshoot to VCC +

2.0V for periods up to 20ns.

Commercial (C) Devices

Ambient Temperature (T^A)………………………. 0°C to +70°C

Extended Range Devices

Ambient Temperature (T^A)…………………… -40°C to +85°C

2. Minimum DC input voltage on A9,

and

is

OE

RESET

VCC Supply Voltages

-0.5V. During voltage transitions, A9,

and

OE

RESET

VCC for all devices . . . . . . . . . . . . . . . . . . . . +2.7V to +3.6V

Operating ranges define those limits between which the

functionally of the device is guaranteed.

may overshoot VSS to -2.0V for periods of up to 20ns.

Maximum DC input voltage on A9 is +11.5V which may

overshoot to 12.5V for periods up to 20ns.

3. No more than one output is shorted at a time. Duration of

the short circuit should not be greater than one second.

the address and data information needed to execute the

command. The contents of the register serve as inputs to the

internal state machine. The state machine outputs dictate the

function of the device. The appropriate device bus operations

table lists the inputs and control levels required, and the

resulting output. The following subsections describe each of

these operations in further detail.

Device Bus Operations

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register itself does

not occupy any addressable memory location. The register is

composed of latches that store the commands, along with

Table 1. A29L160B Device Bus Operations

Operation

A0 – A19

(Note 1)

I/O0 - I/O7

I/O8 - I/O15

=VIH

WE

CE

OE

RESET

=VIL

BYTE

Read

Write

L

H

AIN

DOUT

I/O8~I/O14=High-Z

I/O¹⁵=A-1

L

H

L

H

AIN

DIN

I/O8~I/O14=High-Z

I/O¹⁵=A-1

CMOS Standby

Output Disable

Hardware Reset

X

H

X

H

X

H

X

L

X

High-Z

D^IN

High-Z

X

High-Z

VCC ± 0.3V

L

X

L

H

L

High-Z

X

Sector Protect

(See Note 2)

V^ID

Sector Address,

A6=L, A1=H, A0=L

Sector Unprotect

(See Note 2)

L

H

X

L

V^ID

Sector Address,

A6=H, A1=H, A0=L

D^IN

X

Temporary Sector

Unprotect

X

AIN

DIN

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 10.5 ± 1.0V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In

Notes:

1. Addresses are A19:A0 in word mode (

2. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.

=VIH), A19: A in byte mode (

=VIL).

BYTE

-1

(August, 2014, Version 1.2)

5

AMIC Technology, Corp.

A29L160B Series

I^CC2in the DC Characteristics table represents the active

current specification for the write mode. The "AC

Characteristics" section contains timing specification tables

and timing diagrams for write operations.

Word/Byte Configuration

The

pin determines whether the I/O pins I/O15-I/O0

BYTE

operate in the byte or word configuration. If the

pin is

BYTE

set at logic ”1”, the device is in word configuration, I/O¹⁵-I/O0

are active and controlled by and

Program and Erase Operation Status

.

OE

CE

During an erase or program operation, the system may

check the status of the operation by reading the status bits

on I/O7 - I/O0. Standard read cycle timings and ICC read

specifications apply. Refer to "Write Operation Status" for

more information, and to each AC Characteristics section for

timing diagrams.

If the

pin is set at logic “0”, the device is in byte

BYTE

configuration, and only I/O⁰-I/O7 are active and controlled by

and . I/O8-I/O14 are tri-stated, and I/O15 pin is used

CE

OE

as an input for the LSB(A-1) address function.

Requirements for Reading Array Data

Standby Mode

To read array data from the outputs, the system must drive

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode,

current consumption is greatly reduced, and the outputs are

the

and

pins to VIL.

is the power control and

CE

OE

CE

selects the device.

is the output control and gates array

OE

data to the output pins.

placed in the high impedance state, independent of the

input.

OE

should remain at VIH all the time

WE

during read operation. The

pin determines whether

BYTE

the device outputs array data in words and bytes. The

internal state machine is set for reading array data upon

device power-up, or after a hardware reset. This ensures that

no spurious alteration of the memory content occurs during

the power transition. No command is necessary in this mode

to obtain array data. Standard microprocessor read cycles

that assert valid addresses on the device address inputs

produce valid data on the device data outputs. The device

remains enabled for read access until the command register

contents are altered.

See "Reading Array Data" for more information. Refer to the

AC Read Operations table for timing specifications and to the

Read Operations Timings diagram for the timing waveforms,

l^CC1in the DC Characteristics table represents the active

current specification for reading array data.

The device enters the CMOS standby mode when the

&

CE

pins are both held at VCC ± 0.3V. (Note that this is a

RESET

more restricted voltage range than V^IH.) If

and

CE

RESET

are held at V^IH, but not within VCC ± 0.3V, the device will be

in the standby mode, but the standby current will be greater.

The device requires the standard access time (tCE) before it

is ready to read data.

If the device is deselected during erasure or programming,

the device draws active current until the operation is

completed.

I^CC3and ICC4 in the DC Characteristics tables represent the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy

consumption. The device automatically enables this mode

when addresses remain stable for t^ACC+ 30ns. The automatic

Writing Commands/Command Sequences

To write a command or command sequence (which includes

programming data to the device and erasing sectors of

sleep mode is independent of the

,

and

control

OE

WE

CE

signals. Standard address access timings provide new data

when addresses are changed. While in sleep mode, output

data is latched and always available to the system. ICC4 in the

DC Characteristics table represents the automatic sleep

mode current specification.

memory), the system must drive

and

to VIL, and

WE

CE

to VIH. For program operations, the

BYTE

OE

determines whether the device accepts program data in

bytes or words, Refer to “Word/Byte Configuration” for more

information. The device features an Unlock Bypass mode to

facilitate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are required to

program a word or byte, instead of four.

The “Word/Byte Program Command Sequence” and “Unlock

Bypass Command Sequence” has detail descriptions on

programming data to the device using both standard and

Unlock Bypass command sequence. An erase operation can

erase one sector, multiple sectors, or the entire device. The

Sector Address Tables indicate the address range that each

sector occupies. A "sector address" consists of the address

inputs required to uniquely select a sector. See the

"Command Definitions" section for details on erasing a sector

or the entire chip, or suspending/resuming the erase

operation.

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can then

read autoselect codes from the internal register (which is

separate from the memory array) on I/O⁷- I/O0. Standard

read cycle timings apply in this mode. Refer to the

"Autoselect Mode" and "Autoselect Command Sequence"

sections for more information.

Output Disable Mode

When the

input is at VIH, output from the device is disabled.

OE

The output pins are placed in the high impedance state.

: Hardware Reset Pin

RESET

The

pin provides a hardware method of resetting the

RESET

device to reading array data. When the system drives the

pin low for at least a period of tRP, the device

RESET

immediately terminates any operation in progress, tristates all

data output pins, and ignores all read/write attempts for the

duration of the

pulse. The device also resets the

RESET

internal state machine to reading array data. The operation that

was interrupted should be reinitiated once the device is ready to

accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the

pulse.

RESET

When

is held at VSS ± 0.3V, the device draws

RESET

CMOS standby current (I^CC4). If

is held at VIL but not

RESET

within VSS ± 0.3V, the standby current will be greater.

(August, 2014, Version 1.2)

6

AMIC Technology, Corp.

A29L160B Series

The

pin may be tied to the system reset circuitry. A

RY/

to determine whether the reset operation is

BY

complete. If

RESET

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from the

Flash memory.

is asserted when a program or erase

RESET

operation is not executing (RY/

operation is completed within a time of tREADY (not during

Embedded Algorithms). The system can read data tRH after

pin is “1”), the reset

BY

If

is asserted during a program or erase operation,

pin remains a “0” (busy) until the internal reset

RESET

the RY/

the

pin return to VIH.

RESET

BY

operation is complete, which requires a time tREADY (during

Embedded Algorithms). The system can thus monitor

Refer to the AC Characteristics tables for

parameters and diagram.

RESET

Table 2. A29L160B Top Boot Block Sector Address Table

Sector Size

(Kbytes/

Kwords)

Address Range (in hexadecimal)

Sector A19

A18

A17

A16

A15

A14

A13

A12

Byte Mode

Word Mode (x16)

(x8)

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

64/32

32/16

8/4

000000 - 00FFFF

010000 - 01FFFF

020000 - 02FFFF

030000 - 03FFFF

040000 - 04FFFF

050000 - 05FFFF

060000 - 06FFFF

070000 - 07FFFF

080000 - 08FFFF

090000 - 09FFFF

0A0000 - 0AFFFF

0B0000 - 0BFFFF

0C0000 - 0CFFFF

0D0000 - 0DFFFF

0E0000 - 0EFFFF

0F0000 - 0FFFFF

100000 - 10FFFF

110000 - 11FFFF

120000 - 12FFFF

130000 - 13FFFF

140000 - 14FFFF

150000 - 15FFFF

160000 - 16FFFF

170000 - 17FFFF

180000 - 18FFFF

190000 - 19FFFF

1A0000 - 1AFFFF

1B0000 - 1BFFFF

1C0000 - 1CFFFF

1D0000 - 1DFFFF

1E0000 - 1EFFFF

1F0000 - 1F7FFF

1F8000 - 1F9FFF

1FA000 - 1FBFFF

1FC000 - 1FFFFF

00000 - 07FFF

08000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 77FFF

78000 - 7FFFF

80000 - 87FFF

88000 - 8FFFF

90000 - 97FFF

98000 - 9FFFF

A0000 - A7FFF

A8000 - AFFFF

B0000 - B7FFF

B8000 - BFFFF

C0000 - C7FFF

C8000 - CFFFF

D0000 - D7FFF

D8000 - DFFFF

E0000 - E7FFF

E8000 - EFFFF

F0000 - F7FFF

F8000 - FBFFF

FC000 - FCFFF

FD000 - FDFFF

FE000 - FFFFF

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

1

0

1

8/4

1

X

16/8

Note:

Address range is A19 : A_-1in byte mode and A19 : A0 in word mode. See “Word/Byte Configuration” section.

(August, 2014, Version 1.2)

7

AMIC Technology, Corp.

A29L160B Series

Table 3. A29L160B Bottom Boot Block Sector Address Table

Sector A19

A18

A17

A16

A15

A14

A13

A12 Sector Size

(Kbytes/

Address Range (in hexadecimal)

Byte Mode (x8)

Word Mode (x16)

Kwords)

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

16/8

8/4

000000 - 003FFF

004000 - 005FFF

006000 - 007FFF

008000 - 00FFFF

010000 - 01FFFF

020000 - 02FFFF

030000 - 03FFFF

040000 - 04FFFF

050000 - 05FFFF

060000 - 06FFFF

070000 - 07FFFF

080000 - 08FFFF

090000 - 09FFFF

0A0000 - 0AFFFF

0B0000 - 0BFFFF

0C0000 - 0CFFFF

0D0000 - 0DFFFF

0E0000 - 0EFFFF

0F0000 - 0FFFFF

100000 - 10FFFF

110000 - 11FFFF

120000 - 12FFFF

130000 - 13FFFF

140000 - 14FFFF

150000 - 15FFFF

160000 - 16FFFF

170000 - 17FFFF

180000 - 18FFFF

190000 - 19FFFF

1A0000 - 1AFFFF

1B0000 - 1BFFFF

1C0000 - 1CFFFF

1D0000 - 1DFFFF

1E0000 - 1EFFFF

1F0000 - 1FFFFF

00000 - 01FFF

02000 - 02FFF

03000 - 03FFF

04000 - 07FFF

08000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 77FFF

78000 - 7FFFF

80000 - 87FFF

88000 - 8FFFF

90000 - 97FFF

98000 - 9FFFF

A0000 - A7FFF

A8000 - AFFFF

B0000 – B7FFF

B8000 - BFFFF

C0000 - C7FFF

C8000 - CFFFF

D0000 - D7FFF

D8000 - DFFFF

E0000 - E7FFF

E8000 - EFFFF

F0000 - F7FFF

F8000 - FFFFF

SA2

0

1

8/4

SA3

1

X

32/16

64/32

SA4

X

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

Note:

Address range is A19 : A_-1in byte mode and A19 : A0 in word mode. See “Word/Byte Configuration” section.

(August, 2014, Version 1.2)

8

AMIC Technology, Corp.

A29L160B Series

protection, the sector address must appear on the

appropriate highest order address bits. Refer to the

corresponding Sector Address Tables. The Command

Definitions table shows the remaining address bits that are

don't care. When all necessary bits have been set as

required, the programming equipment may then read the

corresponding identifier code on I/O⁷- I/O0.To access the

autoselect codes in-system, the host system can issue the

autoselect command via the command register, as shown in

the Command Definitions table. This method does not

require V^ID. See "Command Definitions" for details on using

the autoselect mode.

Autoselect Mode

The autoselect mode provides manufacturer and device

identification, and sector protection verification, through

identifier codes output on I/O7 - I/O0. This mode is primarily

intended for programming equipment to automatically match

a

device to be programmed with its corresponding

programming algorithm. However, the autoselect codes can

also be accessed in-system through the command register.

When using programming equipment, the autoselect mode

requires V^ID(9.5V to 11.5V) on address pin A9. Address pins

A6, A1, and A0 must be as shown in Autoselect Codes (High

Voltage Method) table. In addition, when verifying sector

Table 4. A29L160B Autoselect Codes (High Voltage Method)

Mode

Description

A19 A11 A9 A8 A6 A5 A1 A0

I/O⁸

to

I/O⁷

to

WE

CE

OE

to

A12 A10

A7

A2

I/O¹⁵

I/O⁰

Manufacturer ID: AMIC

L

H

X

VID

X

L

X

L

X

37h

Device ID:

22h

C4h

Word

V^ID

H

A29L160B

Byte

X

C4h

49h

(Top Boot Block)

Device ID:

Word

22h

A29L160B

L

H

X

V^ID

VID

X

L

X

L

H

L

Byte

X

49h

7Fh

(Bottom Boot Block)

Continuation ID

01h

(protected)

X

Sector Protection Verification

SA

00h

(unprotected)

L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care.

Note: The autoselect codes may also be accessed in-system via command sequences.

(August, 2014, Version 1.2)

9

AMIC Technology, Corp.

A29L160B Series

Sector Protection/Unprotection

Temporary Sector Unprotect

The hardware sector protection feature disables both

program and erase operations in any sector. The hardware

sector unprotection feature re-enables both program and

erase operations in previously protected sectors.

It is possible to determine whether a sector is protected or

unprotected. See “Autoselect Mode” for details.

This feature allows temporary unprotection of previous

protected sectors to change data in-system. The Sector

Unprotect mode is activated by setting the

pin to VID.

RESET

During this mode, formerly protected sectors can be

programmed or erased by selecting the sector addresses.

Once V^IDis removed from the

pin, all the previously

RESET

Sector protection / unprotection can be implemented via two

methods. The primary method requires VID on the

protected sectors are protected again. Figure 1 shows the

algorithm, and the Temporary Sector Unprotect diagram

shows the timing waveforms, for this feature.

pin only, and can be implemented either in-system or

RESET

via programming equipment. Figure 2 shows the algorithm

and the Sector Protect / Unprotect Timing Diagram illustrates

the timing waveforms for this feature. This method uses

standard microprocessor bus cycle timing. For sector

unprotect, all unprotected sectors must first be protected

prior to the first sector unprotect write cycle. The alternate

method must be implemented using programming

equipment. The procedure requires a high voltage (V^ID) on

address pin A9 and the control pins.

START

The device is shipped with all sectors unprotected.

It is possible to determine whether a sector is protected or

unprotected. See "Autoselect Mode" for details.

RESET = VID

(Note 1)

Hardware Data Protection

The requirement of command unlocking sequence for

programming or erasing provides data protection against

inadvertent writes (refer to the Command Definitions table).

In addition, the following hardware data protection measures

prevent accidental erasure or programming, which might

otherwise be caused by spurious system level signals during

VCC power-up transitions, or from system noise. The device

is powered up to read array data to avoid accidentally writing

data to the array.

Perform Erase or

Program Operations

RESET = VIH

Write Pulse "Glitch" Protection

Temporary Sector

Unprotect

Completed (Note 2)

Noise pulses of less than 5ns (typical) on

do not initiate a write cycle.

,

or

WE

OE CE

Logical Inhibit

Write cycles are inhibited by holding any one of

=VIL,

OE

CE

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

= VIH or

= VIH. To initiate a write cycle,

and

CE

WE

must be a logical zero while

is a logical one.

WE

OE

Power-Up Write Inhibit

Figure 1. Temporary Sector Unprotect Operation

If

=

= VIL and

= VIH during power up, the

OE

WE

device does not accept commands on the rising edge of

. The internal state machine is automatically reset to

CE

WE

reading array data on the initial power-up.

(August, 2014, Version 1.2)

10

AMIC Technology, Corp.

A29L160B Series

START

Protect all sectors:

The indicated portion of

the sector protect

PLSCNT=1

algorithm must be

performed for all

RESET=VID

unprotected sectors prior

to issuing the first sector

unprotect address

Wait 1 us

No

Temporary Sector

Unprotect Mode

First Write

Cycle=60h?

First Write

Cycle=60h?

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

All sectors

protected?

Sector Protec:

Write 60h to sector

address with A6=0,

A1=1, A0=0

Yes

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with A6=1,

A1=1, A0=0

Wait 150 us

Verify Sector

Protect: Write 40h

to sector address

with A6=0, A1=1,

A0=0

Reset

PLSCNT=1

Increment

PLSCNT

Wait 500 ms

Verify Sector

Unprotect : Write

40h to sector

address with A6=1,

A1=1, A0=0

Read from

sector address

with A6=0,

Increment

PLSCNT

A1=1, A0=0

No

Read from sector

address with A6=1,

A1=1, A0=0

No

PLSCNT

=25?

Data=01h?

Yes

No

Set up

next sector

address

Yes

No

PLSCNT=

1000?

Yes

Data=00h?

Yes

Protect another

sector?

Device failed

Yes

No

Remove VID

from RESET

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove VID

from RESET

Sector Protect

complete

Sector Protect

Algorithm

Sector Unprotect

Algorithm

Write reset

Command

Sector Unprotect

complete

Figure 2. In-System Sector Protect/Unprotect Algorithms

(August, 2014, Version 1.2)

11

AMIC Technology, Corp.

A29L160B Series

ready to read array data. The system can read CFI

information at the addresses given in Table 5-8. In word

mode, the upper address bits (A7-MSB) must be all zeros.

To terminate reading CFI data, the system must write the

reset command.

The system can also write the CFI query command when the

device is in the autoselect mode. The device enters the CFI

query mode, and the system can read CFI data at the

addresses given in Table 5-8. The system must write the

reset command to return the device to the autoselect mode.

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines

device and host system software interrogation handshake,

which allows specific vendor-specified software algorithms to

be used for entire families of devices. Software support can

then be device-independent, JEDEC ID-independent, and

forward- and backward-compatible for the specified flash

device families. Flash vendors can standardize their existing

interface for long-term compatibility.

This device enters the CFI Query mode when the system

writes the CFI Query command, 98h, to address 55h in word

mode (or address AAh in byte mode), any time the device is

Table 5. CFI Query Identification String

Addresses

Data

Description

(Word Mode)

(Byte Mode)

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

0051h

0052h

0059h

0002h

0000h

0040h

0000h

Query Unique ASCII string “QRY”

Primary OEM Command Set

Address for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

Table 6 System Interface String

Addresses

(Word Mode)

1Bh

Addresses

(Byte Mode)

36h

Data

Description

0027h

0036h

VCC Min. (write/erase)

I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt

1Ch

38h

VCC Max. (write/erase)

I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

Vpp Min. voltage (00h = no Vpp pin present)

Vpp Max. voltage (00h = no Vpp pin present)

Typical timeout per single byte/word write 2^Nμs

Typical timeout for Min. size buffer write 2^Nμs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

(August, 2014, Version 1.2)

12

AMIC Technology, Corp.

A29L160B Series

Table 7 Device Geometry Definition

Addresses

Data

Description

(Word Mode)

(Byte Mode)

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3BH

3Ch

4Eh

50h

52h

54h

56h

58h

5Ah

5Ch

5Eh

60h

62h

64h

66h

68h

6Ah

6Ch

6Eh

70h

72h

74h

76h

78h

0015h

0002h

0000h

0004h

0000h

0040h

0000h

0001h

0000h

0020h

0000h

0080h

0000h

001Eh

0000h

0001h

Device Size = 2^Nbyte

Flash Device Interface description

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

Number of Erase Block Regions within device

Erase Block Region 1 Information

(refer to the CFI specification)

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

Table 8 Primary Vendor-Specific Extended Query

Addresses

Data

Description

(Word Mode)

(Byte Mode)

40h

41h

42h

43h

44h

80h

82h

84h

86h

88h

0050h

0052h

0049h

0031h

0030h

Query-unique ASCII string “PRI”

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock

0 = Required, 1 = Not Required

Erase Suspend

45h

46h

47h

48h

8Ah

8Ch

8Eh

90h

0000h

0002h

0001h

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29L160 mode

Simultaneous Operation

49h

92h

0004h

4Ah

48h

4Ch

94h

96h

98h

0000h

00 = Not Supported, 01 = Supported

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

(August, 2014, Version 1.2)

13

AMIC Technology, Corp.

A29L160B Series

Command Definitions

Autoselect Command Sequence

Writing specific address and data commands or sequences

into the command register initiates device operations. The

Command Definitions table defines the valid register

command sequences. Writing incorrect address and data

values or writing them in the improper sequence resets the

device to reading array data.

The autoselect command sequence allows the host system to

access the manufacturer and devices codes, and determine

whether or not a sector is protected. The Command

Definitions table shows the address and data requirements.

This method is an alternative to that shown in the Autoselect

Codes (High Voltage Method) table, which is intended for

PROM programmers and requires V^IDon address bit A9.

The autoselect command sequence is initiated by writing two

unlock cycles, followed by the autoselect command. The

device then enters the autoselect mode, and the system may

read at any address any number of times, without initiating

another command sequence.

All addresses are latched on the falling edge of

or

,

CE

WE

whichever happens later. All data is latched on the rising

edge of or , whichever happens first. Refer to the

WE

CE

appropriate timing diagrams in the "AC Characteristics"

section.

A read cycle at address XX00h retrieves the manufacturer

code and another read cycle at XX11h retrieves the

continuation code. A read cycle at address XX01h returns the

device code. A read cycle containing a sector address (SA)

and the address 02h in returns 01h if that sector is protected,

or 00h if it is unprotected. Refer to the Sector Address tables

for valid sector addresses.

Reading Array Data

The device is automatically set to reading array data after

device power-up. No commands are required to retrieve

data. The device is also ready to read array data after

completing an Embedded Program or Embedded Erase

algorithm. After the device accepts an Erase Suspend

command, the device enters the Erase Suspend mode. The

system can read array data using the standard read timings,

except that if it reads at an address within erase-suspended

sectors, the device outputs status data. After completing a

programming operation in the Erase Suspend mode, the

system may once again read array data with the same

exception. See "Erase Suspend/Erase Resume Commands"

for more information on this mode.

The system must issue the reset command to re-enable the

device for reading array data if I/O⁵goes high, or while in the

autoselect mode. See the "Reset Command" section, next.

See also "Requirements for Reading Array Data" in the

"Device Bus Operations" section for more information. The

Read Operations table provides the read parameters, and

Read Operation Timings diagram shows the timing diagram.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte,

depending on the state of the

pin. Programming is a

BYTE

four-bus-cycle operation. The program command sequence is

initiated by writing two unlock write cycles, followed by the

program set-up command. The program address and data are

written next, which in turn initiate the Embedded Program

algorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verify the

programmed cell margin. Table 9 shows the address and data

requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the

device then returns to reading array data and addresses are

longer latched. The system can determine the status of the

Reset Command

Writing the reset command to the device resets the device to

reading array data. Address bits are don't care for this

command. The reset command may be written between the

sequence cycles in an erase command sequence before

erasing begins. This resets the device to reading array data.

Once erasure begins, however, the device ignores reset

commands until the operation is complete.

program operation by using I/O⁷, I/O6, or RY/

. See “Write

BY

Operation Status” for information on these status bits.

Any commands written to the device during the Embedded

Program Algorithm are ignored. Note that a hardware reset

immediately terminates the programming operation. The Byte

Program command sequence should be reinitiated once the

device has reset to reading array data, to ensure data

integrity.

Programming is allowed in any sequence and across sector

boundaries. A bit cannot be programmed from a “0” back to a

“1”. Attempting to do so may halt the operation and set I/O5 to

The reset command may be written between the sequence

cycles in

a

program command sequence before

programming begins. This resets the device to reading array

data (also applies to programming in Erase Suspend mode).

Once programming begins, however, the device ignores

reset commands until the operation is complete.

The reset command may be written between the sequence

cycles in an autoselect command sequence. Once in the

autoselect mode, the reset command must be written to

return to reading array data (also applies to autoselect during

Erase Suspend).

“1”, or cause the

Polling algorithm to indicate the

Data

operation was successful. However, a succeeding read will

show that the data is still “0”. Only erase operations can

convert a “0” to a “1”.

If I/O⁵goes high during a program or erase operation, writing

the reset command returns the device to reading array data

(also applies during Erase Suspend).

(August, 2014, Version 1.2)

14

AMIC Technology, Corp.

A29L160B Series

00h. Addresses are don’t care for both cycle. The device

returns to reading array data.

Figure 3 illustrates the algorithm for the program operation.

See the Erase/Program Operations in “AC Characteristics” for

parameters, and to Program Operation Timings for timing

diagrams.

START

Write Program

Command

Chip Erase Command Sequence

Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the chip erase command, which

in turn invokes the Embedded Erase algorithm. The device

does not require the system to preprogram prior to erase. The

Embedded Erase algorithm automatically preprograms and

verifies the entire memory for an all zero data pattern prior to

electrical erase. The system is not required to provide any

controls or timings during these operations. The Command

Definitions table shows the address and data requirements

for the chip erase command sequence.

Any commands written to the chip during the Embedded

Erase algorithm are ignored. The system can determine the

status of the erase operation by using I/O⁷, I/O6, or I/O2. See

"Write Operation Status" for information on these status bits.

When the Embedded Erase algorithm is complete, the device

returns to reading array data and addresses are no longer

latched.

Data Poll

from System

Embedded

Program

algorithm in

progress

Verify Data ?

Yes

No

Increment Address

Last Address ?

Yes

Figure 4 illustrates the algorithm for the erase operation. See

the Erase/Program Operations tables in "AC Characteristics"

for parameters, and to the Chip/Sector Erase Operation

Timings for timing waveforms.

Programming

Completed

Sector Erase Command Sequence

Sector erase is a six-bus-cycle operation. The sector erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the address of the sector to be

erased, and the sector erase command. The Command

Definitions table shows the address and data requirements

for the sector erase command sequence.

The device does not require the system to preprogram the

memory prior to erase. The Embedded Erase algorithm

automatically programs and verifies the sector for an all zero

data pattern prior to electrical erase. The system is not

required to provide any controls or timings during these

operations.

After the command sequence is written, a sector erase time-

out of 50μs begins. During the time-out period, additional

sector addresses and sector erase commands may be

written. Loading the sector erase buffer may be done in any

sequence, and the number of sectors may be from one sector

to all sectors. The time between these additional cycles must

be less than 50μs, otherwise the last address and command

might not be accepted, and erasure may begin. It is

recommended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional sector

erase commands can be assumed to be less than 50μs, the

system need not monitor I/O³. Any command other than

Sector Erase or Erase Suspend during the time-out period

resets the device to reading array data. The system must

rewrite the command sequence and any additional sector

addresses and commands.

Note : See the appropriate Command Definitions table for

program command sequence.

Figure 3. Program Operation

Unlock Bypass Command Sequence

The Unlock Bypass feature allows the system to program

bytes or words to the device faster than using the standard

program command sequence. The Unlock Bypass command

sequence is initiated by first writing two unlock cycles. This is

followed by a third write cycle containing the Unlock Bypass

command, 20h. The device then enters the Unlock Bypass

mode. A two-cycle Unlock Bypass program command

sequence is all that is required to program in this mode. The

first cycle in this sequence contains the Unlock Bypass

program command, A0h; the second cycle contains the

program address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial two

unlock cycles required in the standard program command

sequence, resulting in faster total programming time. Table 9

shows the requirements for the command sequence.

During the Unlock Bypass mode, only the Unlock Bypass

Program and Unlock Bypass Reset commands are valid. To

exit the Unlock Bypass mode, the system must issue the two-

cycle Unlock Bypass reset command sequence. The first

cycle must contain the data 90h; the second cycle the data

(August, 2014, Version 1.2)

15

AMIC Technology, Corp.

A29L160B Series

The system can monitor I/O3 to determine if the sector erase

timer has timed out. (See the " I/O³: Sector Erase Timer"

section.) The time-out begins from the rising edge of the final

The system must write the Erase Resume command

(address bits are "don't care") to exit the erase suspend

mode and continue the sector erase operation. Further writes

of the Resume command are ignored. Another Erase

Suspend command can be written after the device has

resumed erasing.

pulse in the command sequence.

WE

Once the sector erase operation has begun, only the Erase

Suspend command is valid. All other commands are ignored.

When the Embedded Erase algorithm is complete, the device

returns to reading array data and addresses are no longer

latched. The system can determine the status of the erase

operation by using I/O⁷, I/O6, or I/O2. Refer to "Write

Operation Status" for information on these status bits.

START

4 illustrates the algorithm for the erase operation. Refer to

the Erase/Program Operations tables in the "AC

Characteristics" section for parameters, and to the Sector

Erase Operations Timing diagram for timing waveforms.

Write Erase

Command

Sequence

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt

a sector erase operation and then read data from, or

program data to, any sector not selected for erasure. This

command is valid only during the sector erase operation,

including the 50μs time-out period during the sector erase

command sequence. The Erase Suspend command is

ignored if written during the chip erase operation or

Embedded Program algorithm. Writing the Erase Suspend

command during the Sector Erase time-out immediately

terminates the time-out period and suspends the erase

operation. Addresses are "don't cares" when writing the

Erase Suspend command.

Data Poll

from System

Embedded

Erase

algorithm in

progress

No

Data = FFh ?

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum of

20μs to suspend the erase operation. However, when the

Erase Suspend command is written during the sector erase

time-out, the device immediately terminates the time-out

period and suspends the erase operation.

Yes

Erasure Completed

After the erase operation has been suspended, the system

can read array data from or program data to any sector not

selected for erasure. (The device "erase suspends" all

sectors selected for erasure.) Normal read and write timings

and command definitions apply. Reading at any address

within erase-suspended sectors produces status data on I/O⁷

- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to

determine if a sector is actively erasing or is erase-

suspended. See "Write Operation Status" for information on

these status bits.

Note :

1. See the appropriate Command Definitions table for erase

command sequences.

2. See "I/O

3

: Sector Erase Timer" for more information.

Figure 4. Erase Operation

After an erase-suspended program operation is complete,

the system can once again read array data within non-

suspended sectors. The system can determine the status of

the program operation using the I/O⁷or I/O6 status bits, just

as in the standard program operation. See "Write Operation

Status" for more information.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend mode.

The device allows reading autoselect codes even at

addresses within erasing sectors, since the codes are not

stored in the memory array. When the device exits the

autoselect mode, the device reverts to the Erase Suspend

mode, and is ready for another valid operation. See

"Autoselect Command Sequence" for more information.

(August, 2014, Version 1.2)

16

AMIC Technology, Corp.

A29L160B Series

Table 9. A29L160B Command Definitions

Bus Cycles (Notes 2 - 4)

Third Fourth

Addr Data Addr Data Addr Data Addr

Command

Sequence

(Note 1)

First

Second

Fifth

Sixth

Data

Addr Data Addr Data

Read (Notes 5, 6)

Reset (Note 6)

1

RA

XXX

555

AAA

555

AAA

555

AAA

555

RD

F0

Word

Byte

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

2AA

555

AAA

555

AAA

555

Manufacturer ID

4

AA

55

90

X00

37

X01

X02

X01

X02

X03

X06

22C4

C4

2249

49

Device ID,

Top Boot Block

Device ID,

Bottom Boot Block

AAA

555

Continuation ID

7F

AAA

XX00

XX01

00

(SA)

X02

Word

Byte

555

2AA

555

Sector Protect Verify

(Note 8)

4

AA

55

90

(SA)

X04

AAA

01

Word

Byte

Word

Byte

Word

Byte

55

AA

CFI Query (Note 9)

Program

1

4

3

98

AA

555

AAA

555

AAA

XXX

555

AAA

555

AAA

XXX

2AA

555

2AA

555

PA

XXX

2AA

555

2AA

555

AAA

555

55

A0

20

PA

PD

Unlock Bypass

AAA

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

2

A0

90

PD

00

Word

555

AAA

555

AAA

555

2AA

555

2AA

555

AAA

Chip Erase

Byte

6

AA

55

80

AA

55

10

30

Word

Sector Erase

Byte

SA

AAA

Erase Suspend (Note 12)

Erase Resume (Note 13)

1

B0

30

Legend:

X = Don't care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the

whichever happens later.

or

pulse,

WE

CE

PD = Data to be programmed at location PA. Data latches on the rising edge of

or

pulse, whichever happens first.

CE

WE

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19 - A12 select a unique sector.

Note:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles are write operation.

4. Address bits A19 - A11 are don't cares for unlock and command cycles, unless SA or PA required.

5. No unlock or command cycles required when reading array data.

6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O⁵goes high

(while the device is providing status data).

7. The fourth cycle of the autoselect command sequence is a read cycle.

8. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more

information.

9. Command is valid when device is ready to read array data or when device is in autoselect mode.

10. The Unlock Bypass command is required prior to the Unlock Bypass Program command.

11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the Unlock Bypass mode.

12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.

13. The Erase Resume command is valid only during the Erase Suspend mode.

(August, 2014, Version 1.2)

17

AMIC Technology, Corp.

A29L160B Series

Write Operation Status

Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/

the A29L160B to determine the status of a write operation.

Table 10 and the following subsections describe the

are provided in

BY

START

functions of these status bits. I/O⁷, I/O6 and RY/

each

BY

offer a method for determining whether a program or erase

operation is complete or in progress. These three bits are

discussed first.

Read I/O

Address = VA

7-I/O0

I/O7:

Polling

Data

The

Polling bit, I/O7, indicates to the host system

Data

whether an Embedded Algorithm is in progress or completed,

Yes

I/O

7

= Data ?

No

or whether the device is in Erase Suspend. Polling is

Data

pulse in the

valid after the rising edge of the final

program or erase command sequence.

WE

During the Embedded Program algorithm, the device outputs

on I/O⁷the complement of the datum programmed to I/O7.

This I/O⁷status also applies to programming during Erase

Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to I/O7.

The system must provide the program address to read valid

status information on I/O⁷. If a program address falls within a

No

I/O5 = 1?

Yes

protected sector,

Polling on I/O7 is active for

Data

approximately 2μs, then the device returns to reading array

data.

Read I/O

7

- I/O0

During the Embedded Erase algorithm,

Polling

Data

Address = VA

produces a "0" on I/O7. When the Embedded Erase algorithm

is complete, or if the device enters the Erase Suspend mode,

Polling produces a "1" on I/O7.This is analogous to the

Data

complement/true datum output described for the Embedded

Program algorithm: the erase function changes all the bits in

a sector to "1"; prior to this, the device outputs the

"complement," or "0." The system must provide an address

within any of the sectors selected for erasure to read valid

status information on I/O⁷.

Yes

I/O7

= Data ?

No

After an erase command sequence is written, if all sectors

selected for erasing are protected,

Polling on I/O7 is

Data

active for approximately 100μs, then the device returns to

reading array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are protected.

When the system detects I/O7 has changed from the

complement to true data, it can read valid data at I/O⁷- I/O0

on the following read cycles. This is because I/O⁷may

change asynchronously with I/O⁰- I/O6 while Output Enable

FAIL

PASS

Note :

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

(

) is asserted low. The

Polling Timings (During

Data

OE

Embedded Algorithms) figure in the "AC Characteristics"

section illustrates this. Table 10 shows the outputs for

2. I/O

7

should be rechecked even if I/O

may change simultaneously with I/O

5 = "1" because

I/O7

5

.

Data

Polling algorithm.

Polling on I/O⁷. Figure 5 shows the

Data

Figure 5. Data Polling Algorithm

(August, 2014, Version 1.2)

18

AMIC Technology, Corp.

A29L160B Series

RY/

: Read/

Busy

BY

I/O2: Toggle Bit II

The RY/

is a dedicated, open-drain output pin that

BY

The "Toggle Bit II" on I/O2, when used with I/O6, indicates

whether a particular sector is actively erasing (that is, the

Embedded Erase algorithm is in progress), or whether that

sector is erase-suspended. Toggle Bit II is valid after the

indicates whether an Embedded algorithm is in progress or

complete. The RY/ status is valid after the rising edge of

BY

pulse in the command sequence. Since RY/

the final

WE

BY

pins can be tied

rising edge of the final

pulse in the command sequence.

is an open-drain output, several RY/

BY

together in parallel with a pull-up resistor to VCC.

WE

I/O²toggles when the system reads at addresses within those

sectors that have been selected for erasure. (The system may

If the output is low (Busy), the device is actively erasing or

programming. (This includes programming in the Erase

Suspend mode.) If the output is high (Ready), the device is

ready to read array data (including during the Erase Suspend

mode), or is in the standby mode.

use either

or

to control the read cycles.) But I/O2

CE

OE

cannot distinguish whether the sector is actively erasing or is

erase-suspended. I/O⁶, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but cannot

distinguish which sectors are selected for erasure. Thus, both

status bits are required for sector and mode information.

Refer to Table 10 to compare outputs for I/O²and I/O6.

Figure 6 shows the toggle bit algorithm in flowchart form, and

the section " I/O²: Toggle Bit II" explains the algorithm. See

also the " I/O⁶: Toggle Bit I" subsection. Refer to the Toggle

Bit Timings figure for the toggle bit timing diagram. The I/O²

vs. I/O⁶figure shows the differences between I/O2 and I/O6 in

graphical form.

Table 10 shows the outputs for RY/

. Refer to “

RESET

BY

Timings”, “Timing Waveforms for Program Operation” and

“Timing Waveforms for Chip/Sector Erase Operation” for

more information.

I/O6: Toggle Bit I

Toggle Bit I on I/O6 indicates whether an Embedded Program

or Erase algorithm is in progress or complete, or whether the

device has entered the Erase Suspend mode. Toggle Bit I

may be read at any address, and is valid after the rising edge

Reading Toggle Bits I/O6, I/O2

of the final

pulse in the command sequence (prior to the

WE

Refer to Figure 6 for the following discussion. Whenever the

system initially begins reading toggle bit status, it must read

I/O7 - I/O0 at least twice in a row to determine whether a

toggle bit is toggling. Typically, a system would note and store

the value of the toggle bit after the first read. After the second

read, the system would compare the new value of the toggle

bit with the first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system can

read array data on I/O⁷- I/O0 on the following read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the system also

should note whether the value of I/O⁵is high (see the section

on I/O⁵). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may

have stopped toggling just as I/O⁵went high. If the toggle bit

is no longer toggling, the device has successfully completed

the program or erase operation. If it is still toggling, the device

did not complete the operation successfully, and the system

must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines

that the toggle bit is toggling and I/O⁵has not gone high. The

system may continue to monitor the toggle bit and I/O⁵

through successive read cycles, determining the status as

described in the previous paragraph. Alternatively, it may

choose to perform other system tasks. In this case, the

system must start at the beginning of the algorithm when it

returns to determine the status of the operation (top of Figure

6).

program or erase operation), and during the sector erase

time-out.

During an Embedded Program or Erase algorithm operation,

successive read cycles to any address cause I/O⁶to toggle.

(The system may use either

or

to control the read

CE

OE

cycles.) When the operation is complete, I/O6 stops toggling.

After an erase command sequence is written, if all sectors

selected for erasing are protected, I/O6 toggles for

approximately 100μs, then returns to reading array data. If not

all selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores the

selected sectors that are protected.

The system can use I/O⁶and I/O2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), I/O⁶toggles. When the device

enters the Erase Suspend mode, I/O⁶stops toggling.

However, the system must also use I/O²to determine which

sectors are erasing or erase-suspended. Alternatively, the

system can use I/O⁷(see the subsection on " I/O7 :

Data

Polling").

If a program address falls within a protected sector, I/O⁶

toggles for approximately 2μs after the program command

sequence is written, then returns to reading array data.

I/O⁶also toggles during the erase-suspend-program mode,

and stops toggling once the Embedded Program algorithm is

complete.

The Write Operation Status table shows the outputs for

Toggle Bit I on I/O⁶. Refer to Figure 6 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the "AC

Characteristics" section for the timing diagram. The I/O2 vs.

I/O⁶figure shows the differences between I/O2 and I/O6 in

graphical form. See also the subsection on " I/O²: Toggle Bit

II".

I/O5: Exceeded Timing Limits

I/O5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions I/O5 produces a "1." This is a failure condition that

indicates the program or erase cycle was not successfully

completed.

(August, 2014, Version 1.2)

19

AMIC Technology, Corp.

A29L160B Series

The I/O⁵failure condition may appear if the system tries to

program a "1 "to a location that is previously programmed to

"0." Only an erase operation can change a "0" back to a "1."

Under this condition, the device halts the operation, and

when the operation has exceeded the timing limits, I/O⁵

produces a "1."

START

Read I/O

7

-I/O

0

Under both these conditions, the system must issue the reset

command to return the device to reading array data.

I/O3: Sector Erase Timer

After writing a sector erase command sequence, the system

may read I/O³to determine whether or not an erase

operation has begun. (The sector erase timer does not apply

to the chip erase command.) If additional sectors are

selected for erasure, the entire time-out also applies after

each additional sector erase command. When the time-out is

complete, I/O³switches from "0" to "1." The system may

ignore I/O³if the system can guarantee that the time

between additional sector erase commands will always be

less than 50μs. See also the "Sector Erase Command

Sequence" section.

Read I/O7-I/O

0

(Note 1)

No

Toggle Bit

= Toggle ?

Yes

After the sector erase command sequence is written, the

No

I/O5 = 1?

system should read the status on I/O⁷(

Polling) or I/O6

Data

(Toggle Bit 1) to ensure the device has accepted the

command sequence, and then read I/O³. If I/O3 is "1", the

internally controlled erase cycle has begun; all further

commands (other than Erase Suspend) are ignored until the

erase operation is complete. If I/O³is "0", the device will

accept additional sector erase commands. To ensure the

command has been accepted, the system software should

check the status of I/O³prior to and following each

subsequent sector erase command. If I/O³is high on the

second status check, the last command might not have been

accepted. Table 10 shows the outputs for I/O3.

Yes

- I/O

Read I/O

7

0

(Notes 1,2)

Twice

No

Toggle Bit

= Toggle ?

Yes

Program/Erase

Operation Not

Commplete, Write

Reset Command

Program/Erase

Operation Complete

Notes :

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as I/O

5

changes to "1". See text.

Figure 6. Toggle Bit Algorithm

(August, 2014, Version 1.2)

20

AMIC Technology, Corp.

A29L160B Series

Table 10. Write Operation Status

I/O7

I/O6

I/O5

(Note 2)

0

I/O3

I/O2

RY/

BY

Operation

(Note 1)

Standard

Mode

Embedded Program Algorithm

Embedded Erase Algorithm

Toggle

N/A

1

No toggle

0

I/O7

0

Toggle

0

1

Erase

Reading within Erase

Suspended Sector

1

No toggle

N/A

Suspend

Mode

Reading within Non-Erase

Suspend Sector

Data

I/O7

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

Toggle

Notes:

1. I/O⁷and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. I/O⁵switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “I/O5: Exceeded Timing Limits” for more information.

Maximum Negative Input Overshoot

20ns

+0.8V

-0.5V

-2.0V

20ns

Maximum Positive Input Overshoot

20ns

VCC+2.0V

VCC+0.5V

2.0V

20ns

(August, 2014, Version 1.2)

21

AMIC Technology, Corp.

A29L160B Series

DC Characteristics

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Description

Min.

Typ.

Max.

Unit

ILI

Input Leakage Current

A9 Input Load Current

Output Leakage Current

VIN = VSS to VCC. VCC = VCC Max

VCC = VCC Max, A9 =11.5V

±2.0

35

μA

ILIT

ILO

VOUT = VSS to VCC. VCC = VCC Max

±2.0

5 MHz

15

20

= VIL,

= VIH

CE

OE

Byte Mode

VCC Active Read Current

(Notes 1, 2)

1 MHz

5 MHz

1 MHz

5

15

5

8

20

8

ICC1

mA

= VIL,

CE

OE

Word Mode

VCC Active Write (Program/Erase)

Current (Notes 2, 3, 4)

ICC2

30

50

mA

= VIL,

= VIH,

=VIH

OE

CE

ICC3

ICC4

VCC Standby Current (Note 2)

3

10

μA

= VCC ± 0.3V

CE

RESET

= VSS ± 0.3V

VCC Standby Current During Reset

(Note 2)

RESET

Automatic Sleep Mode

(Notes 2, 4, 5)

ICC5

3

10

V^IH= VCC ± 0.3V; VIL = VSS ± 0.3V

μA

VIL

VIH

Input Low Level

-0.5

0.8

V

Input High Level

0.7 x VCC

VCC + 0.3

Voltage for Autoselect and

Temporary Unprotect Sector

Output Low Voltage

VID

VCC = 3.3V

9.5

11.5

0.45

V

VOL

VOH1

VOH2

IOL = 4.0mA, VCC = VCC Min

IOH = -2.0mA, VCC = VCC Min

IOH = -100μA, VCC = VCC Min

V

0.85 x VCC

VCC - 0.4

Output High Voltage

Notes:

1. The I^CCcurrent listed is typically less than 2mA/MHz, with

at VIH. Typical VCC is 3.3V.

OE

2. Maximum I^CCspecifications are tested with VCC = VCC max.

3. I^CCactive while Embedded Algorithm (program or erase) is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t^ACC+ 30ns. Typical sleep mode current

is 200nA.

5. Not 100% tested.

(August, 2014, Version 1.2)

22

AMIC Technology, Corp.

A29L160B Series

DC Characteristics (continued)

Zero Power Flash

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1MHz

ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

10

8

3.6V

2.7V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note : T = 25°C

Typical ICC1 vs. Frequency

(August, 2014, Version 1.2)

23

AMIC Technology, Corp.

A29L160B Series

AC Characteristics

Read Only Operations

Parameter

Symbols

Description

Test Setup

Speed

Unit

JEDEC

Std

-70

tAVAV

tRC

Read Cycle Time (Note 1)

Min.

70

ns

= VIL

CE

OE

tAVQV

tACC

Address to Output Delay

Max.

70

tELQV

tGLQV

tCE

tOE

Chip Enable to Output Delay

Output Enable to Output Delay

Max.

Min.

70

30

0

ns

= VIL

OE

Read

tOEH

Output Enable Hold Time (Note 1)

Toggle and

Min.

10

ns

Polling

Data

tEHQZ

tGHQZ

tDF

Chip Disable to Output High Z (Note 1)

Output Disable to Output High Z (Note 1)

Max.

25

ns

Output Hold Time from Addresses,

Whichever Occurs First (Note 1)

or

CE OE

,

tAXQX

tOH

Min.

0

ns

Notes:

1. Not 100% tested.

2. See Test Conditions and Test Setup for test specifications.

Timing Waveforms for Read Only Operation

t

RC

Addresses

CE

Addresses Stable

t

ACC

t

DF

t

OE

t

OEH

WE

t

CE

t

OH

High-Z

Output

Output Valid

RESET

RY/BY

0V

(August, 2014, Version 1.2)

24

AMIC Technology, Corp.

A29L160B Series

AC Characteristics

Hardware Reset (

Parameter

)

RESET

Description

Test Setup

All Speed Options

Unit

JEDEC

Std

Pin Low (During Embedded

Algorithms) to Read or Write (See Note)

RESET

t^READY

Max

20

μs

Pin Low (Not During Embedded

RESET

Algorithms) to Read or Write (See Note)

t^READY

Max

500

ns

tRP

tRH

Min

500

50

0

ns

μs

Pulse Width

RESET

High Time Before Read (See Note)

Recovery Time

tRB

RY/

BY

tRPD

20

Low to Standby Mode

RESET

Note: Not 100% tested.

Timings

RESET

RY/BY

CE, OE

RESET

t

RH

t

RP

t

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t

Ready

RY/BY

t

RB

CE, OE

RESET

t

RP

(August, 2014, Version 1.2)

25

AMIC Technology, Corp.

A29L160B Series

Temporary Sector Unprotect

Parameter

Description

All Speed Options

Unit

JEDEC

Std

t^VIDR

VID Rise and Fall Time (See Note)

Min

500

4

ns

Setup Time for Temporary Sector

RESET

t^RSP

μs

Unprotect

Note: Not 100% tested.

Temporary Sector Unprotect Timing Diagram

12V

0 or 3V

RESET

0 or 3V

tVIDR

Program or Erase Command Sequence

CE

WE

tRSP

RY/BY

AC Characteristics

Word/Byte Configuration (

Parameter

)

BYTE

Description

All Speed Options

Unit

JEDEC

Std

t^ELFL/tELFH

Max

5

ns

to

CE BYTE

Switching Low or High

Switching Low to Output High-Z

Switching High to Output Active

BYTE

t^FLQZ

t^HQV

Max

Min

25

70

ns

(August, 2014, Version 1.2)

26

AMIC Technology, Corp.

A29L160B Series

Timings for Read Operations

BYTE

CE

OE

BYTE

t

ELFL

Data Output

(I/O -I/O14

Data Output

(I/O0-I/O7)

BYTE

I/O -I/O14

0

)

Switching

from word to

byte mode

I/O15

Output

Address Input

I/O15 (A-1)

t

FLQZ

t

ELFH

BYTE

Data Output

(I/O -I/O

Data Output

(I/O0-I/O14)

I/O -I/O14

0

7

)

BYTE

Switching

from byte to

word mode

I/O15

Output

Address Input

I/O15 (A-1)

t

FHQV

Timings for Write Operations

BYTE

CE

The falling edge of the last WE signal

WE

BYTE

t

SET

(tAS

)

t

HOLD(tAH)

Note:

Refer to the Erase/Program Operations table for t^ASand tAH specifications.

(August, 2014, Version 1.2)

27

AMIC Technology, Corp.

A29L160B Series

AC Characteristics

Erase and Program Operations

Parameter

Description

Speed

Unit

JEDEC

Std

-70

70

0

tAVAV

tAVWL

tWLAX

tDVWH

tWHDX

tWC

tAS

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min.

ns

tAH

tDS

45

35

0

tDH

tOES

Data Hold Time

Output Enable Setup Time

0

Read Recover Time Before Write

high to low)

tGHWL

Min.

0

ns

(

WE

OE

tELWL

tWHEH

tWLWH

tWHWL

tCS

tCH

Min.

Typ.

0

ns

Setup Time

Hold Time

CE

tWP

tWPH

Write Pulse Width

45

30

6

Write Pulse Width High

Byte

tWHWH1

tWHWH2

tWHWH1

Byte Programming Operation (Note 2)

μs

Word

Typ.

12

tWHWH2

Sector Erase Operation (Note 2)

VCC Set Up Time (Note 1)

0.3

sec

tvcs

tRB

Min.

Min

50

0

μs

ns

Recovery Time from RY/

(Note 1)

BY

tBUSY

90

Program/Erase Valid to RY/

Delay (Note 1)

BY

Notes:

1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

(August, 2014, Version 1.2)

28

AMIC Technology, Corp.

A29L160B Series

Timing Waveforms for Program Operation

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

tWC

tAS

Addresses

CE

PA

555h

PA

t

AH

tCH

OE

t

WP

t

WHWH1

WE

t

CS

t

WPH

t

DS

t

DH

Data

A0h

PD

DOUT

Status

t

RB

t

BUSY

RY/BY

VCC

t

VCS

Note :

1. PA = program addrss, PD = program data, Dout is the true data at the program address.

2. Illustration shows device in word mode.

(August, 2014, Version 1.2)

29

AMIC Technology, Corp.

A29L160B Series

Timing Waveforms for Chip/Sector Erase Operation

Erase Command Sequence (last two cycles)

Read Status Data

VA

tAS

tWC

SA

555h for chip erase

Addresses

CE

2AAh

tAH

OE

tCH

t

WP

WE

t

WPH

tWHWH2

tCS

tDS

tDH

In

Data

55h

30h

10h for chip erase

Complete

Progress

tRB

tBUSY

RY/BY

tVCS

VCC

Note :

1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").

2. Illustratin shows device in word mode.

(August, 2014, Version 1.2)

30

AMIC Technology, Corp.

A29L160B Series

Timing Waveforms for

Polling (During Embedded Algorithms)

Data

t

RC

Addresses

CE

VA

t

ACC

CE

t

CH

t

OE

t

DF

t

OEH

WE

t

OH

High-Z

Valid Data

I/O

7

Complement

Status Data

True

High-Z

I/O0

- I/O

6

High-Z

Status Data

t

BUSY

RY/BY

Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

(August, 2014, Version 1.2)

31

AMIC Technology, Corp.

A29L160B Series

Timing Waveforms for Toggle Bit (During Embedded Algorithms)

tRC

Addresses

CE

VA

t

ACC

CE

t

tCH

t

OE

t

DF

t

OEH

WE

t

OH

I/O6

,

I/O2

High-Z

Valid Status

(first read)

Valid Status

Valid Data

t

BUSY

(second read)

(stop togging)

RY/BY

Note: VA = Valid Address; not required for I/O⁶. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

(August, 2014, Version 1.2)

32

AMIC Technology, Corp.

A29L160B Series

Timing Waveforms for Sector Protect/Unprotect

V

ID

IH

V

RESET

SA, A6,

A1, A0

Valid*

Status

Sector Protect/Unprotect

Verify

40h

60h

Data

CE

Sector Protect:150us

Sector Unprotect:15ms

1us

WE

OE

Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0

Timing Waveforms for I/O2 vs. I/O6

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

WE

I/O

Erase

Suspend

Program

Erase

Erase Suspend

Read

Erase

Complete

Read

6

I/O2

and I/O

6

toggle with OE and CE

Note : Both I/O

6

and I/O

2

toggle with OE or CE. See the text on I/O

6

and I/O

2

in the section "Write Operation Status" for

more information.

(August, 2014, Version 1.2)

33

AMIC Technology, Corp.

A29L160B Series

Timing Waveforms for Alternate

Controlled Write Operation

CE

PA for program

SA for sector erase

555 for chip erase

555 for program

2AA for erase

Data Polling

PA

Addresses

t

WC

tAS

tAH

tWH

WE

OE

t

WHWH1 or 2

t

CP

t

BUSY

t

CPH

CE

t

WS

tDS

t

DH

Data

I/O7

DOUT

t

RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET

RY/BY

Note :

1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O

7

= Complement of Data Input, DOUT = Array Data.

2. Figure indicates the last two bus cycles of the command sequence.

Erase and Programming Performance

Parameter

Sector Erase Time

Typ. (Note 1)

Max. (Note 2)

Unit

sec

μs

Comments

0.3

8

1.5

32

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

Byte Programming Time

Word Programming Time

6

100

180

16

11

8

Excludes system-level

overhead (Note 5)

μs

Chip Programming Time

(Note 3)

Byte Mode

Word Mode

sec

3

12

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 10,000 cycles. Additionally, programming

typically assumes checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 2.7V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then

does the device set I/O⁵= 1. See the section on I/O5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 9

for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.

(August, 2014, Version 1.2)

34

AMIC Technology, Corp.

A29L160B Series

Latch-up Characteristics

Description

Min.

Max.

VCC + 1.0V

+100mA

11.5V

Input Voltage with respect to VSS on all I/O pins

VCC Current

-1.0V

-100mA

-1.0V

Input voltage with respect to VSS on all pins except I/O pins

(including A9,

and

)

RESET

OE

Includes all pins except VCC. Test conditions: VCC = 3.3V, one pin at time.

TSOP Pin Capacitance

Parameter Symbol

Parameter Description

Input Capacitance

Test Setup

Typ.

Max.

Unit

CIN

COUT

CIN2

V^IN=0

V^OUT=0

V^IN=0

6

pF

7.5

12

9

Output Capacitance

8.5

7.5

Control Pin Capacitance

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0MHz

(August, 2014, Version 1.2)

35

AMIC Technology, Corp.

A29L160B Series

Test Conditions

Test Specifications

Test Condition

-70

Unit

Output Load

1 TTL gate

Output Load Capacitance, CL(including jig capacitance)

Input Rise and Fall Times

30

5

pF

ns

V

Input Pulse Levels

0.0 - 3.0

1.5

Input timing measurement reference levels

Output timing measurement reference levels

V

1.5

V

Test Setup

3.3 V

2.7 KΩ

Device

Under

Test

Diodes = IN3064 or Equivalent

CL

6.2 KΩ

(August, 2014, Version 1.2)

36

AMIC Technology, Corp.

A29L160B Series

Part Numbering Scheme

XXX X X XX X X / X

X

A29L

Packing

Q = Tape & Reel

Package Material

F = PB free

Temperature*

U = - 40°C ~ + 85°C

Blank = 0°C ~ + 70°C

Speed Grade

Package Type

V = 48-pin TSOP

G = 48-ball BGA

T = Top Boot

U = Bottom Boot

Device Version*

B = B Chip Version

Device Density

001 = 1Mbits

004 = 4Mbits

040 = 4Mbits

400 = 4Mbits

008 = 8Mbits

800 = 8Mbits

160 = 16Mbits

Device Type

A29L = AMIC 3.3V Single Bank

Parallel NOR Flash

* Optional

(August, 2014, Version 1.2)

37

AMIC Technology, Corp.

A29L160B Series

Ordering Information

Top Boot Sector Flash

Standby

Current

Typ. (μA)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Access Time

(ns)

Package

Part No.

Typ. (mA)

A29L160BTV-70F

A29L160BTV-70UF

A29L160BTG-70F

A29L160BTG-70UF

48 Pin Pb-Free TSOP

48-ball Pb-Free TFBGA

70

9

20

0.2

Note: -U is for industrial operating temperature range: -40°C to +85°C

Bottom Boot Sector Flash

Standby

Current

Typ. (μA)

Active Read

Current

Typ. (mA)

Program/Erase

Access Time

(ns)

Part No.

Current

Typ. (mA)

Package

A29L160BUV-70F

A29L160BUV-70UF

A29L160BUG-70F

A29L160BUG-70UF

48 Pin Pb-Free TSOP

48-ball Pb-Free TFBGA

70

9

20

0.2

Note: -U is for industrial operating temperature range: -40°C to +85°C

(August, 2014, Version 1.2)

38

AMIC Technology, Corp.

A29L160B Series

Package Information

TSOP 48L (Type I) Outline Dimensions

unit: inches/mm

D

D1

1

48

D

24

25

θ

L

Detail "A"

Dimensions in inches

Dimensions in mm

Symbol

Min

-

Nom

Max

Min

Nom

Max

A

A1

A2

b

-

0.047

0.006

0.042

0.011

0.008

0.795

0.728

0.476

-

1.20

0.15

0.002

0.037

0.007

0.004

0.779

0.720

-

0.05

0.94

0.18

0.12

19.80

18.30

-

1.00

0.039

0.009

-

1.06

0.22

0.27

c

-

0.20

D

D1

E

e

0.787

0.724

0.472

0.020 BASIC

20.00

18.40

12.00

0.50 BASIC

0.60

20.20

18.50

12.10

L

0.020

0.024 0.0275

0.011 Typ.

0.50

0.70

S

y

0.28 Typ.

-

0.004

8°

-

0.10

8°

0°

-

θ

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

(August, 2014, Version 1.2)

39

AMIC Technology, Corp.

A29L160B Series

Package Information

48 Balls CSP (6 x 8 mm) Outline Dimensions

(48TFBGA)

unit: mm

TOP VIEW

BOTTOM VIEW

b

1

2 3 4 5 6

6

5 4 3 2 1

H

G

F

H

G

F

E

D

C

B

A

E

D

C

B

A

e

D1

Ball*A1 CORNER

SIDE VIEW

D

C

SEATING PLANE

0.10 C

Dimensions in mm

Symbol

Min.

Nom.

Max.

A

A1

b

-

0.25

1.20

0.30

0.40

6.10

0.20

0.30

5.90

-

D

6.00

D1

e

4.00 BSC

0.80

-

E

7.90

8.00

8.10

E1

5.60 BSC

(August, 2014, Version 1.2)

40

AMIC Technology, Corp.


型号：	A29L160BTG-70F/Q
厂家：	AMIC TECHNOLOGY
描述：	Flash, 1MX16, 70ns, PBGA48, TFBGA-48 内存集成电路
文件：	总41页 (文件大小：465K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A29L160BTG-70F/Q [AMICC]

相关型号：

A29L160BTG-70UF

A29L160BTV-70F

A29L160BTV-70F/Q

A29L160BTV-70UF

A29L160BUG-70F/Q

A29L160BUG-70UF

A29L160BUG-70UF/Q

A29L160BUV-70F

A29L160BUV-70F/Q

A29L160BUV-70UF

A29L160BUV-70UF/Q

A29L160C