A29L161ATG-60I [AMICC]
Flash, 1MX16, 60ns, PBGA48, TFBGA-48;
| 型号： | A29L161ATG-60I |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | Flash, 1MX16, 60ns, PBGA48, TFBGA-48 |
| 文件： | 总32页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A29L161A Series
2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only,
Boot Sector Flash Memory
Document Title
2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No. History
Issue Date
Remark
0.0
Initial issue
March 17, 2006
Preliminary
PRELIMINARY (March, 2006, Version 0.0)
AMIC Technology, Corp.
A29L161A Series
2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only,
Boot Sector Flash Memory
Features
ꢀSingle power supply operation
- Embedded Program algorithm automatically writes and
- Regulated voltage range: 3.0 to 3.6 volt read and write
verifies data at specified addresses
operations for compatibility with high performance 3.3 ꢀTypical 100,000 program/erase cycles per sector
volt microprocessors
ꢀAccess times:
- 60/70 (max.)
ꢀCurrent:
ꢀ20-year data retention at 125°C
- Reliable operation for the life of the system
ꢀCFI (Common Flash Interface) compliant
- Provides device-specific information to the system,
allowing host software to easily reconfigure for different
Flash devices
- 9 mA typical active read current
- 20 mA typical program/erase current
- 200 nA typical CMOS standby
ꢀCompatible with JEDEC-standards
- Pinout and software compatible with single-power-supply
Flash memory standard
- 200 nA Automatic Sleep Mode current
ꢀFlexible sector architecture
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors
- Any combination of sectors can be erased
- Supports full chip erase
ꢀ
Polling and toggle bits
- Provides a software method of detecting completion of
program or erase operations
Data
ꢀUnlock Bypass Program Command
- Reduces overall programming time when issuing
multiple program command sequence
ꢀTop or bottom boot block configurations available
ꢀEmbedded Algorithms
ꢀErase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes the
erase operation
ꢀPackage options
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
- 48-ball TFBGA
- All Pb-free (Lead-free) products are RoHS compliant
PRELIMINARY (March, 2006, Version 0.0)
1
AMIC Technology, Corp.
A29L161A Series
General Description
The A29L161A is a 16Mbit, 3.3 volt-only Flash memory
organized as 2,097,152 bytes of 8 bits or 1,048,576 words of
16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16
bits of data appear on I/O0~I/O15. The A29L161A is offered in
48-ball FBGA packages. This device is designed to be
programmed in-system with the standard system 3.3 volt
VCC supply. Additional 12.0 volt VPP is not required for in-
system write or erase operations. However, the A29L161A
can also be programmed in standard EPROM programmers.
The A29L161A has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O6 toggle bit, the
A29L161A has a second toggle bit, I/O2, to indicate whether
the addressed sector is being selected for erase. The
A29L161A also offers the ability to program in the Erase
Suspend mode. The standard A29L161A offers access times
of 60 and 70ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention the
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm
-
an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two
write cycles to program data instead of four.
The host system can detect whether a program or erase
operation is complete by reading the I/O7 (
Polling) and
Data
I/O6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29L161A is fully erased
when shipped from the factory.
The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.
device has separate chip enable (
), write enable (
)
WE
CE
and output enable (
) controls.
OE
The device requires only a single 3.3 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29L161A is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Pin Configurations
ꢀTFBGA
TFBGA
Top View, Balls Facing Down
G6
A6
B6
C6
D6
E6
F6
H6
A13
A12
A14
A15
A16
NC
I/O15(A-1)
VSS
G5
A5
B5
C5
D5
E5
F5
H5
A9
A8
A10
A11
I/O
7
I/O14
I/O13
I/O
6
A4
B4
C4
D4
E4
F4
G4
H4
NC
NC
I/O
5
I/O12
VCC
I/O
4
WE
A19
G3
A3
B3
C3
D3
E3
F3
H3
NC
NC
A18
NC
I/O
2
I/O10
I/O11
I/O
3
C2
A6
D2
A5
E2
F2
G2
H2
A2
B2
A7
A17
I/O
0
I/O
8
I/O
9
I/O
1
G1
A1
B1
C1
A2
D1
A1
E1
F1
H1
A3
A4
A0
OE
OE
VSS
PRELIMINARY (March, 2006, Version 0.0)
2
AMIC Technology, Corp.
A29L161A Series
Block Diagram
I/O0 - I/O15 (A-1)
VCC
VSS
Sector Switches
Input/Output
Buffers
Erase Voltage
Generator
State
Control
WE
PGM Voltage
Generator
Command
Register
Chip Enable
Output Enable
Logic
STB
Data Latch
CE
OE
Y-Gating
Y-Decoder
STB
VCC Detector
Timer
A0-A19
X-decoder
Cell Matrix
Pin Descriptions
Pin No.
A0 - A19
I/O0 - I/O15
Description
Address Inputs
Data Inputs/Outputs
Chip Enable
CE
Write Enable
WE
Output Enable
OE
VSS
VCC
NC
Ground
Power Supply
Pin not connected internally
PRELIMINARY (March, 2006, Version 0.0)
3
AMIC Technology, Corp.
A29L161A Series
Absolute Maximum Ratings*
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended periods
may affect device reliability.
Storage Temperature Plastic Packages. . . -65°C to + 150°C
Ambient Temperature with Power Applied. -55°C to + 125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . . ……. . -0.5V to +4.0V
A9 &
(Note 2) . . . . . . . . . . . . . . . . . . . . . . -0.5 to +12.5V
OE
All other pins (Note 1) . . . . . . . . . . …. . -0.5V to VCC + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . …. . 200mA
Notes:
Operating Ranges
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on input and I/O pins is VCC +0.5V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0V
for periods up to 20ns.
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . ….. . . 0°C to +70°C
Extended Range Devices
Ambient Temperature (TA)
For –I series. . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C
For –U series . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
2. Minimum DC input voltage on A9 and
is
-0.5V.
OE
During voltage transitions, A9 and
may overshoot
OE
VSS to -2.0V for periods of up to 20ns. Maximum DC
input voltage on A9 is +12.5V which may overshoot to
14.0V for periods up to 20ns.
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . . . …...+3.0V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
Device Bus Operations
execute the command. The contents of the register serve as
inputs to the internal state machine. The state machine
outputs dictate the function of the device. The appropriate
device bus operations table lists the inputs and control levels
required, and the resulting output. The following subsections
describe each of these operations in further detail.
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to
Table 1. A29L161A Device Bus Operations
Operation
A0 – A19
I/O0 - I/O15
OE
WE
CE
Read
Write
CMOS Standby
Output Disable
Legend:
L
L
L
H
X
H
H
L
X
H
AIN
AIN
X
DOUT
DIN
High-Z
High-Z
VCC ± 0.3 V
L
X
L = Logic Low = VIL, H = Logic High = VIH, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
PRELIMINARY (March, 2006, Version 0.0)
4
AMIC Technology, Corp.
A29L161A Series
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the
and
pins to VIL.
is the power control and
CE
OE
CE
selects the device.
is the output control and gates array
OE
data to the output pins.
Program and Erase Operation Status
should remain at VIH all the time
WE
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O7 - I/O0. Standard read cycle timings and ICC read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section for
timing diagrams.
during read operation. The internal state machine is set for
reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious alteration of
the memory content occurs during the power transition. No
command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data
on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
lCC1 in the DC Characteristics table represents the active
current specification for reading array data.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the
input.
OE
The device enters the CMOS standby mode when the
CE
pin is both held at VCC ± 0.3V. (Note that this is a more
restricted voltage range than VIH.) If are held at VIH, but
not within VCC ± 0.3V, the device will be in the standby
mode, but the standby current will be greater. The device
requires the standard access time (tCE) before it is ready to
read data.
Writing Commands/Command Sequences
CE
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive
and
to VIL, and
CE
WE
to VIH. The device features an Unlock Bypass mode to
OE
facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The “
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics tables represent the standby
current specification.
Program Command Sequence” section has details on
programming data to the device using both standard and
Unlock Bypass command sequence. An erase operation can
erase one sector, multiple sectors, or the entire device. The
Sector Address Tables indicate the address range that each
sector occupies. A "sector address" consists of the address
inputs required to uniquely select a sector. See the
"Command Definitions" section for details on erasing a sector
or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7 - I/O0. Standard
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The automatic
sleep mode is independent of the
,
and
control
OE
WE
CE
signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and always available to the system.
Output Disable Mode
When the
input is at VIH, output from the device is
OE
disabled. The output pins are placed in the high impedance
state.
PRELIMINARY (March, 2006, Version 0.0)
5
AMIC Technology, Corp.
A29L161A Series
Table 2. A29L161A Top Boot Block Sector Address Table
Sector Size
(Kwords)
Address Range
(in hexadecimal)
Sector A19
A18
A17
A16
A15
A14
A13
A12
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
4
00000 - 07FFF
08000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 7FFFF
80000 - 87FFF
88000 - 8FFFF
90000 - 97FFF
98000 - 9FFFF
A0000 - A7FFF
A8000 - AFFFF
B0000 - B7FFF
B8000 - BFFFF
C0000 - C7FFF
C8000 - CFFFF
D0000 - D7FFF
D8000 - DFFFF
E0000 - E7FFF
E8000 - EFFFF
F0000 - F7FFF
F8000 - FBFFF
FC000 - FCFFF
FD000 - FDFFF
FE000 - FFFFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
1
1
0
1
4
1
1
X
8
PRELIMINARY (March, 2006, Version 0.0)
6
AMIC Technology, Corp.
A29L161A Series
Table 3. A29L161A Bottom Boot Block Sector Address Table
Sector Size
(Kwords)
Address Range
(in hexadecimal)
Sector A19
A18
A17
A16
A15
A14
A13
A12
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
0
8
00000 - 01FFF
02000 - 02FFF
03000 - 03FFF
04000 - 07FFF
08000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 7FFFF
80000 - 87FFF
88000 - 8FFFF
90000 - 97FFF
98000 - 9FFFF
A0000 - A7FFF
A8000 - AFFFF
B0000 – B7FFF
B8000 - BFFFF
C0000 - C7FFF
C8000 - CFFFF
D0000 - D7FFF
D8000 - DFFFF
E0000 - E7FFF
E8000 - EFFFF
F0000 - F7FFF
F8000 - FFFFF
4
SA2
0
1
1
4
SA3
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
PRELIMINARY (March, 2006, Version 0.0)
7
AMIC Technology, Corp.
A29L161A Series
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically match
In addition, when verifying sector protection, the sector
address must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Address
Tables. The Command Definitions table shows the remaining
address bits that are don't care. When all necessary bits
have been set as required, the programming equipment may
then read the corresponding identifier code on I/O7 - I/O0.To
access the autoselect codes in-system, the host system can
issue the autoselect command via the command register, as
shown in the Command Definitions table. This method does
not require VID. See "Command Definitions" for details on
using the autoselect mode.
a
device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5 V) on address pin A9. Address
pins A6, A1, and A0 must be as shown in Autoselect Codes
(High Voltage Method) table.
Table 4. A29L161A Autoselect Codes (High Voltage Method)
Description
A19 A11 A9 A8 A6 A5 A1 A0
I/O8
to
I/O7
to
WE
CE
OE
to
to
to
to
A12 A10
A7
A2
I/O15
I/O0
Manufacturer ID: AMIC
L
L
L
L
H
H
X
X
X
X
VID
X
L
L
X
L
L
L
X
37h
Device ID:
A29L161A
VID
X
X
H
22h
C4h
(Top Boot Block)
Device ID:
A29L161A
(Bottom Boot Block)
22h
X
49h
7Fh
L
L
L
L
H
H
X
X
X
X
VID
X
X
L
L
X
X
L
H
H
Continuation ID
VID
H
01h
(protected)
00h
X
X
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L
(unprotected)
L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care.
Note: The autoselect codes may also be accessed in-system via command sequences
Hardware Data Protection
Power-Up Write Inhibit
The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up transitions, or from system noise. The device
is powered up to read array data to avoid accidentally writing
data to the array.
If
=
= VIL and
= VIH during power up, the
OE
WE
device does not accept commands on the rising edge of
. The internal state machine is automatically reset to
CE
WE
reading array data on the initial power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines
device and host system software interrogation handshake,
which allows specific vendor-specified software algorithms to
be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and
forward- and backward-compatible for the specified flash
device families. Flash vendors can standardize their existing
interface for long-term compatibility.
This device enters the CFI Query mode when the system
writes the CFI Query command, 98h, to address 55h any
time the device is ready to read array data. The system can
read CFI information at the addresses given in Table 5-8.
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on
do not initiate a write cycle.
,
or
WE
OE CE
Logical Inhibit
Write cycles are inhibited by holding any one of
=VIL,
OE
CE
= VIH or
= VIH. To initiate a write cycle,
and
WE
CE
must be a logical zero while
is a logical one.
WE
OE
PRELIMINARY (March, 2006, Version 0.0)
8
AMIC Technology, Corp.
A29L161A Series
In word mode, the upper address bits (A7-MSB) must be all
zeros. To terminate reading CFI data, the system must write
the reset command.
The system can also write the CFI query command when the
device is in the autoselect mode. The device enters the CFI
query mode, and the system can read CFI data at the
addresses given in Table 5-8. The system must write the
reset command to return the device to the autoselect mode.
Table 5. CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
Table 6 System Interface String
Description
Addresses
Data
1Bh
0027h
VCC Min. (write/erase)
I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt
1Ch
0036h
VCC Max. (write/erase)
I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
Vpp Min. voltage (00h = no Vpp pin present)
Vpp Max. voltage (00h = no Vpp pin present)
Typical timeout per single word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
PRELIMINARY (March, 2006, Version 0.0)
9
AMIC Technology, Corp.
A29L161A Series
Table 7 Device Geometry Definition
Description
Addresses
Data
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3BH
3Ch
0015h
0002h
0000h
0000h
0000h
0004h
0000h
0000h
0040h
0000h
0001h
0000h
0020h
0000h
0000h
0000h
0080h
0000h
001Eh
0000h
0000h
0001h
Device Size = 2N byte
Flash Device Interface description
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device
Erase Block Region 1 Information
(refer to the CFI specification)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
Table 8 Primary Vendor-Specific Extended Query
Description
Addresses
Data
40h
41h
42h
43h
44h
0050h
0052h
0049h
0031h
0030h
Query-unique ASCII string “PRI”
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
45h
46h
47h
48h
0000h
0002h
0001h
0001h
0 = Required, 1 = Not Required
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29L160 mode
Simultaneous Operation
49h
0004h
4Ah
48h
4Ch
0000h
0000h
0000h
00 = Not Supported, 01 = Supported
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
PRELIMINARY (March, 2006, Version 0.0)
10
AMIC Technology, Corp.
A29L161A Series
Command Definitions
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
The Command Definitions table shows the address and data
requirements. This method is an alternative to that shown in
the Autoselect Codes (High Voltage Method) table, which is
intended for PROM programmers and requires VID on address
bit A9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX11h retrieves the
continuation code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address (SA)
and the address 02h in returns 01h if that sector is protected,
or 00h if it is unprotected. Refer to the Sector Address tables
for valid sector addresses.
All addresses are latched on the falling edge of
or
,
CE
WE
whichever happens later. All data is latched on the rising
edge of or , whichever happens first. Refer to the
WE
CE
appropriate timing diagrams in the "AC Characteristics"
section.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm. After the device accepts an Erase Suspend
command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended
sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See "Erase Suspend/Erase Resume Commands"
for more information on this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O5 goes high, or while in the
autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically provides internally generated program pulses
and verify the programmed cell margin.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
longer latched. The system can determine the status of the
program operation by using I/O7, I/O6. See “Write Operation
Status” for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a “0” back to a
“1”. Attempting to do so may halt the operation and set I/O5 to
Reset Command
Writing the reset command to the device resets the device to
reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
“1”, or cause the
Polling algorithm to indicate the
Data
operation was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations can
convert a “0” to a “1”.
The reset command may be written between the sequence
cycles in
a
program command sequence before
Unlock Bypass Command Sequence
programming begins. This resets the device to reading array
data (also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect during
Erase Suspend). If I/O5 goes high during a program or erase
operation, writing the reset command returns the device to
reading array data (also applies during Erase Suspend).
The unlock bypass feature allows the system to program
words to the device faster than using the standard program
command sequence. The unlock bypass command
sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass
mode.
A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The
first cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the
program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table 9
shows the requirements for the command sequence.
Autoselect Command Sequence
The autoselect command sequence allows the host system to
access the manufacturer and devices codes, and determine
whether or not a sector is protected.
PRELIMINARY (March, 2006, Version 0.0)
11
AMIC Technology, Corp.
A29L161A Series
The Command Definitions table shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O7, I/O6, or I/O2. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
START
Write Program
Command
Sequence
Figure 4 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
Data Poll
from System
Embedded
Program
Sector Erase Command Sequence
algorithm in
progress
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-
out of 50µs begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50µs, otherwise the last address and command
might not be accepted, and erasure may begin. It is
recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sector
erase commands can be assumed to be less than 50µs, the
system need not monitor I/O3. Any command other than
Sector Erase or Erase Suspend during the time-out period
resets the device to reading array data. The system must
rewrite the command sequence and any additional sector
addresses and commands.
Verify Data ?
Yes
No
No
Increment Address
Last Address ?
Yes
Programming
Completed
Note : See the appropriate Command Definitions table for
program command sequence.
Figure 3. Program Operation
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The first
cycle must contain the data 90h; the second cycle the data
00h. Addresses are don’t care for both cycle. The device
returns to reading array data.
Figure 3 illustrates the algorithm for the program operation.
See the Erase/Program Operations in “AC Characteristics” for
parameters, and to Program Operation Timings for timing
diagrams.
The system can monitor I/O3 to determine if the sector erase
timer has timed out. (See the " I/O3: Sector Erase Timer"
section.) The time-out begins from the rising edge of the final
pulse in the command sequence.
WE
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7, I/O6, or I/O2. Refer to "Write
Operation Status" for information on these status bits.
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations.
4 illustrates the algorithm for the erase operation. Refer to
the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
PRELIMINARY (March, 2006, Version 0.0)
12
AMIC Technology, Corp.
A29L161A Series
Erase Suspend/Erase Resume Commands
START
The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50µs time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm. Writing the Erase Suspend
command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase
operation. Addresses are "don't cares" when writing the
Erase Suspend command.
Write Erase
Command
Sequence
Data Poll
from System
Embedded
Erase
algorithm in
progress
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of
20µs to suspend the erase operation. However, when the
Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out
period and suspends the erase operation.
No
Data = FFh ?
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on I/O7
- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to
determine if a sector is actively erasing or is erase-
suspended. See "Write Operation Status" for information on
these status bits.
After an erase-suspended program operation is complete,
the system can once again read array data within non-
suspended sectors. The system can determine the status of
the program operation using the I/O7 or I/O6 status bits, just
as in the standard program operation. See "Write Operation
Status" for more information.
Yes
Erasure Completed
Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O
3
: Sector Erase Timer" for more information.
Figure 4. Erase Operation
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further writes
of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.
PRELIMINARY (March, 2006, Version 0.0)
13
AMIC Technology, Corp.
A29L161A Series
Table 9. A29L161A Command Definitions
Bus Cycles (Notes 2 - 5)
Third Fourth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command
Sequence
(Note 1)
First
Second
Fifth
Sixth
Read (Note 6)
Reset (Note 7)
Manufacturer ID
Device ID, Top Boot Block
1
1
4
4
RA
XXX
555
555
RD
F0
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
555
90
90
90
90
X00
X01
X01
X03
37
22C4
2249
7F
Device ID, Bottom Boot Block 4 555
Continuation ID
4
555
(SA) XX00
Sector Protect Verify (Note 9)
4
555
AA
2AA
55
555
90
X02
PA
XX01
CFI Query (Note 10)
Program
1
4
3
2
2
6
6
1
1
55
98
AA
AA
A0
90
555
555
XXX
XXX
555
555
XXX
XXX
2AA
2AA
PA
55
55
PD
00
55
55
555
555
A0
20
PD
Unlock Bypass
Unlock Bypass Program (Note 11)
Unlock Bypass Reset (Note 12)
Chip Erase
XXX
2AA
2AA
AA
AA
B0
30
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend (Note 13)
Erase Resume (Note 14)
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the
whichever happens later.
or
pulse,
WE
CE
PD = Data to be programmed at location PA. Data latches on the rising edge of
or
pulse, whichever happens first.
CE
WE
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19 - A12 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A19 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high
(while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
information.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more
information.
10. Command is valid when device is ready to read array data or when device is in autoselect mode.
11. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass
mode.
13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
14. The Erase Resume command is valid only during the Erase Suspend mode.
PRELIMINARY (March, 2006, Version 0.0)
14
AMIC Technology, Corp.
A29L161A Series
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100µs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the device
enters the Erase Suspend mode, I/O6 stops toggling.
However, the system must also use I/O2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
Write Operation Status
Several bits, I/O2, I/O3, I/O5, I/O6, I/O7 are provided in the
A29L161A to determine the status of a write operation. Table
10 and the following subsections describe the functions of
these status bits. I/O7 and I/O6 offer a method for determining
whether a program or erase operation is complete or in
progress. These three bits are discussed first.
I/O7:
Polling
Data
The
Polling bit, I/O7, indicates to the host system
Data
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Polling is
Data
pulse in the
system can use I/O7 (see the subsection on " I/O7 :
Data
valid after the rising edge of the final
program or erase command sequence.
WE
Polling").
If a program address falls within a protected sector, I/O6
toggles for approximately 2µs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O6. Refer to Figure 6 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O2 vs.
I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form. See also the subsection on " I/O2: Toggle Bit
II".
During the Embedded Program algorithm, the device outputs
on I/O7 the complement of the datum programmed to I/O7.
This I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
protected sector,
Polling on I/O7 is active for
Data
approximately 2µs, then the device returns to reading array
data.
During the Embedded Erase algorithm,
produces a "0" on I/O7. When the Embedded Erase algorithm
Polling
Data
is complete, or if the device enters the Erase Suspend mode,
I/O2: Toggle Bit II
Polling produces a "1" on I/O7.This is analogous to the
Data
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in
a sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O7.
rising edge of the final
pulse in the command sequence.
WE
I/O2 toggles when the system reads at addresses within those
sectors that have been selected for erasure. (The system may
After an erase command sequence is written, if all sectors
use either
or
to control the read cycles.) But I/O2
CE
OE
selected for erasing are protected,
Polling on I/O7 is
Data
cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information.
Refer to Table 10 to compare outputs for I/O2 and I/O6.
Figure 6 shows the toggle bit algorithm in flowchart form, and
the section " I/O2: Toggle Bit II" explains the algorithm. See
also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle
Bit Timings figure for the toggle bit timing diagram. The I/O2
vs. I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form.
active for approximately 100µs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 - I/O0
on the following read cycles. This is because I/O7 may
change asynchronously with I/O0 - I/O6 while Output Enable
(
) is asserted low. The
Polling Timings (During
Data
OE
Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this. Table 10 shows the outputs for
Data
Polling algorithm.
Polling on I/O7. Figure 5 shows the
Data
Reading Toggle Bits I/O6, I/O2
I/O6: Toggle Bit I
Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7 - I/O0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and store
the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O7 - I/O0 on the following read cycle.
Toggle Bit I on I/O6 indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
of the final
pulse in the command sequence (prior to the
WE
program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.
(The system may use either
or
to control the read
CE
OE
cycles.) When the operation is complete, I/O6 stops toggling.
PRELIMINARY (March, 2006, Version 0.0)
15
AMIC Technology, Corp.
A29L161A Series
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O5 went high. If the toggle bit
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O5 has not gone high. The
system may continue to monitor the toggle bit and I/O5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6).
START
Read I/O7-I/O0
Address = VA
Yes
I/O7
= Data ?
No
No
I/O5: Exceeded Timing Limits
I/O5 = 1?
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
Yes
Read I/O
Address = VA
7
- I/O
0
The I/O5 failure condition may appear if the system tries to
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and
when the operation has exceeded the timing limits, I/O5
produces a "1." Under both these conditions, the system
must issue the reset command to return the device to
reading array data.
Yes
I/O7
= Data ?
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read I/O3 to determine whether or not an erase
operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out is
complete, I/O3 switches from "0" to "1." The system may
ignore I/O3 if the system can guarantee that the time
between additional sector erase commands will always be
less than 50µs. See also the "Sector Erase Command
Sequence" section.
No
FAIL
PASS
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
After the sector erase command sequence is written, the
system should read the status on I/O7 (
Polling) or I/O6
Data
2. I/O
7
should be rechecked even if I/O
may change simultaneously with I/O
5 = "1" because
I/O7
5
.
(Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until the
erase operation is complete. If I/O3 is "0", the device will
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have been
accepted. Table 10 shows the outputs for I/O3.
Figure 5. Data Polling Algorithm
PRELIMINARY (March, 2006, Version 0.0)
16
AMIC Technology, Corp.
A29L161A Series
START
Read I/O
7
-I/O
0
Read I/O7-I/O
0
(Note 1)
No
Toggle Bit
= Toggle ?
Yes
No
I/O5 = 1?
Yes
- I/O
Read I/O
7
0
(Notes 1,2)
Twice
No
Toggle Bit
= Toggle ?
Yes
Program/Erase
Operation Not
Commplete, Write
Reset Command
Program/Erase
Operation Complete
Notes :
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as I/O
5
changes to "1". See text.
Figure 6. Toggle Bit Algorithm
PRELIMINARY (March, 2006, Version 0.0)
17
AMIC Technology, Corp.
A29L161A Series
Table 10. Write Operation Status
I/O7
I/O6
I/O5
I/O3
I/O2
Operation
(Note 1)
(Note 2)
(Note 1)
Standard
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
0
0
0
N/A
1
No toggle
Toggle
I/O7
0
Erase
Suspend
Mode
Reading within Erase
Suspended Sector
1
No toggle
N/A
Toggle
Reading within Non-Erase
Suspend Sector
Data
I/O7
Data
Data
0
Data
N/A
Data
N/A
Erase-Suspend-Program
Toggle
Notes:
1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “I/O5: Exceeded Timing Limits” for more information.
Maximum Negative Input Overshoot
20ns
20ns
+0.8V
-0.5V
-2.0V
20ns
Maximum Positive Input Overshoot
20ns
VCC+2.0V
VCC+0.5V
2.0V
20ns
20ns
PRELIMINARY (March, 2006, Version 0.0)
18
AMIC Technology, Corp.
A29L161A Series
DC Characteristics
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
Min.
Typ.
Max.
Unit
ILI
Input Load Current
VIN = VSS to VCC. VCC = VCC Max
VCC = VCC Max, A9 =12.5V
VOUT = VSS to VCC. VCC = VCC Max
5 MHz
±1.0
35
µA
µA
µA
ILIT
ILO
A9 Input Load Current
Output Leakage Current
±1.0
16
9
2
VCC Active Read Current
(Notes 1, 2)
ICC1
mA
= VIL,
= VIH
CE
OE
1 MHz
4
VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)
ICC2
ICC3
20
30
5
mA
= VIL,
= VIH
=VIH
CE
CE
OE
VCC Standby Current (Note 2)
0.2
0.2
µA
ICC5
VIL
Automatic Sleep Mode (Note 2, 4, 5)
Input Low Level
5
0.8
VIH = VCC ± 0.3V; VIL = VSS ± 0.3V
µA
V
-0.5
0.7 x VCC
11.5
VIH
Input High Level
VCC + 0.3
12.5
V
VID
Voltage for Autoselect
Output Low Voltage
VCC = 3.3 V
V
VOL
VOH1
VOH2
IOL = 4.0mA, VCC = VCC Min
IOH = -2.0 mA, VCC = VCC Min
IOH = -100 µA, VCC = VCC Min
0.45
V
0.85 x VCC
VCC - 0.4
V
Output High Voltage
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with
at VIH. Typical VCC is 3.3V.
OE
2. Maximum ICC specifications are tested with VCC = VCC max.
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode current
is 200nA.
5. Not 100% tested.
PRELIMINARY (March, 2006, Version 0.0)
19
AMIC Technology, Corp.
A29L161A Series
DC Characteristics (continued)
Zero Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1MHz
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
8
3.6V
2.7V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note : T = 25°C
Typical ICC1 vs. Frequency
PRELIMINARY (March, 2006, Version 0.0)
20
AMIC Technology, Corp.
A29L161A Series
AC Characteristics
Read Only Operations
Parameter
Symbols
Description
Test Setup
Speed
Unit
JEDEC
Std
-70
-60
Read Cycle Time (Note 1)
Address to Output Delay
tAVAV
tAVQV
tRC
Min.
70
60
ns
ns
= VIL
tACC
CE
Max.
70
60
= VIL
OE
Chip Enable to Output Delay
Output Enable to Output Delay
tELQV
tGLQV
tCE
Max.
Max.
Min.
70
30
0
60
20
0
ns
ns
ns
= VIL
OE
tOE
Read
Output Enable Hold
tOEH
Toggle and
Polling
Time (Note 1)
ns
Min.
10
25
10
25
Data
Chip Enable to Output High Z (Notes 1)
tEHQZ
tGHQZ
tHZ
tDF
Max.
ns
ns
Output Enable to Output High Z (Notes 1)
25
0
25
0
Output Hold Time from Addresses,
or
CE
tAXQX
tOH
Min.
ns
, Whichever Occurs First (Note 1)
OE
Notes:
1. Not 100% tested.
2. See Test Conditions and Test Setup for test specifications.
Timing Waveforms for Read Only Operation
tRC
Addresses
Addresses Stable
tACC
CE
tDF
tOE
OE
tOEH
WE
tCE
tOH
High-Z
High-Z
Output
Output Valid
PRELIMINARY (March, 2006, Version 0.0)
21
AMIC Technology, Corp.
A29L161A Series
AC Characteristics
Erase and Program Operations
Parameter
Description
Speed
Unit
JEDEC
tAVAV
Std
tWC
tAS
-70
70
0
-60
60
0
Write Cycle Time (Note 1)
Min.
Min.
Min.
Min.
Min.
Min.
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
tAVWL
tWLAX
tDVWH
tWHDX
tAH
45
35
0
45
35
0
Data Setup Time
tDS
Data Hold Time
tDH
Output Enable Setup Time
Read Recover Time Before Write
tOES
0
0
tGHWL
tGHWL
Min.
0
0
ns
(
high to
low)
WE
OE
tELWL
tWHEH
tWLWH
tWHWL
tCS
tCH
Min.
Min.
Min.
0
0
0
0
ns
ns
ns
ns
Setup Time
Hold Time
CE
CE
tWP
tWPH
45
45
Write Pulse Width
Write Pulse Width High
Min.
Typ.
30
30
30
30
tWHWH1
tWHWH2
tWHWH1
Programming Operation (Note 2)
µs
sec
µs
tWHWH2
Sector Erase Operation (Note 2)
VCC Set Up Time (Note 1)
Typ.
Min.
1.0
50
1.0
50
tvcs
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
PRELIMINARY (March, 2006, Version 0.0)
22
AMIC Technology, Corp.
A29L161A Series
Timing Waveforms for Program Operation
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tWC
tAS
Addresses
CE
PA
PA
555h
PA
tAH
tCH
tWP
OE
tWHWH1
WE
tCS
tWPH
tDS
tDH
Data
A0h
PD
DOUT
Status
tVCS
VCC
Note :
1. PA = program addrss, PD = program data, Dout is the true data at the program address.
2. Illustration shows device in word mode.
PRELIMINARY (March, 2006, Version 0.0)
23
AMIC Technology, Corp.
A29L161A Series
Timing Waveforms for Chip/Sector Erase Operation
Erase Command Sequence (last two cycles)
Read Status Data
VA
VA
tAS
tWC
SA
Addresses
CE
2AAh
555h for chip erase
tAH
OE
tCH
tWP
WE
tWPH
tDH
tWHWH2
tCS
tDS
In
Data
55h
30h
10h for chip erase
Complete
Progress
tVCS
VCC
Note :
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
2. Illustratin shows device in word mode.
PRELIMINARY (March, 2006, Version 0.0)
24
AMIC Technology, Corp.
A29L161A Series
Timing Waveforms for
Polling (During Embedded Algorithms)
Data
tRC
Addresses
VA
VA
VA
tAC
C
CE
tCH
OE
tCE
tOE
tDF
tOEH
WE
tOH
High-Z
Valid Data
Valid Data
I/O7
Complement
Complement
Status Data
True
True
High-Z
I/O0 - I/O6
High-Z
Status Data
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
PRELIMINARY (March, 2006, Version 0.0)
25
AMIC Technology, Corp.
A29L161A Series
Timing Waveforms for Toggle Bit (During Embedded Algorithms)
tRC
Addresses
CE
VA
VA
VA
VA
tAC
C
tCE
tCH
tOE
OE
tDF
tOEH
WE
tOH
I/O6 , I/O2
High-Z
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stop togging)
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Timing Waveforms for I/O2 vs. I/O6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
WE
I/O
Erase
Suspend
Program
Erase
Erase
Erase Suspend
Erase Suspend
Read
Erase
Complete
Read
6
I/O2
I/O2
and I/O
6
toggle with OE and CE
Note : Both I/O
6
and I/O
2
toggle with OE or CE. See the text on I/O
6
and I/O
2
in the section "Write Operation Status" for
more information.
PRELIMINARY (March, 2006, Version 0.0)
26
AMIC Technology, Corp.
A29L161A Series
Timing Waveforms for Alternate
Controlled Write Operation
CE
PA for program
SA for sector erase
555 for chip erase
555 for program
2AA for erase
Data Polling
PA
Addresses
tWC
tAS
tAH
tWH
WE
OE
tWHWH1 or 2
tCP
tCPH
tDH
CE
tWS
tDS
Data
DOUT
I/O7
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter
Sector Erase Time
Typ. (Note 1)
Max. (Note 2)
Unit
sec
sec
µs
Comments
1.0
28
30
8
Excludes 00h programming
prior to erasure
Chip Erase Time
Programming Time
500
25
Excludes
system-level
overhead (Note 5)
Chip Programming Time
Notes:
20
sec
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 100,000 cycles. Additionally,
programming typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 3.0V, 100,000 cycles.
3. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
4. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 9
for further information on command definitions.
5. The device has a guaranteed minimum erase and program cycle endurance of 10,000 cycles.
PRELIMINARY (March, 2006, Version 0.0)
27
AMIC Technology, Corp.
A29L161A Series
Latch-up Characteristics
Description
Min.
Max.
VCC+1.0V
+100 mA
12.5V
Input Voltage with respect to VSS on all I/O pins
VCC Current
-1.0V
-100 mA
-1.0V
Input voltage with respect to VSS on all pins except I/O pins
(including A9,
)
OE
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.
Data Retention
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
20
125°C
Test Conditions
Test Specifications
Test Condition
-60
-70
Unit
Output Load
1 TTL gate
Output Load Capacitance, CL(including jig
capacitance)
30
30
5
pF
Input Rise and Fall Times
5
0.0 - 3.0
1.5
ns
V
Input Pulse Levels
0.0 - 3.0
Input timing measurement reference levels
Output timing measurement reference levels
1.5
1.5
V
1.5
V
Test Setup
3.3 V
2.7 KΩ
Device
Under
Test
Diodes = IN3064 or Equivalent
CL
6.2 KΩ
PRELIMINARY (March, 2006, Version 0.0)
28
AMIC Technology, Corp.
A29L161A Series
Ordering Information
Top Boot Sector Flash
Standby
Current
Typ. (µA)
Active Read Program/Era
Access Time
(ns)
Package
Part No.
Current Typ.
(mA)
se Current
Typ. (mA)
A29L161ATG-60
A29L161ATG-60U
A29L161ATG-60I
A29L161ATG-60F
A29L161ATG-60UF
A29L161ATG-60IF
A29L161ATG-70
A29L161ATG-70U
A29L161ATG-70I
A29L161ATG-70F
A29L161ATG-70UF
A29L161ATG-70IF
48-ball TFBGA
48-ball TFBGA
48-ball TFBGA
60
9
20
0.2
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
48-ball TFBGA
48-ball TFBGA
48-ball TFBGA
70
9
20
0.2
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
Note: -U is for industrial operating temperature range: -40°C to +85°C
-I is for industrial operating temperature range: -25°C to +85°C
PRELIMINARY (March, 2006, Version 0.0)
29
AMIC Technology, Corp.
A29L161A Series
Ordering Information (continued)
Bottom Boot Sector Flash
Standby
Current
Typ. (µA)
Active Read Program/Era
Access Time
Part No.
(ns)
Current Typ.
(mA)
se Current
Typ. (mA)
Package
A29L161AUG-60
A29L161AUG-60U
48-ball TFBGA
48-ball TFBGA
A29L161AUG-60I
60
48-ball TFBGA
9
20
0.2
A29L161AUG-60F
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
48-ball TFBGA
A29L161AUG-60UF
A29L161AUG-60IF
A29L161AUG-70
A29L161AUG-70U
48-ball TFBGA
A29L161AUG-70I
70
48-ball TFBGA
9
20
0.2
A29L161AUG-70F
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
A29L161AUG-70UF
A29L161AUG-70IF
Note: -U is for industrial operating temperature range: -40°C to +85°C
industrial operating temperature
for
range:
-25°C
to
+85°C
PRELIMINARY (March, 2006, Version 0.0)
30
AMIC Technology, Corp.
A29L161A Series
Package Information
48 Balls CSP (6 x 8 mm) Outline Dimensions
(48TFBGA)
unit: mm
TOP VIEW
BOTTOM VIEW
b
1
2 3 4 5 6
6
5 4 3 2 1
H
G
F
H
G
F
E
D
C
B
A
E
D
C
B
A
e
D1
Ball*A1 CORNER
SIDE VIEW
D
C
SEATING PLANE
0.10
C
Dimensions in mm
Symbol
Min.
Nom.
Max.
A
A1
b
-
-
0.25
1.20
0.30
0.40
6.10
0.20
0.30
5.90
-
D
6.00
D1
e
4.00 BSC
0.80
-
-
E
7.90
8.00
8.10
E1
5.60 BSC
PRELIMINARY (March, 2006, Version 0.0)
31
AMIC Technology, Corp.
相关型号：
©2020 ICPDF网 联系我们和版权申明