首页 |元器件品牌

A29L400ATV-70I [AMICC]

512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory; 512K ×8位/ 256K ×16位CMOS 3.0伏只，引导扇区闪存
A29L400ATV-70I
型号： A29L400ATV-70I
厂家： AMIC TECHNOLOGY    AMIC TECHNOLOGY
描述：

512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
512K ×8位/ 256K ×16位CMOS 3.0伏只，引导扇区闪存

闪存
文件： 总38页 (文件大小：539K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
A29L400A Series  
512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only,  
Boot Sector Flash Memory  
Preliminary  
Document Title  
512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory  
Revision History  
Rev. No. History  
Issue Date  
Remark  
0.0  
Initial issue  
July 24, 2005  
Preliminary  
PRELIMINARY (July, 2005, Version 0.0)  
AMIC Technology, Corp.  
A29L400A Series  
512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only,  
Boot Sector Flash Memory  
Preliminary  
Features  
ꢀSingle power supply operation  
ꢀEmbedded Algorithms  
- Full voltage range: 2.7 to 3.6 volt read and write  
operations for battery-powered applications  
- Regulated voltage range: 3.0 to 3.6 volt read and write  
operations for compatibility with high performance 3.3  
volt microprocessors  
- Embedded Erase algorithm will automatically erase the  
entire chip or any combination of designated sectors  
and verify the erased sectors  
- Embedded Program algorithm automatically writes and  
verifies data at specified addresses  
ꢀAccess times:  
ꢀTypical 100,000 program/erase cycles per sector  
- 70/90 (max.)  
ꢀCurrent:  
ꢀ20-year data retention at 125°C  
- Reliable operation for the life of the system  
ꢀCompatible with JEDEC-standards  
- 4 mA typical active read current  
- 20 mA typical program/erase current  
- 200 nA typical CMOS standby  
- Pinout and software compatible with single-power-  
supply Flash memory standard  
- 200 nA Automatic Sleep Mode current  
ꢀFlexible sector architecture  
- Superior inadvertent write protection  
ꢀ
Polling and toggle bits  
Data  
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors  
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX7 sectors  
- Any combination of sectors can be erased  
- Supports full chip erase  
- Provides a software method of detecting completion of  
program or erase operations  
ꢀReady /  
pin (RY /  
)
BY  
BUSY  
- Provides a hardware method of detecting completion of  
program or erase operations  
ꢀErase Suspend/Erase Resume  
- Sector protection:  
A hardware method of protecting sectors to prevent  
any inadvertent program or erase operations within that  
sector. Temporary Sector Unprotect feature allows  
code changes in previously locked sectors  
ꢀExtended operating temperature range: -40°C ~ +85°C  
for –U series  
- Suspends a sector erase operation to read data from,  
or program data to, a non-erasing sector, then  
resumes the erase operation  
ꢀHardware reset pin (  
)
RESET  
ꢀUnlock Bypass Program Command  
- Reduces overall programming time when issuing  
multiple program command sequence  
ꢀTop or bottom boot block configurations available  
- Hardware method to reset the device to reading array  
data  
ꢀPackage options  
- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA  
PRELIMINARY (July, 2005, Version 0.0)  
1
AMIC Technology, Corp.  
A29L400A Series  
General Description  
The A29L400A is an 4Mbit, 3.0 volt-only Flash memory  
organized as 524,288 bytes of 8 bits or 262,144 words of 16  
bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits  
of data appear on I/O0~I/O15. The A29L400A is offered in 48-  
ball TFBGA, 44-pin SOP and 48-Pin TSOP packages. This  
device is designed to be programmed in-system with the  
standard system 3.0 volt VCC supply. Additional 12.0 volt  
VPP is not required for in-system write or erase operations.  
However, the A29L400A can also be programmed in  
standard EPROM programmers.  
Device erasure occurs by executing the proper erase  
command sequence. This initiates the Embedded Erase  
algorithm  
-
an internal algorithm that automatically  
preprograms the array (if it is not already programmed)  
before executing the erase operation. During erase, the  
device automatically times the erase pulse widths and  
verifies proper erase margin. The Unlock Bypass mode  
facilitates faster programming times by requiring only two  
write cycles to program data instead of four.  
The host system can detect whether a program or erase  
The A29L400A has the first toggle bit, I/O6, which indicates  
whether an Embedded Program or Erase is in progress, or it  
is in the Erase Suspend. Besides the I/O6 toggle bit, the  
A29L400A has a second toggle bit, I/O2, to indicate whether  
the addressed sector is being selected for erase. The  
A29L400A also offers the ability to program in the Erase  
Suspend mode. The standard A29L400A offers access times  
of 70 and 90ns, allowing high-speed microprocessors to  
operate without wait states. To eliminate bus contention the  
operation is complete by observing the RY /  
pin, or by  
BY  
reading the I/O7 (  
Polling) and I/O6 (toggle) status bits.  
Data  
After a program or erase cycle has been completed, the  
device is ready to read array data or accept another  
command.  
The sector erase architecture allows memory sectors to be  
erased and reprogrammed without affecting the data contents  
of other sectors. The A29L400A is fully erased when shipped  
from the factory.  
The hardware sector protection feature disables operations  
for both program and erase in any combination of the  
sectors of memory. This can be achieved via programming  
equipment.  
The Erase Suspend/Erase Resume feature enables the user  
to put erase on hold for any period of time to read data from,  
or program data to, any other sector that is not selected for  
erasure. True background erase can thus be achieved.  
device has separate chip enable (  
), write enable (  
)
WE  
CE  
and output enable (  
) controls.  
OE  
The device requires only a single 3.0 volt power supply for  
both read and write functions. Internally generated and  
regulated voltages are provided for the program and erase  
operations.  
The A29L400A is entirely software command set compatible  
with the JEDEC single-power-supply Flash standard.  
Commands are written to the command register using  
standard microprocessor write timings. Register contents  
serve as input to an internal state-machine that controls the  
erase and programming circuitry. Write cycles also internally  
latch addresses and data needed for the programming and  
erase operations. Reading data out of the device is similar to  
reading from other Flash or EPROM devices.  
The hardware  
pin terminates any operation in  
RESET  
progress and resets the internal state machine to reading  
array data. The pin may be tied to the system reset  
RESET  
circuitry. A system reset would thus also reset the device,  
enabling the system microprocessor to read the boot-up  
firmware from the Flash memory.  
The device offers two power-saving features. When  
addresses have been stable for a specified amount of time,  
the device enters the automatic sleep mode. The system can  
also place the device into the standby mode. Power  
consumption is greatly reduced in both these modes.  
Device programming occurs by writing the proper program  
command sequence. This initiates the Embedded Program  
algorithm - an internal algorithm that automatically times the  
program pulse widths and verifies proper program margin.  
PRELIMINARY (July, 2005, Version 0.0)  
2
AMIC Technology, Corp.  
A29L400A Series  
Pin Configurations  
ꢀSOP  
ꢀTSOP (I)  
NC  
1
RESET  
44  
43  
42  
2
3
4
WE  
A8  
RY/BY  
A17  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
NC  
NC  
WE  
RESET  
NC  
NC  
RY/BY  
NC  
A17  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
2
3
4
5
6
7
8
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
A16  
BYTE  
VSS  
I/O15 (A-1)  
I/O7  
I/O14  
I/O6  
I/O13  
I/O5  
I/O12  
I/O4  
VCC  
I/O11  
I/O3  
I/O10  
I/O2  
I/O9  
I/O1  
I/O8  
A7  
A6  
A5  
A9  
41  
40  
39  
A10  
A11  
5
6
A4  
A3  
A2  
A1  
A0  
A12  
7
38  
8
A13  
A14  
A15  
37  
36  
35  
34  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
A29L400AV  
A16  
CE  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
BYTE  
VSS  
VSS  
OE  
I/O15 (A-1)  
I/O7  
I/O0  
I/O8  
I/O1  
I/O9  
I/O2  
29  
28  
27  
26  
25  
I/O0  
OE  
VSS  
CE  
A0  
I/O14  
I/O6  
I/O13  
I/O5  
20  
21  
22  
I/O12  
I/O4  
I/O10  
I/O3  
VCC  
I/O11  
23  
ꢀTFBGA  
TFBGA  
Top View, Balls Facing Down  
A6  
B6  
C6  
D6  
E6  
F6  
G6  
H6  
A13  
A12  
A14  
A15  
A16  
BYTE  
I/O15(A-1)  
VSS  
G5  
A5  
B5  
C5  
D5  
E5  
F5  
H5  
A9  
A8  
A10  
A11  
I/O7  
I/O14  
I/O13  
I/O6  
A4  
B4  
C4  
D4  
E4  
F4  
G4  
H4  
WE  
RESET  
NC  
NC  
I/O5  
I/O12  
VCC  
I/O4  
A3  
B3  
C3  
D3  
E3  
F3  
G3  
H3  
RY/BY  
NC  
NC  
NC  
I/O2  
I/O10  
I/O11  
I/O3  
A2  
B2  
C2  
A6  
D2  
A5  
E2  
F2  
G2  
H2  
A7  
A17  
I/O0  
I/O8  
I/O9  
I/O1  
A1  
B1  
C1  
A2  
D1  
A1  
E1  
F1  
G1  
H1  
A3  
A4  
A0  
CE  
OE  
VSS  
PRELIMINARY  
(July, 2005, Version 0.0)  
3
AMIC Technology, Corp.  
A29L400A Series  
Block Diagram  
RY/BY  
I/O0 - I/O15 (A-1)  
VCC  
VSS  
Sector Switches  
Input/Output  
Buffers  
Erase Voltage  
Generator  
RESET  
State  
Control  
WE  
BYTE  
PGM Voltage  
Generator  
Command  
Register  
Chip Enable  
Output Enable  
Logic  
STB  
Data Latch  
CE  
OE  
Y-Decoder  
Y-Gating  
STB  
VCC Detector  
Timer  
A0-A17  
X-decoder  
Cell Matrix  
Pin Descriptions  
Pin No.  
A0 - A17  
I/O0 - I/O14  
Description  
Address Inputs  
Data Inputs/Outputs  
Data Input/Output, Word Mode  
I/O15  
I/O15 (A-1)  
A-1  
LSB Address Input, Byte Mode  
Chip Enable  
CE  
WE  
Write Enable  
Output Enable  
OE  
Hardware Reset  
RESET  
BYTE  
Selects Byte Mode or Word Mode  
Ready/  
- Output  
BUSY  
RY/  
BY  
VSS  
Ground  
VCC  
NC  
Power Supply  
Pin not connected internally  
PRELIMINARY  
(July, 2005, Version 0.0)  
4
AMIC Technology, Corp.  
A29L400A Series  
Absolute Maximum Ratings*  
*Comments  
Stresses above those listed under "Absolute Maximum  
Ratings" may cause permanent damage to this device.  
These are stress ratings only. Functional operation of  
this device at these or any other conditions above  
those indicated in the operational sections of these  
specification is not implied or intended. Exposure to  
the absolute maximum rating conditions for extended periods  
may affect device reliability.  
Storage Temperature Plastic Packages. . . .-65°C to + 150°C  
Ambient Temperature with Power Applied.. -55°C to + 125°C  
Voltage with Respect to Ground  
VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . ……. -0.5V to +4.0V  
A9,  
&
(Note 2) . . . . . . . . . . . ….. -0.5 to +12.5V  
RESET  
OE  
All other pins (Note 1) . . . . . . . . . . . . …-0.5V to VCC + 0.5V  
Output Short Circuit Current (Note 3) . . …. . . . . . . 200mA  
Notes:  
Operating Ranges  
1. Minimum DC voltage on input or I/O pins is -0.5V. During  
voltage transitions, input or I/O pins may undershoot VSS  
to -2.0V for periods of up to 20ns. Maximum DC voltage  
on input and I/O pins is VCC +0.5V. During voltage  
transitions, input or I/O pins may overshoot to VCC +2.0V  
for periods up to 20ns.  
Commercial (C) Devices  
Ambient Temperature (TA) . . . . . . . . . . . . . . . . 0°C to +70°C  
Extended Range Devices  
Ambient Temperature (TA) . . . . . . . . . . . . . . . -40°C to +85°C  
2. Minimum DC input voltage on A9,  
and  
is  
-
OE  
RESET  
and  
VCC Supply Voltages  
0.5V. During voltage transitions, A9,  
OE  
RESET  
VCC for all devices . . . . . . . . . . . . . . .. . . . . . +2.7V to +3.6V  
Operating ranges define those limits between which the  
functionally of the device is guaranteed.  
may overshoot VSS to -2.0V for periods of up to 20ns.  
Maximum DC input voltage on A9 is +12.5V which may  
overshoot to 14.0V for periods up to 20ns.  
3. No more than one output is shorted at a time. Duration of  
the short circuit should not be greater than one second.  
Device Bus Operations  
This section describes the requirements and use of the  
device bus operations, which are initiated through the  
internal command register. The command register itself does  
not occupy any addressable memory location. The register is  
composed of latches that store the commands, along with  
the address and data information needed to execute the  
command. The contents of the register serve as inputs to the  
internal state machine. The state machine outputs dictate the  
function of the device. The appropriate device bus operations  
table lists the inputs and control levels required, and the  
resulting output. The following subsections describe each of  
these operations in further detail.  
Table 1. A29L400A Device Bus Operations  
Operation  
A0 – A17  
(Note 1)  
I/O0 - I/O7  
I/O8 - I/O15  
=VIH  
WE  
CE  
OE  
RESET  
=VIL  
BYTE  
BYTE  
Read  
L
L
H
H
AIN  
DOUT  
DOUT  
I/O8~I/O4=High-Z  
I/O15=A-1  
Write  
L
H
X
H
X
H
L
X
H
X
L
H
AIN  
X
DIN  
DIN  
High-Z  
CMOS Standby  
Output Disable  
Hardware Reset  
High-Z  
High-Z  
High-Z  
DIN  
High-Z  
High-Z  
High-Z  
X
High-Z  
VCC ± 0.3 V  
VCC ± 0.3 V  
L
X
L
H
L
X
High-Z  
High-Z  
X
X
Sector Protect  
(See Note 2)  
VID  
Sector Address,  
A6=L, A1=H, A0=L  
Sector Unprotect  
(See Note 2)  
L
H
X
L
VID  
VID  
Sector Address,  
A6=H, A1=H, A0=L  
DIN  
X
X
X
Temporary Sector  
Unprotect  
X
X
AIN  
DIN  
DIN  
Legend:  
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In  
Notes:  
1. Addresses are A17:A0 in word mode (  
2. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.  
=VIH), A17: A in byte mode (  
=VIL).  
BYTE  
BYTE  
-1  
PRELIMINARY  
(July, 2005, Version 0.0)  
5
AMIC Technology, Corp.  
A29L400A Series  
ICC2 in the DC Characteristics table represents the active  
current specification for the write mode. The "AC  
Characteristics" section contains timing specification tables  
and timing diagrams for write operations.  
Word/Byte Configuration  
The  
pin determines whether the I/O pins I/O15-I/O0  
BYTE  
operate in the byte or word configuration. If the  
pin is  
BYTE  
set at logic ”1”, the device is in word configuration, I/O15-I/O0  
are active and controlled by and  
Program and Erase Operation Status  
.
OE  
CE  
During an erase or program operation, the system may  
check the status of the operation by reading the status bits  
on I/O7 - I/O0. Standard read cycle timings and ICC read  
specifications apply. Refer to "Write Operation Status" for  
more information, and to each AC Characteristics section for  
timing diagrams.  
If the  
pin is set at logic “0”, the device is in byte  
BYTE  
configuration, and only I/O0-I/O7 are active and controlled by  
and . I/O8-I/O14 are tri-stated, and I/O15 pin is used  
CE  
OE  
as an input for the LSB(A-1) address function.  
Requirements for Reading Array Data  
Standby Mode  
To read array data from the outputs, the system must drive  
When the system is not reading or writing to the device, it  
can place the device in the standby mode. In this mode,  
current consumption is greatly reduced, and the outputs are  
the  
and  
pins to VIL.  
is the power control and  
CE  
OE  
CE  
selects the device.  
is the output control and gates array  
OE  
data to the output pins.  
placed in the high impedance state, independent of the  
input.  
OE  
should remain at VIH all the time  
WE  
during read operation. The  
pin determines whether  
BYTE  
the device outputs array data in words and bytes. The  
internal state machine is set for reading array data upon  
device power-up, or after a hardware reset. This ensures that  
no spurious alteration of the memory content occurs during  
the power transition. No command is necessary in this mode  
to obtain array data. Standard microprocessor read cycles  
that assert valid addresses on the device address inputs  
produce valid data on the device data outputs. The device  
remains enabled for read access until the command register  
contents are altered.  
See "Reading Array Data" for more information. Refer to the  
AC Read Operations table for timing specifications and to the  
Read Operations Timings diagram for the timing waveforms,  
lCC1 in the DC Characteristics table represents the active  
current specification for reading array data.  
The device enters the CMOS standby mode when the  
&
CE  
pins are both held at VCC ± 0.3V. (Note that this is a  
RESET  
more restricted voltage range than VIH.) If  
and  
CE  
RESET  
are held at VIH, but not within VCC ± 0.3V, the device will be  
in the standby mode, but the standby current will be greater.  
The device requires the standard access time (tCE) before it  
is ready to read data.  
If the device is deselected during erasure or programming,  
the device draws active current until the operation is  
completed.  
ICC3 and ICC4 in the DC Characteristics tables represent the  
standby current specification.  
Automatic Sleep Mode  
The automatic sleep mode minimizes Flash device energy  
consumption. The device automatically enables this mode  
when addresses remain stable for tACC +30ns. The automatic  
Writing Commands/Command Sequences  
To write a command or command sequence (which includes  
programming data to the device and erasing sectors of  
sleep mode is independent of the  
,
and  
control  
OE  
WE  
CE  
signals. Standard address access timings provide new data  
when addresses are changed. While in sleep mode, output  
data is latched and always available to the system. ICC4 in the  
DC Characteristics table represents the automatic sleep  
mode current specification.  
memory), the system must drive  
and  
to VIL, and  
CE  
WE  
to VIH. For program operations, the  
pin  
BYTE  
OE  
determines whether the device accepts program data in  
bytes or words, Refer to “Word/Byte Configuration” for more  
information. The device features an Unlock Bypass mode to  
facilitate faster programming. Once the device enters the  
Unlock Bypass mode, only two write cycles are required to  
program a word or byte, instead of four.  
The “ Word / Byte Program Command Sequence” section  
has details on programming data to the device using both  
standard and Unlock Bypass command sequence. An erase  
operation can erase one sector, multiple sectors, or the  
entire device. The Sector Address Tables indicate the  
address range that each sector occupies. A "sector address"  
consists of the address inputs required to uniquely select a  
sector. See the "Command Definitions" section for details on  
erasing a sector or the entire chip, or suspending/resuming  
the erase operation.  
Output Disable Mode  
When the  
input is at VIH, output from the device is  
OE  
disabled. The output pins are placed in the high impedance  
state.  
: Hardware Reset Pin  
RESET  
The  
pin provides a hardware method of resetting  
RESET  
the device to reading array data. When the system drives the  
pin low for at least a period of tRP, the device  
RESET  
immediately terminates any operation in progress, tristates  
all data output pins, and ignores all read/write attempts for  
the duration of the  
pulse. The device also resets the  
RESET  
After the system writes the autoselect command sequence,  
the device enters the autoselect mode. The system can then  
read autoselect codes from the internal register (which is  
separate from the memory array) on I/O7 - I/O0. Standard  
read cycle timings apply in this mode. Refer to the  
"Autoselect Mode" and "Autoselect Command Sequence"  
sections for more information.  
internal state machine to reading array data. The operation  
that was interrupted should be reinitiated once the device is  
ready to accept another command sequence, to ensure data  
integrity.  
Current is reduced for the duration of the  
pulse.  
RESET  
When  
is held at VSS ± 0.3V, the device draws  
RESET  
PRELIMINARY  
(July, 2005, Version 0.0)  
6
AMIC Technology, Corp.  
A29L400A Series  
CMOS standby current (ICC4 ). If  
is held at VIL but not  
RESET  
within VSS ± 0.3V, the standby current will be greater.  
The pin may be tied to the system reset circuitry. A  
RY/  
to determine whether the reset operation is  
BY  
complete. If  
is asserted when a program or erase  
RESET  
RESET  
operation is not executing (RY/  
operation is completed within a time of tREADY (not during  
Embedded Algorithms). The system can read data tRH after  
pin is “1”), the reset  
BY  
system reset would thus also reset the Flash memory,  
enabling the system to read the boot-up firmware from the  
Flash memory.  
the  
pin return to VIH.  
RESET  
If  
is asserted during a program or erase operation,  
RESET  
Refer to the AC Characteristics tables for  
parameters and diagram.  
RESET  
the RY/  
pin remains a “0” (busy) until the internal reset  
BY  
operation is complete, which requires a time tREADY (during  
Embedded Algorithms). The system can thus monitor  
Table 2. A29L400A Top Boot Block Sector Address Table  
Sector  
A17  
A16  
A15  
A14  
A13  
A12  
Sector Size  
Address Range (in hexadecimal)  
(Kbytes/Kwords)  
(x8)  
(x16)  
Address Range  
00000h - 0FFFFh  
10000h - 1FFFFh  
20000h - 2FFFFh  
30000h - 3FFFFh  
40000h - 4FFFFh  
50000h - 5FFFFh  
60000h - 6FFFFh  
70000h - 77FFFh  
Address Range  
00000h - 07FFFh  
08000h - 0FFFFh  
10000h - 17FFFh  
18000h - 1FFFFh  
20000h - 27FFFh  
28000h - 2FFFFh  
30000h - 37FFFh  
38000h - 3BFFFh  
SA0  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
32/16  
8/4  
1
78000h - 79FFFh 3C000h - 3CFFFh  
7A000h - 7BFFFh 3D000h - 3DFFFh  
7C000h - 7FFFFh 3E000h - 3FFFFh  
1
0
1
8/4  
1
1
X
16/8  
Table 3. A29L400A Bottom Boot Block Sector Address Table  
Sector  
A17  
A16  
A15  
A14  
A13  
A12  
Sector Size  
Address Range  
(Kbytes/Kwords)  
(x8)  
(x16)  
Address Range  
00000h - 03FFFh  
04000h - 05FFFh  
06000h - 07FFFh  
08000h - 0FFFFh  
10000h - 1FFFFh  
20000h - 2FFFFh  
30000h - 3FFFFh  
40000h - 4FFFFh  
50000h - 5FFFFh  
60000h - 6FFFFh  
70000h - 7FFFFh  
Address Range  
00000h - 01FFFh  
02000h - 02FFFh  
03000h - 03FFFh  
04000h - 07FFFh  
08000h - 0FFFFh  
10000h - 17FFFh  
18000h - 1FFFFh  
20000h - 27FFFh  
28000h - 2FFFFh  
30000h - 37FFFh  
38000h - 3FFFFh  
SA0  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
X
0
16/8  
8/4  
0
1
1
8/4  
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32/16  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
X
X
X
X
X
X
X
PRELIMINARY  
(July, 2005, Version 0.0)  
7
AMIC Technology, Corp.  
A29L400A Series  
Autoselect Mode  
The autoselect mode provides manufacturer and device  
identification, and sector protection verification, through  
identifier codes output on I/O7 - I/O0. This mode is primarily  
intended for programming equipment to automatically  
match a device to be programmed with its corresponding  
programming algorithm. However, the autoselect codes  
can also be accessed in-system through the command  
register.  
When using programming equipment, the autoselect mode  
requires VID (11.5V to 12.5 V) on address pin A9. Address  
pins A6, A1, and A0 must be as shown in Autoselect  
Codes (High Voltage Method) table. In addition, when  
verifying sector protection, the sector address must appear  
on the appropriate highest order address bits. Refer to the  
corresponding Sector Address Tables. The Command  
Definitions table shows the remaining address bits that are  
don't care. When all necessary bits have been set as  
required, the programming equipment may then read the  
corresponding identifier code on I/O7 - I/O0.To access the  
autoselect codes in-system, the host system can issue the  
autoselect command via the command register, as shown  
in the Command Definitions table. This method does not  
require VID. See "Command Definitions" for details on using  
the autoselect mode.  
Table 4. A29L400A Autoselect Codes (High Voltage Method)  
Description  
Mode  
A17 A11 A9 A8 A6 A5 A1 A0  
I/O8  
to  
I/O7  
to  
WE  
CE OE  
to  
to  
to  
A7  
X
to  
A2  
X
A12 A10  
I/O15  
X
I/O0  
37h  
34h  
Manufacturer ID: AMIC  
Device ID:  
L
L
L
L
H
H
X
X
X
X
VID  
L
L
L
L
L
Word  
Byte  
B3h  
A29L400A  
VID  
X
X
H
X
34h  
B5h  
(Top Boot Block)  
Device ID:  
Word  
B3h  
A29L400A  
L
L
L
L
H
H
X
X
X
X
VID  
X
X
L
L
X
X
L
H
H
Byte  
X
B5h  
7Fh  
(Bottom Boot  
Block)  
Continuation ID  
VID  
H
X
X
X
01h  
(protected)  
Sector Protection  
Verification  
L
L
H
SA  
X
VID  
X
L
X
H
L
00h  
(unprotected)  
L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care.  
Note: The autoselect codes may also be accessed in-system via command sequences.  
PRELIMINARY  
(July, 2005, Version 0.0)  
8
AMIC Technology, Corp.  
A29L400A Series  
Sector Protection/Unprotection  
Temporary Sector Unprotect  
The hardware sector protection feature disables both  
program and erase operations in any sector. The hardware  
sector unprotection feature re-enables both program and  
erase operations in previously protected sectors.  
It is possible to determine whether a sector is protected or  
unprotected. See “Autoselect Mode” for details.  
This feature allows temporary unprotection of previous  
protected sectors to change data in-system. The Sector  
Unprotect mode is activated by setting the  
pin to VID.  
RESET  
During this mode, formerly protected sectors can be  
programmed or erased by selecting the sector addresses.  
Once VID is removed from the  
pin, all the previously  
RESET  
Sector protection / unprotection can be implemented via two  
methods. The primary method requires VID on the  
protected sectors are protected again. Figure 1 shows the  
algorithm, and the Temporary Sector Unprotect diagram  
shows the timing waveforms, for this feature.  
pin only, and can be implemented either in-system or  
RESET  
via programming equipment. Figure 2 shows the algorithm  
and the Sector Protect / Unprotect Timing Diagram illustrates  
the timing waveforms for this feature. This method uses  
standard microprocessor bus cycle timing. For sector  
unprotect, all unprotected sectors must first be protected  
prior to the first sector unprotect write cycle. The alternate  
method must be implemented using programming  
equipment. The procedure requires a high voltage (VID) on  
address pin A9 and the control pins.  
START  
RESET = VID  
(Note 1)  
The device is shipped with all sectors unprotected.  
It is possible to determine whether a sector is protected or  
unprotected. See "Autoselect Mode" for details.  
Hardware Data Protection  
Perform Erase or  
Program Operations  
The requirement of command unlocking sequence for  
programming or erasing provides data protection against  
inadvertent writes (refer to the Command Definitions table).  
In addition, the following hardware data protection measures  
prevent accidental erasure or programming, which might  
otherwise be caused by spurious system level signals during  
VCC power-up transitions, or from system noise. The device  
is powered up to read array data to avoid accidentally writing  
data to the array.  
RESET = VIH  
Write Pulse "Glitch" Protection  
Temporary Sector  
Unprotect  
Completed (Note 2)  
Noise pulses of less than 5ns (typical) on  
do not initiate a write cycle.  
,
or  
WE  
OE CE  
Logical Inhibit  
Notes:  
Write cycles are inhibited by holding any one of  
=VIL,  
OE  
CE  
1. All protected sectors unprotected.  
2. All previously protected sectors are protected once again.  
= VIH or  
= VIH. To initiate a write cycle,  
and  
WE  
CE  
must be a logical zero while  
is a logical one.  
WE  
OE  
Figure 1. Temporary Sector Unprotect Operation  
Power-Up Write Inhibit  
If  
=
= VIL and  
= VIH during power up, the  
OE  
WE  
device does not accept commands on the rising edge of  
. The internal state machine is automatically reset to  
CE  
WE  
reading array data on the initial power-up.  
PRELIMINARY (July, 2005, Version 0.0)  
9
AMIC Technology, Corp.  
A29L400A Series  
START  
START  
Protect all sectors:  
The indicated portion of  
the sector protect  
PLSCNT=1  
PLSCNT=1  
algorithm must be  
performed for all  
RESET=VID  
RESET=VID  
unprotected sectors prior  
to issuing the first sector  
unprotect address  
Wait 1 us  
Wait 1 us  
No  
No  
No  
Temporary Sector  
Unprotect Mode  
First Write  
Cycle=60h?  
First Write  
Cycle=60h?  
Temporary Sector  
Unprotect Mode  
Yes  
Yes  
Set up sector  
address  
All sectors  
protected?  
Sector Protect  
Write 60h to sector  
address with A6=0,  
A1=1, A0=0  
Yes  
Set up first sector  
address  
Sector Unprotect:  
Write 60h to sector  
address with A6=1,  
A1=1, A0=0  
Wait 150 us  
Verify Sector  
Protect: Write 40h  
to sector address  
with A6=0, A1=1,  
A0=0  
Reset  
PLSCNT=1  
Increment  
PLSCNT  
Wait 500 ms  
Verify Sector  
Unprotect : Write  
40h to sector  
address with A6=1,  
A1=1, A0=0  
Read from  
sector address  
with A6=0,  
Increment  
PLSCNT  
A1=1, A0=0  
No  
Read from sector  
address with A6=1,  
A1=1, A0=0  
No  
PLSCNT  
=25?  
Data=01h?  
Yes  
No  
Set up  
next sector  
address  
Yes  
No  
PLSCNT=  
1000?  
Yes  
Data=00h?  
Yes  
Protect another  
sector?  
Device failed  
Yes  
No  
Remove VID  
from RESET  
No  
Last sector  
verified?  
Device failed  
Write reset  
command  
Yes  
Remove VID  
from RESET  
Sector Protect  
complete  
Sector Protect  
Algorithm  
Sector Unprotect  
Algorithm  
Write reset  
Command  
Sector Unprotect  
complete  
Figure 2. In-System Sector Protect/Unprotect Algorithms  
PRELIMINARY (July, 2005, Version 0.0)  
10  
AMIC Technology, Corp.  
A29L400A Series  
Command Definitions  
Autoselect Command Sequence  
Writing specific address and data commands or sequences  
into the command register initiates device operations. The  
Command Definitions table defines the valid register  
command sequences. Writing incorrect address and data  
values or writing them in the improper sequence resets the  
device to reading array data.  
The autoselect command sequence allows the host system  
to access the manufacturer and devices codes, and  
determine whether or not a sector is protected. The  
Command Definitions table shows the address and data  
requirements. This method is an alternative to that shown in  
the Autoselect Codes (High Voltage Method) table, which is  
intended for PROM programmers and requires VID on  
address bit A9.  
The autoselect command sequence is initiated by writing two  
unlock cycles, followed by the autoselect command. The  
device then enters the autoselect mode, and the system may  
read at any address any number of times, without initiating  
another command sequence.  
A read cycle at address XX00h retrieves the manufacturer  
code and another read cycle at XX03h retrieves the  
continuation code. A read cycle at address XX01h returns the  
device code. A read cycle containing a sector address (SA)  
and the address 02h in returns 01h if that sector is protected,  
or 00h if it is unprotected. Refer to the Sector Address tables  
for valid sector addresses.  
All addresses are latched on the falling edge of  
or  
,
CE  
WE  
whichever happens later. All data is latched on the rising  
edge of or , whichever happens first. Refer to the  
WE  
CE  
appropriate timing diagrams in the "AC Characteristics"  
section.  
Reading Array Data  
The device is automatically set to reading array data after  
device power-up. No commands are required to retrieve  
data. The device is also ready to read array data after  
completing an Embedded Program or Embedded Erase  
algorithm. After the device accepts an Erase Suspend  
command, the device enters the Erase Suspend mode. The  
system can read array data using the standard read timings,  
except that if it reads at an address within erase-suspended  
sectors, the device outputs status data. After completing a  
programming operation in the Erase Suspend mode, the  
system may once again read array data with the same  
exception. See "Erase Suspend/Erase Resume Commands"  
for more information on this mode.  
The system must write the reset command to exit the  
autoselect mode and return to reading array data.  
Word/Byte Program Command Sequence  
The system may program the device by word or byte,  
depending on the state of the  
pin. Programming is a  
BYTE  
four-bus-cycle operation. The program command sequence  
is initiated by writing two unlock write cycles, followed by the  
program set-up command. The program address and data  
are written next, which in turn initiate the Embedded Program  
algorithm. The system is not required to provide further  
controls or timings. The device automatically provides  
internally generated program pulses and verify the  
programmed cell margin. Table 5 shows the address and  
data requirements for the byte program command sequence.  
When the Embedded Program algorithm is complete, the  
device then returns to reading array data and addresses are  
longer latched. The system can determine the status of the  
The system must issue the reset command to re-enable the  
device for reading array data if I/O5 goes high, or while in the  
autoselect mode. See the "Reset Command" section, next.  
See also "Requirements for Reading Array Data" in the  
"Device Bus Operations" section for more information. The  
Read Operations table provides the read parameters, and  
Read Operation Timings diagram shows the timing diagram.  
Reset Command  
Writing the reset command to the device resets the device to  
reading array data. Address bits are don't care for this  
command. The reset command may be written between the  
sequence cycles in an erase command sequence before  
erasing begins. This resets the device to reading array data.  
Once erasure begins, however, the device ignores reset  
commands until the operation is complete.  
program operation by using I/O7, I/O6, or RY/  
. See “Write  
BY  
Operation Status” for information on these status bits.  
Any commands written to the device during the Embedded  
Program Algorithm are ignored. Note that a hardware reset  
immediately terminates the programming operation. The Byte  
Program command sequence should be reinitiated once the  
device has reset to reading array data, to ensure data  
integrity.  
Programming is allowed in any sequence and across sector  
boundaries. A bit cannot be programmed from a “0” back to a  
“1”. Attempting to do so may halt the operation and set I/O5  
The reset command may be written between the sequence  
cycles in  
a
program command sequence before  
programming begins. This resets the device to reading array  
data (also applies to programming in Erase Suspend mode).  
Once programming begins, however, the device ignores  
reset commands until the operation is complete.  
The reset command may be written between the sequence  
cycles in an autoselect command sequence. Once in the  
autoselect mode, the reset command must be written to  
return to reading array data (also applies to autoselect during  
Erase Suspend).  
to “1”, or cause the  
Polling algorithm to indicate the  
Data  
operation was successful. However, a succeeding read will  
show that the data is still “0”. Only erase operations can  
convert a “0” to a “1”.  
If I/O5 goes high during a program or erase operation, writing  
the reset command returns the device to reading array data  
(also applies during Erase Suspend).  
PRELIMINARY  
(July, 2005, Version 0.0)  
11  
AMIC Technology, Corp.  
A29L400A Series  
cycle must contain the data 90h; the second cycle the data  
00h. Addresses are don’t care for both cycle. The device  
returns to reading array data.  
START  
Figure 3 illustrates the algorithm for the program operation.  
See the Erase/Program Operations in “AC Characteristics” for  
parameters, and to Program Operation Timings for timing  
diagrams.  
Write Program  
Command  
Sequence  
Chip Erase Command Sequence  
Chip erase is a six-bus-cycle operation. The chip erase  
command sequence is initiated by writing two unlock cycles,  
followed by a set-up command. Two additional unlock write  
cycles are then followed by the chip erase command, which  
in turn invokes the Embedded Erase algorithm. The device  
does not require the system to preprogram prior to erase. The  
Embedded Erase algorithm automatically preprograms and  
verifies the entire memory for an all zero data pattern prior to  
electrical erase. The system is not required to provide any  
controls or timings during these operations. The Command  
Definitions table shows the address and data requirements  
for the chip erase command sequence.  
Any commands written to the chip during the Embedded  
Erase algorithm are ignored. The system can determine the  
status of the erase operation by using I/O7, I/O6, or I/O2. See  
"Write Operation Status" for information on these status bits.  
When the Embedded Erase algorithm is complete, the device  
returns to reading array data and addresses are no longer  
latched.  
Data Poll  
from System  
Embedded  
Program  
algorithm in  
progress  
Verify Data ?  
Yes  
No  
Increment Address  
Last Address ?  
Yes  
Figure 4 illustrates the algorithm for the erase operation. See  
the Erase/Program Operations tables in "AC Characteristics"  
for parameters, and to the Chip/Sector Erase Operation  
Timings for timing waveforms.  
Programming  
Completed  
Sector Erase Command Sequence  
Sector erase is a six-bus-cycle operation. The sector erase  
command sequence is initiated by writing two unlock cycles,  
followed by a set-up command. Two additional unlock write  
cycles are then followed by the address of the sector to be  
erased, and the sector erase command. The Command  
Definitions table shows the address and data requirements  
for the sector erase command sequence.  
Note : See the appropriate Command Definitions table for  
program command sequence.  
Figure 3. Program Operation  
The device does not require the system to preprogram the  
memory prior to erase. The Embedded Erase algorithm  
automatically programs and verifies the sector for an all zero  
data pattern prior to electrical erase. The system is not  
required to provide any controls or timings during these  
operations.  
Unlock Bypass Command Sequence  
The unlock bypass feature allows the system to program  
bytes or words to the device faster than using the standard  
program command sequence. The unlock bypass command  
sequence is initiated by first writing two unlock cycles. This is  
followed by a third write cycle containing the unlock bypass  
command, 20h. The device then enters the unlock bypass  
After the command sequence is written, a sector erase time-  
out of 50µs begins. During the time-out period, additional  
sector addresses and sector erase commands may be  
written. Loading the sector erase buffer may be done in any  
sequence, and the number of sectors may be from one sector  
to all sectors. The time between these additional cycles must  
be less than 50µs, otherwise the last address and command  
might not be accepted, and erasure may begin. It is  
recommended that processor interrupts be disabled during  
this time to ensure all commands are accepted. The  
interrupts can be re-enabled after the last Sector Erase  
command is written. If the time between additional sector  
erase commands can be assumed to be less than 50µs, the  
system need not monitor I/O3. Any command other than  
Sector Erase or Erase Suspend during the time-out period  
resets the device to reading array data. The system must  
mode.  
A two-cycle unlock bypass program command  
sequence is all that is required to program in this mode. The  
first cycle in this sequence contains the unlock bypass  
program command, A0h; the second cycle contains the  
program address and data. Additional data is programmed in  
the same manner. This mode dispenses with the initial two  
unlock cycles required in the standard program command  
sequence, resulting in faster total programming time. Table 5  
shows the requirements for the command sequence.  
During the unlock bypass mode, only the Unlock Bypass  
Program and Unlock Bypass Reset commands are valid. To  
exit the unlock bypass mode, the system must issue the two-  
cycle unlock bypass reset command sequence. The first  
PRELIMINARY  
(July, 2005, Version 0.0)  
12  
AMIC Technology, Corp.  
A29L400A Series  
rewrite the command sequence and any additional sector  
addresses and commands.  
The system can monitor I/O3 to determine if the sector erase  
timer has timed out. (See the " I/O3: Sector Erase Timer"  
section.) The time-out begins from the rising edge of the final  
After an erase-suspended program operation is complete,  
the system can once again read array data within non-  
suspended sectors. The system can determine the status of  
the program operation using the I/O7 or I/O6 status bits, just  
as in the standard program operation. See "Write Operation  
Status" for more information.  
pulse in the command sequence.  
WE  
The system may also write the autoselect command  
sequence when the device is in the Erase Suspend mode.  
The device allows reading autoselect codes even at  
addresses within erasing sectors, since the codes are not  
stored in the memory array. When the device exits the  
autoselect mode, the device reverts to the Erase Suspend  
mode, and is ready for another valid operation. See  
"Autoselect Command Sequence" for more information.  
The system must write the Erase Resume command  
(address bits are "don't care") to exit the erase suspend  
mode and continue the sector erase operation. Further writes  
of the Resume command are ignored. Another Erase  
Suspend command can be written after the device has  
resumed erasing.  
Once the sector erase operation has begun, only the Erase  
Suspend command is valid. All other commands are ignored.  
When the Embedded Erase algorithm is complete, the device  
returns to reading array data and addresses are no longer  
latched. The system can determine the status of the erase  
operation by using I/O7, I/O6, or I/O2. Refer to "Write  
Operation Status" for information on these status bits.  
4 illustrates the algorithm for the erase operation. Refer to  
the Erase/Program Operations tables in the "AC  
Characteristics" section for parameters, and to the Sector  
Erase Operations Timing diagram for timing waveforms.  
Erase Suspend/Erase Resume Commands  
The Erase Suspend command allows the system to interrupt  
a sector erase operation and then read data from, or  
program data to, any sector not selected for erasure. This  
command is valid only during the sector erase operation,  
including the 50µs time-out period during the sector erase  
command sequence. The Erase Suspend command is  
ignored if written during the chip erase operation or  
Embedded Program algorithm. Writing the Erase Suspend  
command during the Sector Erase time-out immediately  
terminates the time-out period and suspends the erase  
operation. Addresses are "don't cares" when writing the  
Erase Suspend command.  
START  
Write Erase  
Command  
Sequence  
When the Erase Suspend command is written during a  
sector erase operation, the device requires a maximum of  
20µs to suspend the erase operation. However, when the  
Erase Suspend command is written during the sector erase  
time-out, the device immediately terminates the time-out  
period and suspends the erase operation.  
Data Poll  
from System  
Embedded  
Erase  
algorithm in  
progress  
After the erase operation has been suspended, the system  
can read array data from or program data to any sector not  
selected for erasure. (The device "erase suspends" all  
sectors selected for erasure.) Normal read and write timings  
and command definitions apply. Reading at any address  
within erase-suspended sectors produces status data on I/O7  
- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to  
determine if a sector is actively erasing or is erase-  
suspended. See "Write Operation Status" for information on  
these status bits.  
No  
Data = FFh ?  
Yes  
Erasure Completed  
Note :  
1. See the appropriate Command Definitions table for erase  
command sequences.  
2. See "I/O  
3
: Sector Erase Timer" for more information.  
Figure 4. Erase Operation  
PRELIMINARY  
(July, 2005, Version 0.0)  
13  
AMIC Technology, Corp.  
A29L400A Series  
Table 5. A29L400A Command Definitions  
Bus Cycles (Notes 2 - 5)  
Command  
Sequence  
(Note 1)  
First  
Second  
Third  
Fourth  
Fifth  
Sixth  
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data  
Read (Note 6)  
Reset (Note 7)  
1
1
RA  
XXX  
555  
AAA  
555  
RD  
F0  
Word  
Byte  
Word  
Byte  
2AA  
555  
2AA  
555  
AAA  
555  
Manufacturer ID  
4
4
AA  
55  
55  
90  
X00  
37  
B334  
34  
X01  
X02  
X01  
X02  
X03  
Device ID,  
Top Boot Block  
AA  
AA  
90  
90  
AAA  
555  
555  
2AA  
555  
AAA  
555  
Word  
Byte  
B3B5  
B5  
Device ID,  
Bottom Boot Block  
55  
4
4
AAA  
AAA  
Word  
Byte  
555  
AAA  
555  
2AA  
555  
2AA  
555  
AAA  
555  
Continuation ID  
AA  
AA  
55  
55  
90  
7F  
X06  
XX00  
(SA)  
X02  
Word  
Sector Protect Verify  
(Note 9)  
XX01  
00  
4
90  
(SA)  
X04  
Byte  
AAA  
555  
555  
AAA  
555  
01  
Word  
Byte  
2AA  
Program  
Unlock Bypass  
4
3
AA  
AA  
55  
55  
A0  
20  
PA  
PD  
AAA  
555  
AAA  
555  
2AA  
555  
PA  
AAA  
555  
AAA  
Word  
Byte  
Unlock Bypass Program (Note 10)  
Unlock Bypass Reset (Note 11)  
Word  
2
2
XXX A0  
XXX 90  
PD  
00  
XXX  
2AA  
555  
555  
AA  
555  
AAA  
555  
555  
AAA  
555  
2AA  
555  
2AA  
555  
555  
Chip Erase  
6
6
55  
55  
80  
80  
AA  
AA  
55  
55  
10  
30  
Byte  
AAA  
AAA  
Word  
555  
2AA  
555  
Sector Erase  
AA  
SA  
Byte  
AAA  
AAA  
AAA  
Erase Suspend (Note 12)  
Erase Resume (Note 13)  
1
1
XXX  
XXX  
B0  
30  
Legend:  
X = Don't care  
RA = Address of the memory location to be read.  
RD = Data read from location RA during read operation.  
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the  
whichever happens later.  
or  
pulse,  
WE  
CE  
PD = Data to be programmed at location PA. Data latches on the rising edge of  
or  
pulse, whichever happens first.  
CE  
WE  
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17 - A12 select a unique sector.  
Note:  
1. See Table 1 for description of bus operations.  
2. All values are in hexadecimal.  
3. Except when reading array or autoselect data, all bus cycles are write operation.  
4. Data bits I/O15~I/O8 are don’t care for unlock and command cycles.  
5. Address bits A17 - A11 are don't cares for unlock and command cycles, unless SA or PA required.  
6. No unlock or command cycles required when reading array data.  
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high  
(while the device is providing status data).  
8. The fourth cycle of the autoselect command sequence is a read cycle.  
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.  
10. The Unlock Bypass command is required prior to the Unlock Bypass Program command.  
11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.  
12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.  
13. The Erase Resume command is valid only during the Erase Suspend mode.  
PRELIMINARY  
(July, 2005, Version 0.0)  
14  
AMIC Technology, Corp.  
A29L400A Series  
Write Operation Status  
START  
Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/  
are provided in  
BY  
the A29L400A to determine the status of a write operation.  
Table 6 and the following subsections describe the functions  
of these status bits. I/O7, I/O6 and RY/  
each offer a  
BY  
method for determining whether  
a program or erase  
Read I/O  
Address = VA  
7-I/O0  
operation is complete or in progress. These three bits are  
discussed first.  
I/O7:  
Polling  
Data  
The  
Polling bit, I/O7, indicates to the host system  
Data  
Yes  
whether an Embedded Algorithm is in progress or completed,  
I/O  
7
= Data ?  
No  
or whether the device is in Erase Suspend. Polling is  
Data  
pulse in the  
valid after the rising edge of the final  
program or erase command sequence.  
WE  
During the Embedded Program algorithm, the device outputs  
on I/O7 the complement of the datum programmed to I/O7.  
This I/O7 status also applies to programming during Erase  
Suspend. When the Embedded Program algorithm is  
complete, the device outputs the datum programmed to I/O7.  
The system must provide the program address to read valid  
status information on I/O7. If a program address falls within a  
No  
I/O5 = 1?  
Yes  
protected sector,  
Polling on I/O7 is active for  
Data  
approximately 2µs, then the device returns to reading array  
Read I/O  
Address = VA  
7
- I/O0  
data.  
During the Embedded Erase algorithm,  
Polling  
Data  
produces a "0" on I/O7. When the Embedded Erase algorithm  
is complete, or if the device enters the Erase Suspend mode,  
Polling produces a "1" on I/O7.This is analogous to the  
Data  
complement/true datum output described for the Embedded  
Program algorithm: the erase function changes all the bits in  
a sector to "1"; prior to this, the device outputs the  
"complement," or "0." The system must provide an address  
within any of the sectors selected for erasure to read valid  
status information on I/O7.  
Yes  
I/O7  
= Data ?  
No  
After an erase command sequence is written, if all sectors  
selected for erasing are protected,  
Polling on I/O7 is  
Data  
active for approximately 100µs, then the device returns to  
reading array data. If not all selected sectors are protected,  
the Embedded Erase algorithm erases the unprotected  
sectors, and ignores the selected sectors that are protected.  
When the system detects I/O7 has changed from the  
complement to true data, it can read valid data at I/O7 - I/O0  
on the following read cycles. This is because I/O7 may  
change asynchronously with I/O0 - I/O6 while Output Enable  
FAIL  
PASS  
Note :  
1. VA = Valid address for programming. During a sector  
erase operation, a valid address is an address within any  
sector selected for erasure. During chip erase, a valid  
address is any non-protected sector address.  
(
) is asserted low. The  
Polling Timings (During  
Data  
OE  
Embedded Algorithms) in the "AC Characteristics" section  
illustrates this. Table 6 shows the outputs for Polling  
2. I/O  
7
should be rechecked even if I/O  
may change simultaneously with I/O  
5 = "1" because  
I/O7  
5
.
Data  
Polling algorithm.  
on I/O7. Figure 5 shows the  
Data  
Figure 5. Data Polling Algorithm  
PRELIMINARY (July, 2005, Version 0.0)  
15  
AMIC Technology, Corp.  
A29L400A Series  
RY/  
: Read/  
Busy  
BY  
I/O2: Toggle Bit II  
The RY/  
is a dedicated, open-drain output pin that  
BY  
The "Toggle Bit II" on I/O2, when used with I/O6, indicates  
whether a particular sector is actively erasing (that is, the  
Embedded Erase algorithm is in progress), or whether that  
sector is erase-suspended. Toggle Bit II is valid after the  
indicates whether an Embedded algorithm is in progress or  
complete. The RY/ status is valid after the rising edge of  
BY  
pulse in the command sequence. Since  
the final  
WE  
rising edge of the final  
sequence.  
I/O2 toggles when the system reads at addresses within  
those sectors that have been selected for erasure. (The  
pulse in the command  
WE  
RY/  
is an open-drain output, several RY/  
pins can be  
BY  
BY  
tied together in parallel with a pull-up resistor to VCC. (The  
RY/ pin is not available on the 44-pin SOP package)  
BY  
If the output is low (Busy), the device is actively erasing or  
programming. (This includes programming in the Erase  
Suspend mode.) If the output is high (Ready), the device is  
ready to read array data (including during the Erase Suspend  
mode), or is in the standby mode.  
system may use either  
or  
to control the read  
CE  
OE  
cycles.) But I/O2 cannot distinguish whether the sector is  
actively erasing or is erase-suspended. I/O6, by comparison,  
indicates whether the device is actively erasing, or is in  
Erase Suspend, but cannot distinguish which sectors are  
selected for erasure. Thus, both status bits are required for  
sector and mode information. Refer to Table 6 to compare  
outputs for I/O2 and I/O6.  
Table 6 shows the outputs for RY/  
. Refer to “  
RESET  
BY  
Timings”, “Timing Waveforms for Program Operation” and  
“Timing Waveforms for Chip/Sector Erase Operation” for  
more information.  
Figure 6 shows the toggle bit algorithm in flowchart form,  
and the section " I/O2: Toggle Bit II" explains the algorithm.  
See also the " I/O6: Toggle Bit I" subsection. Refer to the  
Toggle Bit Timings figure for the toggle bit timing diagram.  
The I/O2 vs. I/O6 figure shows the differences between I/O2  
and I/O6 in graphical form.  
I/O6: Toggle Bit I  
Toggle Bit I on I/O6 indicates whether an Embedded Program  
or Erase algorithm is in progress or complete, or whether the  
device has entered the Erase Suspend mode. Toggle Bit I  
may be read at any address, and is valid after the rising edge  
Reading Toggle Bits I/O6, I/O2  
of the final  
pulse in the command sequence (prior to the  
WE  
program or erase operation), and during the sector erase  
time-out.  
During an Embedded Program or Erase algorithm operation,  
successive read cycles to any address cause I/O6 to toggle.  
Refer to Figure 6 for the following discussion. Whenever the  
system initially begins reading toggle bit status, it must read  
I/O7 - I/O0 at least twice in a row to determine whether a  
toggle bit is toggling. Typically, a system would note and  
store the value of the toggle bit after the first read. After the  
second read, the system would compare the new value of  
the toggle bit with the first. If the toggle bit is not toggling,  
the device has completed the program or erase operation.  
The system can read array data on I/O7 - I/O0 on the  
following read cycle.  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the system  
also should note whether the value of I/O5 is high (see the  
section on I/O5). If it is, the system should then determine  
again whether the toggle bit is toggling, since the toggle bit  
may have stopped toggling just as I/O5 went high. If the  
toggle bit is no longer toggling, the device has successfully  
completed the program or erase operation. If it is still  
toggling, the device did not complete the operation  
successfully, and the system must write the reset command  
to return to reading array data.  
(The system may use either  
or  
to control the read  
CE  
OE  
cycles.) When the operation is complete, I/O6 stops toggling.  
After an erase command sequence is written, if all sectors  
selected for erasing are protected, I/O6 toggles for  
approximately 100µs, then returns to reading array data. If  
not all selected sectors are protected, the Embedded Erase  
algorithm erases the unprotected sectors, and ignores the  
selected sectors that are protected.  
The system can use I/O6 and I/O2 together to determine  
whether a sector is actively erasing or is erase-suspended.  
When the device is actively erasing (that is, the Embedded  
Erase algorithm is in progress), I/O6 toggles. When the  
device enters the Erase Suspend mode, I/O6 stops toggling.  
However, the system must also use I/O2 to determine which  
sectors are erasing or erase-suspended. Alternatively, the  
system can use I/O7 (see the subsection on " I/O7 :  
Data  
Polling").  
The remaining scenario is that the system initially  
determines that the toggle bit is toggling and I/O5 has not  
gone high. The system may continue to monitor the toggle  
bit and I/O5 through successive read cycles, determining the  
status as described in the previous paragraph. Alternatively,  
it may choose to perform other system tasks. In this case,  
the system must start at the beginning of the algorithm when  
it returns to determine the status of the operation (top of  
Figure 6).  
If a program address falls within a protected sector, I/O6  
toggles for approximately 2µs after the program command  
sequence is written, then returns to reading array data.  
I/O6 also toggles during the erase-suspend-program mode,  
and stops toggling once the Embedded Program algorithm is  
complete.  
The Write Operation Status table shows the outputs for  
Toggle Bit I on I/O6. Refer to Figure 6 for the toggle bit  
algorithm, and to the Toggle Bit Timings figure in the "AC  
Characteristics" section for the timing diagram. The I/O2 vs.  
I/O6 figure shows the differences between I/O2 and I/O6 in  
graphical form. See also the subsection on " I/O2: Toggle Bit  
II".  
PRELIMINARY (July, 2005, Version 0.0)  
16  
AMIC Technology, Corp.  
A29L400A Series  
I/O5: Exceeded Timing Limits  
START  
I/O5 indicates whether the program or erase time has  
exceeded a specified internal pulse count limit. Under these  
conditions I/O5 produces a "1." This is a failure condition that  
indicates the program or erase cycle was not successfully  
completed.  
The I/O5 failure condition may appear if the system tries to  
program a "1 "to a location that is previously programmed to  
"0." Only an erase operation can change a "0" back to a "1."  
Under this condition, the device halts the operation, and  
when the operation has exceeded the timing limits, I/O5  
produces a "1."  
Read I/O  
7
-I/O  
0
Read I/O7-I/O  
0
(Note 1)  
No  
Under both these conditions, the system must issue the  
reset command to return the device to reading array data.  
I/O3: Sector Erase Timer  
Toggle Bit  
= Toggle ?  
After writing a sector erase command sequence, the system  
may read I/O3 to determine whether or not an erase  
operation has begun. (The sector erase timer does not apply  
to the chip erase command.) If additional sectors are  
selected for erasure, the entire time-out also applies after  
each additional sector erase command. When the time-out  
is complete, I/O3 switches from "0" to "1." The system may  
ignore I/O3 if the system can guarantee that the time  
between additional sector erase commands will always be  
less than 50µs. See also the "Sector Erase Command  
Sequence" section.  
Yes  
No  
I/O5 = 1?  
Yes  
- I/O  
Read I/O  
7
0
After the sector erase command sequence is written, the  
(Notes 1,2)  
Twice  
system should read the status on I/O7 (  
Polling) or I/O6  
Data  
(Toggle Bit I) to ensure the device has accepted the  
command sequence, and then read I/O3. If I/O3 is "1", the  
internally controlled erase cycle has begun; all further  
commands (other than Erase Suspend) are ignored until the  
erase operation is complete. If I/O3 is "0", the device will  
accept additional sector erase commands. To ensure the  
command has been accepted, the system software should  
check the status of I/O3 prior to and following each  
subsequent sector erase command. If I/O3 is high on the  
second status check, the last command might not have been  
accepted. Table 6 shows the outputs for I/O3.  
No  
Toggle Bit  
= Toggle ?  
Yes  
Program/Erase  
Operation Not  
Commplete, Write  
Reset Command  
Program/Erase  
Operation Complete  
Notes :  
1. Read toggle bit twice to determine whether or not it is  
toggling. See text.  
2. Recheck toggle bit because it may stop toggling as I/O  
5
changes to "1". See text.  
Figure 6. Toggle Bit Algorithm  
PRELIMINARY  
(July, 2005, Version 0.0)  
17  
AMIC Technology, Corp.  
A29L400A Series  
Table 6. Write Operation Status  
I/O7  
I/O6  
I/O5  
(Note 2)  
0
I/O3  
I/O2  
RY/  
BY  
Operation  
(Note 1)  
(Note 1)  
Standard  
Mode  
Embedded Program Algorithm  
Embedded Erase Algorithm  
Toggle  
Toggle  
N/A  
1
No toggle  
0
I/O7  
0
0
0
Toggle  
Toggle  
0
1
Erase  
Reading within Erase  
Suspended Sector  
1
No toggle  
N/A  
Suspend  
Mode  
Reading within Non-Erase  
Suspended Sector  
Data  
I/O7  
Data  
Data  
0
Data  
N/A  
Data  
N/A  
1
0
Erase-Suspend-Program  
Toggle  
Notes:  
1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.  
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.  
See “I/O5: Exceeded Timing Limits” for more information.  
Maximum Negative Input Overshoot  
20ns  
20ns  
+0.8V  
-0.5V  
-2.0V  
20ns  
Maximum Positive Input Overshoot  
20ns  
VCC+2.0V  
VCC+0.5V  
2.0V  
20ns  
20ns  
PRELIMINARY  
(July, 2005, Version 0.0)  
18  
AMIC Technology, Corp.  
A29L400A Series  
DC Characteristics  
CMOS Compatible (TA=0°C to 70°C or -40°C to +85°C)  
Parameter  
Symbol  
ILI  
Parameter Description  
Test Description  
Min.  
Typ.  
Max.  
Unit  
Input Load Current  
VIN = VSS to VCC. VCC = VCC Max  
VCC = VCC Max, A9 =12.5V  
±1.0  
35  
µA  
µA  
µA  
mA  
ILIT  
ILO  
A9 Input Load Current  
Output Leakage Current  
VOUT = VSS to VCC. VCC = VCC Max  
±1.0  
10  
ICC1  
VCC Active Read Current  
(Notes 1, 2)  
5 MHz  
1 MHz  
4
2
= VIL,  
= VIH  
CE  
OE  
OE  
Byte Mode  
4
5 MHz  
1 MHz  
4
2
10  
4
= VIL,  
= VIH  
=VIH  
CE  
Word Mode  
ICC2  
VCC Active Write (Program/Erase)  
Current (Notes 2, 3, 4)  
20  
30  
mA  
= VIL,  
= VIH,  
CE  
OE  
ICC3  
ICC4  
VCC Standby Current (Note 2)  
0.2  
0.2  
5
5
µA  
µA  
= VCC ± 0.3V  
CE  
RESET  
VCC Standby Current During Reset  
(Note 2)  
= VSS ± 0.3V  
RESET  
ICC5  
Automatic Sleep Mode  
(Note 2, 4, 5)  
0.2  
5
VIH = VCC ± 0.3V; VIL = VSS ± 0.3V  
µA  
VIL  
VIH  
VID  
Input Low Level  
-0.5  
0.7 x VCC  
11.5  
0.8  
VCC + 0.3  
12.5  
V
V
V
Input High Level  
Voltage for Autoselect and  
Temporary Unprotect Sector  
Output Low Voltage  
Output High Voltage  
VCC = 3.3 V  
VOL  
VOH1  
VOH2  
IOL = 4.0mA, VCC = VCC Min  
IOH = -2.0 mA, VCC = VCC Min  
IOH = -100 µA, VCC = VCC Min  
0.45  
V
V
V
0.85 x VCC  
VCC - 0.4  
Notes:  
1. The ICC current listed is typically less than 2 mA/MHz, with  
at VIH. Typical VCC is 3.0V.  
OE  
2. Maximum ICC specifications are tested with VCC = VCC max.  
3. ICC active while Embedded Algorithm (program or erase) is in progress.  
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode current  
is 200nA.  
5. Not 100% tested.  
PRELIMINARY  
(July, 2005, Version 0.0)  
19  
AMIC Technology, Corp.  
A29L400A Series  
DC Characteristics (continued)  
Zero Power Flash  
25  
20  
15  
10  
5
0
0
500  
1000  
1500  
2000  
2500  
3000  
3500  
4000  
Time in ns  
Note: Addresses are switching at 1MHz  
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)  
10  
8
3.6V  
2.7V  
6
4
2
0
1
2
3
4
5
Frequency in MHz  
Note : T = 25°C  
Typical ICC1 vs. Frequency  
PRELIMINARY  
(July, 2005, Version 0.0)  
20  
AMIC Technology, Corp.  
A29L400A Series  
AC Characteristics  
Read Only Operations (TA=0°C to 70°C or -40°C to +85°C)  
Parameter Symbols  
Description  
Test Setup  
Speed  
Unit  
JEDEC  
Std  
-70  
-90  
Read Cycle Time (Note 1)  
Address to Output Delay  
tAVAV  
tRC  
Min.  
70  
90  
ns  
= VIL  
tAVQV  
tACC  
CE  
Max.  
70  
90  
ns  
= VIL  
OE  
Chip Enable to Output Delay  
Output Enable to Output Delay  
tELQV  
tGLQV  
tCE  
Max.  
Max.  
Min.  
70  
30  
0
90  
35  
0
ns  
ns  
ns  
= VIL  
OE  
tOE  
Read  
Output Enable Hold  
tOEH  
Toggle and  
Polling  
Time (Note 1)  
ns  
Min.  
10  
25  
10  
30  
Data  
Chip Enable to Output High Z  
(Notes 1)  
tEHQZ  
tGHQZ  
tDF  
tDF  
Max.  
ns  
ns  
Output Enable to Output High Z  
(Notes 1)  
25  
0
30  
0
Output Hold Time from Addresses,  
tAXQX  
tOH  
Min.  
ns  
or  
, Whichever Occurs First  
CE OE  
(Note 1)  
Notes:  
1. Not 100% tested.  
2. See Test Conditions and Test Setup for test specifications.  
Timing Waveforms for Read Only Operation  
t
RC  
Addresses  
CE  
Addresses Stable  
t
ACC  
t
DF  
t
OE  
OE  
t
OEH  
WE  
t
CE  
t
OH  
High-Z  
High-Z  
Output  
Output Valid  
RESET  
RY/BY  
0V  
PRELIMINARY (July, 2005, Version 0.0)  
21  
AMIC Technology, Corp.  
A29L400A Series  
AC Characteristics  
Hardware Reset (  
Parameter  
) (TA=0°C to 70°C or -40°C to +85°C)  
RESET  
Description  
Test Setup  
All Speed Options  
Unit  
JEDEC  
Std  
Pin Low (During Embedded  
Algorithms) to Read or Write (See Note)  
RESET  
tREADY  
Max  
20  
µs  
Pin Low (Not During Embedded  
RESET  
Algorithms) to Read or Write (See Note)  
tREADY  
Max  
500  
ns  
tRP  
tRH  
Min  
Min  
Min  
Min  
500  
50  
0
ns  
ns  
ns  
µs  
Pulse Width  
RESET  
RESET  
High Time Before Read (See Note)  
Recovery Time  
tRB  
RY/  
BY  
tRPD  
20  
Low to Standby Mode  
RESET  
Note: Not 100% tested.  
Timings  
RESET  
RY/BY  
CE, OE  
RESET  
t
RH  
t
RP  
tReady  
Reset Timings NOT during Embedded Algorithms  
Reset Timings during Embedded Algorithms  
t
Ready  
RY/BY  
tRB  
CE, OE  
RESET  
t
RP  
PRELIMINARY  
(July, 2005, Version 0.0)  
22  
AMIC Technology, Corp.  
A29L400A Series  
Temporary Sector Unprotect (TA=0°C to 70°C or –40°C to +85°C)  
Parameter  
Description  
All Speed Options  
Unit  
JEDEC  
Std  
tVIDR  
VID Rise and Fall Time (See Note)  
Min  
Min  
500  
4
ns  
Setup Time for Temporary Sector  
RESET  
tRSP  
µs  
Unprotect  
Note: Not 100% tested.  
Temporary Sector Unprotect Timing Diagram  
12V  
0 or 3V  
RESET  
0 or 3V  
t
VIDR  
tVIDR  
Program or Erase Command Sequence  
CE  
WE  
t
RSP  
RY/BY  
PRELIMINARY  
(July, 2005, Version 0.0)  
23  
AMIC Technology, Corp.  
A29L400A Series  
AC Characteristics  
Word/Byte Configuration (  
Parameter  
) (TA=0°C to 70°C or -40°C to +85°C)  
BYTE  
Description  
All Speed Options  
Unit  
JEDEC  
Std  
-70  
-90  
tELFL/tELFH  
Max  
5
ns  
to  
Switching Low or High  
BYTE  
CE  
Switching Low to Output High-Z  
Switching High to Output Active  
BYTE  
BYTE  
tFLQZ  
tHQV  
Max  
Min  
25  
70  
30  
90  
ns  
ns  
Timings for Read Operations  
BYTE  
CE  
OE  
BYTE  
t
ELFL  
Data Output  
(I/O -I/O14  
Data Output  
(I/O0-I/O7)  
BYTE  
Switching  
I/O -I/O14  
0
0
)
from word to  
byte mode  
I/O15  
Output  
Address Input  
I/O15 (A-1)  
t
FLQZ  
t
ELFH  
BYTE  
Data Output  
(I/O -I/O  
Data Output  
(I/O -I/O14  
I/O -I/O14  
0
0
7
)
0
)
BYTE  
Switching  
from byte to  
word mode  
I/O15  
Output  
Address Input  
I/O15 (A-1)  
t
FHQV  
Timings for Write Operations  
BYTE  
CE  
The falling edge of the last WE signal  
WE  
BYTE  
t
SET  
(tAS  
)
t
HOLD(tAH)  
Note:  
Refer to the Erase/Program Operations table for tAS and tAH specifications.  
PRELIMINARY  
(July, 2005, Version 0.0)  
24  
AMIC Technology, Corp.  
A29L400A Series  
AC Characteristics  
Erase and Program Operations (TA=0°C to 70°C or -40°C to +85°C)  
Parameter  
Description  
Speed  
Unit  
JEDEC  
Std  
tWC  
tAS  
-70  
-90  
tAVAV  
tAVWL  
tWLAX  
tDVWH  
tWHDX  
Write Cycle Time (Note 1)  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
70  
90  
ns  
ns  
ns  
ns  
ns  
ns  
Address Setup Time  
Address Hold Time  
0
tAH  
45  
35  
45  
45  
Data Setup Time  
tDS  
Data Hold Time  
tDH  
0
0
Output Enable Setup Time  
Read Recover Time Before Write  
tOES  
tGHWL  
tGHWL  
Min.  
0
ns  
(
high to  
low)  
WE  
OE  
tELWL  
tWHEH  
tWLWH  
tWHWL  
tCS  
tCH  
Min.  
Min.  
Min.  
Min.  
0
0
ns  
ns  
ns  
ns  
Setup Time  
Hold Time  
CE  
CE  
Write Pulse Width  
tWP  
tWPH  
35  
35  
Write Pulse Width High  
30  
5
Byte  
Typ.  
Typ.  
Byte Programming Operation  
(Note 2)  
tWHWH1  
tWHWH2  
tWHWH1  
µs  
Word  
7
tWHWH2  
tvcs  
Sector Erase Operation (Note 2)  
VCC Set Up Time (Note 1)  
Typ.  
Min.  
Min  
Min  
1.0  
50  
0
sec  
µs  
ns  
ns  
tRB  
Recovery Time from RY/  
BY  
tBUSY  
90  
Program/Erase Valid to RY/  
Delay  
BY  
Notes:  
1. Not 100% tested.  
2. See the "Erase and Programming Performance" section for more information.  
PRELIMINARY  
(July, 2005, Version 0.0)  
25  
AMIC Technology, Corp.  
A29L400A Series  
Timing Waveforms for Program Operation  
Program Command Sequence (last two cycles)  
Read Status Data (last two cycles)  
t
WC  
tAS  
Addresses  
CE  
PA  
PA  
555h  
PA  
t
AH  
t
CH  
OE  
t
WP  
t
WHWH1  
WE  
t
CS  
t
WPH  
t
DS  
t
DH  
Data  
A0h  
PD  
DOUT  
Status  
t
RB  
t
BUSY  
RY/BY  
VCC  
t
VCS  
Note :  
1. PA = program addrss, PD = program data, Dout is the true data at the program address.  
2. Illustration shows device in word mode.  
PRELIMINARY  
(July, 2005, Version 0.0)  
26  
AMIC Technology, Corp.  
A29L400A Series  
Timing Waveforms for Chip/Sector Erase Operation  
Erase Command Sequence (last two cycles)  
Read Status Data  
t
AS  
t
WC  
SA  
555h for chip erase  
VA  
Addresses  
CE  
2AAh  
VA  
t
AH  
OE  
t
CH  
tWP  
WE  
tWPH  
tWHWH2  
t
CS  
tDS  
t
DH  
In  
Progress  
Data  
55h  
30h  
10h for chip erase  
Complete  
tRB  
t
BUSY  
RY/BY  
t
VCS  
VCC  
Note :  
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").  
2. Illustratin shows device in word mode.  
PRELIMINARY  
(July, 2005, Version 0.0)  
27  
AMIC Technology, Corp.  
A29L400A Series  
Timing Waveforms for  
Polling (During Embedded Algorithms)  
Data  
t
RC  
Addresses  
CE  
VA  
VA  
VA  
t
ACC  
CE  
t
t
CH  
t
OE  
OE  
t
DF  
t
OEH  
WE  
t
OH  
High-Z  
Valid Data  
Valid Data  
I/O  
7
Complement  
Complement  
Status Data  
True  
True  
High-Z  
I/O0  
- I/O  
6
High-Z  
Status Data  
t
BUSY  
RY/BY  
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data  
read cycle.  
PRELIMINARY  
(July, 2005, Version 0.0)  
28  
AMIC Technology, Corp.  
A29L400A Series  
Timing Waveforms for Toggle Bit (During Embedded Algorithms)  
tRC  
Addresses  
CE  
VA  
VA  
VA  
VA  
tACC  
tCE  
tCH  
tOE  
OE  
WE  
tDF  
tOEH  
tOH  
I/O6 , I/O2  
High-Z  
Valid Status  
(first read)  
Valid Status  
Valid Status  
Valid Data  
tBUSY  
(second read)  
(stop togging)  
RY/BY  
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status  
read cycle, and array data read cycle.  
Timing Waveforms for Sector Protect/Unprotect  
VID  
VIH  
RESET  
SA, A6,  
A1, A0  
Valid*  
Valid*  
Valid*  
Status  
Sector Protect/Unprotect  
Verify  
40h  
60h  
60h  
Data  
CE  
Sector Protect:150us  
Sector Unprotect:15ms  
1us  
WE  
OE  
Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0  
PRELIMINARY  
(July, 2005, Version 0.0)  
29  
AMIC Technology, Corp.  
A29L400A Series  
Timing Waveforms for I/O2 vs. I/O6  
Enter  
Erase  
Enter Erase  
Suspend Program  
Erase  
Resume  
Embedded  
Suspend  
Erasing  
WE  
Erase  
Suspend  
Program  
Erase  
Erase  
Erase Suspend  
Read  
Erase Suspend  
Read  
Erase  
Complete  
I/O6  
I/O2  
I/O2  
and I/O  
6
toggle with OE and CE  
Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Status" for  
more information.  
Timing Waveforms for Alternate  
Controlled Write Operation  
CE  
PA for program  
SA for sector erase  
555 for chip erase  
555 for program  
2AA for erase  
Data Polling  
PA  
Addresses  
t
WC  
tAS  
t
AH  
t
WH  
WE  
OE  
t
WHWH1 or 2  
t
CP  
t
BUSY  
t
CPH  
CE  
t
WS  
t
DS  
t
DH  
Data  
I/O  
7
DOUT  
t
RH  
A0 for program  
55 for erase  
PD for program  
30 for sector erase  
10 for chip erase  
RESET  
RY/BY  
Note :  
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O  
2. Figure indicates the last two bus cycles of the command sequence.  
7 = Complement of Data Input, D OUT = Array Data.  
PRELIMINARY (July, 2005, Version 0.0)  
30  
AMIC Technology, Corp.  
A29L400A Series  
Erase and Programming Performance  
Parameter  
Sector Erase Time  
Typ. (Note 1)  
Max. (Note 2)  
Unit  
sec  
sec  
Comments  
Excludes 00h programming prior  
to erasure  
1.0  
10  
5
8
Chip Erase Time  
Byte Programming Time  
300  
500  
18  
µs  
Word Programming Time  
7
7
5
Excludes system-level overhead  
(Note 5)  
µs  
Byte Mode  
Word Mode  
sec  
Chip Programming Time  
(Note 3)  
12  
sec  
Notes:  
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 10,000 cycles. Additionally, programming  
typically assumes checkerboard pattern.  
2. Under worst case conditions of 90°C, VCC = 2.7V, 100,000 cycles.  
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes  
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then  
does the device set I/O5 = 1. See the section on I/O5 for further information.  
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.  
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 5  
for further information on command definitions.  
6. The device has a guaranteed minimum erase and program cycle endurance of 10,000 cycles.  
Latch-up Characteristics  
Description  
Min.  
-1.0V  
Max.  
VCC+1.0V  
+100 mA  
12.5V  
Input Voltage with respect to VSS on all I/O pins  
VCC Current  
-100 mA  
-1.0V  
Input voltage with respect to VSS on all pins except I/O pins  
(including A9,  
and  
)
RESET  
OE  
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.  
TSOP and SOP Pin Capacitance  
Parameter Symbol  
Parameter Description  
Input Capacitance  
Test Setup  
VIN=0  
Typ.  
6
Max.  
7.5  
12  
Unit  
pF  
CIN  
COUT  
CIN2  
Output Capacitance  
VOUT=0  
VIN=0  
8.5  
7.5  
pF  
Control Pin Capacitance  
9
pF  
Notes:  
1. Sampled, not 100% tested.  
2. Test conditions TA = 25°C, f = 1.0MHz  
Data Retention  
Parameter  
Test Conditions  
150°C  
Min  
10  
Unit  
Years  
Years  
Minimum Pattern Data Retention Time  
20  
125°C  
PRELIMINARY  
(July, 2005, Version 0.0)  
31  
AMIC Technology, Corp.  
A29L400A Series  
Test Conditions  
Test Specifications  
Test Condition  
-70  
-90  
Unit  
Output Load  
1 TTL gate  
Output Load Capacitance, CL(including jig capacitance)  
Input Rise and Fall Times  
30  
5
100  
5
pF  
ns  
V
Input Pulse Levels  
0.0 - 3.0  
1.5  
0.0 - 3.0  
1.5  
Input timing measurement reference levels  
Output timing measurement reference levels  
V
1.5  
1.5  
V
Test Setup  
3.3 V  
2.7 KΩ  
Device  
Under  
Test  
Diodes = IN3064 or Equivalent  
CL  
6.2 KΩ  
PRELIMINARY  
(July, 2005, Version 0.0)  
32  
AMIC Technology, Corp.  
A29L400A Series  
Ordering Information  
Top Boot Sector Flash  
Standby  
Current  
Typ. (µA)  
Active Read  
Current  
Typ. (mA)  
Program/Erase  
Current  
Access Time  
Part No.  
Package  
(ns)  
Typ. (mA)  
A29L400ATM-70  
A29L400ATM-70F  
A29L400ATM-70U  
A29L400ATM-70UF  
A29L400ATM-70I  
A29L400ATM-70IF  
A29L400ATV-70  
A29L400ATV-70F  
A29L400ATV-70U  
A29L400ATV-70UF  
A29L400ATV-70I  
A29L400ATV-70IF  
A29L400ATG-70  
A29L400ATG-70F  
A29L400ATG-70U  
A29L400ATG-70UF  
A29L400ATG-70I  
A29L400ATG-70IF  
A29L400ATM-90  
A29L400ATM-90F  
A29L400ATM-90U  
A29L400ATM-90UF  
A29L400ATM-90I  
A29L400ATM-90IF  
A29L400ATV-90  
A29L400ATV-90F  
A29L400ATV-90U  
A29L400ATV-90UF  
A29L400ATV-90I  
A29L400ATV-90IF  
A29L400ATG-90  
A29L400ATG-90F  
A29L400ATG-90U  
A29L400ATG-90UF  
A29L400ATG-90I  
A29L400ATG-90IF  
44Pin SOP  
44Pin Pb-Free SOP  
44Pin SOP  
44Pin Pb-Free SOP  
44Pin SOP  
44Pin Pb-Free SOP  
48Pin TSOP  
48Pin Pb-Free TSOP  
48Pin TSOP  
70  
4
20  
0.2  
48Pin Pb-Free TSOP  
48Pin TSOP  
48Pin Pb-Free TSOP  
48-ball TFBGA  
48-ball Pb-Free TFBGA  
48-ball TFBGA  
48-ball Pb-Free TFBGA  
48-ball TFBGA  
48-ball Pb-Free TFBGA  
44Pin SOP  
44Pin Pb-Free SOP  
44Pin SOP  
44Pin Pb-Free SOP  
44Pin SOP  
44Pin Pb-Free SOP  
48Pin TSOP  
48Pin Pb-Free TSOP  
48Pin TSOP  
90  
4
20  
0.2  
48Pin Pb-Free TSOP  
48Pin TSOP  
48Pin Pb-Free TSOP  
48-ball TFBGA  
48-ball Pb-Free TFBGA  
48-ball TFBGA  
48-ball Pb-Free TFBGA  
48-ball TFBGA  
48-ball Pb-Free TFBGA  
Note: -U is for industrial operating temperature range: -40°C to +85°C  
-I is for industrial operating temperature range: -25°C to +85°C  
PRELIMINARY  
(July, 2005, Version 0.0)  
33  
AMIC Technology, Corp.  
A29L400A Series  
Ordering Information (continued)  
Bottom Boot Sector Flash  
Standby  
Current  
Typ. (µA)  
Active Read  
Current  
Typ. (mA)  
Program/Erase  
Current  
Access Time  
Part No.  
(ns)  
Package  
Typ. (mA)  
A29L400AUM-70  
A29L400AUM-70F  
A29L400AUM-70U  
A29L400AUM-70UF  
A29L400AUM-70I  
A29L400AUM-70IF  
A29L400AUV-70  
A29L400AUV-70F  
44Pin SOP  
44Pin Pb-Free SOP  
44Pin SOP  
44Pin Pb-Free SOP  
44Pin SOP  
44Pin Pb-Free SOP  
48Pin TSOP  
48Pin Pb-Free TSOP  
48Pin TSOP  
A29L400AUV-70U  
70  
A29L400AUV-70UF  
4
20  
0.2  
48Pin Pb-Free TSOP  
48Pin TSOP  
A29L400AUV-70I  
A29L400AUV-70IF  
A29L400AUG-70  
A29L400AUG-70F  
A29L400AUG-70U  
A29L400AUG-70UF  
A29L400AUG-70I  
A29L400AUG-70IF  
A29L400AUM-90  
A29L400AUM-90F  
A29L400AUM-90U  
A29L400AUM-90UF  
A29L400AUM-90I  
A29L400AUM-90IF  
A29L400AUV-90  
A29L400AUV-90F  
48Pin Pb-Free TSOP  
48-ball TFBGA  
48-ball Pb-Free TFBGA  
48-ball TFBGA  
48-ball Pb-Free TFBGA  
48-ball TFBGA  
48-ball Pb-Free TFBGA  
44Pin SOP  
44Pin Pb-Free SOP  
44Pin SOP  
44Pin Pb-Free SOP  
44Pin SOP  
44Pin Pb-Free SOP  
48Pin TSOP  
48Pin Pb-Free TSOP  
48Pin TSOP  
A29L400AUV-90U  
90  
A29L400AUV-90UF  
4
20  
0.2  
48Pin Pb-Free TSOP  
48Pin TSOP  
A29L400AUV-90I  
A29L400AUV-90IF  
A29L400AUG-90  
A29L400AUG-90F  
A29L400AUG-90U  
A29L400AUG-90UF  
A29L400AUG-90I  
A29L400AUG-90IF  
48Pin Pb-Free TSOP  
48-ball TFBGA  
48-ball Pb-Free TFBGA  
48-ball TFBGA  
48-ball Pb-Free TFBGA  
48-ball TFBGA  
48-ball Pb-Free TFBGA  
Note: -U is for industrial operating temperature range: -40°C to +85°C  
-I is for industrial operating temperature range: -25°C to +85°C  
PRELIMINARY  
(July, 2005, Version 0.0)  
34  
AMIC Technology, Corp.  
A29L400A Series  
Package Information  
SOP 44L Outline Dimensions  
unit: inches/mm  
23  
44  
Gauge Plane  
0.010"  
θ
L
1
22  
b
Detail F  
D
S
L1  
e
y
Seating Plane  
See Detail F  
Dimensions in inches  
Dimensions in mm  
Symbol  
Min  
-
Nom  
-
Max  
0.118  
-
Min  
Nom  
-
Max  
3.00  
A
A1  
A2  
b
-
0.10  
2.62  
0.33  
0.18  
-
0.004  
-
-
-
0.103  
0.106  
0.016  
0.008  
1.122  
0.496  
0.050  
0.631  
0.032  
0.0675  
-
0.109  
0.020  
0.010  
1.130  
0.500  
-
2.69  
0.40  
0.20  
28.50  
12.60  
1.27  
16.03  
0.80  
1.71  
-
2.77  
0.50  
0.25  
28.70  
12.70  
-
0.013  
C
D
E
0.007  
-
0.490  
12.45  
-
e
-
HE  
L
0.620  
0.643  
0.040  
-
15.75  
0.61  
-
16.33  
1.02  
-
0.024  
L1  
S
-
-
0.045  
0.004  
8°  
-
1.14  
0.10  
8°  
y
-
-
-
-
-
-
θ
0°  
0°  
Notes:  
1. The maximum value of dimension D includes end flash.  
2. Dimension E does not include resin fins.  
3. Dimension S includes end flash.  
PRELIMINARY  
(July, 2005, Version 0.0)  
35  
AMIC Technology, Corp.  
A29L400A Series  
Package Information  
TSOP 48L (Type I) Outline Dimensions  
unit: inches/mm  
D
D1  
1
48  
D
24  
25  
θ
L
Detail "A"  
Detail "A"  
Dimensions in inches  
Dimensions in mm  
Symbol  
Min  
-
Nom  
Max  
Min  
Nom  
Max  
A
A1  
A2  
b
-
0.047  
0.006  
0.042  
0.011  
0.008  
0.795  
0.728  
0.476  
-
-
1.20  
0.15  
0.002  
0.037  
0.007  
0.004  
0.779  
0.720  
-
-
0.039  
0.009  
-
0.05  
0.94  
0.18  
0.12  
19.80  
18.30  
-
-
1.00  
1.06  
0.22  
0.27  
c
-
0.20  
D
D1  
E
e
0.787  
0.724  
0.472  
0.020 BASIC  
0.020  
0.011 Typ.  
-
20.00  
18.40  
12.00  
0.50 BASIC  
0.50  
20.20  
18.50  
12.10  
L
0.016  
0.024  
0.40  
0.60  
S
y
0.28 Typ.  
-
-
0.004  
8°  
-
0.10  
8°  
0°  
-
0°  
-
θ
Notes:  
1. The maximum value of dimension D includes end flash.  
2. Dimension E does not include resin fins.  
3. Dimension S includes end flash.  
PRELIMINARY  
(July, 2005, Version 0.0)  
36  
AMIC Technology, Corp.  
A29L400A Series  
Package Information  
48LD CSP (6 x 8 mm) Outline Dimensions  
(48TFBGA)  
unit: mm  
TOP VIEW  
BOTTOM VIEW  
b
1
2 3 4 5 6  
6
5 4 3 2 1  
H
G
F
H
G
F
E
D
C
B
A
E
D
C
B
A
e
D1  
Ball*A1 CORNER  
SIDE VIEW  
D
C
SEATING PLANE  
0.10 C  
Dimensions in mm  
Symbol  
Min.  
Nom.  
Max.  
A
A1  
b
-
-
0.25  
1.20  
0.30  
0.40  
6.10  
0.20  
0.30  
5.90  
-
D
6.00  
D1  
e
4.00 BSC  
0.80  
-
-
E
7.90  
8.00  
8.10  
E1  
5.60 BSC  
PRELIMINARY  
(July, 2005, Version 0.0)  
37  
AMIC Technology, Corp.  

相关型号：

A29L400ATV-70IF

 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
AMICC

A29L400ATV-70U

 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
AMICC

A29L400ATV-70UF

 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
AMICC

A29L400ATV-90

 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
AMICC

A29L400ATV-90F

 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
AMICC

A29L400ATV-90I

 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
AMICC

A29L400ATV-90IF

 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
AMICC

A29L400ATV-90U

 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
AMICC

A29L400ATV-90UF

 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
AMICC

A29L400AUG-70

 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
AMICC

A29L400AUG-70F

 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
AMICC

A29L400AUG-70I

 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
AMICC
©2020 ICPDF网 联系我们和版权申明