A418316S_技术文档

A418316 Series

Preliminary

256K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

Document Title

256K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

Revision History

Rev. No. History

0.0 Initial issue

Issue Date

July 21, 2003

Remark

Preliminary

PRELIMINARY (July, 2003,Version 0.0)

AMIC Technology, Inc.

A418316 Series

PRELIMINARY

(July, 2003,Version 0.0)

1

AMIC Technology, Inc.

A418316 Series

Preliminary

256K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

Features

nOrganization: 262,144 words X 16 bits

nPart Identification

- A418316 (512 Ref.)

n Single 5.0V power supply/built-in VBB generator

nLow power consumption

nIndustrial operating temperature range: -40°C to 85°C

for -U

nSeparate

(

,

) for byte selection

UCAS LCAS

CAS

n512 Refresh Cycle in 8ms

- Operating: 110mA (-25 max)

- Standby: 2.5mA (TTL), 1.0mA (CMOS)

1.0mA (Self-refresh current)

nHigh speed

nRead-modify-write, RAS -only, CAS -before- RAS ,

Hidden refresh capability

nTTL-compatible, three-state I/O

nJEDEC standard packages

- 25/35 ns RAS access time

- 400mil, 40-pin SOJ

- 12/17 ns column address access time

- 400mil, 40/44 TSOP type II package

- 8/10 ns CAS access time

- 15/19 ns FAST Page Mode Cycle Time

This allow random access of up to 512 words within a row

at a 66/52 MHz FAST cycle, making the A418316 ideally

suited for graphics, digital signal processing and high

performance computing systems.

General Description

The A418316 is a new generation randomly accessed

memory for graphics, organized in a 262,144-word by 16-

bit configuration. This product can execute Byte Write

and Byte Read operation via two

pins.

CAS

The A418316 offers an accelerated Fast Page Mode

Pin Descriptions

Pin Configuration

Symbol

Description

Address Inputs

nSOJ

n TSOP

A0 – A8

I/O0 - I/O15 Data Input/Output

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

44

43

42

41

40

39

38

37

36

35

VSS

I/O15

I/O14

I/O13

I/O12

VSS

I/O11

I/O10

I/O9

VCC

1

VSS

VCC

I/O0

I/O1

I/O2

I/O3

VCC

I/O4

I/O5

I/O6

I/O7

1

I/O0

I/O1

2

I/O15

I/O14

Row Address Strobe

RAS

3

I/O2

I/O3

VCC

I/O4

I/O5

I/O6

I/O7

NC

I/O13

I/O12

VSS

I/O11

I/O10

I/O9

I/O8

NC

4

Column Address Strobe for Lower Byte

LCAS

UCAS

WE

5

6

(I/O0 – I/O7)

7

Column Address Strobe for Upper Byte

(I/O8 – I/O15)

8

9

10

11

12

13

14

15

10

I/O8

Write Enable

32

31

30

29

28

27

26

25

NC

LCAS

UCAS

OE

NC

WE

RAS

NC

A0

13

14

15

16

17

18

19

20

21

22

LCAS

UCAS

WE

RAS

NC

A0

A1

A2

Output Enable

OE

A8

OE

VCC

VSS

NC

5.0V Power Supply

Ground

A7

A6

16

17

18

19

20

A8

A7

A6

A5

A1

A2

A5

A4

VSS

No Connection

A3

VCC

22

21

24

23

A4

A3

VSS

VCC

cycle with a feature called Extended Data Out (FAST).

PRELIMINARY

(July, 2003,Version 0.0)

1

AMIC Technology, Inc.

A418316 Series

Selection Guide

Symbol

Description

-25

-35

Unit

tRAC

25

35

ns

Maximum RAS Access Time

tAA

Maximum Column Address Access Time

Maximum CAS Access Time

12

8

17

10

ns

tCAC

tOEA

8

10

ns

Maximum Output Enable ( OE) Access Time

Minimum Read or Write Cycle Time

Minimum FAST Cycle Time

tRC

tPC

44

15

62

19

ns

Functional Description

The A418316 reads and writes data by multiplexing an 18-

bit address into a 9-bit row and 9-bit column address.

. While holding RAS low,

strobe changing column addresses, thus achieving shorter

cycle times.

can be toggled to

CAS

and

are used to strobe the row address and the

CAS

RAS

column address, respectively.

The A418316 offers an accelerated Fast Page Mode cycle.

The A418316 has two

inputs:

controls I/O0-

CAS

LCAS

A memory cycle is terminated by returning both RAS and

high. Memory cell data will retain its correct state by

maintaining power and accessing all 512 combinations of

the 9-bit row addresses, regardless of sequence, at least

CAS

I/O7, and

controls I/O8 - I/O15,

and

UCAS

LCAS

function in an identical manner to

in that either will

CAS

generate an internal

signal. The

function and

CAS

once every 8ms through any RAS cycle (Read, Write) or

timing are determined by the first

(

or

UCAS

RAS Refresh cycle (RAS-only, CBR, or Hidden). The CBR

Refresh cycle automatically controls the row addresses by

invoking the refresh counter and controller.

) to transition low and by the last to transition high.

LCAS

Byte Read and Byte Write are controlled by using

LCAS

and

separately.

UCAS

Power-On

A Read cycle is performed by holding the WE signal high

during RAS/ operation. A Write cycle is executed by

The initial application of the VCC supply requires a 200 µs

wait followed by a minimum of any eight initialization cycles

CAS

holding the WE signal low during RAS /

operation;

containing a RAS clock. During Power-On, the VCC

CAS

the input data is latched by the falling edge of WE or

, whichever occurs later. The data inputs and outputs

current is dependent on the input levels of RAS and

.

CAS

are routed through 16 common I/O pins, with RAS,

It is recommended that RAS and

track with VCC or

CAS

be held at a valid VIH during Power-On to avoid current

surges.

,

CAS

WE and OE controlling the in direction.

FAST Page Mode operation all 512 columns within a

selected row to be randomly accessed at a high data rate.

A FAST Page Mode cycle is initiated with a row address

latched by RAS followed by a column address latched by

PRELIMINARY

(July, 2003,Version 0.0)

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AMIC Technology, Inc.

A418316 Series

Block Diagram

OE

WE

OE Clock

Generator

WE Clock

Generator

UCAS

LCAS

CAS Clock

Generator

I/O⁰

Data I/O

Buffers

AY0 - AY8

Column

Address

Buffers

to

Column Decoders

I/O¹⁵

Sense Amplifiers

.

^.512 x 16 ^.

A0 - A8

Refresh

Counter &

Controller

.

Memory Array

512 x 512 x 16

512

Row

Address

Buffers

.

AX0 - AX8

VCC

VSS

RAS Clock

Generator

RAS

Recommended Operating Conditions (Ta = 0°C to +70°C or -40°C to +85°C)

Symbol

VCC

VSS

VIH

Description

Power Supply

Min.

4.5

Typ.

5.0

0.0

-

Max.

5.5

Unit

V

Notes

1

Input High Voltage

Input Low Voltage

0.0

V

2.4

VCC + 1.0

0.8

V

VIL

-0.5

-

V

PRELIMINARY

(July, 2003,Version 0.0)

3

AMIC Technology, Inc.

A418316 Series

Truth Table

Function

Address

L

I/Os

L

Notes

RAS

H

WE

L

OE

L

LCAS

UCAS

Standby

H

L

H

L

Read: Word

Read: Lower Byte

L

H

L

Row/Col.

Data Out

L

H

L

I/O0-7 = Data Out

I/O8-15 = High-Z

Read: Upper Byte

L

H

L

Row/Col.

I/O0-7 = High-Z

I/O8-15 = Data Out

Write: Word(Early)

L

X

Row/Col.

Data In

Write: Lower Byte(Early)

H

I/O0-7 = Data In

I/O8-15 = X

Write: Upper Byte(Early)

Read-Write

L

H

L

X

Row/Col.

I/O0-7 = X

I/O8-15 = Data In

1.2

H® L

L® H

Data Out ® Data In

Fast-Page-Mode Read: Hi-Z

-First cycle

L

H

Row/Col.

Col.

Data Out

2

H® L

-Subsequent Cycles

Fast-Page-Mode Write (Early)

-First cycle

L

X

Row/Col.

Col.

Data In

1

H® L

-Subsequent Cycles

Fast-Page-Mode Read-Write

-First cycle

L

Row/Col.

Col.

Data In

1, 2

H® L

L

H® L

L

H® L

H

L® H

L

-Subsequent Cycles

Hidden Refresh Read

Hidden Refresh Write

Row/Col.

Row

Data Out

2

1

L® H® L

L

X

Data In ® High-Z

H

X

High-Z

RAS-Only Refresh

CBR Refresh

L

X

High-Z

3

H® L

Self Refresh

Note:

1. Byte Write may be executed with either

2. Byte Read may be executed with either

or

active.

UCAS

LCAS

or

UCAS LCAS

3. Only one

signal (

or

UCAS LCAS

) must be active.

CAS

PRELIMINARY

(July, 2003,Version 0.0)

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AMIC Technology, Inc.

A418316 Series

Absolute Maximum Ratings*

*Comments

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to this device.

These are stress ratings only. Functional operation of

this device at these or any other conditions above

those indicated in the operational sections of these

specification is not implied or intended. Exposure to

the absolute maximum rating conditions for extended

periods may affect device reliability.

Input Voltage (Vin) . . . . . . . . . . . . . . . . . . . . -1.0V to +7.0V

Output Voltage (Vout) . . . . . . . . . . . . . . . . . -1.0V to +7.0V

Power Supply Voltage (VCC) . . . . . . . . . . . -1.0V to +7.0V

Operating Temperature (TOPR) . . . . . . . . . . . . 0°C to +70°C

Storage Temperature (TSTG) . . . . . . . . . . . -55°C to +150°C

Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec

Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

Short Circuit Output Current (Iout) . . . . . . . . . . . . . . . 50mA

Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA

DC Electrical Characteristics (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)

Symbol

Parameter

-25

-35

Unit

Test Conditions

Notes

Min.

Max.

Min.

Max.

IIL

Input Leakage

Current

-5

+5

-5

+5

mA

0V £ Vin £ VCC

Pins not under

Test = 0V

IOL

Output Leakage

Current

-5

-

+5

-5

-

+5

DOUT disabled,

0V £ Vout £ VCC

mA

ICC1

Operating

Power Supply

Current

115

105

mA

1, 2

RAS,

,

and

UCAS LCAS

Address cycling;

tRC = min.

ICC2

ICC3

TTL Supply

Current Supply

Current

-

2.5

-

2.5

mA

RAS=

VIH

=

UCAS LCAS

Average Power

Supply Current,

115

105

1

1, 2

1

RAS and Address

cycling,

RAS Refresh

Mode

=

= VIH,

UCAS LCAS

tRC = min.

ICC4

ICC5

FAST Page

Mode Average

Power Supply

Current

-

115

-

105

mA

RAS and address = VIL,

and

,

UCAS LCAS

Address cycling;

tPC = min.

CAS -before-

RAS and

or

UCAS

RAS Refresh

Power Supply

Current

cycling;

tRC = min.

LCAS

ICC6

ICC7

CMOS Standby

Power Supply

Current

-

1.0

-

1.0

mA

RAS=

=

UCAS LCAS

VCC - 0.2V

Self Refresh

Mode Current

RAS=

£VSS+0.2V

CAS

All other input high

levels are VCC-0.2V or

input low levels are VSS

+0.2V

VOH

VOL

2.4

-

2.4

-

V

IOUT = -5.0mA

IOUT = 4.2mA

Output Voltage

0.4

PRELIMINARY

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AMIC Technology, Inc.

A418316 Series

AC Characteristics (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)

Test Conditions:

Input timing reference level: VIH/VIL=2.4V/0.8V

Output reference level: VOH/VOL=2.0V/0.8V

Output Load: 2TTL gate + CL (50pF)

Assumed tT=2ns

Std

-25

-35

#

Symbol

Parameter

Unit

Notes

Min.

1

Max.

50

Min.

1

Max.

50

tT

Transition Time (Rise and Fall)

ns

4, 5

1

tRC

Random Read or Write Cycle

Time

44

-

62

-

2

3

4

5

6

tRP

15

25

7

-

23

35

9

-

ns

RAS Precharge Time

RAS Pulse Width

tRAS

tCAS

tRCD

tRAD

10K

21

10K

25

CAS Pulse Width

10

8

10

8

6

7

RAS to CAS Delay Time

14

18

RAS to Column Address Delay

Time

7

8

9

tRSH

tCSH

tCRP

5

25

5

-

6

31

5

-

ns

CAS to RAS Hold Time

CAS Hold Time

CAS to RAS Precharge Time

Row Address Setup Time

Row Address Hold Time

10

11

12

tASR

tRAH

tCLZ

0

5

0

-

0

6

0

-

ns

8

CAS to Output in Low Z

Access Time from RAS

Access Time from CAS

13

14

15

tRAC

tCAC

tAA

-

25

8

-

35

10

17

ns

6,7

6, 13

7, 13

Access Time from Column

Address

12

16

17

tOEA

tAR

-

8

-

10

-

ns

OE Access Time

Column Address Hold Time from

RAS

22

31

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AMIC Technology, Inc.

A418316 Series

AC Characteristics (continued) (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)

Test Conditions:

Input timing reference level: VIH/VIL=2.4V/0.8V

Output reference level: VOH/VOL=2.0V/0.8V

Output Load: 2TTL gate + CL (50pF)

Assumed tT=2ns

-25

-35

Std

#

Symbol

Parameter

Unit

Notes

Min.

Max.

Min.

Max.

18

19

20

tRCS

tRCH

Read Command Setup Time

Read Command Hold Time

0

-

0

-

ns

9

tRRH

tRAL

tCOH

Read Command Hold Time

Reference to RAS

0

12

3

-

0

17

3

-

21

22

ns

Column Address to RAS Lead

Time

Output Hold After CAS Low

Output Buffer Turn-Off Delay Time

Column Address Setup Time

Column Address Hold Time

23

24

25

26

tOFF

tASC

tCAH

tOES

-

3

-

3

-

ns

8, 10

0

5

0

6

7

-

Low to CAS High Set Up

OE

27

28

29

tWCS

tWCH

tWCR

Write Command Setup Time

Write Command Hold Time

0

5

-

0

6

-

ns

11

22

31

Write Command Hold Time to RAS

Write Command Pulse Width

30

31

tWP

5

7

-

6

-

ns

tRWL

10

Write Command to RAS Lead

Time

32

tCWL

5

-

7

-

ns

Write Command to CAS Lead

Time

33

34

35

tDS

tDH

Data-in setup Time

Data-in Hold Time

0

5

-

0

6

-

ns

12

tDHR

22

31

Data-in Hold Time to RAS

PRELIMINARY

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AMIC Technology, Inc.

A418316 Series

AC Characteristics (continued) (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)

Test Conditions:

Input timing reference level: VIH/VIL=2.4V/0.8V

Output reference level: VOH/VOL=2.0V/0.8V

Output Load: 2TTL gate + CL (50pF)

Assumed tT=2ns

-25

-35

Std

#

Symbol

Parameter

Unit

Notes

Min.

62

Max.

Min. Max.

36

37

tRWC

tRWD

Read-Modify-Write Cycle Time

-

85

46

-

ns

34

11

RAS to WE Delay Time

(Read-Modify-Write)

38

39

40

tCWD

tAWD

tOEH

17

21

5

-

21

28

6

-

ns

CAS to WE Delay Time (Read-

Modify-Write)

Column Address to WE Delay

Time (Read-Modify-Write)

OE Hold Time from WE

OE High Pulse Width

41

42

tOEP

tPC

5

-

5

-

ns

Read or Write Cycle Time (FAST

Page)

15

19

14

13

43

tCPA

-

17

-

21

ns

Access Time from CAS Precharge

(FAST Page)

44

45

tCP

4

-

6

-

ns

CAS Precharge Time

tPCM

FAST Page Mode RMW Cycle

Time

32

40

46

tCRW

24

-

30

-

ns

FAST Page Mode CAS Pulse

Width (RMW)

47

48

tRASP

tCSR

30

5

200K

-

35

5

200K

-

ns

RAS Pulse Width (FAST Page)

3

CAS Setup Time

( CAS -before-RAS)

49

50

tCHR

tRPC

7

-

10

-

ns

CAS Hold Time

( CAS -before-RAS)

10

RAS to CAS Precharge Time

PRELIMINARY

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AMIC Technology, Inc.

A418316 Series

AC Characteristics (continued) (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)

Test Conditions:

Input timing reference level: VIH/VIL=2.4V/0.8V

Output reference level: VOH/VOL=2.0V/0.8V

Output Load: 2TTL gate + CL (50pF)

Assumed tT=2ns

-25

-35

Std

#

Symbol

Parameter

Unit

Notes

Min. Max. Min.

Max.

51

52

tOEZ

Output Buffer Turn-off Delay from

OE

-

3

-

3

ns

8

tRASS

100

-

100

-

ms

RAS pulse width

(

-B- self refresh)

R

C

53

tRPS

tCHS

44

-

62

ns

RAS precharge time

-B- self refresh)

(

C

R

54

-50

CAS hold time ( -B- self refresh)

R

C

Notes:

1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.

2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.

3. An initial pause of 200ms is required after power-up followed by any 8 RAS cycles before proper device operation is

achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before-RAS initialization cycles instead of 8

RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks.

4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to two TTL loads and

50pF, VIL (min.) ³ GND and VIH (max.) £ VCC.

5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured

between VIH and VIL.

6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference

point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.

7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference

point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.

8. Assumes three state test load (5pF and a 500W Thevenin equivalent).

9. Either tRCH or tRRH must be satisfied for a read cycle.

10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output

voltage levels.

11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet

as electrical characteristics only. If tWCS ³ tWCS (min.) and tWCH ³ tWCH (min.), the cycle is an early write cycle

and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ³ tRWD (min.) , tCWD ³

tCWD (min.) and tAWD ³ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from

the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is

indeterminate.

12. These parameters are referenced to

read-modify-write cycles.

and

leading edge in early write cycles and to WE leading edge in

LCAS

UCAS

13. Access time is determined by the longer of tAA or tCAC or tCPA.

14. tASC ³ tCP to achieve tPC (min.) and tCPA (max.) values.

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AMIC Technology, Inc.

A418316 Series

Word Read Cycle

t

RC(1)

t

RAS(3)

t

RP(2)

RAS

t

CSH(8)

t

CRP(9)

t

RCD(5)

t

RSH(7)

tCRP(9)

t

CAS(4)

UCAS

LCAS

t

RAD(6)

t

RAL(21)

t

ASR(10)

tRAH(11)

t

ASC(24)

t

CAH(25)

A0~A8

Row Address

Column Address

t

AR(17)

t

RCH(19)

t

RCS(18)

t

RRH(20)

WE

OE

t

OEA(16)

t

CAC(14)

t

AA(15)

t

OFF(23)

t

RAC(13)

t

OEZ(51)

I/O0 ~

I/O15

High-Z

Valid Data-out

t

CLZ(12)

: High or Low

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AMIC Technology, Inc.

A418316 Series

Word Write Cycle (Early Write)

t

RC(1)

t

RAS(3)

t

RP(2)

RAS

t

CSH(8)

t

CRP(9)

t

RCD(5)

t

RSH(7)

tCRP(9)

t

CAS(4)

UCAS

LCAS

t

AR(17)

t

RAD(6)

t

RAL(21)

t

ASR(10)

tRAH(11)

t

CAH(25)

t

ASC(24)

Row Address

Column Address

A0~A8

t

WCR(29)

t

CWL(32)

t

RWL(31)

t

WP(30)

WE

OE

t

WCS(27)

t

WCH(28)

t

DHR(35)

t

DS(33)

t

DH(34)

I/O0 ~

I/O15

Valid Data-in

: High or Low

PRELIMINARY

(July, 2003, Version 0.0)

11

AMIC Technology, Inc.

A418316 Series

Word Write Cycle (Late Write)

t

RC(1)

t

RAS(3)

t

RP(2)

RAS

t

CSH(8)

t

CRP(9)

t

RCD(5)

t

RSH(7)

tCRP(9)

UCAS

LCAS

t

CAS(4)

t

AR(17)

t

RAD(6)

t

RAL(21)

t

ASR(10)

tRAH(11)

t

CAH(25)

t

ASC(24)

Row Address

Column Address

A0~A8

t

CWL(32)

RWL(31)

t

WCR(29)

t

WP(30)

WE

OE

t

OEH(40)

t

DHR(35)

t

DS(33)

t

DH(34)

High-Z

I/O

0 ~

Vaild Data-in

I/O15

: High or Low

PRELIMINARY

(July, 2003, Version 0.0)

12

AMIC Technology, Inc.

A418316 Series

Word Read-Modify-Write Cycle

t

RWC(36)

t

RAS(3)

t

RP(2)

RAS

t

CSH(8)

t

CRP(9)

t

RCD(5)

t

RSH(7)

tCRP(9)

UCAS

LCAS

t

AR(17)

t

RAD(6)

t

ASR(10)

t

RAH(11)

t

ASC(24)

tCAH(25)

A0~A8

WE

Row Address

Column Address

t

AWD(39)

CWD(38)

t

CWL(32)

t

RCS(18)

t

RWD(37)

t

RWL(31)

t

WP(30)

t

OEA(16)

t

OEZ(51)

OE

t

OEH(40)

t

CAC(14)

AA(15)

t

DS(33)

tDH(34)

t

RAC(13)

High-Z

I/O

I/O15

0 ~

Data-out

Data-in

t

CLZ(12)

: High or Low

PRELIMINARY

(July, 2003, Version 0.0)

13

AMIC Technology, Inc.

A418316 Series

FAST Page Mode Word Read Cycle

t

RASP(47)

tRP(2)

RAS

t

CSH(8)

t

PC(42)

tRSH(7)

t

CRP(9)

t

CRP(9)

t

RCD(5)

t

CP(44)

t

CAS(4)

t

CAS(4)

tCAS(4)

UCAS

LCAS

CSH(8)

t

RAL(21)

t

AR(16)

t

CAH(25)

t

RAD(6)

t

CAH(25)

t

ASR(10)

tRAH(11)

t

ASC(24)

t

ASC(24)

Row

Column

A0~A8

WE

t

CAH(25)

t

RCS(18)

t

RCS(18)

t

RCH(19)

t

RCH(25)

t

RCS(18)

t

AA(15)

t

AA(15)

t

RRH(20)

t

CPA(43)

t

OEA(16)

t

OEA(16)

t

OES(26)

OE

t

CAC(14)

t

RAC(13)

tOEP(41)

t

OFF(23)

OEZ(51)

t

CAC(14)

t

CAC(14)

t

COH(22)

t

CLZ(12)

t

OEZ(51)

I/O0 ~

I/O15

Data-out

t

CLZ(12)

: High or Low

PRELIMINARY

(July, 2003, Version 0.0)

14

AMIC Technology, Inc.

A418316 Series

FAST Page Mode Early Word Write Cycle

t

RASP(47)

tRP(2)

RAS

t

CSH(8)

t

PC(42)

tRSH(7)

t

CRP(9)

tCRP(9)

t

RCD(5)

t

CAS(4)

t

CP(44)

t

CAS(4)

t

CP(44)

tCAS(4)

UCAS

LCAS

t

RAL(21)

t

RAD(6)

t

CAH(25)

ASC(24)

t

CAH(25)

ASC(24)

tCAH(25)

t

RAH(11)

t

ASR(10)

t

ASC(24)

t

A0~A8

Row

Column

t

CWL(32)

t

CWL(32)

t

CWL(32)

RWL(31)

t

WCS(27)

t

WCS(27)

t

WCS(27)

t

WCH(28)

t

WCH(28)

tWCH(28)

WE

OE

t

WP(30)

t

WP(30)

tWP(30)

t

DH(34)

DS(33)

t

DH(34)

DS(33)

tDH(34)

t

DS(33)

t

I/O

I/O15

0 ~

Data-in

: High or Low

PRELIMINARY

(July, 2003, Version 0.0)

15

AMIC Technology, Inc.

A418316 Series

FAST Page Mode Word Read-Modify-Write Cycle

t

RP(2)

t

RASP(47)

RAS

t

CSH(8)

t

PCM(45)

tRSH(7)

t

CRP(9)

t

CRP(9)

t

RCD(5)

t

CP(44)

tCRW(46)

t

CRW(46)

t

CP(44)

tCRW(46)

UCAS

LCAS

t

RAL(21)

CAH(25)

t

ASC(24)

t

RAD(6)

t

CAH(25)

t

CAH(25)

t

RAH(11)

t

ASR(10)

t

ASC(24)

t

ASC(24)

A0~A8

Row

Column

t

CWL(32)

t

CWL(32)

tCWL(32)

t

RWD(37)

t

RWL(31)

t

CWD(38)

t

RCS(18)

t

CWD(38)

tCWD(38)

WE

t

WP(30)

AWD(39)

t

WP(30)

AWD(39)

tWP(30)

t

AWD(39)

t

OEA(16)

CAC(14)

t

OEA(16)

t

OEA(16)

OE

t

OEH(40)

t

CPA(43)

AA(15)

t

CPA(43)

AA(15)

t

AA(15)

t

OEZ(51)

tOEZ(51)

t

OEZ(51)

t

DH(34)

t

DH(34)

t

DH(34)

t

RAC(13)

t

DS(33)

t

DS(33)

t

DS(33)

I/O

I/O15

0

~

High-Z

t

CLZ(12)

t

CLZ(12)

tCLZ(12)

Data-in

Data-out

: High or Low

PRELIMINARY

(July, 2003, Version 0.0)

16

AMIC Technology, Inc.

A418316 Series

RAS Only Refresh Cycle

t

RC(1)

t

RAS(3)

tRP(2)

RAS

t

RPC(50)

t

CRP(9)

UCAS

LCAS

t

ASR(10)

tRAH(11)

A0~A8

Row

Note: WE, OE = Don't care.

: High or Low

CAS Before RAS Refresh Cycle

t

RC(1)

t

RP(2)

t

RAS(3)

tRP(2)

RAS

t

RPC(50)

tCHR(49)

t

CSR(48)

t

CP(44)

UCAS

LCAS

t

OFF(23)

High-Z

I/O

0 ~

I/O15

Note: WE, OE, Address = Don't care.

: High or Low

PRELIMINARY

(July, 2003, Version 0.0)

17

AMIC Technology, Inc.

A418316 Series

Hidden Refresh Cycle (Word Read)

tRC(1)

tRAS(3)

tRP(2)

tRAS(3)

tRP(2)

RAS

tAR(17)

tRCD(5)

tCRP(9)

tRSH(7)

tCHR(49)

tCRP(9)

UCAS

LCAS

tRAD(6)

tRAL(21)

tCAH(25)

tASR(10)

tRAH(11)

tASC(24)

Row

Column

A0~A8

tRCS(18)

tRRH(20)

WE

OE

tAA(15)

tOEZ(51)

tOEA(16)

tCAC(14)

tOFF(23)

tCLZ(12)

tRAC(13)

High-Z

I/O0 ~

Valid Data-out

I/O15

: High or Low

PRELIMINARY

(July, 2003, Version 0.0)

18

AMIC Technology, Inc.

A418316 Series

Hidden Refresh Cycle (Early Word Write)

t

RC(1)

tRC(1)

t

RAS(3)

t

RP(2)

t

RAS(3)

tRP(2)

RAS

t

AR(17)

t

CRP(9)

t

RCD(5)

t

RSH(7)

t

CHR(49)

tCRP(9)

UCAS

LCAS

t

RAD(6)

tRAL(21)

t

ASR(10)

t

CAH(25)

t

RAH(11)

ASC(24)

Row

Column

A0~A8

WE

t

WCS(27)

tWCH(28)

t

WP(30)

OE

t

DS(33)

tDH(34)

I/O

I/O15

0 ~

Valid Data-in

: High or Low

PRELIMINARY

(July, 2003, Version 0.0)

19

AMIC Technology, Inc.

A418316 Series

Self Refresh Mode

t

RP(2)

t

RASS(52)

tRPS(53)

RAS

t

CHS(54)

t

CRP(9)

t

CSR(48)

t

RPC(50)

UCAS

LCAS

t

CP(44)

t

ASR(10)

ROW

COL

A0~A8

t

OFF(23)

High-Z

I/O

0 ~

I/O15

: High or Low

Note: WE, OE = Don't care.

nSelf Refresh Mode.

a. Entering the Self Refresh Mode:

The A418316 Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal “low”

longer than 100ms.

b. Continuing the Self Refresh Mode:

The Self Refresh Mode is continued by holding RAS “low” after entering the Self Refresh Mode.

It does not depend on CAS being “high” or “low” after entering the Self Refresh Mode continue the Self Refresh Mode.

c. Exiting the Self Refresh Mode:

The A418316 exits the Self Refresh Mode when the RAS signal is brought “high”.

PRELIMINARY

(July, 2003, Version 0.0)

20

AMIC Technology, Inc.

A418316 Series

Capacitance (f = 1MHz, Ta = Room Temperature, VCC = 5.0V ± 10%)

Symbol

CIN1

Signals

A0 - A8

Parameter

Max.

Unit

pF

Test Conditions

Vin = 0V

5

7

CIN2

Input Capacitance

pF

Vin = 0V

RAS ,

,

UCAS

, WE ,

LCAS

OE

CI/O

I/O0 - I/O15

I/O Capacitance

7

pF

Vin = Vout = 0V

Ordering Codes

25ns

35ns

Self-Refresh

Package RAS Access Time

SOJ 40L (400mil)

A418316S-25

A418316V-25

A418316V-25U

A418316S-35

A418316V-35

A418316V-35U

Yes

TSOP 40/44 L type II (400mil)

Note: -U is for industrial operating temperature range.

PRELIMINARY

(July, 2003, Version 0.0)

21

AMIC Technology, Inc.

A418316 Series

Package Information

SOJ 40L (400mil) Outline Dimensions

unit: inches/mm

40

21

1

20

D

b

S

e

1

b

e1

y

Seating Plane

q

Dimensions in inches

Dimensions in mm

Symbol

Min

-

Nom

-

Max

0.144

-

Min

Nom

-

Max

A

A1

A2

b1

b

-

3.66

-

0.025

0.105

0.026

0.016

0.008

1.020

0.395

0.044

0.355

0.430

0.081

-

0.64

2.67

0.66

0.41

0.20

25.91

10.03

1.12

9.114

10.92

2.083

-

0.110

0.028

0.018

0.010

1.025

0.400

0.050

0.366

0.440

0.093

-

0.115

0.032

0.022

0.014

1.030

0.405

0.056

0.376

0.450

0.105

0.050

0.004

10°

2.79

0.71

0.46

0.25

26.04

10.16

1.27

9.383

11.18

2.39

-

2.92

0.81

0.56

0.36

26.16

10.29

1.42

9.652

11.43

2.70

1.27

0.10

10°

C

D

E

e

e1

HE

L

S

y

-

q

0°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension e1 is for PC Board surface mount pad pitch design

reference only.

4. Dimension S includes end flash.

PRELIMINARY

(July, 2003, Version 0.0)

22

AMIC Technology, Inc.

A418316 Series

Package Information

TSOP 40/44L (Type II) (400mil) Outline Dimensions

unit: inches/mm

44

q

L

1

D

L

L1

S

B

e

y

Dimensions in inches

Dimensions in mm

Symbol

Min

-

Nom

-

Max

Min

-

Nom

-

Max

1.20

0.15

1.05

0.42

0.23

18.54

10.29

A

A1

A2

B

0.047

0.006

0.041

0.017

0.009

0.730

0.405

0.002

0.037

0.013

0.003

0.720

0.395

-

0.05

0.95

0.32

0.08

18.28

10.03

-

0.039

0.015

0.005

0.725

0.400

0.031 BSC

0.463

0.020

0.031

-

1.00

0.37

0.13

18.41

10.16

0.80 BSC

11.76

0.50

0.80

-

c

D

E

e

HE

L

0.455

0.471

0.024

-

11.56

11.96

0.60

-

0.016

0.40

L1

S

-

0.035

0.004

5°

0.90

0.10

5°

y

-

1°

3°

1°

3°

q

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

PRELIMINARY

(July, 2003,Version 0.0)

23

AMIC Technology, Inc.


型号：	A418316S
厂家：	AMIC TECHNOLOGY
描述：	256K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE 256K ×16的CMOS动态的，快速页模式内存
文件：	总25页 (文件大小：264K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A418316S [AMICC]

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