A48P3616AV-4F [AMICC]
DRAM;
| 型号： | A48P3616AV-4F |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | DRAM 动态存储器 |
| 文件： | 总66页 (文件大小：1492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A48P3616A
Preliminary
8M X 16 Bit DDR DRAM
Document Title
8M X 16 Bit DDR DRAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
Initial issue
July 29, 2010
Preliminary
PRELIMINARY (July, 2010, Version 0.0)
AMIC Technology, Corp.
A48P3616A
Preliminary
8M X 16 Bit DDR DRAM
Features
CAS Latency and Frequency
Differential clock inputs (CK and CK )
Four internal banks for concurrent operation.
Data mask (DM) for write data.
DLL aligns DQ and DQS transitions with CK transitions.
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS.
Burst lengths: 2, 4, or 8
Maximum Operating Frequency (MHz)
CAS
Latency
DDR500 (4)
133
DDR400 (5)
2
2.5
3
133
166
200
-
200
CAS Latency: 2/2.5/3/4
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
4096 refresh cycles / 64ms (4 banks concurrent refresh)
2.5V (SSTL_2 compatible) I/O
VDD = VDDQ = 2.5V ± 0.2V
Industrial operating temperature range: -40ºC to +85ºC
for -U series.
250
4
250
Double data rate architecture: two data transfers per
clock cycle.
Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver.
Available Lead Free packaging
All Pb-free (Lead-free) products are RoHS compliant
DQS is edge-aligned with data for reads and is center-
aligned with data for writes.
General Description
The 128Mb DDR SDRAM uses
a
double-data-rate
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for
the 128Mb DDR SDRAM effectively consists of a single 2n-
bit wide, one clock cycle data transfer at the internal DRAM
core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank
architecture of DDR SDRAMs allows for concurrent
operation, thereby providing high effective bandwidth by
hiding row pre-charge and activation time.
The 128Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class
II compatible.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
PRELIMINARY (July, 2010, Version 0.0)
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AMIC Technology, Corp.
A48P3616A
Pin Configuration
TSOP (II)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
1
66
VSS
2
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
65
64
63
62
64
60
59
58
57
56
55
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VDDQ
LDQS
NC
VSSQ
UDQS
NC
VDD
VREF
VSS
NC
LDM*
WE
UDM*
CK
CAS
RAS
CS
CK
CKE
NC
NC
NC
BA0
BA1
A10/AP
A0
A11
A9
A8
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
Column Address Table
Organization
Row Address
Column Address
8Mb x16
A0-A11
A0-A8
* DM is internally loaded to match DQ and DQS identically
Preliminary (July, 2010, Version 0.0)
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AMIC Technology, Corp.
A48P3616A
Block Diagram (8Mb x 16)
CKE
CK
CK
CS
WE
CAS
RAS
CK, CK
DLL
Bank3
Bank2
Bank1
Mode
Registers
12
Bank0
Memory
Array
Data
16
16
14
12
4096
32
16
(4096 x 256 x 32)
DQS
Generator
1
Sense Amplifiers
DQ0-DQ15,
LDM, UDM
DQS
COL0
Input
32
Register
LDQS, UDQS
1
1
1
I/O Gating DM
Mask Logic
A0-A11,
14
Write
FIFO
&
Mask
2
1
2
BA0, BA1
1
32
256
Drivers
16
16
16
(x32)
2
16
32 16
Data
Column
Decoder
CLK CLK
Out
In
8
Column-Address
Counter/Latch
9
CK,
CK
1
COL0
COL0
1
Note:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and
DQS signals.
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AMIC Technology, Corp.
A48P3616A
Pin Descriptions
Symbol
Type
Description
Clock: CK and CK are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and negative edge of CK.
Input
CK, CK
CK
Output (read) data is referenced to the crossings of CK and
crossing).
(both directions of
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock
signals and device input buffers and output drivers. Taking CKE Low provides
Precharge Power Down and Self Refresh operation (all banks idle), or Active Power
Down (row Active in any bank). CKE is synchronous for power down entry and exit,
and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be
maintained high throughout read and write accesses. Input buffers, excluding CK,
CKE
Input
CK
and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during self refresh.
Chip Select: All commands are masked when CS is registered high. CS provides
Input
Input
CS
for external bank selection on systems with multiple banks. CS is considered part of
the command code.
Command Inputs: RAS , CAS , WE (along with CS ) define the command being
entered.
RAS , CAS , WE
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled high coincident with that input data during a Write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. During a Read, DM can be driven high, low, or
floated. LDM corresponds to the data on DQ0-DQ7; UDM corresponds to the data on
DQ8-DQ15.
UDM, LDM
BA0, BA1
Input
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. BA0 and BA1 also determines if the mode
register or extended mode register is to be accessed during a MRS or EMRS cycle.
Address Inputs: Provide the row address for Active commands, and the column
address and Auto Precharge bit for Read/Write commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 low) or all
banks (A10 high). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op-code during a Mode Register Set
command.
A0-A11
Input
DQ
Input / Output Data Input/Output: Data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read
LDQS, UDQS
Input / Output data, centered in write data. Used to capture write data. LDQS corresponds to the
data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15
NC
No Connect: No internal electrical connection is present.
DQ Power Supply: 2.5V ± 0.2V.
DQ Ground
VDDQ
VSSQ
VDD
Supply
Supply
Supply
Supply
Supply
Power Supply: 2.5V ± 0.2V.
Ground
VSS
SSTL_2 reference voltage: (VDDQ / 2) ± 1%.
VREF
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AMIC Technology, Corp.
A48P3616A
Functional Description
Initialization
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 134,217,728 bits. The
128Mb DDR SDRAM is internally configured as a quad-bank
DRAM.
The following relationships must be followed: VDDQ is driven
after or with VDD such that VDDQ < VDD + 0.3V VTT is driven
after or with VDDQ such that VTT < VDDQ + 0.3V VREF is driven
after or with VDDQ such that VREF < VDDQ + 0.3V
The 128Mb DDR SDRAM uses
a
double-data-rate
The DQ and DQS outputs are in the High-Z state, where they
remain until driven in normal operation (by a read access).
After all power supply and reference voltages are stable, and
the clock is stable, the DDR SDRAM requires a 200μs delay
prior to applying an executable command.
architecture to achieve high-speed operation. The double-
data-rate architecture is essentially a 2n prefetch architecture,
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for
the 128Mb DDR SDRAM consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half clock cycle data transfers
at the I/O pins.
Once the 200μs delay has been satisfied, a Deselect or
NOP command should be applied, and CKE must be brought
HIGH. Following the NOP command, a Precharge ALL
command must be applied. Next a Mode Register Set
command must be issued for the Extended Mode Register,
to enable the DLL, then a Mode Register Set command must
be issued for the Mode Register, to reset the DLL, and to
program the operating parameters. 200 clock cycles are
required between the DLL reset and any read command. A
Precharge ALL command should be applied, placing the
device in the “all banks idle” state
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-A11 select the row).
The address bits registered coincident with the Read or Write
command are used to select the starting column location for
the burst access.
Once in the idle state, two auto refresh cycles must be
performed. Additionally, a Mode Register Set command for
the Mode Register, with the reset DLL bit deactivated (i.e. to
program operating parameters without resetting the DLL)
must be performed. Following these cycles, the DDR
SDRAM is ready for normal operation.
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
DDR SDRAM’s may be reinitialized at any time during
normal operation by asserting a valid MRS command to
either the base or extended mode registers without affecting
the contents of the memory array. The contents of either the
mode register or extended mode register can be modified at
any valid time during device operation without affecting the
state of the internal address refresh counters used for device
refresh.
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AMIC Technology, Corp.
A48P3616A
Register Definition
Mode Register
Burst Length
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, and
an operating mode. The Mode Register is programmed via
the Mode Register Set command (with BA0 = 0 and BA1 = 0)
and retains the stored information until it is programmed
again or the device loses power (except for bit A8, which is
self-clearing).
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable. The
burst length determines the maximum number of column
locations that can be accessed for a given Read or Write
command. Burst lengths of 2, 4, or 8 locations are available
for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
Mode Register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved), A4-A6
specify the CAS latency, and A7-A11 specify the operating
mode.
When a Read or Write command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst wraps within the block if a boundary is reached.
The block is uniquely selected by A1-Ai when the burst
length is set to two, by A2-Ai when the burst length is set to
four and by A3-Ai when the burst length is set to eight (where
Ai is the most significant column address bit for a given
configuration). The remaining (least significant) address bit(s)
is (are) used to select the starting location within the block.
The programmed burst length applies to both Read and
Write bursts.
The Mode Register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements results in unspecified operation.
Mode Register Operation
BA0
0*
A11
A10
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Address Bus
BA1
0*
Operating Mode
CAS Latency
Burst Length
Mode Register
CAS Latency
A3 Burst Type
Burst Length
Operating Mode
A11-A9 A8 A7 A6-A0
Type
A6
A5
A4
Type
0
1
Sequential A2 A1 A0
Type
Normal operation
Do not reset DLL
0
0
0
1
0
0
Valid
Valid
0
0
0
Reserved
Interleave
0
0
0
0
0
1
Reserved
Normal operation
in DLL Reset
0
0
1
Reserved
2
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
2
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
4
3
4
8
Reserved
Reserved
Reserved
Reserved
Reserved
2.5
Reserved
Note:
* BA0 and BA1 must be 0, 0 to select the Mode Register
(vs. the Extended Mode Register).
PRELIMINARY (July, 2010, Version 0.0)
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AMIC Technology, Corp.
A48P3616A
Burst Type
Read Latency
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3.
The Read latency, or CAS latency, is the delay, in clock
cycles, between the registration of a Read command and the
availability of the first burst of output data. The latency can
be programmed 2, 2.5, 3 or 4 clocks.
The ordering of accesses within a burst is determined by the
burst length, the burst type and the starting column address,
as shown in Burst Definition on page 7.
If a Read command is registered at clock edge n, and the
latency is m clocks, the data is available nominally coincident
with clock edge n + m.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
Burst Definition
Starting Column Address
Burst Length
Order of Accesses Within a Burst
A2
A1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Sequential
0-1
Type = Interleaved
0-1
2
4
1-0
1-0
0
0
1
1
0
0
1
1
0
0
1
1
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0
0
0
0
0
1
1
1
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
8
Note:
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
PRELIMINARY (July, 2010, Version 0.0)
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AMIC Technology, Corp.
A48P3616A
Operating Mode
The normal operating mode is selected by issuing a Mode
Register Set Command with bits A7-A11 to zero, and bits A0-
A6 set to the desired values. A DLL reset is initiated by
issuing a Mode Register Set command with bits A7 and A9-
A11 each set to zero, bit A8 set to one, and bits A0-A6 set to
the desired values. A Mode Register Set command issued to
reset the DLL should always be followed by a Mode Register
Set command to select normal operating mode.
All other combinations of values for A7-A11 are reserved for
future use and/or test modes. Test modes and reserved
states should not be used as unknown operation or
incompatibility with future versions may result.
CAS Latencies
CAS Latency = 2, BL = 4
CK
CK
Command
DQS
Read
NOP
NOP
NOP
NOP
NOP
CL=2
DQ
CAS Latency = 2.5, BL = 4
CK
CK
Command
DQS
Read
NOP
NOP
NOP
NOP
NOP
CL=2.5
DQ
CAS Latency = 3, BL = 4
CK
CK
Command
DQS
Read
NOP
NOP
NOP
NOP
NOP
CL=3
DQ
Shown with nominal tAC, tDQSCK and tDQSQ
: Don't care
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A48P3616A
is required during power up initialization, and upon returning
to normal operation after having disabled the DLL for the
purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is
automatically re-enabled upon exit of self refresh operation.
Any time the DLL is enabled, 200 clock cycles must occur to
allow time for the internal clock to lock to the externally
applied clock before a Read command can be issued. This is
the reason for introducing timing parameter tXSRD for DDR
SDRAM’s (Exit Self Refresh to Read Command). Non- Read
commands can be issued 2 clocks after the DLL is enabled
via the EMRS command (tMRD) or 10 clocks after the DLL is
enabled via self refresh exit command (tXSNR, Exit Self
Refresh to Non-Read Command).
Extended Mode Register
The Extended Mode Register controls functions beyond
those controlled by the Mode Register; these additional
functions include DLL enable/disable, bit A0; output drive
strength selection, bit A1. These functions are controlled via
the bit settings shown in the Extended Mode Register
Definition. The Extended Mode Register is programmed via
the Mode Register Set command (with BA0 = 1 and BA1 = 0)
and retains the stored information until it is programmed
again or the device loses power. The Extended Mode
Register must be loaded when all banks are idle, and the
controller must wait the specified time before initiating any
subsequent operation. Violating either of these requirements
result in unspecified operation.
Output Drive Strength
DLL Enable/Disable
The normal drive strength for all outputs is specified to be
SSTL_2, Class II.
The DLL must be enabled for normal operation. DLL enable
Extended Mode Register Definition
BA0
1*
A11
0
A10
0
A9
0
A8
0
A7
0
A6
0
A5
0
A4
0
A3
0
A2
0
A1
A0
Address Bus
BA1
0*
Extended
Mode Register
DS
DLL
Drive Strength
A0
0
DLL
A1
Type
Normal
Week
Enable
Disable
0
1
1
Note:
* BA0 and BA1 must be 1, 0 to select the Extended Mode Register
(vs. the base Mode Register)
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AMIC Technology, Corp.
A48P3616A
Commands
Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM device. A verbal description of each
command follows.
Name (Function)
Address
MNE
Note
CS
H
L
RAS CAS
WE
X
H
H
H
L
Deselect (Nop)
X
H
L
X
H
H
L
X
X
NOP
NOP
ACT
Read
Write
BST
1, 9
1, 9
1, 3
1, 4
1, 4
1, 8
1, 5
No Operation (Nop)
Active (Select Bank And Activate Row)
L
Bank/Row
Bank/Col
Bank/Col
X
Read (Select Bank And Activate Column, And Start Read Burst)
Write (Select Bank And Activate Column, And Start Write Burst)
Burst Terminate
L
H
H
H
L
L
L
L
H
H
L
L
Precharge (Deactivate Row In Bank Or Banks)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
Mode Register Set
L
L
Code
PRE
L
L
H
L
X
AR/SR 1, 6, 7
MRS 1, 2
L
L
L
Op-Code
Note:
1. CKE is high for all commands shown except Self Refresh.
2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0
selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A11 provide the op-code to be written to
the selected Mode Register.)
3. BA0-BA1 provide bank address and A0-A11 provide row address.
4. BA0, BA1 provide bank address; A0-A8 provide column address; A10 high enables the Auto Precharge feature (non-
persistent), A10 low disables the Auto Precharge feature.
5. A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”
6. This command is auto refresh if CKE is high; Self Refresh if CKE is low.
7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts
with Auto Precharge enabled or for write bursts
9. Deselect and NOP are functionally interchangeable.
Truth Table 1b: DM Operation
Name (Function)
Write Enable
Write Inhibit
DM
L
DQs
Valid
X
Note
1
1
H
Note: Used to mask write data; provided coincident with the corresponding data.
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AMIC Technology, Corp.
A48P3616A
Deselect
Write
The Write command is used to initiate a burst write access to
an active (open) row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-A8
selects the starting column location. The value on input A10
determines whether or not Auto Precharge is used.
The Deselect function prevents new commands from
being executed by the DDR SDRAM. The DDR
SDRAM is effectively deselected. Operations already
in progress are not affected.
No Operation (NOP)
If Auto Precharge is selected, the row being accessed is
precharged at the end of the Write burst; if Auto Precharge is
not selected, the row remains open for subsequent accesses.
Input data appearing on the DQs is written to the memory
array subject to the DM input logic level appearing coincident
with the data. If a given DM signal is registered low, the
corresponding data is written to memory; if the DM signal is
registered high, the corresponding data inputs are ignored,
and a Write is not executed to that byte/column location.
The No Operation (NOP) command is used to perform a
NOP to a DDR SDRAM. This prevents unwanted commands
from being registered during idle or wait states. Operations
already in progress are not affected.
Mode Register Set
The mode registers are loaded via inputs A0-A11, BA0 and
BA1 while issuing the Mode Register Set Command. See
mode register descriptions in the Register Definition section.
The Mode Register Set command can only be issued when
all banks are idle and no bursts are in progress. A
subsequent executable command cannot be issued until tMRD
is met.
Precharge
The Precharge command is used to deactivate (close) the
open row in a particular bank or the open row(s) in all banks.
The bank(s) will be available for a subsequent row access a
specified time (tRP) after the Precharge command is issued.
Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. Otherwise BA0,
BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior
to any Read or Write commands being issued to that bank. A
precharge command is treated as a NOP if there is no open
row in that bank, or if the previously open row is already in
the process of precharging.
Active
The Active command is used to open (or activate) a row in a
particular bank for a subsequent access. The value on the
BA0, BA1 inputs selects the bank, and the address provided
on inputs A0-A11 selects the row. This row remains active (or
open) for accesses until a Precharge (or Read or Write with
Auto Precharge) is issued to that bank. A Precharge (or
Read or Write with Auto Precharge) command must be
issued and completed before opening a different row in the
same bank.
Auto Precharge
Auto Precharge is a feature which performs the same
individual-bank precharge function described above, but
without requiring an explicit command. This is accomplished
by using A10 to enable Auto Precharge in conjunction with a
specific Read or Write command. A precharge of the
bank/row that is addressed with the Read or Write command
is automatically performed upon completion of the Read or
Write burst. Auto Precharge is non-persistent in that it is
either enabled or disabled for each individual Read or Write
command. Auto Precharge ensures that the precharge is
initiated at the earliest valid stage within a burst. This is
determined as if an explicit Precharge command was issued
at the earliest possible time without violating tRAS(min). The
user must not issue another command to the same bank until
the precharge (tRP) is completed.
Read
The Read command is used to initiate a burst read access to
an active (open) row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-A8
selects the starting column location. The value on input A10
determines whether or not Auto Precharge is used. If Auto
Precharge is selected, the row being accessed is precharged
at the end of the Read burst; if Auto Precharge is not
selected, the row remains open for subsequent accesses.
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Burst Terminate
Self Refresh
The Burst Terminate command is used to truncate read
bursts (with Auto Precharge disabled). The most recently
registered Read command prior to the Burst Terminate
command is truncated, as shown in the Operation section of
this data sheet. Write burst cycles are not to be terminated
with the Burst Terminate command.
The Self Refresh command can be used to retain data in the
DDR SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the DDR SDRAM retains data
without external clocking. The Self Refresh command is
initiated as an Auto Refresh command coincident with CKE
transitioning low. The DLL is automatically disabled upon
entering Self Refresh, and is automatically enabled upon
exiting Self Refresh (200 clock cycles must then occur before
a Read command can be issued). Input signals except CKE
(low) are “Don’t Care” during Self Refresh operation.
Auto Refresh
Auto Refresh is used during normal operation of the DDR
SDRAM and is analogous to CAS Before RAS (CBR)
Refresh in previous DRAM types. This command is
nonpersistent, so it must be issued each time a refresh is
required.
The procedure for exiting self refresh requires a sequence of
commands. CK (and CK) must be stable prior to CKE
returning high. Once CKE is high, the SDRAM must have
NOP commands issued for tXSNR because time is required
for the completion of any internal refresh in progress. A
simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for 200 clock cycles before
applying any other command.
The refresh addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during
an Auto Refresh command. The 128Mb DDR SDRAM
requires Auto Refresh cycles at an average periodic interval
of 15.6μs (maximum).
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Operations
Bank/Row Activation
During Read bursts, the valid data-out element from the
starting column address is available following the CAS
latency after the Read command. Each subsequent data-out
element is valid nominally at the next positive or negative
clock edge (i.e. at the next crossing of CK and CK). The
following timing figure entitled “Read Burst: CAS Latencies
(Burst Length=4)” illustrates the general timing for each
supported CAS latency setting. DQS is driven by the DDR
SDRAM along with output data. The initial low state on DQS
is known as the read preamble; the low state coincident with
the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other commands
have been initiated, the DQS and DQS goes High-Z. Data
from any Read burst may be concatenated with or truncated
with data from a subsequent Read command. In either case,
a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of
a completed burst or the last desired data element of a
longer burst which is being truncated. The new Read
command should be issued x cycles after the first Read
command, where x equals the number of desired data
element pairs (pairs are required by the 2n prefetch
architecture). This is shown in timing figure entitled
“Consecutive Read Bursts: CAS Latencies (Burst Length =4
or 8)”. A Read command can be initiated on any positive
Before any Read or Write commands can be issued to a
bank within the DDR SDRAM, a row in that bank must be
“opened” (activated). This is accomplished via the Active
command and addresses A0-A11, BA0 and BA1 (see
Activating a Specific Row in a Specific Bank), which decode
and select both the bank and the row to be activated. After
opening a row (issuing an Active command), a Read or Write
command may be issued to that row, subject to the tRCD
specification. A subsequent Active command to a different
row in the same bank can only be issued after the previous
active row has been “closed” (precharged). The minimum
time interval between successive Active commands to the
same bank is defined by tRC. A subsequent Active command
to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row-access
overhead. The minimum time interval between successive
Active commands to different banks is defined by tRRD.
Reads
Subsequent to programming the mode register with CAS
latency, burst type, and burst length, Read bursts are
initiated with a Read command.
The starting column and bank addresses are provided with
the Read command and Auto Precharge is either enabled or
disabled for that burst access. If Auto Precharge is enabled,
the row that is accessed starts precharge at the completion
of the burst, provided tRAS has been satisfied. For the generic
Read commands used in the following illustrations, Auto
Precharge is disabled.
clock cycle following
a
previous Read command.
Nonconsecutive Read data is shown in timing figure entitled
“Non-Consecutive Read Bursts: CAS Latencies (Burst
Length = 4)”. Full-speed Random Read Accesses: CAS
Latencies (Burst Length = 2, 4 or 8) within a page (or pages)
can be performed as shown on page 18.
Activating a Specific Row in a Specific Bank
CK
CK
CKE
CS
HIGH
RAS
CAS
WE
A0-A11
RA
BA
RA = row address
BA = bank address
BA0, BA1
: Don't care
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tRCD and tRRD Definition
CK
CK
Command
A0-A11
ACT
ROW
BA x
NOP
ACT
ROW
BA y
NOP
NOP
RD/WR
COL
NOP
NOP
BA0, BA1
BA y
tRRD
tRCD
: Don't care
Read Command
CK
CK
CKE
CS
HIGH
RAS
CAS
WE
A0-A8
A10
CA
EN AP
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
DIS AP
BA
BA0, BA1
: Don't care
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Read Burst: CAS Latencies (Burst Length = 4)
CAS Latency = 2
CK
CK
Command
Address
Read
NOP
NOP
NOP
NOP
NOP
BA a,
COL n
CL=2
DQS
DQ
DOa-n
CAS Latency = 2.5
CK
CK
Command
Address
Read
NOP
NOP
NOP
NOP
NOP
BA a,
COL n
CL=2.5
DQS
DQ
DOa-n
CAS Latency = 3
CK
CK
Command
Address
Read
NOP
NOP
NOP
NOP
NOP
BA a,
COL n
CL=3
DQS
DQ
DOa-n
: Don't care
DOa-n = data out from bank a, column n.
3 subsequent elements of data out appear in the programmed order following DOa-n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
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Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)
CAS Latency = 2
CK
CK
Command
Address
Read
NOP
Read
NOP
NOP
NOP
BA a,
COL n
BA a,
COL b
CL=2
DQS
DQ
DOa-n
DOa-b
CAS Latency = 2.5
CK
CK
Command
Address
Read
NOP
Read
NOP
NOP
NOP
BA a,
COL n
BA a,
COL b
CL=2.5
DQS
DQ
DOa-n
DOa-b
CAS Latency = 3
CK
CK
Command
Address
Read
NOP
Read
NOP
NOP
NOP
BA a,
COL n
BA a,
COL b
CL=3
DQS
DQ
DOa-n
DOa-b
: Don't care
DOa-n (or a-b) = data out from bank a, column n (or bank a, column b).
When burst length = 4, the bursts are concatenated.
When burst length = 8, the second burst interrupts the first.
3 subsequent elements of data out appear in the programmed order following DOa-n.
3 (or 7) subsequent elements of data out appear in the programmed order following DOa-b.
Shown with nominal tAC, tDQSCK, and tDQSQ.
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Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)
CAS Latency = 2
CK
CK
Command
Address
Read
NOP
NOP
Read
NOP
NOP
BA a,
COL n
BA a,
COL b
CL=2
DQS
DQ
DOa-n
DOa-b
CAS Latency = 2.5
CK
CK
Command
Read
NOP
NOP
Read
NOP
NOP
NOP
BA a,
COL n
BA a,
COL b
Address
CL=2.5
DQS
DQ
DOa-n
DOa-b
CAS Latency = 3
CK
CK
Command
Address
Read
NOP
NOP
Read
NOP
NOP
NOP
BA a,
COL n
BA a,
COL b
CL= 3
DQS
DQ
DOa-n
DOa-b
: Don't care
DOa-n (or a-b) = data out from bank a, column n (or bank a, column b).
3 subsequent elements of data out appear in the programmed order following DOa-n (and following DOa-b).
Shown with nominal tAC, tDQSCK, and tDQSQ.
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Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
CAS Latency = 2
CK
CK
Command
Address
Read
Read
Read
Read
NOP
NOP
BA a,
COL n
BA a,
COL x
BA a,
COL b
BA a,
COL g
CL=2
DQS
DQ
,
,
,
DOa-n
DOa-x
DOa-b
DOa-g
DOa-n
DOa-x
DOa-b
CAS Latency = 2.5
CK
CK
Command
Address
Read
Read
Read
Read
NOP
NOP
BA a,
COL n
BA a,
COL x
BA a,
COL b
BA a,
COL g
CL=2.5
DQS
DQ
,
,
,
DOa-b
DOa-n
DOa-x
DOa-b
DOa-n
DOa-x
CAS Latency = 3
CK
CK
Command
Address
Read
Read
Read
Read
NOP
NOP
BA a,
COL n
BA a,
COL x
BA a,
COL b
BA a,
COL g
CL=3
DQS
DQ
,
,
DOa-n
DOa-x
DOa-b
DOa-n
DOa-x
: Don't care
DOa-n, etc. = data out from bank a, column n etc.
n, etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).
Reads are to active rows in any banks.
Shown with nominal tAC, tDQSCK, and tDQSQ.
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Data from any Read burst may be truncated with a Burst
Terminate command, as shown in timing figure entitled
Terminating a Read Burst: CAS Latencies (Burst Length = 8)
on page 20. The Burst Terminate latency is equal to the read
(CAS) latency, i.e. the Burst Terminate command should be
issued x cycles after the Read command, where x equals the
number of desired data element pairs.
The Precharge command should be issued x cycles after the
Read command, where x equals the number of desired data
element pairs (pairs are required by the 2n prefetch
architecture). This is shown in timing figure Read to
Precharge: CAS Latencies (Burst Length = 4 or 8) on page
22 for Read latencies of 2, 2.5, 3 and 4. Following the
Precharge command, a subsequent command to the same
bank cannot be issued until tRP is met. Note that part of the
row precharge time is hidden during the access of the last
data elements.
Data from any Read burst must be completed or truncated
before a subsequent Write command can be issued. If
truncation is necessary, the Burst Terminate command must
be used, as shown in timing figure entitled Read to Write:
CAS Latencies (Burst Length = 4 or 8) on page 21. The
example is shown for tDQSS(min). The tDQSS(max) case, not
shown here, has a longer bus idle time. tDQSS(min) and
tDQSS(max) are defined in the section on Writes.
In the case of a Read being executed to completion, a
Precharge command issued at the optimum time (as
described above) provides the same operation that would
result from the same Read burst with Auto Precharge
enabled. The disadvantage of the Precharge command is
that it requires that the command and address busses be
available at the appropriate time to issue the command. The
advantage of the Precharge command is that it can be used
to truncate bursts.
A Read burst may be followed by, or truncated with, a
Precharge command to the same bank (provided that Auto
Precharge was not activated).
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Terminating a Read Burst: CAS Latencies (Burst Length = 8)
CAS Latency = 2
CK
CK
Command
Address
Read
NOP
BST
NOP
NOP
NOP
BA a,
COL n
CL=2
DQS
DQ
DOa-n
No further output data after this point.
DQS tristated.
CAS Latency = 2.5
CK
CK
Command
Address
Read
NOP
BST
NOP
NOP
NOP
BA a,
COL n
CL=2.5
DQS
DQ
DOa-n
No further output data after this point.
DQS tristated.
CAS Latency = 3
CK
CK
Command
Address
Read
NOP
BST
NOP
NOP
NOP
BA a,
COL n
CL=3
DQS
DQ
DOa-n
No further output data after this point.
DQS tristated.
: Don't care
DOa-n = data out from bank a, column n.
Cases shown are bursts of 8 terminated after 4 data elements.
3 subsequent elements of data out appear in the programmed order following DOa-n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
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Read to Write: CAS Latencies (Burst Length = 4 or 8)
CAS Latency = 2
CK
CK
Command
Address
Read
BST
NOP
Write
NOP
NOP
BA a,
COL n
BA a,
COL b
tDQSS (min)
CL=2
DQS
DOa-n
DIa-b
DQ
DM
CAS Latency = 2.5
CK
CK
Command
Address
Read
BST
NOP
NOP
Write
NOP
BA a,
COL n
BA a,
COL b
tDQSS (min)
CL=2.5
DQS
DOa-n
DIa-b
DQ
DM
CAS Latency = 3
CK
CK
Command
Address
Read
BST
NOP
NOP
Write
NOP
BA a,
COL n
BA a,
COL b
tDQSS (min)
CL= 3
DQS
DOa-n
DIa-b
DQ
DM
: Don't care
DOa-n = data out from bank a, column n.
DIa-b = data in to bank a, column b.
1 subsequent elements of data out appear in the programmed order following DOa-n.
Data in elements are applied following DIa-b in the programmed order, according to burst length.
Shown with nominal tAC, tDQSCK, and tDQSQ.
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Read to Precharge: CAS Latencies (Burst Length = 4 or 8)
CAS Latency = 2
CK
CK
Command
Read
NOP
PRE
NOP
NOP
ACT
tRP
tRP
tRP
BA a,
ROW
BA a,
BA a or all
Address
COL n
CL=2
DQS
DQ
DOa-n
CAS Latency = 2.5
CK
CK
Command
Read
NOP
PRE
NOP
NOP
ACT
BA a,
ROW
BA a,
COL n
BA a or all
Address
CL=2.5
DQS
DQ
DOa-n
CAS Latency = 3
CK
CK
Command
Read
NOP
PRE
NOP
NOP
ACT
BA a,
ROW
BA a,
COL n
BA a or all
Address
CL= 3
DQS
DQ
DOa-n
: Don't care
DOa-n = data out from bank a, column n.
Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.
3 subsequent elements of data out appear in the programmed order following DOa-n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
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Read with Auto Precharge: CAS Latencies (Burst Length = 4)
CAS Latency = 2
CK
CK
Read with
Auto Precharge
Command
Address
NOP
NOP
NOP
NOP
NOP
tRP
CL=2
DQS
DQ
DOa-n
CAS Latency = 2.5
CK
CK
Read with
Auto Precharge
Command
NOP
NOP
NOP
NOP
ACT
tRP
BA a,
ROW
BA a,
COL n
BA a or all
Address
CL=2.5
DQS
DQ
DOa-n
CAS Latency = 3
CK
CK
Read with
Auto Precharge
Command
NOP
NOP
NOP
NOP
ACT
tRP
BA a,
ROW
BA a,
COL n
BA a or all
Address
CL=3
DQS
DQ
DOa-n
: Don't care
DOa-n = data out from bank a, column n.
Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.
3 subsequent elements of data out appear in the programmed order following DOa-n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
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Writes
Write bursts are initiated with a Write command, as shown in
timing figure Write Command on page 25.
Data for any Write burst may be followed by a subsequent
Read command. To follow a Write without truncating the
write burst, tWTR (Write to Read) should be met as shown in
timing figure Write to Read: Non-Interrupting (CAS Latency =
2; Burst Length = 4) on page 30.
The starting column and bank addresses are provided with
the Write command, and Auto Precharge is either enabled or
disabled for that access. If Auto Precharge is enabled, the
row being accessed is precharged at the completion of the
burst. For the generic Write commands used in the following
illustrations, Auto Precharge is disabled.
Data for any Write burst may be truncated by a subsequent
(interrupting) Read command. This is illustrated in timing
figures “Write to Read: Interrupting (CAS Latency =2; Burst
Length = 8)”, “Write to Read: Minimum DQSS, Odd Number
of Data (3 bit Write), Interrupting (CAS Latency = 2; Burst
During Write bursts, the first valid data-in element is
registered on the first rising edge of DQS following the write
command, and subsequent data elements are registered on
successive edges of DQS. The Low state on DQS between
the Write command and the first rising edge is known as the
write preamble; the Low state on DQS following the last data-
in element is known as the write postamble. The time
between the Write command and the first corresponding
rising edge of DQS (tDQSS) is specified with a relatively wide
range (from 75% to 125% of one clock cycle), so most of the
Write diagrams that follow are drawn for the two extreme
cases (i.e. tDQSS(min) and tDQSS(max)). Timing figure Write Burst
(Burst Length = 4) on page 26 shows the two extremes of
tDQSS for a burst of four. Upon completion of a burst,
assuming no other commands have been initiated, the DQS
and DQS enters High-Z and any additional input data is
ignored.
Length
= 8)”, and “Write to Read: Nominal DQSS,
Interrupting (CAS Latency = 2; Burst Length = 8)”. Note that
only the data-in pairs that are registered prior to the tWTR
period are written to the internal array, and any subsequent
data-in must be masked with DM, as shown in the diagrams
noted previously.
Data for any Write burst may be followed by a subsequent
Precharge command. To follow a Write without truncating the
write burst, tWR should be met as shown in timing figure Write
to Precharge: Non-Interrupting (Burst Length = 4) on page 34.
Data for any Write burst may be truncated by a subsequent
Precharge command, as shown in timing figures Write to
Precharge: Interrupting (Burst Length = 4 or 8) on page 35 to
Write to Precharge: Nominal DQSS (2 bit Write), Interrupting
(Burst Length = 4 or 8) on page 37. Note that only the data-in
pairs that are registered prior to the tWR period are written to
the internal array, and any subsequent data in should be
masked with DM. Following the Precharge command, a
subsequent command to the same bank cannot be issued
until tRP is met.
Data for any Write burst may be concatenated with or
truncated with a subsequent Write command. In either case,
a continuous flow of input data can be maintained. The new
Write command can be issued on any positive edge of clock
following the previous Write command. The first data element
from the new burst is applied after either the last element of a
completed burst or the last desired data element of a longer
burst which is being truncated. The new Write command
should be issued x cycles after the first Write command,
where x equals the number of desired data element pairs
(pairs are required by the 2n prefetch architecture). Timing
figure Write to Write (Burst Length = 4) on page 27 shows
concatenated bursts of 4. An example of nonconsecutive
Writes is shown in timing figure Write to Write: Max DQSS,
Non-Consecutive (Burst Length = 4) on page 28. Full speed
random write accesses within a page or pages can be
performed as shown in timing figure Random Write Cycles
(Burst Length = 2, 4 or 8) on page 29.
In the case of a Write burst being executed to completion, a
Precharge command issued at the optimum time (as
described above) provides the same operation that would
result from the same burst with Auto Precharge. The
disadvantage of the Precharge command is that it requires
that the command and address busses be available at the
appropriate time to issue the command. The advantage of
the Precharge command is that it can be used to truncate
bursts.
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Write Command
CK
CK
CKE
CS
HIGH
RAS
CAS
WE
A0-A8
A10
CA
EN AP
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
DIS AP
BA
BA0, BA1
: Don't care
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Write Burst (Burst Length = 4)
Maximum DQSS
T1
T2
T3
T4
CK
CK
Command
Address
Write
NOP
NOP
NOP
BA a, COL b
tDQSS (max)
DQS
DQ
DIa-b
DM
Minimum DQSS
T1
T2
T3
T4
CK
CK
Command
Address
Write
NOP
NOP
NOP
BA a, COL b
tDQSS (min)
DQS
DQ
DIa-b
DM
: Don't care
DIa-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DIa-b.
A non-interrupted burst is shown.
A10 is Low with the Write command (Auto Precharge is disabled).
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Write to Write (Burst Length = 4)
Maximum DQSS
T5 T6
T1
T2
T3
T4
CK
CK
Command
Address
Write
NOP
Write
NOP
NOP
NOP
BA a,
COL b
BA a,
COL n
tDQSS (max)
DQS
DIa-b
DIa-n
DQ
DM
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Address
Write
NOP
Write
NOP
NOP
NOP
BA a,
COL b
BA a,
COL n
tDQSS (min)
DQS
DIa-b
DIa-n
DQ
DM
: Don't care
DIa-b = data in for bank a, column b, etc.
3 subsequent elements of data in are applied in the programmed order following DIa-b.
3 subsequent elements of data in are applied in the programmed order following DIa-n.
A non-interrupted burst is shown.
Each Write command may be to any bank.
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Write To Write: Max DQSS, Non-Consecutive (Burst Length = 4)
T1
T2
T3
T4
T5
CK
CK
Command
Address
Write
NOP
NOP
Write
NOP
BA a,
COL n
BA a,
COL b
tDQSS (max)
DQS
DIa-b
DIa-n
DQ
DM
: Don't care
DIa-b, etc. = data in for bank a, column b, etc.
3 subsequent elements of data in are applied in the programmed order following DIa-b.
3 subsequent elements of data in are applied in the programmed order following DIa-n.
A non-interrupted burst is shown.
Each Write command may be to any bank.
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Random Write Cycles (Burst Length = 2, 4 or 8)
.
Maximum DQSS
T5
T1
T2
T3
T4
CK
CK
Command
Address
Write
Write
Write
Write
Write
BA a,
COL b
BA a,
COL x
BA a,
COL n
BA a,
COL a
BA a,
COL g
tDQSS (max)
DQS
,
,
,
,
DIa-a
DIa-b
DIa-x
DIa-n
DIa-a
DIa-b
DIa-x
DIa-n
DQ
DM
Minimum DQSS
T1
T2
T3
T4
T5
CK
CK
Command
Address
Write
Write
Write
Write
Write
BA a,
COL b
BA a,
COL x
BA a,
COL n
BA a,
COL a
BA a,
COL g
tDQSS (min)
DQS
,
,
,
,
DIa-b
DIa-x
DIa-n
DIa-a
DIa-g
DIa-x
DIa-n
DIa-a
DIa-b
DQ
DM
: Don't care
DIa-b, etc. = data in for bank a, column b, etc.
,
b , etc. = odd or even complement of b, etc (i.e., column address LSB inverted).
Each Write command may be to any bank.
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Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)
Maximum DQSS
T7
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
NOP
Read
NOP
tWTR
BA a,
COL b
BA a,
COL n
Address
DQS
tDQSS (max)
CL=2
DIa-b
DQ
DM
Minimum DQSS
T7
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
NOP
Read
NOP
tWTR
BA a,
COL b
BA a,
COL n
Address
DQS
CL=2
tDQSS (min)
DIa-b
DQ
DM
: Don't care
DIa-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DIa-b.
A non-interrupted burst is shown.
tWTR is referenced from the first positive CK edge after the last data in pair.
A10 is Low with the Write command (Auto Precharge is disabled).
The Road and Write commands may be to any bank.
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Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)
Maximum DQSS
T7
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
NOP
Read
NOP
tWTR
BA a,
COL b
BA a,
COL n
Address
DQS
tDQSS (max)
CL=2
DIa-b
DQ
DM
1
1
1
1
Minimum DQSS
T7
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
NOP
Read
NOP
tWTR
BA a,
BA a,
COL n
Address
DQS
COL b
tDQSS (min)
CL=2
DIa-b
DQ
DM
1
1
1
1
: Don't care
DIa-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DIa-b.
tWTR is referenced from the first positive CK edge after the last data in pair.
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = These bits are incorrectly written into the memory array if DM is low.
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Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS Latency = 2; Burst Length = 8)
T1
T2
T3
T4
T5
T6
T7
CK
CK
Command
Write
NOP
NOP
NOP
NOP
Read
NOP
tWTR
BA a,
BA a,
COL n
Address
DQS
COL b
tDQSS (min)
CL=2
DIa-b
DQ
DM
1
2
2
2
2
: Don't care
DIa-b = data in for bank a, column b.
An interrupted burst is shown, 3 data elements are written.
2 subsequent elements of data in are applied in the programmed order following DIa-b.
tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element).
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = This bit is correctly written into the memory array if DM is low.
2 = These bits are incorrectly written into the memory array if DM is low.
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Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)
T7
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
NOP
Read
NOP
tWTR
BA a,
BA a,
COL n
Address
DQS
COL b
tDQSS (mon)
CL=2
DIa-b
DQ
DM
1
1
1
1
: Don't care
DIa-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DIa-b.
tWTR is referenced from the first positive CK edge after the last desired data in pair.
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = These bits are incorrectly written into the memory array if DM is low.
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Write to Precharge: Non-Interrupting (Burst Length = 4)
Maximum DQSS
T5 T6
T1
T2
T3
T4
CK
CK
Command
Write
NOP
NOP
NOP
NOP
PRE
tWR
BA a,
COL b
BA(a or all)
Address
DQS
tDQSS (max)
tRP
DIa-b
DQ
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
NOP
PRE
tWR
BA a,
BA(a or all)
Address
DQS
COL b
tDQSS (min)
tRP
DIa-b
DQ
DM
: Don't care
DIa-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DIa-b.
A non-interrupted burst is shown.
tWR is referenced from the first positive CK edge after the last data in pair.
A10 is Low with the Write command (Auto Precharge is disabled).
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Write to Precharge: Interrupting (Burst Length = 4 or 8)
Maximum DQSS
T5 T6
T1
T2
T3
T4
CK
CK
Command
Write
NOP
NOP
NOP
PRE
NOP
tWR
BA a,
COL b
BA(a or all)
Address
DQS
tDQSS (max)
tRP
2
DIa-b
DQ
DM
3
3
1
1
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
PRE
NOP
tWR
BA a,
BA(a or all)
Address
DQS
COL b
tDQSS (min)
tRP
2
DIa-b
DQ
DM
3
3
1
1
: Don't care
DIa-b = data in for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DIa-b.
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst, for burst length = 8.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be do not care for programmed bust length of 4.
2 = For programmed bust length of 4, DQS becomes do not care at this point.
3 = These bits are incorrectly written into the memory array if DM is low.
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Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting (Burst Length = 4 or 8)
T1
T2
T3
T4
T5
T6
CK
CK
Command
Address
DQS
Write
NOP
NOP
NOP
PRE
NOP
tWR
BA a,
COL b
BA(a or all)
tDQSS (min)
tRP
2
DIa-b
DQ
DM
3
4
4
1
1
: Don't care
DIa-b = data in for bank a, column b.
An interrupted burst is shown, 1 data elements are written.
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be do not care for programmed bust length of 4.
2 = For programmed bust length of 4, DQS becomes do not care at this point.
3 = This bit is correctly written into the memory array if DM is low.
4 = These bits are incorrectly written into the memory array if DM is low.
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Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)
T1
T2
T3
T4
T5
T6
CK
CK
Command
Address
DQS
Write
NOP
NOP
NOP
PRE
NOP
tWR
BA a,
COL b
BA(a or all)
tDQSS (min)
tRP
2
DIa-b
DQ
DM
1
1
3
3
: Don't care
DIa-b = data in for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DIa-b
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be do not care for programmed bust length of 4.
2 = For programmed bust length of 4, DQS becomes do not care at this point.
3 = These bits are incorrectly written into the memory array if DM is low.
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Precharge
The Precharge command is used to deactivate the open row
in a particular bank or the open row in all banks. The bank(s)
is available for a subsequent row access some specified time
(tRP) after the Precharge command is issued. Input A10
determines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged,
inputs BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
must be activated prior to any Read or Write commands being
issued to that bank.
Precharge Command
CK
CK
CKE
CS
HIGH
RAS
CAS
WE
A0-A9, A11
A10
All Banks
BA = bank address
One Bank
BA
(if A10 is Low, otherwise Don't Care)
BA0, BA1
: Don't care
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Power Down
Power Down is entered when CKE is registered low (no
accesses can be in progress). If Power Down occurs when
all banks are idle, this mode is referred to as Precharge
Power Down; if Power Down occurs when there is a row
active in any bank, this mode is referred to as Active
Power Down. Entering Power Down deactivates the input
and output buffers, excluding CK, CK and CKE. The DLL is
still running in Power Down mode, so for maximum power
savings, the user has the option of disabling the DLL prior
to entering Power Down. In that case, the DLL must be
enabled after exiting Power Down, and 200 clock cycles
must occur before a Read command can be issued.
In Power Down mode, CKE Low and a stable clock signal
must be maintained at the inputs of the DDR SDRAM, and
all other input signals are “Don’t Care”. However, Power
Down duration is limited by the refresh requirements of the
device, so in most applications, the self refresh mode is
preferred over the DLL-disabled Power Down mode.
The Power Down state is synchronously exited when CKE
is registered high (along with a Nop or Deselect command).
A valid, executable command may be applied one clock
cycle later.
Power Down
CK
CK
tIS
tIS
CKE
Command
VALID
NOP
NOP
VALID
No column
access in
progress
Exit
power down
mode
tXPNR/
tXPRD
Enter Power Down mode
(Burst Read or Write operation
must not be in progress)
: Don't care
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Truth Table 2: Clock Enable (CKE)
CKE n-1
Current
CKE n
Command n
Action n
Note
Previous Cycle Previous Cycle
Self Refresh
Self Refresh
Power Down
Power Down
All Banks Idle
All Banks Idle
Bank(s) Active
L
L
L
H
L
X
Maintain Self-Refresh
Exit Self-Refresh
Deselect or NOP
X
1
L
Maintain Power Down
Exit Power Down
L
H
L
Deselect or NOP
Deselect or NOP
Auto Refresh
Deselect or NOP
H
H
H
Precharge Power Down Entry
Self Refresh Entry
L
L
Active Power Down Entry
See “Truth Table 3: Current State
Bank n - Command to Bank n
(Same Bank)” on page 41
H
H
Note:
1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. Command n is the command registered at clock edge n, and action n is a result of command n.
4. All states and sequences not shown are illegal or reserved.
5. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A
minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
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Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State
Command
Action
Note
CS
RAS CAS
WE
NOP. Continue previous operation
H
X
X
X
Deselect
1-6
Any
NOP. Continue previous operation
Select and Activate Row
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
L
H
H
H
L
No Operation
Active
1-6
1-6
Idle
L
Auto Refresh
Mode Register Set
Read
1-7
L
L
1-7
H
H
L
L
H
L
Select column and start Read Burst
Select column and start Write Burst
Deactivate row in bank(s)
1-6, 10
1-6, 10
1-6, 8
Row Active
Read
L
Write
H
L
L
Precharge
Read
H
L
H
L
Select column and start new Read Burst
1-6, 10
1-6, 8
H
H
L
Precharge
Burst Terminate
Read
(Auto Precharge
Disabled)
Burst Terminate
H
H
H
L
L
1-6, 9
H
L
Select column and start Read Burst
Select column and start Write Burst
Truncate Write burst, start Precharge
1-6, 10, 11
1-6, 10
Write
L
Write
(Auto Precharge
Disabled)
H
L
Precharge
1-6, 8, 11
Note:
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD
has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses
are in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle
state.
Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the
“row active” state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when
tRP has been met. Once tRP is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when
tRP has been met. Once tRP is met, the bank is in the idle state.
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during
these states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.
5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on
each positive clock edge during these states.
Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR
SDRAM is in the “all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once
tMRD is met, the DDR SDRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in
the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.
10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or
Writes with Auto Precharge disabled.
11. Requires appropriate DM masking.
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Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
Current State
Command
Action
Note
CS
RAS CAS
WE
NOP/Continue previous operation
H
L
X
H
X
X
H
X
X
H
X
Deselect
1-6
1-6
1-6
1-6
Any
NOP/Continue previous operation
No Operation
Any Command Otherwise
Allowed to Bank m
Idle
X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
L
Active
Read
Select and Activate Row
Row Activating,
Active, or
Precharging
Select column and start Read Burst
Select column and start Write Burst
1-7
1-7
1-6
1-6
1-7
1-6
1-6
1-8
1-7
1-6
L
Write
H
H
L
L
Precharge
Active
Select and Activate Row
L
H
H
L
Read
H
L
Read
Select column and start new Read Burst
(Auto Precharge
Disabled)
H
H
L
Precharge
Active
Select and Activate Row
L
H
H
L
Write
H
H
L
Read
Select column and start Read Burst
Select column and start new Write Burst
(Auto Precharge
Disabled)
L
Write
H
L
Precharge
Note:
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD
has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is
allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses
are in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or
Writes with Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the
access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same
burst was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still
accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR
measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where
the precharge period (or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with
Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to the other bank may be applied; during
the access period, only Active and Precharge commands to the other bank may be applied. In either case, all other related
limitations apply (e.g. contention between Read data and Write data must be avoided).
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Truth Table 5: Current State Bank n - Command to Bank m (Different bank) (continued)
Current State
Command
Action
Note
CS
RAS CAS
WE
Select and Activate Row
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
L
Active
Read
1-6
Read
Select column and start new Read Burst
Select column and start Write Burst
1-7, 10
1-7, 9, 10
1-6
(With Auto
Precharge)
L
Write
H
H
L
L
Precharge
Active
Select and Activate Row
L
H
H
L
1-6
Write
H
H
L
Read
Select column and start Read Burst
Select column and start new Write Burst
1-7, 10
1-7, 10
1-6
(With Auto
Precharge)
L
Write
H
L
Precharge
Note:
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD
has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is
allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses
are in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or
Writes with Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the
access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst
was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still
accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR
measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where
the precharge period (or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with
Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to the other bank may be applied; during
the access period, only Active and Precharge commands to the other bank may be applied. In either case, all other related
limitations apply (e.g. contention between Read data and Write data must be avoided).
PRELIMINARY (July, 2010, Version 0.0)
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AMIC Technology, Corp.
A48P3616A
Simplified State Diagram
Power
Applied
Power
On
PREALL
Precharge
Preall
Self
Refresh
REFS
MRS
REFSX
MRS
MRS
EMRS
REFA
Auto
Refresh
Idle
CKEL
CKEH
Active
Power
Down
ACT
Precharge
Power
Down
CKEH
CKEL
Burst Stop
Row
Active
Write
Read
Read A
Read
Write A
White
Read
Write A
Read A
Read A
PRE
White A
Read A
PRE
PRE
Precharge
Preall
PRE
Automatic Sequence
Command Sequence
PREALL = Precharge All Banks
MRS = Mode Register Set
EMRS = Extended Mode Register Set
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
REFA = Auto Refresh
CKEL = Enter Power Down
CKEH = Exit Power Down
ACT = Active
Write A = Write with Autoprecharge
Read A = Read with Autoprecharge
PRE = Precharge
PRELIMINARY (July, 2010, Version 0.0)
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AMIC Technology, Corp.
A48P3616A
Absolute Maximum Ratings*
Symbol
Parameter
Rating
Unit
VIN, VOUT
VIN
Voltage on I/O pins relative to VSSQ
Voltage on Inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSSQ
Operating Temperature (Ambient)
Storage Temperature (Plastic)
Power Dissipation at TA = 25°C
Output Current
V
V
-0.5 to VDDQ + 0.5
-1 to 3.6
-1 to 3.6
-1 to 3.6
0 to +70
-55 to +150
1
VDD
V
VDDQ
TA
V
°C
°C
W
mA
TATG
PD
IOUT
50
Notes: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Capacitance
Parameter
Symbol
Min
Max
Unit
Note
CI1
2.5
3.5
pF
1
Input Capacitance: CK,
CK
Delta CI1
0.25
pF
1
Delta Input Capacitance: CK,
CK
Input Capacitance: All Other Input-only pins (except DM)
Delta Input Capacitance: All Other Input-only pins (except DM)
Input/Output Capacitance: DQ, DQS, DM
CI2
2.5
4.0
3.5
1.0
5.0
1.0
pF
pF
pF
pF
1
1
Delta CI2
CI/O
1.2
1
Delta Input/Output Capacitance: DQ, DQS, DM
Delta CI/O
Notes:
1. VDDQ = VDD = 2.5V ± 0.2V (minimum range to maximum range), f = 100MHz, TA = 25°C, VODC = VDDQ/2, VOPeak -Peak = 0.2V.
2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.
This is required to match input propagation times of DQ, DQS and DM in the system.
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AMIC Technology, Corp.
A48P3616A
DC Electrical Characteristics and Operating Conditions
(TA = 0ºC to +70ºC for commercial or TA =-40ºC to +85ºC for industrial; VDDQ = 2.5V ± 0.2V, VDD = + 2.5V ± 0.2V)
Symbol
Parameter
Min
Max
Unit Note
VDD
Supply Voltage
2.3
2.3
2.7
2.7
V
V
1
1
VDDQ
I/O Supply Voltage
Supply Voltage
VSS, VSSQ
0
0
V
I/O Supply Voltage
I/O Reference Voltage
VREF
VTT
0.49 x VDDQ
VREF - 0.04
VREF + 0.15
-0.3
0.51 x VDDQ
VREF + 0.04
VDDQ + 0.3
VREF - 0.15
V
V
V
V
1.2
1.3
1
I/O Termination Voltage (System)
Input High Voltage
VIH (DC)
VIL (DC)
Input Low Voltage
1
VIN (DC)
VID (DC)
-0.3
VDDQ + 0.3
VDDQ + 0.6
V
V
1
Input Voltage Level, CK and
Inputs
CK
0.36
1.4
Input Differential Voltage, CK and
Input Leakage Current
Inputs
CK
μA
μA
mA
II
-2
-5
2
5
1
1
1
Any Input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V)
Output Leakage Current
(DQs are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
IOH
IOL
High current (VOUT= 1.95V)
Low current (VOUT= 0.35V)
-16.2
16.2
Notes:
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-
to-peak noise on VREF may not exceed ± 2% of the DC value.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK .
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AMIC Technology, Corp.
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AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to
VREF (or to the crossing point for CK, CK ), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a
result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input low (high) level.
AC Output Load Circuit Diagrams
VTT = VREF
DQS
VREF
VREF
50Ω
Z0 =
VOUT
50Ω
30pF
DQ
VREF
Output Timing
Measurement
Reference Point
AC Input Operating Conditions
(TA = 0ºC to +70ºC for commercial or TA =-40ºC to +85ºC for industrial; VDD = VDDQ = 2.5V ± 0.2V)
Symbol
Parameter/Condition
Min
Max
Unit
Note
VIH (AC)
VIL (AC)
VID (AC)
VIX (AC)
Input High Voltage, DQ, DQS, and DM Signals
Input Low Voltage, DQ, DQS, and DM Signals
VREF + 0.31
V
V
V
V
1, 2
1, 2
VREF – 0.31
VDDQ + 0.6
0.7
1, 2, 3
1, 2, 4
Input Differential Voltage, CK and CK Inputs
Input Crossing Point Voltage, CK and CK Inputs
0.5*VDDQ – 0.2 0.5* VDDQ + 0.2
Notes: 1. Input slew rate = 1V/ns.
2. Inputs are not recognized as valid until VREF stabilizes.
CK
3. VID is the magnitude of the difference between the input level on CK and the input level on
.
4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of
the same.
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AMIC Technology, Corp.
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IDD Specifications and Conditions
(TA = 0ºC to +70ºC for commercial or TA =-40ºC to +85ºC for industrial; VDD = VDDQ = 2.5V ± 0.2V, Output Open, unless
otherwise noted)
Limits (Max.)
Parameter / Test Condition
Unit
Symbol
Note
-4
-5
OPERATING CURRENT FOR ONE BANK ACTIVE-PRECHARGE: One
bank active-precharge; tRC = tRC(min); tCK = tCK(min); DQ, DQS and DM
inputs changing once per clock cycle; Address and control inputs
IDD0
140
135
mA
changing once every two clock cycles; CS = HIGH between valid
commands
OPERATING CURRENTFOR ONE BANK OPERATION: One bank
active-read-precharge; Burst Length = 4; tRC = tRC(min); tCK = tCK(min);
IOUT= 0mA; Address and control inputs changing once per clock cycle;
IDD1
155
150
mA
CS = HIGH between valid commands; 50% of data changing on every
transfer
PRECHARGE POWER DOWN STANDBY CURRENT: All banks idle;
Power Down mode; CKE ≤ VIL(max); tCK = tCK(min); VIN = VREF for DQ,
DQS, and DM
IDD2P
IDD2F
30
65
30
65
mA
mA
PRECHARGE FLOATING STANDBY CURRENT: CS ≥ VIH(min); All
banks idle; CKE ≥ VIH(min); tCK = tCK(min); Address and other control
inputs changing once per clock cycle; VIN = VREF for DQ, DQS, and DM
PRECHARGE QUIET STANDBY CURRENT: CS ≥ VIH(min); All banks
idle; CKE ≥ VIH(min); tCK = tCK(min); Address and other control inputs
stable at ≥ VIH(min) or ≤ VIL(max); VIN = VREF for DQ, DQS, and DM
IDD2Q
IDD3P
60
40
60
40
mA
mA
ACTIVE POWER DOWN STANDBY CURRENT: One bank active; Power
Down mode; CKE ≤ VIL(max); tCK = tCK(min); VIN = VREF for DQ, DQS, and
DM
ACTIVE STANDBY CURRENT: CS ≥ VIH(min); CKE ≥ VIH(min); One
bank active; tRC = tRAS(max); tCK = tCK(min); DQ, DQS and DM inputs
changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
IDD3N
IDD4R
IDD4W
115
195
180
115
180
165
mA
mA
mA
OPERATING CURRENT FOR BURST READ: Burst Length = 2; Read;
Continuous burst; One bank active; Address and control inputs changing
once per clock cycle; tCK = tCK(min); 50% of data changing on every
transfer; IOUT = 0mA
OPERATING CURRENTFOR BURST WRITE: Burst Length = 2; Write ;
Continuous burst; One bank active; Address and control inputs changing
once per clock cycle; tCK = tCK(min); DQ, DQS, and DM inputs changing
twice per clock cycle; 50% of input data changing at every transfer
IDD5
IDD6
AUTO REFRESH CURRENT: tRC = tRFC(min)
155
5
150
5
mA
mA
SELF REFRESH CURRENT: CKE ≤ 0.2V, tCK = tCK(min)
OPERATING CURRENT FOR FOUR BANK OPERATION: four bank
interleaving with Burst Length = 4, refer to note.22 for detailed test
condition
IDD7
295
295
mA
22
PRELIMINARY (July, 2010, Version 0.0)
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AMIC Technology, Corp.
A48P3616A
Electrical Characteristics & AC Timing - Absolute Specifications
(TA = 0ºC to +70ºC for commercial or TA =-40ºC to +85ºC for industrial; VDD = VDDQ = 2.5V ±0.2V)
-4
-5
Symbol
AC Characteristics Parameter
Unit
Note
Max
Min
Max
Min
tAC
-0.70
+0.70
-0.70
+0.70
ns
ns
DQ output access time from CK / CK
tDQSCK
-0.6
+0.6
-0.6
+0.6
DQS output access time from CK / CK
CK HIGH level width
tCH
tCL
0.45
0.45
4
0.55
0.55
12
0.45
0.45
-
0.55
0.55
-
tCK
tCK
CK LOW level width
CL=4.0
CL=3.0
CL=2.5
CL=2.0
4
12
5
12
tCK
Clock cycle time
ns
5
12
6
12
7.5
0.4
0.4
2.2
1.75
12
7.5
0.4
0.4
2.2
1.75
12
tDS
tDH
Input setup time (DQ,DM)
Input hold time (DQ,DM)
ns
ns
ns
ns
tIPW
tDIPW
Control & address input pulse width (for each input)
DQ and DM input pulse width (for each input)
tHZ
+0.70
+0.70
ns
14
14
Data-out high impedance time from CK / CK
tLZ
-0.70
+0.70
0.40
-0.70
+0.70
0.40
ns
ns
Data-out low impedance time from CK / CK
DQ valid data delay time from DQS
tDQSQ
tCLmin or
tCHmin
tCLmin or
tCHmin
tHP
Clock half period
ns
20
tQH
tQHS
DQ output hold time from DQS (per access)
Data hold skew factor (for DQS & associated DQ signals)
Write command to first DQS latching transition
DQS input HIGH level width
tHP-tQHS
tHP-tQHS
ns
ns
0.50
1.15
0.50
1.25
tDQSS
tDQSH
tDQSL
tDSS
0.72
0.35
0.35
0.25
0.2
2
0.72
0.35
0.35
0.2
0.2
2
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS input LOW level width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode Register Set command cycle time
Write preamble setup time
tDSH
tMRD
tWPRES
tWPST
0
0
16
15
Write postamble
0.4
0.6
0.4
0.6
tCK
max(0.25*
tCK, 1.5ns)
max(0.25*
tCK, 1.5ns)
tWPRE
Write preamble
ns
tIS
tIH
Input Setup time (address and control)
Input Hold time (address and control)
Read postamble
0.6
0.6
0.4
0.9
0.6
0.6
0.4
0.9
ns
ns
19
19
tRPST
tRPRE
0.6
1.1
0.6
1.1
tCK
tCK
Read preamble
PRELIMINARY (July, 2010, Version 0.0)
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AMIC Technology, Corp.
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Electrical Characteristics & AC Timing - Absolute Specifications (continued)
(TA = 0ºC to +70ºC for commercial or TA =-40ºC to +85ºC for industrial; VDD = VDDQ = 2.5V ±0.2V)
-4
-5
Symbol
Unit
Note
AC Characteristics Parameter
Max
Min
40
Max
Min
40
tRAS
tRC
Row active time
120,000
120,000
ns
ns
ns
ns
Row cycle time(operation)
55
55
tRFC
Auto Refresh to Active/Auto Refresh command period
Row to column delay
70
70
tRCD
tRP
15
15
Row precharge time
15
10
15
15
10
15
ns
ns
ns
tCK
tCK
ns
tRRD
tWR
Act to Act delay time
Write recovery time
tDAL
tWTR
tXSNR
Auto Precharge write recovery + precharge time
Internal Write to Read command delay
Exit Self Refresh to non-Read command
21
2
2
75
75
tXSRD
tXPNR
tXPRD
tREFI
Exit Self Refresh to Read command
Exit Power Down to command
200
1
200
1
tCK
tCK
tCK
μs
Exit Power Down to Read command
Average periodic refresh interval
1
1
18
17
15.6
15.6
Notes:
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to
VREF (or to the crossing point for CK / CK ), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC).
4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch as a
result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above
(below) the DC input LOW (HIGH) level.
5. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-
to-peak noise on VREF may not exceed +2% of the DC value.
6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF.
7. VID is the magnitude of the difference between the input level on CK and the input level on CK .
8. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is properly initialized.
11. The CI1, CI2, CI/O are sampled. VDDQ = 2.5V+0.2V, VDD = 2.5V+0.2V, f =100MHz, TA = 25°C, VOUT(DC) = VDDQ/2,
VOUT(PEAK TO PEAK) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to
facilitate trace matching at the board level).
12. The CK / CK input reference level (for timing referenced to CK / CK ) is the point at which CK and CK cross; the input
reference level for signals other than CK / CK , is VREF.
13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CE ≤ 0.3 VDDQ is
recognized as LOW.
14. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ).
PRELIMINARY (July, 2010, Version 0.0)
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AMIC Technology, Corp.
A48P3616A
15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device.
When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous
write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
18. tXPRD should be 200 tCLK in the condition of the unstable CK operation during the Power Down mode.
19. For command/address and CK & CK slew rate > 1.0V/ns.
20. Min (tCL,tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device.
21. tDALminimum = (tWR/tCK) + (tRP/tCK).
For each of the terms above, if not already an integer, round to the next highest integer.
22. Operating current for four bank operation: Four banks are being interleaved with tRC(min), Burst Mode, Address and Control
inputs on Deselect edge are not changing. IOUT = 0mA.
Test pattern for -5 (200MHz, CL = 3, tCK = 5ns, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, tRC = 11*tCK);
Setup; A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N
Read; A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N
Test pattern for -4 (250MHz, CL = 3, tCK = 4ns, BL = 4, tRRD = 3*tCK, tRCD = 4*tCK, tRC = 14*tCK);
Setup; A0 N N A1 RA0 N A2 RA1 N A3 RA2 N N RA3
Read; A0 N N A1 RA0 N A2 RA1 N A3 RA2 N N RA3
Repeat the same timing with random address changing, 50% of data changing at every transfer.
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Data Input (Write) (Timing Burst Length = 4)
tDSL
tDSH
DQS
tDH
tDH
tDS
DQ
DM
DIn
tDS
: Don't care
DIn = Data in for column n.
3 subsequent elements of data in are applied in programmed order following DIn.
Data Output (Read) (Timing Burst Length = 4)
CK
CK
tHP
tHP
tHP
tHP1
tHP2
tHP3
tQH3
tHP4
tQH4
DQS
tDQSQ
tQH2
tDQSQ
tDQSQ
tQH1
DQ
tDQSQ
tHP is the half cycle pulse width for each half cycle clock. tHP is referenced to the clock duty cycle only
and not to the data strobe (DQS) duty cycle.
Data Output hold time from Data Strobe is shown as tQH. tQH is a function of the clock high or low time
(tHP) for that given clock cycle. Note correlation of tHP to tQH in the diagram above (tHP1 to tQH1. etc.).
tDQSQ (max) occurs when DQS is the earliest among DQS and DQ signals to transition.
PRELIMINARY (July, 2010, Version 0.0)
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AMIC Technology, Corp.
A48P3616A
Initialize and Mode Register Sets
~
~
~
~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~ ~
~ ~ ~
~
~
~
~
~
~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~ ~ ~
~ ~ ~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~
~
~ ~
~ ~
~ ~
~ ~
~ ~ ~
~ ~ ~
~
~
~
~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~
~
~
~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~
~
~
~
~
~
~ ~
~ ~
~ ~
~ ~
PRELIMINARY (July, 2010, Version 0.0)
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AMIC Technology, Corp.
A48P3616A
Power Down Mode
~ ~
~ ~
~
~
~ ~
~ ~
~ ~ ~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~ ~ ~
PRELIMINARY (July, 2010, Version 0.0)
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AMIC Technology, Corp.
A48P3616A
Auto Refresh Mode
~ ~
~ ~
~ ~
~ ~
~ ~ ~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~ ~ ~
~ ~
~ ~
~ ~
~ ~
~ ~ ~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~ ~ ~
PRELIMINARY (July, 2010, Version 0.0)
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AMIC Technology, Corp.
A48P3616A
Self Refresh Mode
~ ~
~ ~
~
~
~ ~
~ ~
~ ~ ~ ~ ~ ~
~ ~
~ ~ ~ ~ ~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~ ~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~ ~ ~
~ ~
~ ~
~
~
~ ~
~ ~
~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~
~ ~
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PRELIMINARY (July, 2010, Version 0.0)
56
AMIC Technology, Corp.
A48P3616A
Read without Auto Precharge (Burst Length = 4)
PRELIMINARY (July, 2010, Version 0.0)
57
AMIC Technology, Corp.
A48P3616A
Read with Auto Precharge (Burst Length = 4)
PRELIMINARY (July, 2010, Version 0.0)
58
AMIC Technology, Corp.
A48P3616A
Bank Read Access (Burst Length = 4)
PRELIMINARY (July, 2010, Version 0.0)
59
AMIC Technology, Corp.
A48P3616A
Write without Auto Precharge (Burst Length = 4)
PRELIMINARY (July, 2010, Version 0.0)
60
AMIC Technology, Corp.
A48P3616A
Write with Auto Precharge (Burst Length = 4)
PRELIMINARY (July, 2010, Version 0.0)
61
AMIC Technology, Corp.
A48P3616A
Bank Write Access (Burst Length = 4)
PRELIMINARY (July, 2010, Version 0.0)
62
AMIC Technology, Corp.
A48P3616A
Write DM Operation (Burst Length = 4)
PRELIMINARY (July, 2010, Version 0.0)
63
AMIC Technology, Corp.
A48P3616A
Ordering Information
Part No.
Speed
Org.
Comments
Package
Clock(MHz)
66PIN TSOP
Pb-Free
A48P3616AV-4F
A48P3616AV-4UF
A48P3616AV-5F
A48P3616AV-5UF
8M x 16
250
200
DDR500
66PIN TSOP
Pb-Free
66PIN TSOP
Pb-Free
8M x 16
DDR400
66PIN TSOP
Pb-Free
Note: -U is for industrial operating temperature range -40ºC to +85ºC.
PRELIMINARY (July, 2010, Version 0.0)
64
AMIC Technology, Corp.
A48P3616A
Package Information
TSOP 66L TYPE II (10.16 x 22.22mm) Outline Dimensions
unit: mm
Detail "A"
66
34
1
33
D
ZD
θ
A1
e
L
b
C
0.10
C
Detail "A"
Dimensions in mm
Symbol
Min
-
Nom
Max
1.20
0.15
1.05
0.38
0.21
22.32
11.96
10.26
0.60
A
A1
A2
b
-
0.05
0.95
0.22
0.12
22.12
11.56
10.06
0.40
-
1.00
-
c
-
D
22.22
11.76
10.16
0.50
0.65 BSC
-
E
E1
L
e
0°
8°
θ
ZD
0.71 REF
Notes:
1. Dimension D does not include mold protrusions or gate burrs.
2. Dimension E1 does not include interlead mold protrusions.
3. Dimension b does not include damber protrusion / intrusion.
4. All dimensions and tolerances take reference to JEDEC MS-024 FC.
PRELIMINARY (July, 2010, Version 0.0)
65
AMIC Technology, Corp.
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