A627308 [AMICC]
128K X 8 BIT CMOS SRAM; 128K ×8位CMOS SRAM
| 型号： | A627308 |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 128K X 8 BIT CMOS SRAM |
| 文件： | 总16页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A627308 Series
Preliminary
128K X 8 BIT CMOS SRAM
Document Title
128K X 8 BIT CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
Initial issue
August 15, 2000
October 25, 2000
Preliminary
Omit 100ns grade items
Change ICC1 from 70mA to 45mA
Change ISB1 from 25mA to 15mA
Change ISB1 from 15mA to 25mA
0.2
February 6, 2001
PRELIMINARY
(February, 2001, Version 0.2)
AMIC Technology, Inc.
A627308 Series
Preliminary
128K X 8 BIT CMOS SRAM
Features
n Power supply range: 4.5V to 5.5V
n Access times: 70 ns (max.)
n Current:
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy
application
Operating: 45mA (max.)
Standby: 25mA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL compatible
n Data retention voltage: 2V (min.)
n Available in 32-pin SOP, TSOP, sTSOP (8X
13.4mm) forward type packages
General Description
The A627308 is a low operating current 1048,576-bit
static random access memory organized as 131,072
words by 8 bits and operates on a power supply voltage
from 4.5V to 5.5V.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable inputs are provided for power down and
a write enable and an output enable input are included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
n SOP
n TSOP/(sTSOP)
(forward type)
NC
1
VCC
A15
CE2
32
31
30
A16
A14
A12
A7
2
3
A11
A9
A8
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
WE
A13
A8
4
29
28
27
26
7
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
I/O
5
6
6
I/O
A6
5
I/O
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
A5
A4
A3
A2
A9
7
A627308V
(A627308X)
8
A11
OE
25
24
23
22
9
10
11
12
13
14
15
16
9
A10
10
11
12
13
14
15
16
CE1
A1
A0
A6
A5
A4
I/O7
21
20
19
18
17
I/O 0
I/O 1
I/O 2
GND
I/O6
I/O5
I/O4
I/O3
PRELIMINARY
(February, 2001, Version 0.2)
1
AMIC Technology, Inc.
A627308 Series
Block Diagram
VCC
GND
A0
ROW
512 X 2048
A14
A15
A16
DECODER
MEMORY ARRAY
I/O0
COLUMN I/O
INPUT DATA
CIRCUIT
I/O7
CE2
CE1
OE
CONTROL
CIRCUIT
WE
Pin Descriptions - SOP
Pin Description - TSOP/sTSOP
Pin No.
Symbol
Description
Pin No.
Symbol
Description
2 - 12, 23,
25 - 28, 31
1 - 4, 7,
10 - 20, 31
A0 - A16
Address Inputs
A0 - A16
Address Inputs
13 - 15,
17 - 21
21 - 23,
25 - 29
I/O0 - I/O7
Data Inputs/Outputs
Chip Enable 1
I/O0 - I/O7
Data Inputs/Outputs
Chip Enable 1
22
30
CE1
CE2
CE1
CE2
30
24
Chip Enable 2
Output Enable
6
Chip Enable 2
Output Enable
32
OE
OE
29
Write Enable
5
Write Enable
WE
VCC
GND
NC
WE
VCC
GND
NC
32
16
1
Power Supply
Ground
8
24
9
Power Supply
Ground
No Connection
No Connection
PRELIMINARY
(February, 2001, Version 0.2)
2
AMIC Technology, Inc.
A627308 Series
Recommended DC Operating Conditions
(TA = 0°C to + 70°C)
Symbol
VCC
GND
VIH
Parameter
Supply Voltage
Min.
4.5
0
Typ.
Max.
Unit
V
5.0
5.5
Ground
0
-
0
V
Input High Voltage
Input Low Voltage
Output Load
2.2
-0.5
-
VCC + 0.5
V
VIL
-
+0.8
30
1
V
CL
-
pF
-
TTL
Output Load
-
-
Absolute Maximum Ratings*
*Comments
VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +
7.0V
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC + 0.5V
Operating Temperature, Topr . . . . . . . . -25°C to + 85°C
Storage Temperature, Tstg . .. . . . . . . . -55°C to + 125°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . . 260°C, 10 sec
DC Electrical Characteristics (TA = 0°C to + 70°C, VCC = 5.0V±10%, GND = 0V)
A627308-70S
Symbol
Parameter
Unit
Conditions
Min.
Max.
Input Leakage Current
Output Leakage Current
-
1
VIN = GND to VCC
çILIú
mA
mA
CE1 = VIH or CE2 = VIL or
-
-
-
1
7
çILOú
OE = VIH or WE = VIL
VI/O = GND to VCC
Active Power Supply Current
Dynamic Operating Current
CE1 = VIL, CE2 = VIH
II/O = 0mA
ICC
mA
mA
Min. Cycle, Duty = 100%
ICC1
45
CE1 = VIL, CE2 = VIH
II/O = 0mA
CE1 = VIL, CE2 = VIH
VIH = VCC , VIL = 0V
F = 1MHz, II/O = 0mA
Dynamic Operating Current
ICC2
-
7
mA
PRELIMINARY
(February, 2001, Version 0.2)
3
AMIC Technology, Inc.
A627308 Series
DC Electrical Characteristics (continued)
A627308-70S
Symbol
Parameter
Unit
Conditions
Min.
Max.
CE1 = VIH or
CE2 = VIL
ISB
-
-
0.5
mA
Standby Power
Supply Current
CE2 £ 0.2V, or
ISB1
25
mA
³ VCC - 0.2V
CE1
VOL
VOH
Output Low Voltage
Output High Voltage
-
0.4
-
V
V
IOL = 2.1mA
2.4
IOH = -1.0mA
Truth Table
Mode
CE2
X
I/O Operation
High Z
High Z
High Z
DOUT
Supply Current
CE1
H
OE
X
WE
X
ISB, ISB1
Standby
X
L
X
X
ISB, ISB1
Output Disable
Read
L
L
L
H
H
L
H
ICC, ICC1, ICC2
ICC, ICC1, ICC2
ICC, ICC1, ICC2
H
H
Write
H
X
L
DIN
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
-
-
6
8
CI/O*
Input/Output Capacitance
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
PRELIMINARY
(February, 2001, Version 0.2)
4
AMIC Technology, Inc.
A627308 Series
AC Characteristics (TA = 0°C to + 70°, VCC = 5.0V±10%)
A627308-70S
Symbol
Parameter
Unit
Min.
Max.
Read Cycle
tRC
Read Cycle Time
70
-
-
ns
ns
ns
tAA
Address Access Time
70
70
tACE1
-
CE1
CE2
Chip Enable Access Time
tACE2
tOE
-
-
70
35
-
ns
ns
ns
Output Enable to Output Valid
Chip Enable to Output in Low Z
tCLZ1
10
CE1
CE2
tCLZ2
tOLZ
10
5
-
-
ns
ns
ns
Output Enable to Output in Low Z
Chip Disable to Output in High Z
tCHZ1
0
25
CE1
CE2
tCHZ2
tOHZ
tOH
0
0
25
25
-
ns
ns
ns
Output Disable to Output in High Z
Output Hold from Address Change
10
Write Cycle
tWC
Write Cycle Time
70
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Chip Enable to End of Write
Address Setup Time
tAS
-
tAW
Address Valid to End of Write
Write Pulse Width
60
50
0
-
tWP
-
tWR
Write Recovery Time
-
tWHZ
tDW
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
30
-
30
0
tDH
-
tOW
5
-
Notes: tCHZ1, tCHZ2, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
PRELIMINARY
(February, 2001, Version 0.2)
5
AMIC Technology, Inc.
A627308 Series
Timing Waveforms
Read Cycle 1(1)
tRC
Address
tAA
OE
tOE
tOH
5
tOLZ
CE1
tACE1
5
5
tCHZ1
tCLZ1
CE2
5
tACE2
tOHZ
5
tCHZ2
5
tCLZ2
DOUT
Read Cycle 2 (1, 2, 4)
tRC
Address
tAA
tOH
tOH
DOUT
PRELIMINARY
(February, 2001, Version 0.2)
6
AMIC Technology, Inc.
A627308 Series
Timing Waveforms (continued)
Read Cycle 3 (1, 3, 4, 6)
CE1
tACE1
5
tCLZ1
5
tCHZ1
DOUT
Read Cycle 4 (1, 4, 7, 8)
CE2
tACE2
5
tCHZ2
5
tCLZ2
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7. CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
PRELIMINARY
(February, 2001, Version 0.2)
7
AMIC Technology, Inc.
A627308 Series
Timing Waveforms (continued)
Write Cycle 1(6)
(Write Enable Controlled)
tWC
Address
3
tAW
tWR
5
tCW
(4)
(4)
CE1
CE2
1
2
tAS
tWP
WE
tDW
tDH
DIN
tWHZ
tOW
DOUT
PRELIMINARY
(February, 2001, Version 0.2)
8
AMIC Technology, Inc.
A627308 Series
Timing Waveforms (continued)
Write Cycle 2(6)
(Chip Enable Controlled)
tWC
Address
3
tAW
tWR
5
tCW
CE1
CE2
(4)
(4)
1
tAS
5
tCW
2
tWP
WE
tDW
tDH
DIN
7
tWHZ
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
(February, 2001, Version 0.2)
9
AMIC Technology, Inc.
A627308 Series
AC Test Conditions
Input Pulse Levels
0V to 3V
5 ns
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
See Figures 1 and 2
TTL
TTL
CL
CL
30pF
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = 0°C to + 70°C)
Symbol
VDR
Parameter
VCC for Data Retention
Min.
2.0
-
Max.
5.5
Unit
V
Conditions
CE2 £ 0.2V, or
CE1 ³ VCC - 0.2V
VCC = 2.0V, CE2 £ 0.2V, or
CE1 ³ VCC - 0.2V
ICCDR
Data Retention Current
10*
mA
tCDR
tR
Chip Disable to Data Retention Time
Operation Recovery Time
0
-
-
ns
ns
tRC
See Retention Waveform
VCC Rise Time from Data Retention Voltage
to Operating Voltage
tVR
5
-
ms
* A627308-70S
ICCDR: Max. 3mA at TA = 0°C to + 40°C
PRELIMINARY
(February, 2001, Version 0.2)
10
AMIC Technology, Inc.
A627308 Series
Low VCC Data Retention Waveform (1) (CE1 Controlled)
DATA RETENTION MODE
VCC
CE1
4.5V
4.5V
tCDR
tR
VDR
³ 2V
tVR
VIH
VIH
CE1
³ VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE
VCC
CE2
4.5V
4.5V
tCDR
tR
VDR
³ 2V
tVR
VIL
VIL
CE2
£ 0.2V
PRELIMINARY
(February, 2001, Version 0.2)
11
AMIC Technology, Inc.
A627308 Series
Ordering Information
Part No.
Operating Current
Max. (mA)
Standby Current
Access Time
(ns)
Package
Max. (mA)
A627308M-70S
A627308V-70S
A627308X-70S
32L SOP
32L TSOP
32L sTSOP
70
45
25
PRELIMINARY
(February, 2001, Version 0.2)
12
AMIC Technology, Inc.
A627308 Series
Package Information
SOP (W.B.) 32L Outline Dimensions
unit: inches/mm
32
17
q
L
16
1
b
Detail F
D
LE
e
S
y
See Detail F
Seating Plane
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
-
Max
0.118
-
Min
Nom
-
Max
3.00
A
A1
A2
b
-
0.004
0.101
0.014
0.006
-
-
0.10
2.57
0.36
0.15
-
-
-
0.106
0.016
0.008
0.805
0.445
0.050
0.556
0.031
0.055
-
0.111
0.020
0.012
0.817
0.450
0.056
0.566
0.039
0.063
0.036
0.004
10°
2.69
0.41
0.20
20.45
11.30
1.27
14.12
0.79
1.40
-
2.82
0.51
0.31
20.75
11.43
1.42
14.38
0.99
1.60
0.91
0.10
10°
c
D
E
0.440
0.044
0.546
0.023
0.047
-
11.18
1.12
13.87
0.58
1.19
-
e
HE
L
LE
S
y
-
-
-
-
0°
-
0°
-
q
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY
(February, 2001, Version 0.2)
13
AMIC Technology, Inc.
A627308 Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
D
q
L
LE
Detail "A"
HD
Detail "A"
y
S
b
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
Min
Nom
Max
A
A1
A2
b
-
0.047
0.006
0.041
0.011
0.008
0.728
0.319
-
-
1.20
0.15
1.05
0.27
0.20
18.50
8.10
0.002
0.037
0.007
0.004
0.720
-
-
0.039
0.009
-
0.05
0.95
0.18
0.11
18.30
-
-
1.00
0.22
-
c
D
E
0.724
0.315
0.020 BSC
0.787
0.020
0.032
-
18.40
8.00
0.50 BSC
20.00
0.50
0.80
-
e
HD
L
0.779
0.795
0.024
-
19.80
20.20
0.60
-
0.016
0.40
LE
S
-
-
-
-
0.020
0.003
5°
0.50
0.08
5°
y
-
-
-
-
-
-
q
0°
0°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY
(February, 2001, Version 0.2)
14
AMIC Technology, Inc.
A627308 Series
Package Information
sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
q
L
LE
D1
D
Detail "A"
Detail "A"
0.076MM
S
b
SEATING PLANE
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
-
Max
0.049
-
Min
Nom
-
Max
-
A
A1
A2
b
1.25
-
-
-
0.002
0.037
0.007
0.05
0.95
0.17
0.142
7.90
0.039
0.008
0.041
0.009
1.00
1.05
0.23
0.158
8.10
0.20
c
0.0056 0.0059 0.0062
0.150
8.00
E
0.311
0.315
0.020 TYP
0.528
0.319
e
0.50 TYP
13.40
11.80
0.50
D
D1
L
0.520
0.461
0.012
0.535
0.469
0.028
13.20
11.70
0.30
13.60
11.90
0.70
0.465
0.020
LE
S
0.0275 0.0315 0.0355
0.0109 TYP
0.700
0.800
0.278 TYP
3°
0.900
q
0°
3°
5°
0°
5°
Notes:
1. The maximum value of dimension D1 includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY
(February, 2001, Version 0.2)
15
AMIC Technology, Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明