A64S0616G-55I [AMICC]
DRAM;
| 型号： | A64S0616G-55I |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | DRAM 动态存储器 |
| 文件： | 总15页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A64S0616
Preliminary
1M X 16 Bit Low Voltage Super RAMTM
Document Title
1M X 16 Bit Low Voltage Super RAMTM
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
0.2
Initial issue
November 30, 2001
Preliminary
Add tASC, tAHC, tCEH, tWEH
July 31, 2002
Change VCCmax from 3.1V to 3.3V
October 21, 2002
Change tCW from 60ns to 70ns for -70 and from 70ns to 85ns
for -85
Change tWP from 50ns to 55ns for -70 and from 55ns to 60ns
for -85
Change tWHZ from 20ns to 25ns for -70 and from 20ns to 25ns
for -85
0.3
November 7, 2002
Change power on CE1=50ns
Change avoid timing
0.4
0.5
Change tOHZ from 25ns to 14ns
March 4, 2003
June 24, 2003
Change tBE from 70ns to 35ns for -70 and from 85ns to 45ns
For -85
Add –55 grade spec.
PRELIMINARY
(June, 2003, Version 0.5)
AMIC Technology, Corp.
A64S0616
Preliminary
1M X 16 Bit Low Voltage Super RAMTM
Features
n Operating voltage: 2.7V to 3.3V
n Access times: 55/70/85 ns (max.)
n Current:
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Industrial operating temperature range: -25°C to +85°C
for -I
A64S0616 series: Operating: 35mA (max.)
Power Down Standby: 10mA (max.)
n Available in 48-ball Mini BGA (6X8) package.
n Fully SRAM compatible operation
n Full static operation, no clock or refreshing required
General Description
The A64S0616 is a low operating current 16,777,216-bit
Super RAM organized as 1,048,576 words by 16 bits and
operates on low power supply voltage from 2.7V to 3.3V.
It is built using AMIC’s high performance CMOS DRAM
process.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output enable
input are included for easy interfacing.
Using hidden refresh technique, the A64S0616 provides
a 100% compatible asynchronous interface.
This A64S0616 is suited for low power application such as
mobile phone and PDA or other battery-operated handheld
device.
Pin Configuration
n Mini BGA (6X8) Top View
1
2
3
4
5
6
A
B
C
D
E
F
A0
A1
A2
CE2
LB
OE
HB
I/O8
A3
A5
A4
A6
I/O0
I/O2
VCC
VSS
I/O6
I/O7
NC
CE1
I/O9
VSS
VCC
I/O14
I/O15
A18
I/O10
I/O1
I/O11
I/O12
I/O13
A19
A8
A17
GND
A14
A12
A9
A7
I/O3
I/O4
I/O5
A16
A15
A13
A10
G
H
WE
A11
A64S0616G
PRELIMINARY
(Juen, 2003, Version 0.5)
1
AMIC Technology, Corp.
A64S0616
Block Diagram
VCC
VSS
GND
A0
16,777,216
DECODER
MEMORY ARRAY
A18
A19
I/O
0
I/O8
INPUT
DATA
COLUMN I/O
INPUT
DATA
CIRCUIT
CIRCUIT
I/O15
I/O
7
CE1
CE2
LB
CONTROL
CIRCUIT
HB
OE
WE
Pin Description
Symbol
A0 - A19
CE1
Description
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Data Input/Outputs
Write Enable Input
CE2
I/O0 - I/O15
WE
LB
Byte Enable Input (I/O0 to I/O7)
Byte Enable Input (I/O8 to I/O15)
Output Enable Input
Power
HB
OE
VCC
VSS
Ground
GND
NC
Ground
No Connection
PRELIMINARY
(June, 2003, Version 0.5)
2
AMIC Technology, Corp.
A64S0616
Recommended DC Operating Conditions
(TA = 0°C to + 70°C or -25°C to 85°C)
Symbol
VCC
VSS
GND
VIH
Parameter
Min.
2.7
0
Max.
Unit
V
Supply Voltage
Ground
3.3
0
V
Ground
0
0
V
Input High Voltage
Input Low Voltage
Output Load
Output Load
2.4
-0.3
-
VCC + 0.3
V
VIL
+0.6
30
1
V
CL
pF
-
TTL
-
Absolute Maximum Ratings*
*Comments
VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V
Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . 260°C, 10 sec
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C or -25°C to 85°C, VCC = 2.7V to 3.3V, GND = 0V)
-55
-70
-85
Symbol
Parameter
Unit
Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Input Leakage Current
Output Leakage Current
-
1
-
1
-
1
VIN = GND to VCC
çILIú
mA
mA
CE1 = VIH or CE2 = VIL or
-
-
-
1
35
5
-
-
-
1
35
5
-
-
-
1
30
5
çILOú
OE = VIH or WE = VIL
VI/O = GND to VCC
Min. Cycle, Duty = 100%
ICC1
ICC2
mA
mA
CE1 = VIL, CE2 = VIH
II/O = 0mA
Dynamic Operating
Current
CE1 = VIL, CE2 = VIH
VIH = VCC, VIL = 0V,
f = 1MHz, II/O = 0mA
PRELIMINARY
(June, 2003, Version 0.5)
3
AMIC Technology, Corp.
A64S0616
DC Electrical Characteristics (continued)
Symbol
Parameter
-55
-70
-85
Unit
Conditions
Min.
Max.
Min.
Max.
Min.
Max.
CE1 ³ VCC - 0.2V
CE2 ³ VCC - 0.2V
VIN ³ 0V
Standby Power
Supply Current
ISB1
ISB2
-
-
100
10
-
-
100
10
-
-
100
10
mA
mA
Power Down Mode
Standby Current
CE2 £ 0.2V
VOL
VOH
Output Low Voltage
Output High Voltage
-
0.4
-
-
0.4
-
-
0.4
-
V
V
IOL = 2.1mA
IOH = -1.0mA
2.4
2.4
2.4
Truth Table
I/O0 to I/O7 Mode
I/O8 to I/O15 Mode
VCC Current
CE1
H
CE2
H
OE
X
WE
X
LB
X
H
X
L
HB
X
H
X
L
Not selected
Not selected
Not selected
Read
Not selected
Not selected
Not selected
Read
ISB1
X
H
X
X
ISB1
X
L
X
X
ISB2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
L
H
L
H
L
H
L
Read
High - Z
H
L
High - Z
Read
L
Write
Write
L
L
H
H
X
H
L
L
H
L
Write
Not Write/Hi - Z
Write
H
Not Write/Hi - Z
High - Z
High - Z
H
X
X
High - Z
High - Z
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
10
Unit
pF
Conditions
VIN = 0V
Input Capacitance
-
-
CI/O*
Input/Output Capacitance
10
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
PRELIMINARY
(June, 2003, Version 0.5)
4
AMIC Technology, Corp.
A64S0616
Initialization
The A64S0616 is initialized in the power-on sequence according to the following.
1. To stabilize internal circuits, after turning on the power, a 350ms or longer wait time must precede any signal toggling.
2. After the wait time, it can be normal operation.
Power on Chart
VCC(min)
VCC
CE1
350us
CE2
Wait Time
Normal Operation
Notes: 1. Following power application, make CE2 and CE1 high level during the wait time interval.
2. After power on sequence, the normal operating CE2 must keep at high.
Power on / Depower down State Machine
Power on
CE1=VIH
,
CE2=VIH
Wait 350us
Initial State
CE1=VIL
,
CE2=VIH
CE1=V IH
CE2=V IH
CE1=VIH
CE2=VIH
,
,
Active
CE1=VIH
CE1=V IH
CE2=V IH
,
CE2=VIL
,
CE1=VIL
,
CE2=VIH
Standby
Mode
Power Down
Mode
CE1=VIH
CE2=VIL
,
Standby Mode Characteristics
Standby Mode
Standby
Memory Cell Data Hold
Standby Supply Current (mA)
100 (ISB1)
Valid
Power down
Invalid
10 (ISB2)
PRELIMINARY
(June, 2003, Version 0.5)
5
AMIC Technology, Corp.
A64S0616
Avoid Timing
Following figure 1 is show you an abnormal timing which is not supported on Super RAM.
CE1
WE
Less than 30ns
Address
Figure 1
PRELIMINARY
(June, 2003, Version 0.5)
6
AMIC Technology, Corp.
A64S0616
AC Characteristics (TA = 0°C to +70°C or -25°C to 85°C, VCC = 2.7V to 3.3V)
Symbol
Parameter
-55
-70
-85
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
55
-
-
70
-
-
85
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSKEW
tAA
Address Skew
10
55
55
30
30
-
10
70
70
35
35
-
10
85
85
45
45
-
Address Access Time
-
-
-
tACE
tBE
Chip Enable Access Time
-
-
-
Byte Enable Access Time
-
-
-
tOE
Output Enable to Output Valid
Chip Enable to Output in Low Z
Byte Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Byte Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
-
-
-
tCLZ
10
5
5
0
0
0
5
0
10
5
5
0
0
0
10
0
10
5
5
0
0
0
10
0
tBLZ
-
-
-
tOLZ
tCHZ
tBHZ
tOHZ
tOH
-
-
-
20
20
14
-
25
25
14
-
35
35
14
-
tASC
-
-
-
Address Setup to CE1 Low
Address Hold Time from CE1 High
CE1 High Pulse With
tAHC
tCEH
0
-
-
0
-
-
0
-
-
ns
ns
10
10
10
Write Cycle
tWC
Write Cycle Time
55
-
-
10
-
70
-
-
10
-
85
-
-
10
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSKEW
tCW
Address Skew
Chip Enable to End of Write
Byte Enable to End of Write
Address Setup Time
55
50
0
70
60
0
85
70
0
tBW
-
-
-
tAS
-
-
-
tAW
Address Valid to End of Write
Write Pulse Width
50
45
0
-
60
55
0
-
70
60
0
-
tWP
-
-
-
tWR
Write Recovery Time
-
-
-
tWHZ
tDW
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
-
20
-
-
25
-
-
25
-
25
0
30
0
35
0
tDH
-
-
-
tOW
5
-
5
-
5
-
tASC
0
-
0
-
0
-
Address Setup to CE1 Low
Address Hold Time from CE1 High
CE1 High Pulse With
tAHC
tCEH
tWEH
0
-
-
-
0
-
-
-
0
-
-
-
ns
ns
ns
10
10
10
10
10
10
WE High Pulse With
Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
PRELIMINARY
(June, 2003, Version 0.5)
7
AMIC Technology, Corp.
A64S0616
Timing Waveforms
Read Cycle 1(1, 2, 4, 6)
tSKEW
tRC
tSKEW
tRC
Address
DOUT
tAA
tOH
tAA
tOH
tASC
CE1
PRELIMINARY
(June, 2003, Version 0.5)
8
AMIC Technology, Corp.
A64S0616
Read Cycle 2-1(1, 3, 6)
t
SKEW
tSKEW
t
RC
tRC
Address
CE1
t
ASC
t
AHC
t
ASC
tAHC
t
AA
t
AA
t
CEH
t
BE
t
ACE
5
tACE
tCLZ
5
5
t
CHZ
tCHZ
5
t
CLZ
t
BE
t
BE
,
HB LB
5
5
5
5
t
BLZ
t
BHZ
t
BLZ
tBHZ
OE
t
5
OE
t
5
OE
5
5
t
OHZ
tOHZ
t
OLZ
tOLZ
DOUT
Read Cycle 2-2(1, 3, 6)
t
SKEW
t
SKEW
t
SKEW
t
RC
t
RC
Address
CE1
t
ASC
t
AHC
t
AA
t
AA
t
ACE
5
5
t
CHZ
t
CLZ
t
BE
t
BE
,
HB LB
5
5
5
5
t
BLZ
t
BHZ
t
BLZ
t
BHZ
OE
t
5
OE
t
5
OE
5
5
t
OHZ
t
OHZ
t
OLZ
t
OLZ
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled
= VIL, HB = VIL and, or LB = VIL.
CE1
3. Address valid prior to or coincident with CE1 and (HB and, or LB ) transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high for Read Cycle.
PRELIMINARY
(June, 2003, Version 0.5)
9
AMIC Technology, Corp.
A64S0616
Timing Waveforms (continued)
Write Cycle 1-1(6)
(Write Enable Controlled)
t
SKEW
t
SKEW
t
WC
t
WC
Address
CE1
t
ASC
t
AHC
t
ASC
tAHC
t
AW
tAW
t
CW
BW
t
t
CEH
t
CW
BW
t
t
t
,
HB LB
AS 1
t
WR3
t
WR3
t
t
AS 1
WP2
WP2
WE
t
DW
t
t
DH
t
DW
t
DH
Data In
t
WHZ4
t
WHZ4
OW
t
OW
Data Out
Write Cycle 1-2(6)
(Write Enable Controlled)
t
SKEW
t
SKEW
t
SKEW
t
WC
t
WC
Address
CE1
t
ASC
tAHC
t
BW
t
BW
,
HB LB
AS 1
t
AS 1
t
WR3
t
WR3
t
t
WP2
t
WP2
WE
t
WEH
t
DW
t
t
DH
t
DW
t
DH
Data In
t
WHZ4
t
WHZ4
OW
tOW
Data Out
PRELIMINARY
(June, 2003, Version 0.5)
10
AMIC Technology, Corp.
A64S0616
Timing Waveforms (continued)
Write Cycle 2-1(6)
(Chip Enable Controlled)
t
SKEW
t
WC
tSKEW
t
WC
Address
CE1
t
AHC
t
AHC
t
AW
tAW
t
ASC
CW2
t
CEH
t
CW2
t
ASC
t
WR3
t
WR3
t
t
BW
tBW
,
HB LB
t
WP
t
WP
WE
t
DW
t
DH
t
DW
tDH
Data In
t
WHZ4
t
WHZ4
t
OW
tOW
Data Out
Write Cycle 2-2(6)
(Chip Enable Controlled)
t
SKEW
t
SKEW
t
SKEW
t
WC
t
WC
Address
CE1
t
AHC
t
AW
t
ASC
WR3
t
WR3
t
t
BW
t
BW
,
HB LB
t
WP
t
WP
WE
t
DW
t
DH
t
DW
t
DH
Data In
t
WHZ4
t
WHZ4
t
OW
t
OW
Data Out
PRELIMINARY
(June, 2003, Version 0.5)
11
AMIC Technology, Corp.
A64S0616
Timing Waveforms (continued)
Write Cycle 3-1(6)
(Byte Enable Controlled)
t
SKEW
t
SKEW
t
WC
t
WC
Address
t
AHC
t
AHC
t
AW
t
AW
t
ASC
t
ASC
t
CW
t
CEH
tCW
CE1
t
WR3
t
WR3
t
AS 1
t
BW2
t
AS 1
t
BW2
,
HB LB
t
WP
tWP
WE
t
DW
t
t
DH
t
DW
tDH
Data In
WHZ4
t
WHZ4
t
OW
tOW
Data Out
Write Cycle 3-2(6)
(Byte Enable Controlled)
t
SKEW
SKEW
t
WC
t
t
SKEW
t
WC
Address
CE1
t
AHC
t
AW
t
ASC
t
WR3
t
WR3
t
AS 1
t
BW2
t
AS 1
t
BW2
,
HB LB
t
WP
tWP
WE
t
DW
t
t
DH
t
DW
tDH
Data In
WHZ4
t
WHZ4
t
OW
tOW
Data Out
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low , WE and (HB and, or LB ).
CE1
or WE or (HB and, or LB ) going high to the end of the Write cycle.
3. tWR is measured from the earliest of
CE1
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high for Write Cycle.
PRELIMINARY
(June, 2003, Version 0.5)
12
AMIC Technology, Corp.
A64S0616
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
5 ns
Input Rise And Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
See Figures 3 and 4
TTL
TTL
CL
CL
30pF
5pF
* Including scope and jig.
* Including scope and jig.
Figure 3. Output Load
Figure 4. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Ordering Information
Power Down Mode
Standby Current
Operating Current
Part No.
Access Time (ns)
Package
Max. (mA)
Max. (mA)
A64S0616G-55
A64S0616G-70
A64S0616G-85
A64S0616G-55I
A64S0616G-70I
A64S0616G-85I
55
70
85
55
70
85
35
35
30
35
35
30
10
10
10
10
10
10
48B Mini BGA
48B Mini BGA
48B Mini BGA
48B Mini BGA
48B Mini BGA
48B Mini BGA
Note: -I is for industrial operating temperature range
PRELIMINARY
(June, 2003, Version 0.5)
13
AMIC Technology, Corp.
A64S0616
Package Information
48LD CSP (6 x 8 mm) Outline Dimensions
(48TFBGA)
unit: mm
TOP VIEW
BOTTOM VIEW
Ball#A1 CORNER
S
S
0.10
0.25
C
C A B
Ball*A1 CORNER
b (48X)
6
5 4 3 2 1
1
2 3 4 5 6
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
B
e
D1
A
SIDE VIEW
D
0.20(4X)
C
SEATING PLANE
Dimensions in mm
Symbol
MIN. NOM. MAX.
A
A1
D
---
0.20
5.90
7.90
---
---
1.20
0.30
6.10
8.10
---
0.25
6.00
8.00
3.75
5.25
0.75
0.35
E
D1
E1
e
---
---
---
---
b
0.30
0.40
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF
& PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.
4. BALL PAD OPENING OF SUBSTRATE IS F 0.3mm (SMD)
SUGGEST TO DESIGN THE PCB LAND SIZE AS F 0.3mm (NSMD)
PRELIMINARY
(June, 2003, Version 0.5)
14
AMIC Technology, Corp.
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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