A64S16161 [AMICC]
2M X 16 Bit Low Voltage Super RAM; 2M x 16位的低电压超RAM
| 型号： | A64S16161 |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 2M X 16 Bit Low Voltage Super RAM |
| 文件： | 总16页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A64S16161
Preliminary
2M X 16 Bit Low Voltage Super RAM
Features
● Memory Cell : Dynamic memory( DRAM )
● Refresh: Completely free
1
2
3
A0
4
5
6
● Power Down: Control by CS2( No Data Retention )
● Byte Control : Capable of single byte operation
● Power Consumption: 100μA( Standby Current )
● Operating Temperature Range: -40’C~+85’C
● Composition:2,097,152 Word X 16 Bit
● Supply Power Voltage:2.70V to 3.30V
● Access Time: 70nS
LB#
DQ8
DQ9
VSS
VCC
DQ14
DQ15
A18
OE#
UB#
DQ10
DQ11
DQ12
DQ13
A19
A8
A1
A2
CE2
DQ0
DQ2
VCC
VSS
DQ6
DQ7
A20
A
B
C
D
E
A3
A4
CE1#
DQ1
DQ3
DQ4
DQ5
WE#
A11
A5
A6
A7
● Access Time ( Page Access Read ): 30nS
● I/O Terminal :Input / Output Common 3-state output
A17
NC
Pin Description
A16
A15
A13
A10
Pin Name
CS1#
CS2
Description
Chip select 1 ( Low Active )
Chip select 2 ( High Active )
Write enable ( Low Active )
Output enable ( Low Active )
Address Input ( A0 to A2 : Page Address)
Lower Byte Input / Output
Upper Byte Input / Output
Lower Byte Control ( Low Active )
Upper Byte Control ( Low Active )
Power Supply
A14
A12
A9
F
WE#
G
H
OE#
A0 to A20
IO0-7
IO8-15
LB#
UB#
VCC
VSS
Ground ( 0V)
Description
A64S16161 is a virtually static RAM, which uses DRAM type memory cells, but it has refresh transparency, so that you need
not to imply refresh operation. Furthermore the interface is completely compatible to a low power Asynchronous type SRAM, you
can operate as same as the Asynchronous SRAM.
A64S16161 is a 2,097,152 Words X 16 bit asynchronous random access memory on a monolithic CMOS chip with
marvelous low power consumption technology. Its low power and also low noise makes it ideal for mobile applications.
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A64S16161
Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
13
8192
Memory Cell
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
256X16
8
256
Column
Decoder
Column Gate
ATD
16
Control
Refresh
Control
CS1#
CS2
CS1#,CS2
Control
Input / Output Buffer
WE#
OE#
LB#
WE#,OE#
LB#,UB#
Control
UB#
I / O0 ．．．．．．．．．．．．．．
I / O15
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Functions
Truth Table
A0-20 CS1#
CS2
H
WE#
H
OE#
L
LB#
L
UB#
L
I/O0~7
Data-Out
Data-Out
High-Z
High-Z
High-Z
Data-In
Data-In
High-Z
High-Z
High-Z
I/O8~15
Data-Out
High-Z
Mode
Read
V
V
V
V
V
V
V
V
X
X
L
L
L
L
L
L
L
L
H
X
H
H
L
L
H
L
Read
H
H
L
H
H
X
Data-Out
High-Z
Read
H
H
X
H
X
Output Disable
Output Disable
Write
H
H
H
H
H
H
X
High-Z
H
L
L
L
Data-In
High-Z
H
L
L
H
L
Write
H
L
H
X
Data-In
High-Z
Write
H
X
X
Standby
Power Down*¹
L
X
X
X
X
High-Z
V : Valid Address. X : High or Low .*1 No Data Retention
Read Operation
It is possible to control data width by LB# and UB# pins.
(1)Reading data from lower byte
Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H and LB #=L.
(2)Reading data from upper byte
Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H and UB #=L.
(3)Reading date from both bytes
Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H , LB #=L and UB #=L.
(4)Page access read
Date can be read by changing A0-A2 when A3-A20 is set while holding CS1#=L, CS2=H, WE #=H, OE #=L, LB #=L and UB #=L.
Writing Operation
(1) Writing data into lower byte ( WE # control )
Data can be written by adding L pulse into WE # when the address is set while holding CS1#=L, CS2=H, OE #=H, LB #=L and
UB #=H.
The data on lower byte are latched up into the memory cell during WE # =L and LB # =L.
(2) Writing data into lower byte (LB # control)
Data can be written by adding L pulse into LB # when the address is set while holding CS1#=L, CS2 =H, OE#=H, UB# =H and
WE#=L.
The data on lower byte are latched up into the memory cell during WE# =L and LB# = L.
(3) Writing data into upper byte (WE # control)
Data can be written by adding L pulse into WE # when the address is set while holding CS1 #=L, CS2 =H, OE #=H, LB # =H and
UB #=L.
The data on upper byte are latched up into the memory cell during WE # =L and UB # = L.
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(4) Writing data into upper byte (UB # control)
Data can be written by adding L pulse into UB # when the address is set while holding CS1 #=L, CS2 =H, OE #=H, LB # =H and
WE #=L.
The data on upper byte are latched up into the memory cell during WE #=L and UB #=L.
(5) Writing data into both byte ( WE # control)
Data can be written by adding L pulse into WE # when the address is set while holding CS1 #=L, CS2=H, OE #=H, LB #=L and
UB #=L.
The data are latched up into the memory cell during WE #=L, LB #=L and UB #=L.
(6) Writing data into both byte (LB #, UB # control)
Data can be written by adding L pulse into LB# and UB# when the address is set while holding CS1#=L, CS2=H, OE #=H and
WE #=L.
The data are latched up into the memory cell during WE #=L, LB #=L and UB #=L
Read or write with using both LB # and UB #, the timing edge of LB # and UB # must be same.
While I/O pins are in the output state, the data that is opposite to the output data should not be given.
Standby cycle
When CS1# is H, the device will be in the standby cycle. In this case data I/O pins are Hi-Z and all input pins are inhibited.
Power Down
When CS2 is L, the device will be in the power down. In this case, an internal refresh stops and the data might be lost.
ABSOLUTE MAXIMUM RATINGS (VSS=0V)
Parameter
Symbol
VCC
VI
Ratings
Unit
V
Supply voltage
-0.5 to 3.6
Input voltage
-0.5* to VCC+0.3
-0.5* to VCC+0.3
0.5
V
Input / Output voltage
Input / Output voltage
Operating temperature
Storage temperature
V I/O
PD
V
W
＇C
｀C
Topr
Tstg
-40 to 85
-65 to 150
* If pulse width is less than 5ns it is – 1.0V
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ELECTRICAL CHARACTERISTICS
DC Recommended Operating Conditions (Ta=-40~85＇C)
Parameter
Symbo1
Min
Max
Unit
VCC
VSS
VIH
VIL
2.70
0
3.30
0
V
V
V
V
Supply voltage
VCC-0.3
-0.3*
VCC+0.3
0.3
Input voltage
* If pulse width is less than 5ns it is –1.0V
DC ELECTRICAL CHARACTERISTICS
DC Characteristics (Ta=-40~85’C)
Typ*¹
Parameter
Symbol
Condition
Min
Max
Unit
µA
﹣
﹣
Input leakage current
Output leakage current
ILI
VI=0V to VCC
-1
-1
1
1
µA
ILO
LB# and UB#=H or CS1#=H or WE#=L
or OE#=H or CS2=L VI/O=0V to VCC
IOH=-0.5ｍA
﹣
﹣
﹣
0.3
25
High level output voltage
Low level output voltage
Power Down Current
Standby Current
VOH
VOL
Vcc-0.3
V
IOL=0.5ｍA
﹣
﹣
﹣
﹣
﹣
-
V
CS2≦0.2V
﹣
µA
IDDPD
IDDS
VCC-0.2V≦CS1#
µA
60
25
3.0
20
100
30
I I/O=0ｍA, tcyc=70ns*²
I I/O=0ｍA, tcyc=1uS*²
I I/O=0ｍA, tcyc=70ns*³
ｍA
ｍA
ｍA
Operating current
IDDA1
IDDA2
IDDA3
Operating current
3.5
30
Operating current
*1:Typical values are measured at Ta=25’C and VCC =3.0V
*2:Random access
*3:Page access read
Terminal Capacitance
(Ta=25’C f=1MHz)
Parameter
Symbol
Conditions
Min
﹣
Max
Unit
Input Capacitance
I/O Capacitance
CI
VI=0V
8
pF
pF
﹣
C I/O
V I/O=0V
10
Note：This parameter is measured by sampling , not of all products.
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AC Electrical Characteristics
Read Cycle (Ta = - 30 ~ 85’C)
Parameter
Symbol
tRC
Teat Conditions
1
Min
70
Max
Unit
nS
Read cycle time
32000
Page read cycle time
Address access time
tRCP
tACC
tACCP
tACS
tOE
1
1
1
1
1
1
1
1
2
2
2
2
2
2
1
30
-
32000
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
70
30
70
35
25
-
Page address access time
CS1 # access time
-
-
OE # access time
-
LB # , UB # access time
CS1# high pulse width
Address set up to OE L #
CS1 # output set time
CS1 # output floating time
LB # , UB # output set time
LB # , UB # output floating time
OE # output set time
tAB
-
tC1H
tASO
tCHZ
tCLZ
tBLZ
tBLZ
tOLZ
tOHZ
tOH
30
-5
0
-
-
-
15
-
0
-
15
-
0
-
OE # output floating time
Output hold time
15
-
5
Write Cycle (Ta= - 40~85’C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Write cycle time
Chip select time
tWC
tCW
tC1H
tAW
tAS
1
1
70
60
30
60
0
32000
-
nS
nS
CS1# H pulse width
Address enable time
Address set up time
Write pulse width
LB,UB select time
Address hold time
Data set up time
Data hold time
1
1
1
1
1
1
1
-
-
-
-
-
-
-
nS
nS
nS
nS
nS
nS
nS
tWP
tBW
tWR
tDW
tDH
40
60
0
30
0
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Power Down Cycle(Ta= - 40~85＇C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
CS1 # H set up time for Power Down entry
CS1 # H hold time before Power Down exit
CS2 L pulse width
tSSP
tSHP
1
1
1
1
0
0
-
-
-
-
nS
nS
nS
µS
TC2LP
tHPD
30
300
CS1 # H hold time after Power Down exit
Power Up Timing Requirement(Ta= - 40~85＇C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
CS1 # CS2 set up time after Power Up
Standby hold time after Power Up
tSHU
tHPU
1
1
0
-
-
nS
µS
300
Data Retention Timing Requirement(Ta= - 40~85＇C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
A3 to A20 hold time during active
CS1# L hold time for A3 to A20 fix
tBAH
tCSH
1
1
-
-
32
32
nS
nS
Either tBAH or tCSH required for data retention.
Address Skew Timing Requirement(Ta= - 40~85＇C)
Parameter
Symbol
Test Conditions
Min
-
Max
10
Unit
nS
Maximum address skew
tSKEW
1
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TEST CONDITION 1
Input pulse voltage level
VCC – 0.3V / 0.3V
tr=tf=3nS
Input ascend / descend time
Input output timing reference level
Output load
2.0V/0.8V
CL=50pF(Includes Jig capacity)+1TTL
TEST CONDITION 2
Input pulse voltage level
Input ascend / descend time
Input output timing reference level
Output load
VCC – 0.3V / 0.3V
tr=tf=3nS
±100mV(The level change from stable voltage
CL=5pF(Includes Jig capacity)+1TTL
I / O
CL
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TIMING CHART
Read Cycle
tRC
Address
CS1#
tACC
tOH
tACS
tCHZ
tAB
LB#/UB#
tASO
tBHZ
tOE
OE#
Dout
tOLZ
tOHZ
tBLZ
tCLZ
CS2 and WE # must be H level for entire read cycle.
Read Cycle ( Page Access [1] )
Address
No Change
tRCP
(A20-A3)
tRC
tRCP
Address
(A2-A0)
CS1#
OE#
tCHZ
tACS
tACCP
tACCP
tOH
tOH
tOH
tCLZ
Dout
CS2 and WE # must be H level for entire read cycle.
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Read Cycle ( Page Access [2] )
Address
No Change
tRCP
(A20-A3)
tRC
tRCP
Address
(A2-A0)
tACS
tOE
CS1#
OE#
tASO
tOLZ
tCHZ
tOH
tACCP
tACCP
tOH
tOH
Dout
CS2 and WE # must be H level for entire read cycle.
Write Cycle ( WE # Control )
tWC
Address
tAW
tCW
CS1#
tBW
LB# / UB#
WE#
tWR
tAS
tWP
tDW
tDH
Din
CS2 and OE # must be H level for entire read cycle.
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Write Cycle ( LB # / UB # Control )
tWC
Address
tAW
tCW
CS1#
tWR
tBW
tAS
LB# / UB#
WE#
tWP
tDW
tDH
Din
CS2 and OE # must be H level for entire read cycle.
Standby
tC1H
CS1#
Active
Standby
Active
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Power Down Mode Entry / Exit
CS1#
tHPD
tSHP
tC2LP
CS2
tSSP
Power Up
CS1#
tSHU
tHPU
CS2
VCC(min)
VCC
Data Retention(1)
tBAH
Address
(A20-A3)
CS1#
This applies for both read and write.
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Data Retention (2)
tCSH
Address
No Change
(A20-A3)
CS1#
This applies for both read and write.
Address Skew(1)
A0-20
tSKEW
tRC / tWC
CS1#
tSKEW is from first address change to last address change
Address Skew(2)
A0-20
tRC / tWC
tSKEW
CS1#
tSKEW is from first address change to last address change
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Address Skew(3)
A0-20
tSKEW
CS1#
tSKEW is from first address change to stand-by
Reference External Wiring Diagram
Address Input
Control
Input / Output
I / O0
WE#
OE#
A0
I / O15
CS1#
A20
CS2
BU#
LB#
A64S16161
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A64S16161
Ordering Information
Power Down Mode
Standby Current
Max. (µA)
Operating Current
Max. (mA)
Part No.
Access Time (ns)
Package
A64S0616G-70I
70
30
25
48B Mini BGA
Note: -I is for industrial operating temperature range
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48 Pins FBGA Package outline drawing
-A-
6.00
0.10
PIN#1
-B-
0.08
C
CAVITY
C
C
-C-
SOLDER BALL
SEATING PLANE
0.10
0.1
C
DETAIL : A
C
C
A
B
M
0.2
“A＂
0.1
M
SECTION C-C
3.75
0.75
H
G
B
F
E
D
C
B
A
A
1
2
DETAIL : B
“B＂
1 2 3 4 5 6
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