A67L8316_技术文档

A67L8316/A67L8318/

A67L7332/A67L7336 Series

256K X 16/18, 128K X 32/36

Preliminary

LVTTL, Pipelined DBA^TMSRAM

Document Title

256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM

Revision History

Rev. No. History

Issue Date

Remark

0.0

0.1

Initial issue

March 11, 1999

Preliminary

Change fast access time from 4.0/4.2/4.5/5.0 ns to

4.5/5.0/6.0 ns

December 29, 1999

PRELIMINARY

(December, 1999, Version 0.1)

AMIC Technology, Inc.

DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc

A67L8316/A67L8318/

A67L7332/A67L7336 Series

256K X 16/18, 128K X 32/36

Preliminary

LVTTL, Pipelined DBA^TMSRAM

Features

n Fast access time: 4.5/5.0/6.0 ns (117/100/83MHz)

n Direct Bus Alternation between READ and WRITE

cycles allows 100% bus utilization

n Signal +3.3V ± 5% power supply

n Individual Byte Write control capability

n Clock-controlled and registered address, data and

control signals

n Registered output for pipelined applications

n Three separate chip enables allow wide range of

options for CE control, address pipelining

n Internally self-timed write cycle

n Clock enable (

) pin to enable clock and suspend

CEN

n Selectable BURST mode (Linear or Interleaved)

n SLEEP mode (ZZ pin) provided

operations

n Available in 100 pin LQFP package

General Description

The AMIC Direct Bus Alternation™ (DBA™) SRAM

family employs high-speed, low-power CMOS designs

using an advanced CMOS process.

Write cycles are internally self-time and synchronous

with the rising edge of the clock input and when R/

is

W

Low. The feature simplified the write interface. Individual

The A67L8316, A67L8318, A67L7332, A67L7336

SRAMs integrate a 256K X 16, 256K X 18, 128K X 32 or

128K X 36 SRAM core with advanced synchronous

peripheral circuitry and a 2-bit burst counter. These

SRAMs are optimized for 100 percent bus utilization

without the insertion of any wait cycles during Write-

Read alternation. The positive edge triggered single

clock input (CLK) controls all synchronous inputs

passing through the registers. The synchronous inputs

include all address, all data inputs, active low chip

Byte enables allow individual bytes to be written.

BW1

BW3

controls I/Oa pins;

controls I/Ob pins;

BW2

controls I/Oc pins; and

controls I/Od pins. Cycle

BW4

types can only be defined when an address is loaded,

i.e., when ADV/ is LOW. Parity/ECC bits are only

LD

available on the X18/36 version.

The SRAM operates from a +3.3V power supply, and all

inputs and outputs are LVTTL-compatible. The device is

ideally suited for high bandwidth utilization systems.

enable ( ), two additional chip enables for easy depth

CE

expansion (CE2,

), cycle start input (ADV/ ),

LD

CE2

synchronous clock enable (

), byte write enables

CEN

(

,

BW4

) and read/write (R/ ).

W

BW1 BW2

BW3

Asynchronous inputs include the output enable (

),

OE

clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and

burst mode (MODE). Burst Mode can provide either

interleaved or linear operation, burst operation can be

initiated by synchronous address Advance/Load

(ADV/ ) pin in Low state. Subsequent burst address

LD

can be internally generated by the chip and controlled by

the same input pin ADV/

in High state.

LD

PRELIMINARY

(December, 1999, Version 0.1)

1

AMIC Technology, Inc.

DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc

A67L8316/A67L8318/

A67L7332/A67L7336 Series

Pin Configuration

128K X 36/32

256K X 18/16

I/Oc0/NC

I/Oc1

NC

1

80

A17

NC

I/Ob8/NC

I/Ob7

2

79

I/Oc2

NC

3

78

77

NC

I/Ob6

VCCQ

VSSQ

I/Oc3

4

VCCQ

VSSQ

NC

5

76

75

74

VSSQ

NC

VSSQ

I/Ob5

6

7

I/Oa8/NC

I/Oc4

I/Ob4

NC

I/Ob0

I/Oc5

8

I/Ob3

I/Oa7

73

72

9

I/Ob1

I/Oc6

VSSQ

VCCQ

I/Oa6

I/Ob2

VSSQ

VCCQ

10

11

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VSSQ

VCCQ

VSSQ

VCCQ

12

13

14

15

16

I/Oa5

I/Oa4

VSS

I/Ob1

I/Ob0

VSS

VCC

I/Oc7

I/Oc8

VCC

VSS

I/Ob2

I/Ob3

A67L8316E

A67L8318E

A67L7332E

A67L7336E

VCC

VSS

ZZ

17

18

I/Od0

I/Od1

VCCQ

VSSQ

I/Od2

I/Od3

I/Od4

I/Ob4

I/Oa3

I/Oa8

I/Oa7

VCCQ

VSSQ

I/Ob5

19

20

21

22

23

24

25

26

27

28

29

30

I/Oa2

VCCQ

VSSQ

I/Ob6

VCCQ

VSSQ

I/Oa1

I/Oa0

NC

I/Oa6

I/Oa5

I/Oa4

I/Oa3

VSSQ

I/Ob7

I/Ob8/NC

NC

I/Od5

VSSQ

VCCQ

NC

VCCQ

NC

VCCQ

I/Oa2

I/Od

I/Od7

I/Od /NC

6

NC

I/Oa1

NC

8

NC

I/Oa0/NC

PRELIMINARY

(December, 1999, Version 0.1)

2

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

Block Diagram (128K X 32/36)

ZZ

MODE

LOGIC

MODE

ADV/LD

CLK

LOGIC

CEN

CLK

BURST

LOGIC

ADDRESS

COUNTER

CLR

WRITE

ADDRESS

REGISTER

ADDRESS

REGISTER

ADDRESS

REGISTERS

A0-A16

8/9

BYTEa

WRITE

DRIVER

8/9

BYTEb

WRITE

DRIVER

OUTPUT

REGISTERS

&

OUTPUT

BUFFERS

128KX8/X9X4

WRITE

REGISTRY

&

CONTROL

LOGIC

ADV/LD

R/W

I/Os

SENSE

AMPS

MEMORY

ARRAY

BYTEc

WRITE

DRIVER

BWE

BW1

BW2

8/9

BYTEd

WRITE

DRIVER

BW3

BW4

DATA-IN

REGISTERS

DATA-IN

REGISTERS

CE

CHIP

ENABLE

LOGIC

PIPELINED

ENABLE

LOGIC

CE2

OUTPUT

ENABLE

LOGIC

OE

PRELIMINARY

(December, 1999, Version 0.1)

3

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

Block Diagram (256K X 16/18)

ZZ

MODE

LOGIC

MODE

ADV/LD

CLK

LOGIC

CEN

CLK

BURST

LOGIC

ADDRESS

COUNTER

CLR

WRITE

ADDRESS

REGISTER

ADDRESS

REGISTER

ADDRESS

REGISTERS

A0-A17

8/9

BYTEa

WRITE

DRIVER

8/9

WRITE

REGISTRY

&

CONTROL

LOGIC

256KX8/X9X2

MEMORY

ARRAY

OUTPUT

REGISTERS

&

OUTPUT

BUFFERS

ADV/LD

I/OS

SENSE

AMPS

R/W

BWE

BYTEb

WRITE

DRIVER

8/9

BW1

BW2

DATA-IN

REGISTERS

DATA-IN

REGISTERS

CE

CHIP

ENABLE

LOGIC

PIPELINED

ENABLE

LOGIC

CE2

OUTPUT

ENABLE

LOGIC

OE

PRELIMINARY

(December, 1999, Version 0.1)

4

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

Pin Description

Pin No.

Symbol

Description

LQFP (X16/X18)

LQFP (X32/X36)

37

36

37

36

A0

A1

A2 - A16

Synchronous Address Inputs : These inputs are registered

and must meet the setup and hold times around the rising

edge of CLK. Pins 83 and 84 are reserved as address bits

for higher-density 9Mb and 18Mb DBA SRAMs, respectively.

A0 and A1 are the two lest significant bits (LSB) of the

address field and set the internal burst counter if burst is

desired.

35,34,33,32,

100,99,82,81,

44,45,46,47,

48,49,50

80

35,34,33,32,

100,99,82,81,

44,45,46,47,

48,49,50

A17

93 (

94 (

)

93 (

94 (

95 (

)

BW1

Synchronous Byte Write Enables : These active low inputs

allow individual bytes to be written when a WRITE cycle is

active and must meet the setup and hold times around the

rising edge of CLK. BYTE WRITEs need to be asserted on

the same cycle as the address, BWs are associated with

BW1

BW2

BW3

)

BW2

BW3

BW4

96 (

)

BW4

addresses and apply to subsequent data.

controls I/Oa

BW1

pins;

controls I/Ob pins;

BW3

controls I/Oc pins;

BW2

controls I/Od pins.

BW4

89

Clock: This signal registers the address, data, chip enables,

byte write enables and burst control inputs on its rising

edge. All synchronous inputs must meet setup and hold

times around the clock are rising edge.

CLK

98

92

98

92

CE

Synchronous Chip Enable : This active low input is used to

enable the device. This input is sampled only when a new

external address is loaded (ADV/

LOW).

LD

CE2

Synchronous Chip Enable : This active low input is used to

enable the device and is sampled only when a new external

address is loaded (ADV/

LOW). This input can be used

LD

for memory depth expansion.

97

CE2

OE

Synchronous Chip Enable : This active high input is used to

enable the device and is sampled only when a new external

address is loaded (ADV/

LOW). This input can be used

LD

for memory depth expansion.

86

85

86

85

Output Enable : This active low asynchronous input enables

the data I/O output drivers.

ADV/

Synchronous Address Advance/Load : When HIGH, this

input is used to advance the internal burst counter,

controlling burst access after the external address is loaded.

LD

When HIGH, R/ is ignored. A LOW on this pin permits a

W

new address to be loaded at CLK rising edge.

PRELIMINARY

(December, 1999, Version 0.1)

5

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

Pin Description (continued)

Pin No.

Symbol

Description

LQFP (X16/X18)

LQFP (X32/X36)

87

CEN

Synchronous Clock Enable : This active low input permits

CLK to propagate throughout the device. When HIGH, the

device ignores the CLK input and effectively internally

extends the previous CLK cycle. This input must meet setup

and hold times around the rising edge of CLK.

64

88

64

88

ZZ

Snooze Enable : This active high asynchronous input

causes the device to enter a low-power standby mode in

which all data in the memory array is retained. When active,

all other inputs are ignored.

R/

Read/Write : This active input determines the cycle type

W

when ADV/

is LOW. This is the only means for

LD

determining READs and WRITEs. READ cycles may not be

converted into WRITEs (and vice versa) other than by

loading a new address. A LOW on this pin permits BYTE

WRITE operations and must meet the setup and hold times

around the rising edge of CLK. Full bus width WRITEs

occur if all byte write enables are LOW.

(a) 58, 59, 62, 63,

68, 69, 72, 73

(b) 8,9,12,13, 18,

19, 22,23

(a) 52, 53, 56, 57,

58, 59, 62, 63

(b) 68, 69, 72, 73,

74, 75, 78, 79

(c) 2, 3, 6, 7, 8, 9,

12, 13,

I/Oa

I/Ob

I/Oc

I/Od

SRAM Data I/O : Byte “a” is I/Oa pins; Byte “b” is I/Ob pins;

Byte “c” is I/Oc pins; Byte “d” is I/Od pins. Input data must

meet setup and hold times around CLK rising edge.

(d) 18, 19, 22, 23,

24, 25, 28, 29

74

24

51

80

1

NC/I/Oa

NC/I/Ob

NC/I/Oc

NC/I/Od

No Connect/Data Bits : On the X16/32 version, these pins

are no connect (NC) and can be left floating or connected to

GND to minimize thermal impedance. On the X18/36

version, these bits are I/Os.

30

31

MODE

Mode : This input selects the burst sequence. A LOW on

this pin selects linear burst. NC or HIGH on this pin selects

interleaved burst. Do not alter input state while device is

operating.

1, 2, 3, 6, 7, 25,

28, 29, 30, 38, 39,

42, 43, 51, 52, 53,

56, 57, 75, 78, 79,

83, 84, 95, 96

38,39,42,43

83,84

NC

No Connect : These pins can be left floating or connected to

GND to minimize thermal impedance.

PRELIMINARY

(December, 1999, Version 0.1)

6

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

Pin Description (continued)

Pin No.

Symbol

Description

LQFP (X16/X18)

LQFP (X32/X36)

15, 41, 65, 91

VCC

Power Supply : See DC Electrical Characteristics and

Operating Conditions for range.

14, 16, 66

These pins do not have to be connected directly to VCC as

long as the input voltage is ³ VIH. This input is not

connected to VCC bus internally.

4, 11, 20, 27,

54, 61, 70, 77

4, 11, 20, 27,

54, 61, 70, 77

VCCQ

Isolated Output Buffer Supply : See DC Electrical

Characteristics and Operating Conditions for range.

17, 40, 90

VSS

Ground : GND.

5,10,21,26,

55,60,71,76

5,10,21,26,

55,60,71,76

VSSQ

Isolated Output Buffer Ground

PRELIMINARY

(December, 1999, Version 0.1)

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AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

Truth Table (Notes 5 - 7)

Address

Used

CE2 ZZ ADV/ R/

LD

OE

X

L

CLK

I/O

Notes

W

CE CE2

BWx

X

CEN

L

Operation

Deselected Cycle,

Power-down

None

H

X

L

X

H

X

L

X

L

H

L

X

L® H High-Z

Deselected Cycle,

Power-down

None

L

X

H

X

H

X

L

X

L

Deselected Cycle,

Power-down

L

X

L

Continue Deselect

Cycle

None

X

H

X

H

X

H

X

H

X

H

L

X

L

1

READ Cycle

(Begin Burst)

External

L

L® H

Q

READ Cycle

X

L

X

L

H

L

X

L

1,7

2

(Continue Burst)

NOP/Dummy READ

(Begin Burst)

External

H

X

L

L® H High-Z

Dummy READ

(Continue Burst)

WRITE Cycle

(Begin Burst)

X

L

X

L

H

L

X

L

1,2,7

3

External

L

L® H

D

WRITE Cycle

(Continue Burst)

NOP/WRITE Abort

(Begin Burst)

X

L

X

L

H

L

X

L

1,3,7

2,3

None

H

X

L

L® H High-Z

WRITE Abort

(Continue Burst)

IGNORE Clock Edge

(Stall)

X

H

X

L

L® H High-Z 1,2,3,7

Current

None

H

X

L® H

-

4

SLEEP Mode

X

High-Z

Notes:

1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or

WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is

executed first.

2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE

Abort means a WRITE command is given, but no operation is performed.

3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off

the output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not

meet their requirements.

4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs

during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock

Edge cycle.

5. X means “Don’t Care.” H means logic HIGH. L means logic LOW.

= H means all byte write signals

BWx

(

,

and

) are HIGH.

BWx

= L means one or more byte write signals are LOW.

BW1 BW2

BW4

BW3

6.

enables WRITEs to Byte “a” (I/Oa pins);

enables WRITEs to Byte “b” (I/Ob pins);

enables WRITEs to

BW3

BW1

BW2

enables WRITEs to Byte “d” (I/Od pins).

Byte “c” (I/Oc pins);

BW4

7. The address counter is incremented for all Continue Burst cycles.

PRELIMINARY

(December, 1999, Version 0.1)

8

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

Partial Truth Table for READ/WRITE Commands (X16/X18)

Operation R/

W

BW1

BW2

READ

H

X

WRITE Byte “a”

WRITE Byte “b”

WRITE all bytes

WRITE Abort/NOP

L

H

L

H

L

H

Note : Using and BYTE WRITE(s), any one or more bytes may be written.

Partial Truth Table for READ/WRITE Commands (X32/X36)

Operation

R/

BW3

X

W

BW1

BW2

BW4

READ

H

X

WRITE Byte “a”

WRITE Byte “b”

WRITE Byte “c”

WRITE Byte “d”

WRITE all bytes

WRITE Abort/NOP

L

H

L

H

L

H

L

H

L

H

L

H

Note : Using R/ and BYTE WRITE(s), any one or more bytes may be written.

W

Linear Burst Address Table (MODE = LOW)

First Address (External)

X . . . X00

Second Address (Internal)

X . . . X01

Third Address (Internal)

X . . . X10

Fourth Address (Internal)

X . . . X11

X . . . X01

X . . . X10

X . . . X11

X . . . X00

X . . . X10

X . . . X11

X . . . X00

X . . . X01

X . . . X11

X . . . X00

X . . . X01

X . . . X10

Interleaved Burst Address Table (MODE = HIGH or NC)

First Address (External)

X . . . X00

Second Address (Internal)

X . . . X01

Third Address (Internal)

X . . . X10

Fourth Address (Internal)

X . . . X11

X . . . X01

X . . . X00

X . . . X11

X . . . X10

X . . . X11

X . . . X00

X . . . X01

X . . . X11

X . . . X10

X . . . X01

X . . . X00

PRELIMINARY

(December, 1999, Version 0.1)

9

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

Absolute Maximum Ratings*

*Comments

Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V

Voltage Relative to GND for any Pin Except VCC (Vin,

Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC

+0.5V

Operating Temperature (Topr) . . . . . . . . . . . 0°C to 70°C

Storage Temperature (Tbias) . . . . . . . . . . -10°C to 85 °C

Storage Temperature (Tstg) . . . . . . . . . . -55°C to 125°C

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to this device.

These are stress ratings only. Functional operation of

this device at these or any other conditions above those

indicated in the operational sections of this specification

is not implied or intended. Exposure to the absolute

maximum rating conditions for extended periods may

affect device reliability.

DC Electrical Characteristics and Operating Conditions

(0°C £ TA £ 70°C, VCC, VCCQ = +3.3V± 5% unless otherwise noted)

Symbol

VIH

Parameter

Input High Voltage

Conditions

Min.

2.0

Max.

VCC+0.3

0.8

Unit

V

Note

1,2

3

VIL

Input Low Voltage

-0.3

-1.0

V

ILI

Input Leakage Current

Output Leakage Current

0V £ VIH £ VCC

1.0

mA

ILO

Output(s) disabled,

1.0

0V £ VIN£ VCC

VOH

VOL

Output High Voltage

Output Low Voltage

Supply Voltage

IOH = -4.0mA

IOL = 8.0mA

2.4

V

1,4

1

0.4

VCC

VCCQ

3.135

3.465

VCC

Isolated Output Buffer Supply

1,5

Capacitance

Symbol

CI

Parameter

Conditions

TA = 25°C; f = 1MHz

VCC = 3.3V

Typ.

Max.

4

Unit

pF

Note

Control Input Capacitance

Input/Output Capacitance (I/O)

Address Capacitance

3

4

3

6

CO

5

pF

CA

3.5

pF

Note : 1. All voltages referenced to VSS (GND).

2. Overshoot : VIH £ +4.6V for t £ tKHKH/2 for I £ 20mA

Undershoot : VIL ³ -0.7V for t £ tKHKH/2 for I £ 20mA

Power-up : VIH £ +3.456V and VCC £ 3.135V for t £ 200ms

3. MODE pin has an internal pull-up and exhibits an input leakage current of ±10mA.

4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values.

AC I/O curves are available upon request.

5. VCC and VCCQ can be externally wired together to the same power supply.

6. This parameter is sampled.

PRELIMINARY

(December, 1999, Version 0.1)

10

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

ICC Operating Condition and Maximum Limits

Max.

-5

Symbol

Parameter

Unit

Conditions

-4.5

-6

Device selected; All inputs £ VIL

or ³ VIH; Cycle time ³ tKC (MIN);

VCC = MAX; Outputs open

ICC

Power Supply Current : Operating

300

250

10

230

mA

Device selected; VCC = MAX;

³ VIH;

CEN

ICC1

Power Supply Current : Idle

12

8

mA

All inputs £ VSS+0.2 or ³ VCC-0.2;

Cycle time ³ tKC (MIN)

Device deselected; VCC = MAX;

All inputs £VSS+0.2 or ³ VCC-0.2;

All inputs static; CLK frequency=0

ISB2

ISB3

10

25

10

25

10

25

mA

CMOS Standby

TTL Standby

Device deselected; VCC = MAX;

All inputs £ VIL; or ³ VIH;

All inputs static; CLK frequency=0

Device deselected; VCC = MAX;

All inputs £ VSS+0.2 or ³ VCC-0.2;

Cycle time ³ tKC (MIN)

mA

ISB4

Clock Running

SLEEP Mode

65

10

60

10

60

10

ISB2Z

ZZ ³ VIH

PRELIMINARY

(December, 1999, Version 0.1)

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AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

AC Characteristics (Note 4)

(0°C £ TA £ 70°C, VCC = 3.3V± 5%)

-4.5

-5

-6

Symbol

Parameter

Unit

Note

Min.

Max.

Min.

Max.

Min.

Max.

Clock

tKHKH

tKF

Clock cycle time

8.5

-

10

-

12

-

83

-

ns

MHz

ns

Clock frequency

Clock HIGH time

Clock LOW time

117

100

tKHKL

tKLKH

3.4

-

3.5

-

4.0

-

ns

Output Times

tKHQV

tKHQX

tKHQX1

tKHQZ

tGLQV

tGLQX

tGHQZ

Clock to output valid

-

1.5

-

4.5

-

1.5

-

5.0

-

1.5

-

6.0

-

ns

Clock to output invalid

Clock to output in Low-Z

Clock to output in High-Z

OE to output valid

-

1,2,3

4

4.5

-

5.0

-

6.0

-

0

1,2,3

OE to output in Low-Z

OE to output in High-Z

-

4.5

-

5.0

-

6.0

Setup Times

tAVKH

tEVKH

tCVKH

tDVKH

Address

Clock enable (

2.0

1.7

-

2.2

2.0

-

2.5

-

ns

5

)

CEN

Control signals

Data-in

Hold Times

tKHAX

tKHEX

tKHCX

tKHDX

Address

Clock enable (

0.5

-

0.5

-

1.0

-

ns

5

CEN

Control signals

Data-in

Notes: 1. This parameter is sampled.

2. Output loading is specified with C1=5pF as in Figure 2.

3. Transition is measured ±200mV from steady state voltage.

4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system for

turnaround timing.

5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of

CLK when ADV/

is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with

LD

stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each

rising edge of CLK (when ADV/ is LOW) to remain enabled.

LD

PRELIMINARY

(December, 1999, Version 0.1)

12

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

AC Test Conditions

Input Pulse Levels

GND to 3V

1.5ns

Input Rise and Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

1.5V

See Figures 1 and 2

+3.3V

317W

Q

ZO=50W

50W

5pF

351W

VT=1.5V

Figure 1

Output Load Equivalent

Figure 2

Output Load Equivalent

PRELIMINARY

(December, 1999, Version 0.1)

13

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

SLEEP Mode

SLEEP Mode is a low current “Power-down” mode in

which the device is deselected and current is reduced to

ISB2Z. This duration of SLEEP Mode is dictated by the

length of time the ZZ is in a HIGH state. After entering

SLEEP Mode, all inputs except ZZ become disabled and

all outputs go to High-Z.

becomes logic HIGH, ISB2Z is guaranteed after the time

tZZI is met, Any operation pending when entering SLEEP

Mode is not guaranteed to successfully complete.

Therefore, SLEEP Mode (READ or WRITE) must not be

initiated until valid pending operations are completed.

Similarly, when exiting SLEEP Mode during tRZZ, only a

DESELECT or READ cycle should be given while the

SRAM is transitioning out of SLEEP Mode.

The ZZ pin is asynchronous, active high input that causes

the device to enter SLEEP Mode. When the ZZ pin

SLEEP Mode Electrical Characteristics

(VCC, VCCQ = +3.3V±5%)

Symbol

ISB2Z

tZZ

Parameter

Conditions

Min.

Max.

10

Unit

mA

ns

Note

Current during SLEEP Mode

ZZ active to input ignored

ZZ inactive to input sampled

ZZ active to snooze current

ZZ inactive to exit snooze current

ZZ ³ VIH

-

0

-

2(tKHKH)

1

tRZZ

ns

tZZI

ns

tRZZI

0

ns

Note : 1. This parameter is sampled.

SLEEP Mode Waveform

CLK

t

ZZ

t

RZZ

ZZ

t

ZZI

ISUPPLY

I

ISB2Z

RZZI

t

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Output

(Q)

High-Z

: Don't Care

PRELIMINARY

(December, 1999, Version 0.1)

14

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

READ/WRITE Timing

1

2

3

4

5

6

7

8

9

10

tKHKH

CLK

CEN

CE

tKHKL

tEVKH

tCVKH

tKHEX

tKHCX

tKLKH

ADV/

LD

R/W

BWx

ADDRESS

A2

A3

A4

A5

A6

A7

A1

tAVKH

tKHAX

tKHQV

tKHQX1

tKHQX

tGLQV

tKHQZ

tDVKH

tKHDX

Q(A4+1)

I/O

D(A1)

D(A2)

D(A2+1)

Q(A3)

Q(A4)

D(A5)

Q(A6)

tKHQX

tGHQZ

tGLQX

OE

COMMAND

BURST

WRITE

D(A2+1)

BURST

READ

Q(A4+1)

READ

Q(A4)

WRITE

D(A1)

WRITE

D(A2)

READ

Q(A3)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

: Don't Care

: Undefined

Note : 1. For this waveform, ZZ is tied LOW.

2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional.

3. represents three signals. When = 0, it represents = 0, = 0, CE2 = 1.

CE

CE2

4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The

most recent data may be from the input data register.

PRELIMINARY

(December, 1999, Version 0.1)

15

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

NOP, STALL and Deselect Cycles

1

2

3

4

5

6

7

8

9

10

CLK

CEN

CE

ADV/

LD

R/W

BWx

ADDRESS

I/O

A1

A2

A3

A4

A5

t

KHQZ

D(A1)

Q(A2)

Q(A3)

D(A4)

Q(A5)

t

KHQX

COMMAND

WRITE

D(A4)

CONTINUE

DESELECT

WRITE

D(A1)

READ

Q(A2)

READ

Q(A3)

READ

Q(A5)

STALL

NOP

DESELECT

: Don't Care

: Undefined

Note : 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates

being used to create a “pause.” A WRITE

= 0, CE2 = 1.

CEN

CE2

is not performed during this cycle.

2. For this waveform, ZZ and

are tied LOW.

OE

represents three signals. When

3.

= 0, it represents

= 0,

CE

4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The

most recent data may be from the input data register.

PRELIMINARY

(December, 1999, Version 0.1)

16

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

Ordering Information

Part No.

Configure

Cycle Time / Access Time

Package

A67L8316E-4.5

A67L8316E-5

A67L8316E-6

A67L8318E-4.5

A67L8318E-5

A67L8318E-6

A67L7332E-4.5

A67L7332E-5

A67L7332E-6

A67L7336E-4.5

A67L7336E-5

A67L7336E-6

8.5ns / 4.5ns

10ns / 5ns

12ns / 6ns

8.5ns / 4.5ns

10ns / 5ns

12ns / 6ns

8.5ns / 4.5ns

10ns / 5ns

12ns / 6ns

8.5ns / 4.5ns

10ns / 5ns

12ns / 6ns

256K X 16

100L LQFP

256K X 18

128K X 32

128K X 36

100L LQFP

PRELIMINARY

(December, 1999, Version 0.1)

17

AMIC Technology, Inc.

A67L8316/A67L8318/

A67L7332/A67L7336 Series

Package Information

LQFP 100L Outline Dimensions

unit: inches/mm

HE

A2

A1

E

y

80

51

81

50

31

100

1

30

b

c

e

q

Dimensions in inches

Dimensions in mm

Symbol

Min.

0.002

0.053

0.011

0.005

0.860

0.783

0.624

0.547

Nom.

-

Max.

Min.

0.05

Nom.

-

Max.

-

A1

A2

b

-

0.055

0.013

-

0.057

0.015

0.008

0.872

0.791

0.636

0.555

1.35

1.40

1.45

0.37

0.20

22.15

20.10

16.15

14.10

0.27

0.32

c

0.12

-

HE

E

0.866

0.787

0.630

0.551

0.026 BSC

0.024

0.039 REF

-

21.85

19.90

15.85

13.90

22.00

20.00

16.00

14.00

0.65 BSC

0.60

HD

D

e

L

0.018

0.030

0.45

0.75

L1

y

1.00 REF

-

0.004

-

0.1

q

0°

3.5°

7°

0°

3.5°

7°

Notes:

1. Dimensions D and E do not include mold protrusion.

2. Dimensions b does not include dambar protrusion.

Total in excess of the b dimension at maximum material condition.

Dambar cannot be located on the lower radius of the foot.

PRELIMINARY

(December, 1999, Version 0.1)

18

AMIC Technology, Inc.


型号：	A67L8316
厂家：	AMIC TECHNOLOGY
描述：	256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM 256K X 16/18 ， 128K X 32/36 LVTTL ，流水线DBA SRAM 静态存储器
文件：	总19页 (文件大小：275K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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