A82DL3228TG-70IF [AMICC]
Memory IC;
| 型号： | A82DL3228TG-70IF |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | Memory IC |
| 文件： | 总61页 (文件大小：869K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A82DL32x8T(U) Series
Stacked Multi-Chip Package (MCP) Flash Memory and SUPER RAM,
A82DL32x8T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memory and 8M (512Kx16 Bit) SUPER RAM
Preliminary
Document Title
Stacked Multi-Chip Package (MCP) Flash Memory and SUPER RAM, A82DL32x8T(U) 32
Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
and 8M (512Kx16 Bit) SUPER RAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
0.2
Initial issue
July 6, 2006
April 12, 2007
April 19, 2007
Preliminary
Modify toggle bit mechanism
Remover deep power down mode and data retention characteristics
Modify timing waveforms
PRELIMINARY (April, 2007, Version 0.2)
AMIC Technology, Corp.
A82DL32x8T(U) Series
Stacked Multi-Chip Package (MCP) Flash Memory and SUPER RAM,
A82DL32x8T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memory and 8M (512Kx16 Bit) SUPER RAM
Preliminary
DISTINCTIVE CHARACTERISTICS
MCP Features
- Suspends erase operations to allow programming in
same bank
Software temporary sector block unprotect command
Software sector protect/unprotect command
Single power supply operation 2.7 to 3.3 volt
High Performance
- Access time as fast as 70ns
Package 69-Ball TFBGA (8x11x1.4 mm)
All Pb-free (Lead-free) products are RoHS compliant
Industrial operating temperature range: -40°C to 85°C for
–U, -25°C to 85°C for –I
Polling and Toggle Bit
Data
- Provides a software method of detecting the status of
program or erase cycles
Unlock Bypass Program command
- Reduces overall programming time when issuing multiple
program command sequences
Flash Features
HARDWARE FEATURES
Any combination of sectors can be erased
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
- Data can be continuously read from one bank while
executing erase/program functions in other bank
- Zero latency between read and write operations
Multiple bank architectures
- Three devices available with different bank sizes (refer to
Table 2)
Package
Ready/
output (RY/
)
BY
Busy
- Hardware method for detecting program or erase cycle
completion
Hardware reset pin (
)
RESET
- Hardware method of resetting the internal state machine
to reading array data
/ACC input pin
- 69-Ball TFBGA (8x11x1.4 mm)
WP
- All Pb-free (Lead-free) products are RoHS compliant
Top or bottom boot block
- Write protect (
outermost boot sectors, regardless of sector protect
status
) function allows protection of two
WP
Manufactured on 0.18 µm process technology
- Compatible with Am29DL32x4G devices
Compatible with JEDEC standards
- Pinout and software compatible with single-power-supply
flash standard
- Acceleration (ACC) function accelerates program timing
Sector protection
- Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
- Temporary Sector Unprotect allows changing data in
protected sectors in-system
PERFORMANCE CHARACTERISTICS
High performance
- Access time as fast as 70ns
- Program time: 6µs/word typical utilizing Accelerate
function
SUPER RAM Features
Ultra low power consumption (typical values)
- 2mA active read current at 1MHz
- 10mA active read current at 5MHz
- 500nA in standby or automatic sleep mode
Typical 100,000 write cycles guaranteed per sector
Power supply range: 2.7V to 3.3V
Access times: 70 ns (max.)
Current:
Very low power version: Operating: 20mA(max.)
Standby: 100uA (max.)
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Output enable and two chips enable inputs for easy
application
SOFTWARE FEATURES
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
PRELIMINARY (April, 2007, Version 0.2)
1
AMIC Technology, Corp.
A82DL32x8T(U) Series
GENERAL DESCRIPTION
A82DL32x8T(U) Features
The A82DL32x8T(U) family consists of 32 megabit, 3.0 volt-
only flash memory devices, organized as 2,097,152 words of
16 bits each or 4,194,304 bytes of 8 bits each. Word mode
data appears on I/O0–I/O15; byte mode data appears on I/O0–
I/O7. The device is designed to be programmed in-system
with the standard 3.0 volt VCC supply, and can also be
programmed in standard EPROM programmers.
The device offers complete compatibility with the JEDEC
single-power-supply Flash command set standard.
Commands are written to the command register using
standard microprocessor write timings. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.
The device is available with an access time of 70ns. The
devices are offered in 69-ball Fine-pitch BGA. Standard
The host system can detect whether a program or erase
operation is complete by using the device status bits:
control pins—chip enable (
), write enable (
), and
WE
RY/
pin, I/O7 (
Polling) and I/O6/I/O2 (toggle bits).
Data
CE_F
BY
After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The device is fully erased when
shipped from the factory.
output enable (
)—control normal read and write
OE
operations, and avoid bus contention issues.
The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any
combination of the sectors of memory. This can be achieved
Simultaneous Read/Write Operations with Zero
Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory space into
two banks. The device can improve overall system
in-s y s t e m or via programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system
can also place the device into the standby mode. Power
consumption is greatly reduced in both modes.
performance by allowing a host system to program or erase
in one bank, then immediately and simultaneously read from
the other bank, with zero latency. This releases the system
from waiting for the completion of program or erase
operations.
The A82DL32x8T(U) devices uses multiple bank archi-
tectures to provide flexibility for different applications. Three
devices are available with these bank sizes:
Device
DL3228
DL3238
DL3248
Bank 1
4 Mb
Bank 2
28 Mb
24 Mb
16 Mb
8 Mb
16 Mb
PRELIMINARY (April, 2007, Version 0.2)
2
AMIC Technology, Corp.
A82DL32x8T(U) Series
Pin Configurations
69-Ball TFBGA
Top View
Flash only
A1
A5
A6
A10
SRAM only
Shared
NC
NC
NC
NC
B1
B3
B4
B5
B6
B7
B8
NC
A7
LB_S
WP/ACC
WE
A8
A11
C2
A3
C3
A6
C4
C5
C6
C7
C8
C9
UB_S
RESET
CE2_S
A19
A12
A15
D2
A2
D4
A5
D4
D5
D6
D7
A9
D8
D9
A18
RY/BY
A20
A13
NC
E1
E2
E3
E4
E7
E8
E9
E10
NC
NC
A1
A4
A17
A10
A14
NC
F9
F1
F2
F3
F4
F7
F8
F10
NC
NC
A0
VSS
I/O1
I/O6
NC
A16
G2
G3
G4
G5
G6
G7
G8
G9
CE_F
OE
I/O9
I/O3
I/O4
I/O13 I/O15(A-1)
BYTE_F
H2
H3
H4
H5
H6
H7
H8
H9
CE1_S
I/O0
I/O10
VCC_F
VCC_S
I/O12
I/O7
VSS
J3
J4
J5
J6
J7
J8
I/O8
I/O2
I/O11
NC
I/O5
I/O14
K1
K5
K6
K10
NC
NC
NC
NC
Special Handling Instructions for TFBGA Package
Special handling is required for Flash Memory products in TFBGA packages.
Flash memory devices in TFBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or
data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time
PRELIMINARY (April, 2007, Version 0.2)
3
AMIC Technology, Corp.
A82DL32x8T(U) Series
Product Information Guide
Part Number
A82DL32x8T(U)
Standard Voltage Range:
70
Speed Options
VCC_F/VCC_S=2.7-3.3V
Max Access Time (ns)
70
70
/
Access (ns)
CE_F CE1_S
Access (ns)
30
OE
MCP Block Diagram
VCC_F
VSS
A20 to A0
A20 to A0
RY/BY
BYTE_F
WP/ACC
CE_F
32M Bit
Flash Memory
I/O15 (A-1) to I/O0
RESET
I/O15 (A-1) to I/O0
VCC_S
VSS
A18 to A0
WE
OE
8M Bit
Super RAM
I/O15 (A-1) to I/O0
LB_S
UB_S
CE1_S
CE2_S
PRELIMINARY (April, 2007, Version 0.2)
4
AMIC Technology, Corp.
A82DL32x8T(U) Series
Flash Block Diagram
VCC_F
VSS
BYTE_F
OE
A0-A20
Upper Bank Address
Upper Bank
X-Decoder
RY/BY
A0-A20
STATE
CONTROL
&
COMMAND
REGISTER
RESET
WE
CE_F
BYTE_F
WP/ACC
Status
I/O0-I/O15
Control
I/O0-I/O15
X-Decoder
Upper Bank
Lower Bank Address
A0-A20
OE
BYTE_F
PRELIMINARY (April, 2007, Version 0.2)
5
AMIC Technology, Corp.
A82DL32x8T(U) Series
Pin Descriptions
Logic Symbol
Pin No.
A0 – A20
I/O0 - I/O14
Description
Address Inputs
Data Inputs/Outputs
21
A0-A20
I/O15 Data Input/Output, Word Mode
A-1 LSB Address Input, Byte Mode
Chip Enable (Flash)
16 or 8
I/O15 (A-1)
I/O0-I/O15(A-1)
LB_S
UB_S
CE1_S
CE2_S
CE_F
OE
CE_F
CE1_S
CE2_S
WE
Chip Enable (SUPER RAM)
Write Enable
WE
Output Enable
OE
WP/ACC
RESET
RY/BY
/ACC
WP
RESET
BYTE_F
Hardware Write Protect/Acceleration Pin
Hardware Reset Pin, Active Low
BYTE_F
Selects 8-bit or 16-bit Mode
RY/
Ready/
Output
BUSY
BY
VSS
Ground
VCC_F
VCC_S
NC
Power Supply (Flash)
Power Supply (SUPER RAM)
Pin Not Connected Internally
Lower Byte(I/O0 - I/O7)
LB_S
UB_S
Upper Byte(I/O8 - I/O15)
PRELIMINARY (April, 2007, Version 0.2)
6
AMIC Technology, Corp.
A82DL32x8T(U) Series
SUPER RAM Block Diagram
VCC_S
VSS
A0
512K X 16
DECODER
MEMORY ARRAY
A16
A18
I/O0
I/O7
I/O8
COLUMN I/O
INPUT
DATA
INPUT
DATA
CIRCUIT
CIRCUIT
I/O15
CE2_S
CE1_S
LB_S
CONTROL
CIRCUIT
UB_S
OE
WE
PRELIMINARY (April, 2007, Version 0.2)
7
AMIC Technology, Corp.
A82DL32x8T(U) Series
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1-1. Device Bus Operations – Flash Word Mode (
= VIH)
BYTE_F
Operation
(Notes 1, 2)
I/O7–
I/O0
I/O15–
I/O8
CE1_S
CE_F
UB_S
(Note3)
LB_S
(Note3)
OE
RESET
CE2_S
WE A0-A20
/ACC
WP
(Note 4)
Read from Flash
Write to Flash
Standby
L
L
H
H
H
L
H
H
H
H
L
H
X
H
H
L
AIN
AIN
X
X
X
X
X
X
X
X
X
H
H
L/H
(Note 5)
L/H
IOUT
IIN
IOUT
IIN
VCC_F
± 0.3 V
VCC_F±
0.3 V
X
H
High-Z
High-Z
High-Z
High-Z
Output Disable
L
X
H
L
L/H
Flash Hardware
Reset
X
H
H
H
H
X
H
X
L
X
X
X
X
X
L/H
L/H
High-Z
High-Z
X
SA,
A6 = L,
A1 = H,
A0 = L
Sector Protect
(Note 4)
L
VID
IIN
SA,
Sector Unprotect
(Note 4)
A6 = H,
A1 = H,
A0 = L
L
X
H
H
H
L
H
H
H
H
X
L
L
X
H
X
X
X
X
VID
VID
H
L/H
L/H
L/H
IIN
IIN
X
Temporary
Sector Unprotect
AIN
AIN
High-Z
H
L
L
H
L
High-Z
IOUT
IOUT
High-Z
IOUT
Read from
SUPER RAM
L
IOUT
H
L
L
High-Z
IIN
IIN
Write to SUPER
RAM
H
High-Z
H
L
H
X
L
AIN
H
L/H
L
L
IIN
IIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–10.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, IIN = Data In, IOUT = Data Out
Notes:
1.Other operations except for those indicated in this column are inhibited.
2.Do not apply
CE_F
3.Don’t care or open
= VIL and
= VIL at the same time.
CE1_S
.
UB_S
or
LB_S
4.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector/Sector Block Protection and Unprotection” section.
5. If
/ACC = VIL, the two outermost boot sectors remain protected. If
/ACC = VIH, the two outermost boot sector
WP
WP
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If /ACC = VHH, all sectors will be unprotected.
WP
PRELIMINARY (April, 2007, Version 0.2)
8
AMIC Technology, Corp.
A82DL32x8T(U) Series
Table 1-2. Device Bus Operations – Flash Byte Mode (
= VIL)
BYTE_F
LB_S
WE A0-A20
Operation
I/O7–
I/O0
I/O15–
I/O8
CE_F
CE1_S
UB_S
(Note3)
OE
RESET
CE2_S
/ACC
WP
(Notes 1, 2)
(Note 4)
(Note3)
Read from Flash
Write to Flash
Standby
L
L
H
H
H
L
H
H
H
H
L
H
X
H
H
L
AIN
AIN
X
X
X
X
X
X
H
H
L/H
(Note 5)
L/H
IOUT
IIN
High-Z
I/O14–8 =Hi-Z;
I/O15=A-1
X
X
X
VCC_F
± 0.3 V
VCC_F±
0.3 V
X
H
High-Z
High-Z
High-Z
High-Z
High-Z
Output Disable
L
X
H
L
L/H
Flash Hardware
Reset
X
H
H
H
H
X
H
X
L
X
X
X
X
X
L/H
L/H
High-Z
SA,
Sector Protect
(Note 4)
A6 = L,
A1 = H,
A0 = L
L
VID
IIN
X
SA,
Sector Unprotect
(Note 4)
A6 = H,
A1 = H,
A0 = L
L
X
H
H
H
L
H
H
H
H
X
L
L
X
H
X
X
X
X
VID
VID
L/H
L/H
L/H
IIN
IIN
X
Temporary
Sector Unprotect
AIN
AIN
High-Z
H
L
L
H
L
High-Z
IOUT
IOUT
High-Z
IOUT
Read from
SUPER RAM
H
H
L
IOUT
H
L
L
High-Z
IIN
IIN
Write to SUPER
RAM
H
High-Z
H
L
H
X
L
AIN
L/H
L
L
IIN
IIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–10.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, IIN = Data In, IOUT = Data Out
Notes:
1.Other operations except for those indicated in this column are inhibited.
2.Do not apply
CE_F
3.Don’t care or open
= VIL and
= VIL at the same time.
CE1_S
or
.
LB_S
UB_S
4.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector/Sector Block Protection and Unprotection” section.
5. If
/ACC = VIL, the two outermost boot sectors remain protected. If
/ACC = VIH, the two outermost boot sector
WP
WP
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If /ACC = VHH, all sectors will be unprotected.
WP
PRELIMINARY (April, 2007, Version 0.2)
9
AMIC Technology, Corp.
A82DL32x8T(U) Series
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Word/Byte Configuration
The
pin determines whether the I/O pins I/O15-I/O0
BYTE_F
Accelerated Program Operation
operate in the byte or word configuration. If the
pin
BYTE_F
is set at logic ”1”, the device is in word configuration, I/O15-
I/O0 are active and controlled by and
The device offers accelerated program operations through
the ACC function. This is one of two functions provided by
.
OE
CE_F
the
/ACC pin. This function is primarily intended to allow
WP
faster manufacturing throughput at the factory.
If the
pin is set at logic “0”, the device is in byte
BYTE_F
configuration, and only I/O0-I/O7 are active and controlled by
and . I/O8-I/O14 are tri-stated, and I/O15 pin is
If the system asserts VHH on this pin, the device automatically
enters the aforementioned Unlock Bypass mode, temporarily
unprotects any protected sectors, and uses the higher
voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program
command sequence as required by the Unlock Bypass
OE
CE_F
used as an input for the LSB(A-1) address function.
Requirements for Reading Array Data
mode. Removing VHH from the
/ACC pin returns the
WP
To read array data from the outputs, the system must drive
device to normal operation. Note that the
not be at VHH for operations other than accelerated program-
ming, or device damage may result. In addition, the
/ACC pin must
WP
the
and
pins to VIL.
is the power control
OE
CE_F
CE_F
and selects the device.
OE
array data to the output pins.
is the output control and gates
/ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result.
WP
should remain at VIH. The
WE
pin determines whether the device outputs array
BYTE_F
data in words or bytes.
Autoselect Functions
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that
no spurious alteration of the memory content occurs during
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. Each bank
remains enabled for read access until the command register
contents are altered.
See "Requirements for Reading Array Data" for more
information. Refer to the AC Read-Only Operations table for
timing specifications and to Figure 11 for the timing
waveform, lCC1_F in the DC Characteristics table represents
the active current specification for reading array data.
If the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7-I/O0. Standard read
cycle timings apply in this mode. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for more
information.
Simultaneous Read/Write Operations with Zero
Latency
This device is capable of reading data from one bank of
memory while programming or erasing in the other bank of
memory. An erase operation may also be suspended to read
from or program to another location within the same bank
(except the sector being erased). Figure 18 shows how read
and write cycles may be initiated for simultaneous operation
with zero latency. ICC6_F and ICC7_F in the DC Characteristics
table represent the current specifications for read-while-pro-
gram and read-while-erase, respectively.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive
and
to VIL, and
WE
CE_F
to VIH.
OE
Standby Mode
For program operations, the
pin determines
BYTE_F
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
whether the device accepts program data in bytes or words,
Refer to “Word/Byte Configuration” for more information.
The device features an Unlock Bypass mode to facilitate
faster programming. Once a bank enters the Unlock Bypass
mode, only two write cycles are required to program a word
or byte, instead of four. The “Word / Byte Program Command
Sequence” section has details on programming data to the
device using both standard and Unlock Bypass command
sequence.
placed in the high impedance state, independent of the
input.
OE
The device enters the CMOS standby mode when the
&
pins are both held at VCC_F ± 0.3V. (Note
RESET
that this is a more restricted voltage range than VIH.) If
and are held at VIH, but not within VCC_F ±
CE_F
RESET
CE_F
An erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables 3-4 indicate the
address range that each sector occupies. The device
address space is divided into two banks: Bank 1 contains the
boot/parameter sectors, and Bank 2 contains the larger, code
sectors of uniform size. A “bank address” is the address bits
required to uniquely select a bank. Similarly, a “sector
address” is the address bits required to uniquely select a
sector.
0.3V, the device will be in the standby mode, but the standby
current will be greater. The device requires the standard
access time (tCE) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3_F in the DC Characteristics tables represent the standby
current specification.
ICC2_F in the DC Characteristics table represents the active
current specification for the write mode. The "AC
PRELIMINARY (April, 2007, Version 0.2)
10
AMIC Technology, Corp.
A82DL32x8T(U) Series
The
pin may be tied to the system reset circuitry. A
Automatic Sleep Mode
RESET
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The automatic
If
is asserted during a program or erase operation,
RESET
sleep mode is independent of the
,
and
WE
OE
CE_F
the RY/
pin remains a “0” (busy) until the internal reset
BY
control signals. Standard address access timings provide
new data when addresses are changed. While in sleep
mode, output data is latched and always available to the
system. ICC4_F in the DC Characteristics table represents the
automatic sleep mode current specification.
operation is complete, which requires a time tREADY (during
Embedded Algorithms). The system can thus monitor
RY/
BY
complete. If
to determine whether the reset operation is
is asserted when a program or erase
RESET
operation is not executing (RY/
operation is completed within a time of tREADY (not during
Embedded Algorithms). The system can read data tRH after
pin is “1”), the reset
BY
: Hardware Reset Pin
RESET
The
pin provides a hardware method of resetting
RESET
the device to reading array data. When the system drives the
pin low for at least a period of tRP, the device
the
pin return to VIH.
RESET
Refer to the AC Characteristics tables for
parameters and diagram.
RESET
RESET
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
Output Disable Mode
the duration of the
pulse. The device also resets the
RESET
When the
input is at VIH, output from the device is
OE
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
disabled. The output pins are placed in the high impedance
state.
Current is reduced for the duration of the
pulse.
RESET
When
is held at VSS ± 0.3V, the device draws
RESET
CMOS standby current (ICC4_F ). If
is held at VIL but
RESET
not within VSS ± 0.3V, the standby current will be greater.
Table 2. A82DL32x8T(U) Device Bank Divisions
Device
Part Number
Bank 1
Sector Sizes
Bank 2
Sector Sizes
Megabits
Megabits
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
Fifty-six
64 Kbyte/32 Kword
A82DL3228
4 Mbit
28 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
Forty-eight
64 Kbyte/32 Kword
A82DL3238
A82DL3248
8 Mbit
24 Mbit
16 Mbit
Eight 8 Kbyte/4 Kword,
Thirty one 64 Kbyte/32 Kword
Thirty-two
64 Kbyte/32 Kword
16 Mbit
PRELIMINARY (April, 2007, Version 0.2)
11
AMIC Technology, Corp.
A82DL32x8T(U) Series
Table 3. Sector Addresses for Top Boot Sector Devices
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
000000XXX
000001XXX
000010XXX
000011XXX
000100XXX
000101XXX
000110XXX
000111XXX
001000XXX
001001XXX
001010XXX
001011XXX
001100XXX
001101XXX
001110XXX
001111XXX
010000XXX
010001XXX
010010XXX
010011XXX
010100XXX
010101XXX
010110XXX
010111XXX
011000XXX
011001XXX
011010XXX
011011XXX
011100XXX
011101XXX
011110XXX
011111XXX
100000XXX
100001XXX
100010XXX
100011XXX
100100XXX
100101XXX
100110XXX
100111XXX
101000XXX
101001XXX
101010XXX
101011XXX
101100XXX
101101XXX
101110XXX
101111XXX
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
000000h–007FFFh
008000h–00FFFFh
010000h–017FFFh
018000h–1FFFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
PRELIMINARY (April, 2007, Version 0.2)
12
AMIC Technology, Corp.
A82DL32x8T(U) Series
Table 3 Sector Addresses for Top Boot Sector Devices
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
Address Range
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
110000XXX
110001XXX
110010XXX
110011XXX
110100XXX
110101XXX
110110XXX
110111XXX
111000XXX
111001XXX
111010XXX
111011XXX
111100XXX
111101XXX
111110XXX
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
3F2000h-3F3FFFh
3F4000h-3F5FFFh
3F6000h-3F7FFFh
3F8000h-3F9FFFh
3FA000h-3FBFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1F8FFFh
1F9000h–1F9FFFh
1FA000h–1FAFFFh
1FB000h–1FBFFFh
1FC000h–1FCFFFh
1FD000h–1FDFFFh
3FC000h-3FDFFFh 1FE000h–1FEFFFh
3FE000h-3FFFFFh
1FF000h–1FFFFFh
Note:
The address range is A20: A-1in byte mode (
=VIL) or A20:A0 in word mode (
=VIH). The bank address bits
BYTE_F
BYTE_F
are A20-A18 for A82DL3228T, A20 and A19 for A82DL3238T, and A20 for A82DL3248T.
PRELIMINARY (April, 2007, Version 0.2)
13
AMIC Technology, Corp.
A82DL32x8T(U) Series
Table 4. Sector Addresses for Bottom Boot Sector Devices
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001XXX
000010XXX
000011XXX
000100XXX
000101XXX
000110XXX
000111XXX
001000XXX
001001XXX
001010XXX
001011XXX
001100XXX
001101XXX
001110XXX
001111XXX
010000XXX
010001XXX
010010XXX
010011XXX
010100XXX
010101XXX
010110XXX
010111XXX
011000XXX
011001XXX
011010XXX
011011XXX
011100XXX
011101XXX
011110XXX
011111XXX
100000XXX
100001XXX
100010XXX
100011XXX
100100XXX
100101XXX
100110XXX
100111XXX
101000XXX
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
000000h-001FFFh
002000h-003FFFh
004000h-005FFFh
006000h-007FFFh
008000h-009FFFh
00A000h-00BFFFh
00C000h-00DFFFh
00E000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
000000h-000FFFh
001000h-001FFFh
002000h-002FFFh
003000h-003FFFh
004000h-004FFFh
005000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
PRELIMINARY (April, 2007, Version 0.2)
14
AMIC Technology, Corp.
A82DL32x8T(U) Series
Table 4. Sector Addresses for Bottom Boot Sector Devices
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
Address Range
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
101001XXX
101010XXX
101011XXX
101100XXX
101101XXX
101110XXX
101111XXX
110000XXX
110001XXX
110010XXX
110011XXX
110100XXX
110101XXX
110110XXX
110111XXX
111000XXX
111001XXX
111010XXX
111011XXX
111100XXX
111101XXX
111110XXX
111111XXX
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
Note:
The address range is A20: A-1in byte mode (
=VIL) or A20:A0 in word mode (
=VIH). The bank address bits
BYTE_F
BYTE_F
are A20-A18 for A82DL3228U, A20 and A19 for A82DL3238U, and A20 for A282DL3248U.
PRELIMINARY (April, 2007, Version 0.2)
15
AMIC Technology, Corp.
A82DL32x8T(U) Series
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically match
must appear on the appropriate highest order address bits.
(see Table 3-4). Table 5 shows the remaining address bits
that are don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.
a
device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (8.5V to 10.5 V) on address pin A9. Address
pins A6, A1, and A0 must be as shown in Table 5. In
addition, when verifying sector protection, the sector address
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command
register, as shown in Table 12. This method does not require
VID. Refer to the Autoselect Command Sequence section for
more information.
Table 5. A82DL32x8T(U) Autoselect Codes (High Voltage Method)
I/O8 to I/O15
A20
to
A12
A11
to
A10
A8
to
A7
A5
to
A4
I/O7
to
I/O0
Description
OE
A9
A6
A3 A2 A1 A0
CE
WE
BYTE BYTE
= VIH
= VIL
Manufacturer ID: AMIC
Device ID: A82DL3228
Device ID: A82DL3238
Device ID: A82DL3248
L
L
L
L
L
L
L
L
H
H
H
H
BA
BA
BA
BA
X
X
X
X
VID
VID
VID
VID
X
X
X
X
L
L
L
L
X
X
X
X
L
X
X
X
L
X
X
X
L
L
L
L
L
H
H
H
X
X
X
X
X
37h
22h
22h
22h
55h (T), 56h (U)
50h (T), 53h (U)
5Ch (T), 5Fh (U)
Continuation ID
L
L
L
L
H
H
X
X
X
VID
VID
X
X
L
L
X
X
X
L
X
L
H
H
H
L
X
X
X
X
7Fh
01h (protected),
00h (unprotected)
Read Sector Status
SA
L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care, BA=Bank Address
Note: The autoselect codes may also be accessed in-system via command sequences.
PRELIMINARY (April, 2007, Version 0.2)
16
AMIC Technology, Corp.
A82DL32x8T(U) Series
Sector/Sector Block Protection and Unprotection
(Note: For the following discussion, the term “sector” applies
to both sectors and sector blocks. A sector block consists of
two or more adjacent sectors that are protected or
unprotected at the same time (see Tables 6 and 7).
Table 6. Top Boot Sector/Sector Block Addresses for
Protection/Unprotection
Table 7. Bottom Boot Sector/Sector Block Addresses for
Protection/Unprotection
Sector /
Sector Block
Sector /
Sector Block
A20–A12
Sector / Sector Block Size
A20–A12
Sector / Sector Block Size
SA0
000000XXX
64 Kbytes
SA70
111111XXX
64 Kbytes
000001XXX,
000010XXX,
000011XXX
111110XXX,
111101XXX,
111100XXX
SA1-SA3
192 (3x64) Kbytes
SA69- SA67
192 (3x64) Kbytes
SA4-SA7
SA8-SA11
0001XXXXX
0010XXXXX
0011XXXXX
0100XXXXX
0101XXXXX
0110XXXXX
0111XXXXX
1000XXXXX
1001XXXXX
1010XXXXX
1011XXXXX
1100XXXXX
1101XXXXX
1110XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
SA66- SA63
SA62- SA59
SA58- SA55
SA54- SA51
1110XXXXX
1101XXXXX
1100XXXXX
1011XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
SA44-SA47
SA48-SA51
SA52-SA55
SA56-SA59
SA50- SA47
1010XXXXX
256 (4x64) Kbytes
SA46-SA43
SA42-SA39
SA38-SA35
SA34-SA31
SA30-SA27
SA26-SA23
SA22-SA19
SA18-SA15
SA14-SA11
1001XXXXX
1000XXXXX
0111XXXXX
0110XXXXX
0101XXXXX
0100XXXXX
0011XXXXX
0010XXXXX
0001XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
111100XXX,
111101XXX,
111110XXX
000001XXX,
000010XXX,
000011XXX
SA60-SA62
192 (3x64) Kbytes
SA10-SA8
192 (3x64) Kbytes
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
000000111
000000110
000000101
000000100
000000011
000000010
000000001
000000000
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
PRELIMINARY (April, 2007, Version 0.2)
17
AMIC Technology, Corp.
A82DL32x8T(U) Series
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors. Sector
protection and unprotection can be implemented via two
methods.
8 Kbyte boot sectors independently of whether those sectors
were protected or unprotected using the method described in
“Sector/Sector Block Protection and Unprotection”. The two
outermost 8 Kbyte boot sectors are the two sectors
containing the lowest addresses in a bottom-boot-configured
device, or the two sectors containing the highest addresses
in a top-boot-configured device.
The primary method requires VID on the
pin only,
RESET
If the system asserts VIH on the
/ACC pin, the device
WP
and can be implemented either in-system or via
programming equipment. Figure 2 shows the algorithms and
Figure 23 shows the timing diagram. This method uses
standard microprocessor bus cycle timing. For sector
unprotect, all unprotected sectors must first be protected
prior to the first sector unprotect write cycle.
The sector unprotect algorithm unprotects all sectors in
parallel. All previously protected sectors must be individually
re-protected. To change data in protected sectors efficiently,
the temporary sector unprotect function is available. See
“Temporary Sector/Sector Block Unprotect”.
reverts to whether the two outermost 8 Kbyte boot sectors
were last set to be protected or unprotected. That is, sector
protection or unprotection for these two sectors depends on
whether they were last protected or unprotected using the
method described in “Sector/Sector Block Protection and
Unprotection”.
Note that the
/ACC pin must not be left floating or
WP
unconnected; inconsistent behavior of the device may result.
Temporary Sector/Sector Block Unprotect
The alternate method for protection and unprotection is by
software temporary sector /sector block unprotect command.
See Figure 2 for Command Flow.
(Note: For the following discussion, the term “sector” applies
to both sectors and sector blocks. A sector block consists of
two or more adjacent sectors that are protected or
unprotected at the same time (see Tables 6 and 7).
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See the Autoselect Mode section for details.
This feature allows temporary unprotection of previously
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the
pin to VID
RESET
(8.5V-10.5V). During this mode, formerly protected sectors
can be programmed or erased by selecting the sector
Write Protect (
/ACC)
WP
The Write Protect function provides a hardware method of
protecting certain boot sectors without using VID. This
addresses. Once VID is removed from the
pin, all the
RESET
previously protected sectors are protected again. Figure 1
shows the algorithm, and Figure 22 shows the timing
diagrams, for this feature.
function is one of two provided by the
/ACC pin.
WP
If the system asserts VIL on the
WP
disables program and erase functions in the two “outermost”
/ACC pin, the device
PRELIMINARY (April, 2007, Version 0.2)
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AMIC Technology, Corp.
A82DL32x8T(U) Series
START
START
555/AA + 2AA/55 + 555/77
(Note 1)
RESET = VID
(Note 1)
Perform Erase or
Program Operations
Perform Erase or
Program Operations
XXX/F0
(Reset Command)
RESET = VIH
Soft-ware Temporary
Sector Unprotect
Completed
Temporary Sector
Unprotect
Completed (Note 2)
(Note 2)
Notes:
Notes:
1. All protected sectors unprotected (If WP/ACC=VIL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once again.
1. All protected sectors unprotected (If WP/ACC=VIL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once again.
Figure 1-2. Temporary Sector Unprotect Operation by Software Mode
Figure 1-1. Temporary Sector Unprotect Operation by RESET Mode
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AMIC Technology, Corp.
A82DL32x8T(U) Series
START
START
Protect all sectors:
The indicated portion of
the sector protect
PLSCNT=1
PLSCNT=1
algorithm must be
performed for all
RESET=VID
RESET=VID
unprotected sectors prior
to issuing the first sector
unprotect address
Wait 1 us
Wait 1 us
No
No
No
Temporary Sector
Unprotect Mode
First Write
Cycle=60h?
First Write
Cycle=60h?
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
All sectors
protected?
Sector Protect:
Write 60h to sector
address with A6=0,
A1=1, A0=0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with A6=1,
A1=1, A0=0
Wait 150 us
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A1=1,
A0=0
Reset
PLSCNT=1
Increment
PLSCNT
Wait 15 ms
Verify Sector
Unprotect : Write
40h to sector
address with A6=1,
A1=1, A0=0
Read from
sector address
with A6=0,
Increment
PLSCNT
A1=1, A0=0
No
Read from sector
address with A6=1,
A1=1, A0=0
No
PLSCNT
=25?
Data=01h?**
Yes
No
Set up
next sector
address
Yes
No
PLSCNT=
1000?
Yes
Data=00h?**
Yes
Protect another
sector?
Device failed
Yes
No
Remove VID
from RESET
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
from RESET
Sector Protect
complete
Sector Protect
Algorithm
Sector Unprotect
Algorithm
Write reset
Command
Note: The term “sector” in the figure applies to both sectors and sector blocks
* No other command is allowed during this process
** Read access time is 200ns-300ns
Sector Unprotect
complete
Figure 2-1. High Voltage Sector/Sector Block Protection and Unprotection Algorithms
PRELIMINARY (April, 2007, Version 0.2)
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AMIC Technology, Corp.
A82DL32x8T(U) Series
START
START
PLSCNT=1
PLSCNT=1
Protect all sectors:
The indicated portion of
the sector protect
555/AA + 2AA/55 +
555/77
555/AA + 2AA/55 +
555/77
algorithm must be
performed for all
unprotected sectors prior
to issuing the first sector
unprotect address
Wait 1 us
Wait 1 us
No
No
No
Temporary Sector
Unprotect Mode
First Write
Cycle=60h?
First Write
Cycle=60h?
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
All sectors
protected?
Sector Protect:
Write 60h to sector
address with A6=0,
A1=1, A0=0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with A6=1,
A1=1, A0=0
Wait 150 us
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A1=1,
A0=0
Reset
PLSCNT=1
Increment
PLSCNT
Wait 15 ms
Verify Sector
Unprotect : Write
40h to sector
address with A6=1,
A1=1, A0=0
Read from
sector address
with A6=0,
Increment
PLSCNT
A1=1, A0=0
No
Read from sector
address with A6=1,
A1=1, A0=0
No
PLSCNT
=25?
Data=01h?**
Yes
No
Set up
next sector
address
Yes
No
PLSCNT=
1000?
Yes
Data=00h?**
Yes
Protect another
sector?
Device failed
Yes
No
Write reset
command
No
Last sector
verified?
Device failed
Sector Protect
complete
Yes
Sector Protect
Algorithm
Write reset
Command
Sector Unprotect
Algorithm
Sector Unprotect
complete
Note: The term “sector” in the figure applies to both sectors and sector blocks
* No other command is allowed during this process
** Access time is 200ns-300ns
Figure 2-2. Software Sector/Sector Block Protection and Unprotection Algorithms
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AMIC Technology, Corp.
A82DL32x8T(U) Series
Hardware Data Protection
Power-Up Write Inhibit
If = VIL and
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to Table 12 for command definitions).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC_F power-up and power-down transitions, or from
system noise.
=
= VIH during power up, the
OE
WE
CE_F
device does not accept commands on the rising edge of
The internal state machine is automatically reset to reading
array data on power-up.
.
WE
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines
device and host system software interrogation handshake,
which allows specific vendor-specified software algorithms to
be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and
forward- and backward-compatible for the specified flash
device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system
writes the CFI Query command, 98h, to address 55h in word
mode (or address AAh in byte mode), any time the device is
ready to read array data. The system can read CFI
information at the addresses given in Tables 8-11. To
Low VCC Write Inhibit
When VCC_F is less than VLKO, the device does not accept
any write cycles. This protects data during VCC_F power-up
and power-down. The command register and all internal
program/erase circuits are disabled, and the device resets to
reading array data. Subsequent writes are ignored until
VCC_F is greater than VLKO. The system must provide the
proper signals to the control pins to prevent unintentional
writes when VCC_F is greater than VLKO.
Write Pulse “Glitch” Protection
terminate reading CFI data, the system must write the reset
command.
Noise pulses of less than 5ns (typical) on
,
or
CE_F
OE
The system can also write the CFI query command when the
device is in the autoselect mode. The device enters the CFI
query mode, and the system can read CFI data at the
addresses given in Tables 8-11. The system must write the
reset command to return the device to the autoselect mode.
do not initiate a write cycle.
WE
Logical Inhibit
Write cycles are inhibited by holding any one of
= VIL,
OE
= VIH or
= VIH. To initiate a write cycle,
WE
CE_F
and
CE_F
is a logical one.
OE
must be a logical zero while
WE
Table 8. CFI Query Identification String
Addresses
Addresses
Data
Description
(Word Mode)
(Byte Mode)
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
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AMIC Technology, Corp.
A82DL32x8T(U) Series
Table 9. System Interface String
Addresses
(Word Mode)
1Bh
Addresses
(Byte Mode)
36h
Data
Description
0027h
0036h
VCC Min. (write/erase)
I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt
VCC Max. (write/erase)
1Ch
38h
I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0003h
0000h
0009h
0000h
0005h
0000h
0004h
0000h
Vpp Min. voltage (00h = no Vpp pin present)
Vpp Max. voltage (00h = no Vpp pin present)
Typical timeout per single byte/word write 2N μs
Typical timeout for Min. size buffer write 2N μs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 10 Device Geometry Definition
Addresses
(Word Mode)
27h
Addresses
(Byte Mode)
4Eh
Data
Description
Device Size = 2N byte
0016h
0002h
0000h
0000h
0000h
0002h
0007h
0000h
0020h
0000h
003Eh
0000h
0000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
28h
50h
Flash Device Interface description
29h
52h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ah
54h
2Bh
56h
Number of Erase Block Regions within device
2Ch
58h
2Dh
5Ah
Erase Block Region 1 Information
(refer to the CFI specification)
2Eh
5Ch
2Fh
5Eh
30h
60h
31h
62h
32h
64h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
33h
66h
34h
68h
35h
6Ah
36h
6Ch
37h
6Eh
38h
40h
39h
72h
3Ah
74h
3BH
3Ch
76h
78h
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AMIC Technology, Corp.
A82DL32x8T(U) Series
Table 11. Primary Vendor-Specific Extended Query
Addresses
Addresses
(Byte Mode)
80h
Data
Description
(Word Mode)
40h
41h
42h
43h
44h
45h
0050h
0052h
0049h
0031h
0033h
0004h
Query-unique ASCII string “PRI”
82h
84h
86h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required, 1 = Not Required
Erase Suspend
88h
8Ah
46h
47h
48h
49h
4Ah
8Ch
8Eh
90h
92h
94h
0002h
0001h
0001h
0004h
00XXh
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = A29L800 mode
Simultaneous Operation
XX = 38 (A82DL3228)
XX = 30 (A82DL3238)
XX = 20 (A82DL3248)
4Bh
4Ch
96h
98h
0000h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt,
D3-D0: 100 mV
4Dh
9Ah
0085h
ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt,
D3-D0: 100 mV
4Eh
4Fh
9Ch
9Eh
0095h
000Xh
Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot
Device
Bank Organization
00 = Data at 4Ah is zero
57h
58h
59h
AEh
B0h
B2h
0002h
00XXh
00XXh
X = 4 (4 banks, models 01, 02)
X = 2 (2 banks, all other models)
Bank 1 Region Information – Number of Sectors on Bank 1
XX = 0F (A82DL3228)
XX = 17 (A82DL3238)
XX = 27 (A82DL3248)
Bank 2 Region Information – Number of Sectors in Bank 2
XX = 38 (A82DL3228)
XX = 30 (A82DL3238)
XX = 20 (A82DL3248)
5Ah
5Bh
B4h
B6h
0000
0000
Bank 3 Region Information – Number of Sector in Bank 3
Bank 4 Region Information – Number of Sector in Bank 4
PRELIMINARY (April, 2007, Version 0.2)
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AMIC Technology, Corp.
A82DL32x8T(U) Series
(or erase-suspend-read mode if that bank was in Erase
Suspend).
COMMAND DEFINITIONS
Writing specific address and data commands or sequences
into the command register initiates device operations. Table
12 defines the valid register command sequences. Writing
incorrect address and data values or writing them in the
improper sequence may place the device in an unknown
state. A reset command is then required to return the device
to reading array data.
Autoselect Command Sequence
The autoselect command sequence allows the host system
to access the manufacturer and device codes, and determine
whether or not a sector is protected. Table 12 shows the
address and data requirements. This method is an
alternative to that shown in Table 5, which is intended for
PROM programmers and requires VID on address pin A9.
The autoselect command sequence may be written to an
address wit h in a bank that is either in t he read or erase-
suspend-read mode. The autoselect command may not be
written while the device is actively programming or erasing in
the other bank.
All addresses are latched on the falling edge of
or
WE
, whichever happens later. All data is latched on the
CE_F
rising edge of
or
, whichever happens first. Refer
WE
CE_F
to the AC Characteristics section for timing diagrams.
Reading Array Data
The autoselect command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle that
contains the bank address and the autoselect command. T he
bank then enter s the autoselect mode. The system may read
at any address within the same bank any number of times
without initiating another autoselect command sequence:
A read cycle at address (BA)XX00h (where BA is the bank
address) returns the manufacturer code.
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm.
After the device accepts an Erase Suspend command, the
corresponding bank enters the erase-suspend-read mode,
after which the system can read data from any non-erase-
suspended sector within the same bank. After completing a
programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
A read cycle at address (BA)XX01h in word mode (or
(BA)XX02h in byte mode) returns the device code.
A read cycle to an address containing a sector address
(SA) within the same bank, and the address 02h on A7-A0
in word mode (or the address 04h on A6-A-1 in byte mode)
returns 01h if the sector is protected, or 00h if it is
unprotected. (Refer to Tables 3-4 for valid sector
addresses).
The system must write the reset command to return to
reading array data (or erase-suspend-read mode if the bank
was previously in Erase Suspend).
The system must issue the reset command to return a bank
to the read (or erase-suspend-read) mode if I/O5 goes high
during an active program or erase operation, or if the bank is
in the autoselect mode. See the next section, Reset
Command, for more information.
See also Requirements for Reading Array Data in the Device
Bus Operations section for more information. The Read-Only
Operations table provides the read parameters, and Figure
11 shows the timing diagram.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the
pin. Programming is
BYTE_F
Reset Command
a four-bus-cycle operation. The program command sequence
is initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data
are written next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 12 shows the address and
data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, that
bank then returns to reading array data and addresses are
no longer latched. The system can determine the status of
Writing the reset command resets the banks to the read or
erase-suspend-read mode. Address bits are don’t cares for
this command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing
begins. This resets the bank to which the system was writing
to reading array data. Once erasure begins, however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the sequence
cycles in
a
program command sequence before
the program operation by using I/O7, I/O6, or RY/
to the Write Operation Status section for information on these
status bits.
. Refer
BY
programming begins. This resets the bank to which the
system was writing to reading array data. If the program
command sequence is written to a bank that is in the Erase
Suspend mode, writing the reset command returns that bank
to the erase-suspend-read mode. Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data. If a bank entered the autoselect
mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode.
If I/O5 goes high during a program or erase operation, writing
the reset command returns the banks to reading array data
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the program operation. The program
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from “0” back to a
“1.” Attempting to do so may cause that bank to set I/O5 = 1,
or cause the I/O7 and I/O6 status bits to indicate the operation
was successful. However, a succeeding read will show that
the data is still “0.” Only erase operations can convert a “0” to
a “1.”
PRELIMINARY (April, 2007, Version 0.2)
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AMIC Technology, Corp.
A82DL32x8T(U) Series
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program
bytes or words to a bank faster than using the standard
program command sequence. The unlock bypass command
sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass
START
Write Program
Command
Sequence
mode.
A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The
first cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the program
address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table
12 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The device
then returns to reading array data.
Data Poll
from System
Embedded
Program
algorithm in
progress
Verify Data ?
No
The device offers accelerated program operations through
Yes
the
/ACC pin. When the system asserts VHH on the
WP
/ACC pin, the device automatically enters the Unlock
WP
Bypass mode. The system may then write the two-cycle
Unlock Bypass program command sequence. The device
No
Increment Address
Last Address ?
uses the higher voltage on the
/ACC pin to accelerate
WP
the operation. Note that the
/ACC pin must not be at VHH
WP
any operation other than accelerated programming, or device
damage may result. In addition, the /ACC pin must not
Yes
WP
be left floating or unconnected; inconsistent behavior of the
device may result.
Programming
Completed
Figure 3 illustrates the algorithm for the program operation.
Refer to the Erase and Program Operations table in the AC
Characteristics section for parameters, and Figure 15 for
timing diagrams.
Note : See Table 14 for program command sequnce.
Figure 3. Program Operation
PRELIMINARY (April, 2007, Version 0.2)
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AMIC Technology, Corp.
A82DL32x8T(U) Series
When the Embedded Erase algorithm is complete, the bank
returns to reading array data and addresses are no longer
latched. Note that while the Embedded Erase operation is in
progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide
any controls or timings during these operations. Table 12
shows the address and data requirements for the chip erase
command sequence.
operation by reading I/O7, I/O6, I/O2, or RY/
bank.
in the erasing
BY
Refer to the Write Operation Status section for information on
these status bits.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
However, note that a hardware reset immediately terminates
the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in the AC
Characteristics section for parameters, and Figure 17 section
for timing diagrams
When the Embedded Erase algorithm is complete, that bank
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7, I/O6, I/O2, or RY/
Write Operation Status section for information on these
status bits.
. Refer to the
BY
Any commands written during the chip erase operation are
ignored. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the chip erase
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in the AC
Characteristics section for parameters, and Figure 17 section
for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to
interrupt a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50 µs time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm.
Sector Erase Command Sequence
When the Erase Suspend command is written during the
sector erase operation, the device requires a maximum of 20
µs to suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase time-
out, the device immediately terminates the time-out period
and suspends the erase operation.
After the erase operation has been suspended, the bank
enters the erase-suspend-read mode. The system can read
data from or program data to any sector not selected for
erasure. (The device “erase suspends” all sectors selected
for erasure.) Reading at any address within erase-suspended
sectors produces status information on I/O7–I/O0. The system
can use I/O7, or I/O6 and I/O2 together, to determine if a
sector is actively erasing or is erase-suspended. Refer to the
Write Operation Status section for information on these
status bits.
After an erase-suspended program operation is complete,
the bank returns to the erase-suspend-read mode. The
system can determine the status of the program operation
using the I/O7 or I/O6 status bits, just as in the standard Byte
Program operation. Refer to the Write Operation Status
section for more information.
In the erase-suspend-read mode, the system can also issue
the autoselect command sequence. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for
details.
Sector erase is a six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock cycles
are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table
12 shows the address and data requirements for the sector
erase command sequence.
The device does not require the system to preprogram prior
to erase. The Embedded Erase algorithm automatically
programs and verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-
out of 50 µs occurs. During the time-out period, additional
sector addresses and sector erase commands within the
bank may be written. Loading the sector erase buffer may be
done in any sequence, and the number of sectors may be
from one sector to all sectors. The time between these
additional cycles must be less than 50µs, otherwise erasure
may begin. Any sector erase address and command
following the exceeded time-out may or may not be accepted.
It is recommended that processor interrupts be disabled
during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. Any command other than Sector Erase
or Erase Suspend during the time-out period resets that bank
to reading array data. The system must rewrite the command
sequence and any additional addresses and commands.
The system can monitor I/O3 to determine if the sector erase
timer has timed out (See the section on I/O3: Sector Erase
Timer.). The time-out begins from the rising edge of the final
To resume the sector erase operation, the system must write
the Erase Resume command. The bank address of the
erase-suspended bank is ignored when writing this command.
Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip has
resumed erasing.
pulse in the command sequence.
WE
PRELIMINARY (April, 2007, Version 0.2)
27
AMIC Technology, Corp.
A82DL32x8T(U) Series
START
Write Erase
Command Sequence
(Notes 1,2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm in
progress
No
Data = FFh ?
Yes
Erasure Completed
Note :
1. See Table 14 for erase command sequence.
2. See the section on I/O3 for information on the sector
erase timer.
Figure 4. Erase Operation
PRELIMINARY (April, 2007, Version 0.2)
28
AMIC Technology, Corp.
A82DL32x8T(U) Series
Command Definitions
Table 12. A82DL32x8T(U) Command Definitions
Bus Cycles (Notes 2–5)
Third Fourth
Addr
Command
Sequence
(Note 1)
First
Second
Fifth
Sixth
Addr Data Addr Data
Data
Addr
Data
Addr
Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
RD
F0
(BA)555
(BA)AAA
(BA)555
(BA)AAA
Word
Byte
Word
Byte
2AA
555
2AA
555
(BA)X00
Manufacturer ID
Device ID
4
4
4
4
3
4
3
AA
AA
AA
AA
AA
AA
AA
55
55
55
55
55
55
55
90
90
90
90
77
A0
20
37
AAA
555
(BA)X01
(BA)X02
(see
Table5)
AAA
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
XXX
XXX
555
AAA
555
AAA
XXX
XXX
55
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
PA
555
AAA
X03
X06
Continuation ID
7F
(BA)555
(BA)AAA
(SA)
Sector Protect Verify
(Note 9)
00/01
(SA)X04
555
AAA
555
Command Temporary
Sector Unprotect (Note15)
Program
PA
PD
AAA
555
Unlock Bypass
AAA
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
2
2
A0
90
PD
00
XXX
2AA
555
2AA
555
Word
555
AAA
555
555
AA A
555
2AA
555
2AA
555
555
Chip Erase
Byte
6
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
AAA
Word
Sector Erase
Byte
SA
AAA
AAA
Erase Suspend (Note 12)
Erase Resume (Note 13)
1
1
B0
30
Word
CFI Query (Note 14)
1
98
Byte
AA
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the
or
pulse,
CE_F
WE
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of
or
pulse, whichever happens first.
CE_F
WE
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20 - A12 select a unique sector.
BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits I/O15-I/O8 are don’t care in command sequences. Except for RD and PD.
5. Unless otherwise noted, address bits A20-A11 are don’t cares.
6. No unlock or command cycles required when bank is reading array data.
7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if I/O5 goes high (while the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain
the manufacture ID, or device ID information. Data bits I/O15-I/O8 are don’t care. See the Autoselect Command Sequence
section for more information.
9. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
10. The Unlock Bypass command is required prior to the Unlock Bypass Program Command.
11. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase operation, and require the bank address.
13. The Erase Resume command is valid only during the Erase.
14. Command is valid when device is ready to read array data or when device is in autoselect mode.
15. Once reset command is applied, software temporary unprotect is exit to return read array data. But under erase suspend
condition, this command is still effective even a reset command has been applied. The reset command which can deactivate
the software temporary unprotect command is useful only after the erase command is complete.
PRELIMINARY (April, 2007, Version 0.2)
29
AMIC Technology, Corp.
A82DL32x8T(U) Series
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7.
Table 13 and the following subsections describe the function
of these bits. I/O7 and I/O6 each offer a method for
determining whether a program or erase operation is
complete or in progress. The device also provides a
START
Read I/O7-I/O0
Address = VA
hardware-based output signal, RY/
an Embedded Program or Erase operation is in progress or
has been completed.
, to determine whether
BY
I/O7:
Polling
Data
Yes
I/O7
= Data ?
No
The
Polling bit, I/O7, indicates to the host system
Data
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Polling is
Data
pulse in the
valid after the rising edge of the final
program or erase command sequence.
WE
During the Embedded Program algorithm, the device outputs
on I/O7 the complement of the datum programmed to I/O7.
This I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
No
I/O5 = 1?
Yes
protected sector,
Polling on I/O7 is active for
Data
Read I/O
7
- I/O0
Address = VA
approximately 1μs, then the device returns to reading array
data.
During the Embedded Erase algorithm,
Polling
Data
produces a "0" on I/O7. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Yes
Polling produces a "1" on I/O7. The system must
Data
I/O7
= Data ?
provide an address within any of the sectors selected for
erasure to read valid status information on I/O7.
After an erase command sequence is written, if all sectors
selected for erasing are protected,
Polling on I/O7 is
Data
No
active for approximately 100μs, then the bank returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
However, if the system reads I/O7 at an address within a
protected sector, the status may not be valid.
FAIL
PASS
Just prior to the completion of an Embedded Program or
Erase operation, I/O7 may change asynchronously with I/O0–
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
I/O6 while Output Enable (
) is asserted low. That is, the
OE
device may change from providing status information to valid
data on I/O7. Depending on when the system samples the
I/O7 output, it may read the status or valid data. Even if the
device has completed the program or erase operation and
I/O7 has valid data, the data outputs on I/O0-I/O6 may be still
invalid. Valid data on I/O0-I/O7 will appear on successive read
cycles.
2. I/O
7
should be rechecked even if I/O
may change simultaneously with I/O
5 = "1" because
I/O7
5
.
Figure 5. Data Polling Algorithm
Table 13 shows the outputs for
Polling on I/O7. Figure
Data
5 shows the
Polling algorithm. Figure 19 in the AC
Data
Characteristics section shows the
diagram.
Polling timing
Data
PRELIMINARY (April, 2007, Version 0.2)
30
AMIC Technology, Corp.
A82DL32x8T(U) Series
RY/
: Ready/
Busy
BY
The RY/
is a dedicated, open-drain output pin that
BY
indicates whether an Embedded algorithm is in progress or
START
complete. The RY/ status is valid after the rising edge of
BY
pulse in the command sequence. Since RY/
the final
WE
BY
pins can be tied
is an open-drain output, several RY/
BY
together in parallel with a pull-up resistor to VCC_F.
Read I/O7-I/O0
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Read I/O7-I/O0
(Note 1)
Table 13 shows the outputs for RY/
.
BY
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
No
Toggle Bit
= Toggle ?
of the final
pulse in the command sequence (prior to the
WE
Yes
program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.
No
I/O5 = 1?
The system may use either
or
to control the read
CE_F
OE
cycles. When the operation is complete, I/O6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100μs, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
Yes
Read I/O7 - I/O0
(Notes 1,2)
Twice
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the device
enters the Erase Suspend mode, I/O6 stops toggling.
However, the system must also use I/O2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
No
Toggle Bit
= Toggle ?
Yes
Program/Erase
system can use I/O7 (see the subsection on " I/O7:
Polling").
Data
Operation Not
Commplete, Write
Reset Command
Program/Erase
Operation Complete
If a program address falls within a protected sector, I/O6
toggles for approximately 1μs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
Table 13 shows the outputs for Toggle Bit I on I/O6. Figure 6
shows the toggle bit algorithm. Figure 20-1, 20-2, 20-3 in the
“AC Characteristics” section show the toggle bit timing
diagrams. Figure 23 shows the differences between I/O2 and
I/O6 in graphical form. See also the subsection on I/O2:
Toggle Bit II.
Note:
The system should recheck the toggle bit even if I/O5=”1"
because the toggle bit may stop toggling as I/O5 changes to
“1”. See the subsections on I/O6 and I/O2 for more information.
Figure 6. Toggle Bit Algorithm
PRELIMINARY (April, 2007, Version 0.2)
31
AMIC Technology, Corp.
A82DL32x8T(U) Series
I/O2: Toggle Bit II
I/O5: Exceeded Timing Limits
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
The device may output a “1” on I/O5 if the system tries to
program a “1” to a location that was previously programmed
to “0.” Only an erase operation can change a “0” back to a
“1.” Under this condition, the device halts the operation, and
when the timing limit has been exceeded, I/O5 produces a
“1.” .
rising edge of the final
pulse in the command sequence.
WE
I/O2 toggles when the system reads at addresses within those
sectors that have been selected for erasure. (The system may
use either
or
to control the read cycles.) But I/O2
CE_F
OE
cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information.
Refer to Table 8 to compare outputs for I/O2 and I/O6.
Under both these conditions, the system must write the reset
command to return to reading array data (or to the erase-
suspend-read mode if a bank was previously in the erase-
suspend-program mode).
Figure 6 shows the toggle bit algorithm in flowchart form, and
the section " I/O2: Toggle Bit II" explains the algorithm. See
also the " I/O6: Toggle Bit I" subsection. Figure 20-1, 20-2, 20-
3 show the toggle bit timing diagram. Figure 21 shows the
differences between I/O2 and I/O6 in graphical form.
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read I/O3 to determine whether or not an erase
operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out is
complete, I/O3 switches from "0" to "1." The system may
ignore I/O3 if the system can guarantee that the time
between additional sector erase commands will always be
less than 50μs. See also the "Sector Erase Command
Sequence" section.
Reading Toggle Bits I/O6, I/O2
Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7-I/O0 at least twice in a row to determine whether a toggle
bit is toggling. Typically, a system would note and store the
value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O7-I/O0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O5 went high. If the toggle bit
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O5 has not gone high. The
system may continue to monitor the toggle bit and I/O5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6).
After the sector erase command sequence is written, the
system should read the status on I/O7 (
Polling) or I/O6
Data
(Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (Except Erase Suspend) are ignored until the
erase operation is complete. If I/O3 is "0", the device will
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have been
accepted.
Table 13 shows the status of I/O3 relative to the other status
bits.
PRELIMINARY (April, 2007, Version 0.2)
32
AMIC Technology, Corp.
A82DL32x8T(U) Series
Table 13. Write Operation Status
I/O7
I/O6
I/O5
(Note 1)
0
I/O3
I/O2
RY/
BY
Status
(Note 2)
(Note 2)
No toggle
Standard
Mode
Embedded Program Algorithm
Toggle
Toggle
N/A
1
0
I/O7
0
Embedded Erase Algorithm
Erase
Erase-Suspend- Suspended Sector
0
0
Toggle
Toggle
0
1
Erase
Suspend
Mode
1
No toggle
N/A
Read
Non-Erase
Data
I/O7
Data
Data
0
Data
N/A
Data
N/A
1
0
Suspend Sector
Erase-Suspend-Program
Toggle
Notes:
1. I/O5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on I/O5 for more information.
2. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
PRELIMINARY (April, 2007, Version 0.2)
33
AMIC Technology, Corp.
A82DL32x8T(U) Series
ABSOLUTE MAXIMUM RATINGS*
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
Storage Temperature Plastic Packages. . . -65°C to + 150°C
Ambient Temperature with Power Applied. -65°C to + 125°C
Voltage with Respect to Ground
VCC_F/VCC_S (Note 1) . . . . . . . .. . . . ……. . -0.5V to +4.0V
A9,
&
(Note 2) . . . . . . . . . . . . -0.5V to +10.5V
RESET
OE
/ACC . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +10.5V
WP
All other pins (Note 1) . . . . . . -0.5V to VCC_F/VCC_S + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . …. . 200mA
OPERATING RANGES
Industrial (I) Devices
Notes:
Ambient Temperature (TA)
For –U series . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
For –I series . . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on input and I/O pins is VCC_F/VCC_F +0.5V. See
Figure 7. During voltage transitions, input or I/O pins may
overshoot to VCC_F/VCC_S +2.0V for periods up to
20ns. See Figure 8.
VCC Supply Voltages
VCC_F/VCC_S for all devices . .. . . . . . . …...+2.7V to +3.3V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
2. Minimum DC input voltage on A9,
,
and
RESET
OE
/ACC is -0.5V. During voltage transitions, A9,
,
WP
WP
OE
/ACC and
may overshoot VSS to -2.0V for
RESET
periods of up to 20ns. See Figure 7. Maximum DC input
voltage on A9 is +10.5V which may overshoot to 14.0V
for periods up to 20ns. Maximum DC input voltage on
/ACC is +10.5V which may overshoot to +12.0V for
period up to 20ns.
WP
3. No more than one output is shorted to ground at a time.
Duration of the short circuit should not be greater than
one second.
Figure 7. Maximum Negative Overshoot Waveform
20ns
20ns
+0.8V
-0.5V
-2.0V
20ns
Figure 8. Maximum Positive Overshoot Waveform
20ns
VCC_F//VCC_S
+2.0V
VCC_F/VCC_S
+0.5V
2.0V
20ns
20ns
PRELIMINARY (April, 2007, Version 0.2)
34
AMIC Technology, Corp.
A82DL32x8T(U) Series
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
Min.
Typ.
Max.
Unit
ILI
Input Load Current
VIN = VSS to VCC_F. VCC_F= VCC_F Max
±1.0
μA
μA
μA
ILIT
ILO
A9 Input Load Current
Output Leakage Current
VCC = VCC Max, A9 =12.5V
35
VOUT = VSS to VCC_F.
VCC = VCC_F Max
±1.0
5 MHz
10
2
16
4
= VIL,
= VIH
OE
CE_F
Byte Mode
1 MHz
VCC_F Active Read Current
(Notes 1, 2)
ICC1_F
mA
5 MHz
1 MHz
10
2
16
4
= VIL,
= VIH
=VIH
OE
OE
CE_F
Word Mode
VCC_F Active Write Current
(Notes 2, 3)
ICC2_F
ICC3_F
20
30
5
mA
μA
μA
= VIL,
CE_F
CE_F
VCC_F Standby Current (Note 2)
0.5
= VIH to
= VCC_F ± 0.3V
CE_F
ICC4_F
ICC5_F
VCC_F Reset Current (Note 2)
= VSS ± 0.3V
RESET
0.5
0.5
5
5
Automatic Sleep Mode
(Note 2, 4)
VIH = VCC_F ± 0.3V;
VIL = VSS ± 0.3V
μA
Byte
Word
Byte
21
21
21
21
45
45
45
45
VCC_F Active Read-While-Program
Current (Notes 1, 2)
= VIL,
= VIH
OE
OE
OE
OE
CE_F
CE_F
CE_F
CE_F
ICC6_F
ICC7_F
mA
mA
VCC_F Active Read-While-Erase Current
(Notes 1, 2)
= VIL,
= VIH
Word
VCC_F Active
= VIL,
= VIL,
= VIH
= VIH
Program-While-Erase-Suspended
Current (Notes 2, 5)
17
ICC8_F
IACC
35
mA
mA
ACC pin
5
10
ACC Accelerated Program Current, Word
or Byte
VCC_F pin
15
30
Input Low Level
Input High Level
VIL
VIH
-0.5
0.8
V
V
0.7 x
VCC_F
VCC_F +
0.3
Voltage for
/ACC Sector
WP
VCC_F = 3.0 V ± 10%
VCC_F = 3.0 V ± 10%
8.5
8.5
10.5
V
V
Protect/Unprotect and Program
VHH
VID
Acceleration
Voltage for Autoselect and
Temporary Unprotect Sector
10.5
0.45
VOL
Output Low Voltage
IOL = 4.0mA, VCC_F = VCC_F Min
IOH = -2.0 mA, VCC_F = VCC_F Min
V
V
VOH1
0.85x
VCC_F
Output High Voltage
VOH2
VLKO
VCC_F -
0.4
V
V
IOH = -100 μA, VCC_F = VCC Min
Low VCC_F Lock-Out Voltage
(Note 5)
2.3
2.5
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with
at VIH.
OE
2. Maximum ICC specifications are tested with VCC_F = VCC_F max.
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC_F + 30ns. Typical sleep mode
current is 500nA.
5. Not 100% tested.
PRELIMINARY (April, 2007, Version 0.2)
35
AMIC Technology, Corp.
A82DL32x8T(U) Series
TEST CONDITIONS
Table 14. Test Specifications
Test Condition
-70
Unit
Output Load
1 TTL gate
Output Load Capacitance, CL(including jig capacitance)
Input Rise and Fall Times
30
5
pF
ns
V
Input Pulse Levels
0.0 - 3.0
1.5
Input timing measurement reference levels
Output timing measurement reference levels
V
1.5
V
Figure 9. Test Setup
3.3 V
2.7 KΩ
Device
Under
Test
Diodes = IN3064 or Equivalent
CL
6.2 KΩ
Figure 10. Input Waveforms and Measurement Levels
3.0V
Measurement Level
Input
1.5V
1.5V
Output
0.0V
PRELIMINARY (April, 2007, Version 0.2)
36
AMIC Technology, Corp.
A82DL32x8T(U) Series
AC CHARACTERISTICS
Read Only Operations
Parameter
Description
Test Setup
Speed
Unit
JEDEC
Std
-70
Read Cycle Time (Note 1)
tAVAV
tRC
Min.
70
ns
ns
= VIL
CE_F
tAVQV
tACC
Address to Output Delay
Max.
70
= VIL
OE
OE
Chip Enable to Output Delay
Output Enable to Output Delay
tELQV
tGLQV
tCE
Max.
Max.
70
30
ns
ns
= VIL
tOE
Chip Enable to Output High Z
(Notes 1,3)
tEHQZ
tGHQZ
tDF
tDF
Max.
Max.
16
16
ns
ns
Output Enable to Output High Z
(Notes 1,3)
Output Hold Time from Addresses,
Whichever Occurs First
or ,
CE OE
tAXQX
tOH
Min.
Min.
Min.
0
0
ns
ns
ns
Read
Toggle and
Polling
tOEH
Output Enable Hold Time
(Note 1)
10
Data
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 14 for test specifications.
3. Measurements performed by placing a 50-ohm termination on the data pin with a bias of (VCC_F)/2. The time from
to the data bus driven to (VCC_F)/2 is taken as tDF.
high
OE
Figure 11. Read Operation Timings
tRC
Addresses
CE_F
Addresses Stable
tACC
tRH
tRH
tDF
tOE
OE
tOEH
WE
tCE
tOH
High-Z
High-Z
Output
Output Valid
RESET
RY/BY
0V
PRELIMINARY (April, 2007, Version 0.2)
37
AMIC Technology, Corp.
A82DL32x8T(U) Series
AC CHARACTERISTICS
Hardware Reset (
Parameter
)
RESET
Description
Test Setup
All Speed Options
Unit
JEDEC
Std
Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
RESET
tREADY
Max
20
μs
Pin Low (Not During Embedded
RESET
Algorithms) to Read or Write (See Note)
tREADY
Max
500
ns
tRP
tRH
Min
Min
Min
Min
500
50
0
ns
ns
ns
μs
Pulse Width
RESET
RESET
High Time Before Read (See Note)
Recovery Time
tRB
RY/
BY
tRPD
20
Low to Standby Mode
RESET
Note: Not 100% tested.
Figure 12.
Timings
RESET
RY/BY
0V
CE_F, OE
RESET
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY
tRB
CE_F, OE
RESET
tRP
PRELIMINARY (April, 2007, Version 0.2)
38
AMIC Technology, Corp.
A82DL32x8T(U) Series
AC CHARACTERISTICS
Word/Byte Configuration (
)
BYTE_F
Parameter
Description
Speed Option
Unit
JEDEC
Std
-70
tELFL/tELFH
Max
5
ns
to
CE_F BYTE_F
Switching Low or High
Switching Low to Output High-Z
Switching High to Output Active
BYTE_F
BYTE_F
tFLQZ
tFHQV
Max
Min
25
70
ns
ns
Figure 13.
Timings for Read Operations
BYTE_F
CE_F
OE
BYTE_F
tELFL
Data Output
(I/O0-I/O14)
Data Output
(I/O0-I/O7)
BYTE_F
I/O0-I/O14
Switching
from word to
byte mode
I/O15
Output
Address Input
I/O15 (A-1)
tFLQZ
tELFH
BYTE_F
Data Output
(I/O0-I/O7)
Data Output
(I/O0-I/O14)
I/O0-I/O14
I/O15 (A-1)
BYTE _F
Switching
from byte to
word mode
I/O15
Output
Address Input
tFHQV
Figure 14.
Timings for Write Operations
BYTE_F
CE_F
The falling edge of the last WE signal
WE
BYTE_F
tSET
(tAS)
tHOLD (tAH)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
PRELIMINARY (April, 2007, Version 0.2)
39
AMIC Technology, Corp.
A82DL32x8T(U) Series
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Description
Speed
Unit
JEDEC
tAVAV
Std
tWC
tAS
-70
70
0
Write Cycle Time (Note 1)
Address Setup Time
Min.
Min.
ns
ns
tAVWL
tASO
tAH
Address Setup Time to
Address Hold Time
low during toggle bit polling
OE
12
40
ns
ns
tWLAX
Min.
Address Hold Time From
toggle bit polling
or
high during
OE
CE_F
tAHT
0
ns
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Data Hold Time
Min.
Min.
Min.
40
0
ns
ns
ns
Output Enable High during toggle bit polling
Read Recover Time Before Write
tOEPH
20
tGHWL
tGHWL
Min.
ns
0
0
(
high to
low)
WE
OE
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
Min.
Min.
Min.
Min.
ns
ns
ns
ns
Setup Time
Hold Time
CE_F
CE_F
0
Write Pulse Width
tWP
tWPH
30
Write Pulse Width High
30
0
Latency Between Read and Write Operations
Min.
Typ.
Typ.
Typ.
tSR/W
Byte
Word
6
9
6
Byte Programming Operation
(Note 2)
tWHWH1
tWHWH1
μs
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
tWHWH2
tWHWH1
sec
sec
tWHWH2
tvcs
Sector Erase Operation (Note 2)
VCC_F Set Up Time (Note 1)
Typ.
Min.
Min
Min
0.7
50
0
μs
ns
ns
tRB
Recovery Time from RY/
BY
tBUSY
90
Program/Erase Valid to RY/
Delay
BY
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
PRELIMINARY (April, 2007, Version 0.2)
40
AMIC Technology, Corp.
A82DL32x8T(U) Series
AC CHARACTERISTICS
Figure 15. Program Operation Timings
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tWC
tAS
Addresses
CE_F
PA
PA
555h
PA
tAH
tCH
tWP
OE
WE
tWHWH1
tCS
tWPH
tDS
tDH
Data
A0h
PD
DOUT
Status
tRB
tBUSY
RY/BY
VCC_F
tVCS
Note :
1. PA = program address, PD = program data, Dout is the true data at the program address.
2. Illustration shows device in word mode.
Figure 16. Accelerated Program Timing Diagram
VHH
VIL or VIH
VIL or VIH
WP/ACC
tVHH
tVHH
PRELIMINARY (April, 2007, Version 0.2)
41
AMIC Technology, Corp.
A82DL32x8T(U) Series
AC CHARACTERISTICS
Figure 17. Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
Read Status Data
tAS
tWC
SA
VA
Addresses
CE_F
2AAh
VA
555h for chip erase
tAH
OE
tCH
tWP
WE
tWPH
tWHWH2
tCS
tDS
tDH
In
Progress
Data
55h
30h
10h for chip erase
Complete
tRB
tBUSY
RY/BY
tVCS
VCC_F
Note :
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
2. Illustration shows device in word mode.
PRELIMINARY (April, 2007, Version 0.2)
42
AMIC Technology, Corp.
A82DL32x8T(U) Series
AC CHARACTERISTICS
Figure 18. Back-to-back Read/Write Cycle Timings
tWC
tRC
tWC
tWC
Addresses
Valid PA
Valid RA
Valid PA
Valid PA
tAH
tACC
tCE
tCPH
CE_F
OE
tCP
tOE
tGHWL
tOEH
tWP
WE
tDF
tWPH
tDS
tOH
tDH
Valid
In
Valid
In
Valid
Out
Valid
In
Data
tSR/W
WE Controlled Write Cycle
Read Cycle
CE Controlled Write Cycles
Figure 19.
Polling Timings (During Embedded Algorithms)
Data
tRC
Addresses
VA
VA
VA
tACC
tCE
CE_F
OE
tCH
tOE
tDF
tOEH
WE
tOH
High-Z
High-Z
Valid Data
Valid Data
I/O7
Complement
Status Data
Complement
Status Data
True
True
I/O0 - I/O6
High-Z
tBUSY
RY/BY
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
PRELIMINARY (April, 2007, Version 0.2)
43
AMIC Technology, Corp.
A82DL32x8T(U) Series
AC CHARACTERISTICS
Figure 20-1. Toggle Bit Timings (During Embedded Algorithms)
tAHT
tAS
Addresses
tAHT
tASO
tCEPH
CE_F
tOEH
tOEPH
WE
OE
tDH
tOE
I/O6 , I/O2
Valid Status
Valid Status
(first read)
Valid Status
Valid Data
Valid Status
(second read)
(stop togging)
RY/BY
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 20-2. Toggle Bit I and Toggle Bit II Mechanism, Chip Enable Controlled
Address Outside the Bank
Being Programmed or Erased
Address in the Bank
Being Programmed or Erased
Address Outside the Bank
Being Programmed or Erased
A0-A19
tAXCL
CE
OE
tCE
tCE
Toggle Bit I/
Toggle Bit II
Toggle Bit I/
Toggle Bit II
I/O6,I/O2
Data
Data
Read Operation Outside the Bank
Being Programmed or Erased
Read Operation in the Bank
Being Programmed or Erased
Read Operation Outside the Bank
Being Programmed or Erased
Note: 1. The Toggle Bit I is output on I/O6,
2. The Toggle Bit II is output on I/O2.
3. tAXCL minimum value is 10ns.
PRELIMINARY (April, 2007, Version 0.2)
44
AMIC Technology, Corp.
A82DL32x8T(U) Series
Figure 20-3. Toggle Bit I and Toggle Bit II Mechanism, Output Enable Controlled
Note: 1. The Toggle Bit I is output on I/O6,
2. The Toggle Bit II is output on I/O2.
3. tAXEL minimum value is 10ns
Figure 21. I/O2 vs. I/O6
Enter
Erase
Enter Erase
Suspend Program
Erase
Resume
Embedded
Suspend
Erasing
WE
Erase
Suspend
Program
Erase
Erase
Erase Suspend
Read
Erase Suspend
Read
Erase
Complete
I/O6
I/O2
I/O2 and I/O6 toggle with OE and CE_F
Note : Both I/O6 and I/O2 toggle with OE or CE_F. See the text on I/O6 and I/O2 in the section "Write Operation Status" for
more information.
PRELIMINARY (April, 2007, Version 0.2)
45
AMIC Technology, Corp.
A82DL32x8T(U) Series
AC CHARACTERISTICS
Temporary Sector/Sector Block Unprotect
Parameter
Description
All Speed Options
Unit
JEDEC
Std
tVIDR
VID Rise and Fall Time (See Note)
VHH Rise and Fall Time (See Note)
Min
500
ns
tVHH
Min
Min
250
4
μs
μs
Setup Time for Temporary
RESET
Sector/Sector Block Unprotect
Hold Time from RY/
tRSP
High for
BY
RESET
Temporary Sector/Sector Block Unprotect
tRRB
Min
4
μs
Note: Not 100% tested.
Figure 22. Temporary Sector/Sector Block Unprotect Timing Diagram
VID
VID
VSS, VIL,
VSS, VIL,
or VIH
or VIH
RESET
tVIDR
tVIDR
Program or Erase Command Sequence
CE_F
WE
tRSP
tRRB
RY/BY
Program/Erase Command Sequence
CE_F
WE
555
AA
2AA
55
555
77
XXX
FQ
Address
I/O0 - I/O7
RY/BY
PRELIMINARY (April, 2007, Version 0.2)
46
AMIC Technology, Corp.
A82DL32x8T(U) Series
AC CHARACTERISTICS
Figure 23. Sector/Sector Block Protect and Unprotect Timing Diagram
VID
VIH
RESET
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Sector Protect/Unprotect
Verify
40h
60h
60h
Data
CE
Status
Sector Protect:150us
Sector Unprotect:15ms
1us
WE
OE
Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0
200ns-300ns
PRELIMINARY (April, 2007, Version 0.2)
47
AMIC Technology, Corp.
A82DL32x8T(U) Series
AC CHARACTERISTICS
Alternate
Controlled Erase and Program Operations
CE_F
Parameter
Description
Speed
Unit
JEDEC
tAVAV
tAVEL
Std
tWC
tAS
tAH
tDS
tDH
-70
70
0
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Min.
Min.
Min.
Min.
Min.
ns
ns
ns
ns
ns
tELAX
40
40
0
tDVEH
tEHDX
Data Setup Time
Data Hold Time
Read Recover Time Before Write
tGHEL
tGHEL
Min.
0
ns
(
High to
Low)
WE
OE
tWLEL
tEHWH
tELEH
tWS
tWH
tCP
Min.
Min.
Min.
0
0
ns
ns
ns
Setup Time
Hold Time
WE
WE
30
Pulse Width
CE_F
tEHEL
tCPH
Min.
30
ns
Pulse Width High
CE_F
Programming Operation
(Note 2)
Byte
Typ.
Typ.
6
9
tWHWH1
tWHWH1
μs
Word
Accelerated Programming Operation,
Word or Byte (Note 2)
Typ.
Typ.
6
μs
tWHWH1
tWHWH2
tWHWH1
tWHWH2
Sector Erase Operation (Note 2)
0.7
sec
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
PRELIMINARY (April, 2007, Version 0.2)
48
AMIC Technology, Corp.
A82DL32x8T(U) Series
AC CHARACTERISTICS
Figure 24. Alternate
Controlled Write (Erase/Program) Operation Timings
CE_F
PA for program
SA for sector erase
555 for chip erase
555 for program
2AA for erase
Data Polling
PA
Addresses
tWC
tAS
tAH
tWH
WE
tGHEL
OE
tCP
tWHWH1 or 2
tBUSY
tCPH
tDH
CE_F
tWS
tDS
Data
DOUT
I/O7
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET
RY/BY
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3.
is the complement of the data written to the device. DOUT is the data written to the device.
I/O7
4. Waveforms are for the word mode.
PRELIMINARY (April, 2007, Version 0.2)
49
AMIC Technology, Corp.
A82DL32x8T(U) Series
SUPER RAM
DC Electrical Characteristics (TA = -40°C to +85°C, VCC_S = 2.7V to 3.3V, GND = 0V)
Parameter
Symbol
ILI
Test Condition
VIN = VSS to VCC
Min.
Typ.
Max.
Unit
Input Leakage Current
Output Leakage Current
-1
1
uA
ILO
CE1_S = VIH,
=
= VIH or
=VIH or
OE
LB
UB
-1
1
uA
WE =VIL, VIO=VSS to VCC
Cycle Time = 1us, 100% duty, IIO=0mA,
ICC1
≤ 0.2V, VIN ≤ 0.2V or
CS
2.0
mA
mA
VIN ≥ VCC-0.2V
ICC2
Cycle time=Min, IIO=0mA, 100% duty
20
= VIL,VIN=VIL or VIH
CE1_S
Output Low Voltage
Output High Voltage
Standby Current(TTL)
VOL
VOH
ISB
IOL = 2 mA
IOH = -1 mA
0.4
V
V
2.2
=VIH,
=
= VIH,
LB
CE1_S
Other inputs = VIH or VIL
≥ VCC-0.2V,
UB
0.3
mA
uA
Standby Current(CMOS)
ISB1
=
LB
UB
≥ VCC-0.2V
CS
100
(
,
Controlled) Other inputs = 0 or VCC
LB
UB
1. Stable power supply required 100 us before device operation.
PRELIMINARY (April, 2007, Version 0.2)
50
AMIC Technology, Corp.
A82DL32x8T(U) Series
Truth Table
CE2_S
I/O 0~I/O7
I/O 8~I/O15
MODE
Power
UB
OE
WE
LB
CE1_S
H
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
X
X
H
H
L
X
X
H
H
H
H
H
L
X
H
L
X
H
X
L
High-Z
High-Z
High-Z
High-Z
Deselected
Deselected
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
High-Z
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
High-Z
High-Z
High-Z
Data Out
Data Out
High-Z
Data In
Data In
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X
L
H
L
L
H
L
L
L
X
X
X
L
H
L
Lower Byte Write
Upper Byte Write
Word Write
L
H
L
L
L
Note: X = H or L
PRELIMINARY (April, 2007, Version 0.2)
51
AMIC Technology, Corp.
A82DL32x8T(U) Series
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
8
Unit
Conditions
VIN = 0V
Input Capacitance
pF
pF
CI/O*
Input/Output Capacitance
10
VI/O = 0V
* These parameters are sampled and not 100% tested.
POWER UP TIME
The initialization sequence is shown in the figure below.
should be HIGH (or CE2_S should be LOW) for at least 200 µs
CE1_S
after VCC_S has reached a stable value. No access must be attempted during this period of 200 µs.
PRELIMINARY (April, 2007, Version 0.2)
52
AMIC Technology, Corp.
A82DL32x8T(U) Series
AC Characteristics (TA = -40°C to +85°C, VCC_S = 2.7V to 3.3V)
70
Unit
Parameter List
Symbol
Min
Max
Read Cycle Time
tRC
tAA
tCO
tOE
tBA
70
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
Output Enable to Valid Output
70
70
35
70
,
Access Time
LB
UB
Chip select to Low-Z Output
Enable to Low-Z Output
tLZ
10
10
ns
ns
tBLZ
,
LB
UB
Output Enable to Low-Z Output
Chip Disable to High-Z Output
tOLZ
tHZ
5
0
0
ns
ns
ns
20
20
tBHZ
,
Disable to High-Z Output
LB
UB
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
tOHZ
tOH
tWC
tCW
tAS
0
5
20
ns
ns
ns
ns
ns
ns
ns
70
60
0
10000
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
tAW
tBW
60
60
,
Valid to End of Write
LB
UB
Write Pulse Width
tWP
tWR
tWHZ
tDW
tDH
50
0
ns
ns
ns
ns
ns
ns
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End of Write to Output Low-Z
0
20
40
0
tOW
5
PRELIMINARY (April, 2007, Version 0.2)
53
AMIC Technology, Corp.
A82DL32x8T(U) Series
Timing Waveforms
Read Cycle 1 ( WE = VIH)
Note (Read Cycle):
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels
2. At any given temperature and voltage condition, tHZ(max.) is less than tOLZ(min.) both for a given device and from device
to device.
3.
is high for the read cycle.
WE
4. Do not access device with cycle timing shorter than tRC for continuous periods >16us.
Read Cycle 2 (Address Controlled,
=
=VIL, CE2_S=
=VIH,
or/and
UB
=VIL)
LB
WE
OE
CE1_S
Note (Read Cycle):
1.
is high for the read cycle.
WE
2. Device is continuously selected.
= VIL, CE2_S = VIH
CE1_S
3.
= VIL.
OE
4. Do not access device with cycle timing shorter than tRC for continuous periods >16us.
PRELIMINARY (April, 2007, Version 0.2)
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AMIC Technology, Corp.
A82DL32x8T(U) Series
Write Cycle 1 (
Controlled)
WE
tWC
ADDR
tWR(4)
tCW(2)
CE1_S
tAW
CE2_S
UB, LB
tBW
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data In
Data Valid
tWHZ
tOW
Data Out
High-Z
Data Undefined(5)
Write Cycle 2 (
Controlled)
CE1_S
tWC
ADDR
tWR(4)
tCW(2)
tAW
tAS(3)
CE1_S
CE2_S
UB, LB
tBW
tWP(1)
WE
tDW
tDH
High-Z
High-Z
Data In
Data Valid
High-Z
Data Out
PRELIMINARY (April, 2007, Version 0.2)
55
AMIC Technology, Corp.
A82DL32x8T(U) Series
Write Cycle 3 (
,
Controlled)
LB
UB
Notes (Write Cycle):
1. A write occurs during the overlap of a low
, high CE2_S and low
. A write begins at the latest transition
WE
CE1_S
among
going low, CE2 going high and /WE going low: A write end at the earliest transition among
going
CE1_S
CE1_S
high, CE2_S going low and
WE
2. tCW is measured from the later of
going high. tWP is measured from the beginning of write to the end of write.
going low or CE2_S going high to the end of write.
CE1_S
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as
, or /WE
CE1_S
going high, and tWR is applied in case a write ends at CE2_S going low.
5. During this period, the I/Os are in Low-Z state and input signals should not be applied.
6. Do not access device with cycle timing shorter than tRC for continuous periods >16us.
PRELIMINARY (April, 2007, Version 0.2)
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AMIC Technology, Corp.
A82DL32x8T(U) Series
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Sector Erase Time
Typ. (Note 1)
Unit
sec
sec
μs
Comments
0.7
45
6
Excludes 00h programming
prior to erasure (Note 3)
Chip Erase Time
Byte Programming Time
Word Programming Time
Accelerated Word/Byte Programming Time
9
μs
Excludes system-level
overhead (Note 4)
6
μs
Chip Programming Time
(Note 2)
Byte Mode
Word Mode
32
20
sec
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 100,000 cycles. Additionally,
programming typically assumes checkerboard pattern.
2. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed.
3. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
4. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 12
for further information on command definitions.
5. The device has a minimum erase and program cycle endurance of 100,000 cycles.
FLASH LATCH-UP CHARACTERISTICS
Description
Min.
-1.0V
Max.
VCC_F+1.0V
+100 mA
12.5V
Input Voltage with respect to VSS on all I/O pins
VCC_F Current
-100 mA
-1.0V
Input voltage with respect to VSS on all pins except I/O pins
(including A9,
and
)
RESET
OE
Includes all pins except VCC_F. Test conditions: VCC_F = 3.0V, one pin at time.
PRELIMINARY (April, 2007, Version 0.2)
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AMIC Technology, Corp.
A82DL32x8T(U) Series
Ordering Information
Top Boot Sector Flash & SUPER RAM
Access Time
Part No.
(ns)
Bank 1
Bank 2
Package
A82DL3228TG-70
A82DL3228TG-70F
69-ball TFBGA
69-ball Pb-Free TFBGA
69-ball TFBGA
A82DL3228TG-70U
70
4M
28M
A82DL3228TG-70UF
69-ball Pb-Free TFBGA
69-ball TFBGA
A82DL3228TG-70I
A82DL3228TG-70IF
A82DL3238TG-70
A82DL3238TG-70F
69-ball Pb-Free TFBGA
69-ball TFBGA
69-ball Pb-Free TFBGA
69-ball TFBGA
A82DL3238TG-70U
70
8M
24M
A82DL3238TG-70UF
69-ball Pb-Free TFBGA
69-ball TFBGA
A82DL3238TG-70I
A82DL3238TG-70IF
A82DL3248TG-70
A82DL3248TG-70F
69-ball Pb-Free TFBGA
69-ball TFBGA
69-ball Pb-Free TFBGA
69-ball TFBGA
A82DL3248TG-70U
70
16M
16M
A82DL3248TG-70UF
69-ball Pb-Free TFBGA
69-ball TFBGA
A82DL3248TG-70I
A82DL3248TG-70IF
69-ball Pb-Free TFBGA
Note: -U is for industrial operating temperature range: -40°C to +85°C
-I is for industrial operating temperature range: -25°C to +85°C
PRELIMINARY (April, 2007, Version 0.2)
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AMIC Technology, Corp.
A82DL32x8T(U) Series
Ordering Information (continued)
Top Boot Sector Flash & SUPER RAM
Access Time
Part No.
(ns)
Bank 1
Bank 2
Package
A82DL3228UG-70
A82DL3228UG-70F
69-ball TFBGA
69-ball Pb-Free TFBGA
69-ball TFBGA
A82DL3228UG-70U
70
4M
28M
A82DL3228UG-70UF
69-ball Pb-Free TFBGA
69-ball TFBGA
A82DL3228UG-70I
A82DL3228UG-70IF
A82DL3238UG-70
A82DL3238UG-70F
69-ball Pb-Free TFBGA
69-ball TFBGA
69-ball Pb-Free TFBGA
69-ball TFBGA
A82DL3238UG-70U
70
8M
24M
A82DL3238UG-70UF
69-ball Pb-Free TFBGA
69-ball TFBGA
A82DL3238UG-70I
A82DL3238UG-70IF
A82DL3248UG-70
A82DL3248UG-70F
69-ball Pb-Free TFBGA
69-ball TFBGA
69-ball Pb-Free TFBGA
69-ball TFBGA
A82DL3248UG-70U
70
16M
16M
A82DL3248UG-70UF
69-ball Pb-Free TFBGA
69-ball TFBGA
A82DL3248UG-70I
A82DL3248UG-70IF
69-ball Pb-Free TFBGA
Note: -U is for industrial operating temperature range: -40°C to +85°C
-I is for industrial operating temperature range: -25°C to +85°C
PRELIMINARY (April, 2007, Version 0.2)
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AMIC Technology, Corp.
A82DL32x8T(U) Series
Package Information
69LD STF BGA (8 x 11mm) Outline Dimensions
unit: mm
D1
e
-A-
aaa
D
Pin #1
-B-
K
J
H
G
F
E
D
C
B
A
aaa
1 2 3 4 5 6 7 8 9 10
See Detail B
M
ddd
C
M
eee C A B
See Detail A
CAVITY
C
B
b
// bbb C
A
-C-
ccc C
SOLDER BALL
1
2
3
SEATING PLANE
Detail A
Detail B
Dimensions in mm
Dimensions in inches
Symbol
Min
Nom
-
Max
Min
-
Nom
-
Max
0.055
0.014
0.040
0.012
0.319
0.437
-
A
A1
-
0.25
0.91
0.22
7.90
10.90
-
1.40
0.35
1.01
0.30
8.10
11.10
-
0.30
0.96
0.26
8.00
11.00
7.20
7.20
0.80
0.40
0.15
0.20
0.12
0.15
0.08
10/10
0.010
0.036
0.009
0.311
0.429
-
0.012
0.038
0.010
0.315
0.433
0.283
0.283
0.031
0.16
A2
c
D
E
D1
E1
e
-
-
-
-
-
-
-
-
b
0.35
0.45
0.14
0.18
aaa
bbb
ccc
ddd
eee
MD/ME
0.006
0.008
0.005
0.006
0.003
10/10
Notes:
1. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
2. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL
DIAMETER, PARALLEL TO PRIMARY DATUM C.
3. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN
THE EDGE OF THE SOLDER BALL AND THE BODY EDGE.
4. REFERENCE DOCUMENT: JEDEC MO-219
5. THE PATTERN OF PIN 1 FIDUCIAL IS FOR REFERENCE ONLY.
PRELIMINARY (April, 2007, Version 0.2)
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AMIC Technology, Corp.
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