LP61L256CS-12 [AMICC]
32K X 8 BIT HIGH SPEED CMOS SRAM; 32K ×8位高速CMOS SRAM
| 型号： | LP61L256CS-12 |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 32K X 8 BIT HIGH SPEED CMOS SRAM |
| 文件： | 总11页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP61L256C
Preliminary
32K X 8 BIT HIGH SPEED CMOS SRAM
Document Title
32K X 8 BIT HIGH SPEED CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
Initial issue
November 9, 2001
Preliminary
PRELIMINARY
(November, 2001, Version 0.0)
AMIC Technology, Inc.
LP61L256C
Preliminary
32K X 8 BIT HIGH SPEED CMOS SRAM
Features
n Single +3.3V power supply
n Access times: 12/15 ns (max.)
n Current: Operating: 120mA (max.)
n All inputs and outputs are directly TTL compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
Standby:
5mA (max.)
n Available in 28-pin SOJ package
n Full static operation, no clock or refreshing required
General Description
The LP61L256C is a high-speed, low-power 262,144-bit
static random access memory organized as 32,768
words by 8 bits and operates on a single 3.3V power
supply. It is built using high performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Minimum standby power is drawn by this device when
CE is at a high level, independent of the other input
levels.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
n SOJ
1
VCC
WE
28
27
26
A14
A12
2
A7
A13
3
4
A8
A6
A5
A4
25
24
23
A9
5
6
A11
A3
A2
A1
A0
OE
7
8
22
A10
21
20
19
18
CE
9
I/O7
10
11
I/O6
I/O5
I/O0
I/O1
12
13
14
17
16
15
I/O2
I/O4
I/O3
GND
PRELIMINARY
(November, 2001, Version 0.0)
1
AMIC Technology, Inc.
LP61L256C Series
Block Diagram
A0
VCC
GND
A5
A6
ROW
256 X 1024
A7
DECODER
MEMORY ARRAY
A9
A10
A11
A12
0
I/O
COLUMN I/O
INPUT DATA
CIRCUIT
COLUMN DECODER
I/O
7
A2
A3
A1
A4 A8 A13 A14
CE
OE
CONTROL
CIRCUIT
WE
Pin Descriptions - SOJ
Pin No.
Symbol
A0 - A14
I/O0 - I/O7
GND
Description
1 - 10, 21, 23 - 26
Address Inputs
Data Inputs/Outputs
Ground
11 - 13, 15 - 19
14
28
20
VCC
Power Supply
Chip Enable
CE
OE
WE
22
27
Output Enable
Write Enable
PRELIMINARY
(November, 2001, Version 0.0)
2
AMIC Technology, Inc.
LP61L256C Series
Recommended DC Operating Conditions
(TA = 0°C to + 70°C)
Symbol
VCC
GND
VIH
Parameter
Supply Voltage
Ground
Min.
3.0
0
Typ.
Max.
3.6
Unit
V
3.3
0
0
V
Input High Voltage
Input Low (1) Voltage
Output Load
2.2
-0.5
-
-
VCC + 0.3
+0.8
V
VIL
0
V
CL
-
30
pF
Absolute Maximum Ratings*
*Comments
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC +0.5V
Operating Temperature, Topr . . . . . . . . . . . 0°C to +70°C
Storage Temperature, Tstg . . . . . . . . . . -55°C to +125°C
Temperature Under Bias, Tbias . . . . . . . . -10°C to +85°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C, VCC = 3.3V ± 10%, GND = 0V)
LP61L256C-12/15
Symbol
Parameter
Unit
Conditions
Min.
Max.
Input Leakage
-
2
VIN = GND to VCC
½ILI½
mA
mA
CE = VIH or OE = VIH
VI/O = GND to VCC
Output Leakage
-
2
½ILO½
CE = VIL, II/O = 0 mA
Min. Cycle, Duty = 100%
ICC1 (2)
ISB
Dynamic Operating Current
-
-
120
30
mA
mA
CE = VIH
Standby Power
Supply Current
CE ³ VCC - 0.2V
VIN ³ VCC -0.2V or
VIN £ 0.2V
ISB1
-
5
mA
VOL
VOH
Output Low Voltage
Output High Voltage
-
0.4
-
V
V
IOL = 8 mA
2.4
IOH = -4 mA
Notes: 1. VIL = -3.0V for pulses less than 20 ns.
2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns.
PRELIMINARY
(November, 2001, Version 0.0)
3
AMIC Technology, Inc.
LP61L256C Series
Truth Table
Mode
I/O Operation
High Z
High Z
DOUT
Supply Current
CE
H
L
OE
X
WE
X
Standby
Output Disable
Read
ISB, ISB1
ICC1
H
H
L
L
H
ICC1
Write
L
X
L
DIN
ICC1
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
10
Unit
pF
Conditions
VIN = 0V
Input Capacitance
CI/O*
Input/Output Capacitance
10
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V ± 10%)
LP61L256C-12
LP61L256C-15
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
12
-
-
12
12
6
15
-
-
15
15
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
tACE
tOE
Chip Enable Access Time
-
-
Output Enable to Output Valid
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
-
-
tCLZ
3
0
0
0
3
-
3
0
-
-
tOLZ
-
-
tCHZ
6
8
tOHZ
tOH
6
0
3
8
-
-
PRELIMINARY
(November, 2001, Version 0.0)
4
AMIC Technology, Inc.
LP61L256C Series
AC Characteristics (continued)
LP61L256C-12
Min. Max.
LP61L256C-15
Unit
Symbol
Parameter
Min.
Max
Write Cycle
tWC
Write Cycle Time
12
10
0
-
-
-
-
-
-
6
-
-
-
15
12
0
-
-
-
-
-
-
8
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Chip Enable to End of Write
Address Setup Time of Write
Address Valid to End of Write
Write Pulse Width
tAS
tAW
10
10
0
12
12
0
tWP
tWR
Write Recovery Time
tWHZ
tDW
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
0
6
7
tDH
0
0
tOW
3
3
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levles.
Timing Waveforms
Read Cycle 1(1)
tRC
Address
tAA
OE
tOE
tOH
5
tOLZ
CE
5
tOHZ
tACE
5
tCHZ
5
tCLZ
DOUT
PRELIMINARY
(November, 2001, Version 0.0)
5
AMIC Technology, Inc.
LP61L256C Series
Timing Waveforms (continued)
Read Cycle 2(1, 2, 4)
tRC
Address
tAA
tOH
tOH
DOUT
Read Cycle 3(1, 3, 4,)
CE
tACE
5
tCLZ
5
tCHZ
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
(November, 2001, Version 0.0)
6
AMIC Technology, Inc.
LP61L256C Series
Timing Waveforms (continued)
Write Cycle 1(6)
(Write Enable Controlled)
tWC
Address
tAW
3
tWR
5
tCW
CE
(4)
1
2
tAS
tWP
WE
tDW
tDH
DIN
7
tWHZ
7
tOW
DOUT
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
tAW
1
3
5
tAS
tWR
tCW
(4)
CE
WE
DIN
2
tWP
tDW
tDH
7
tWHZ
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE and a low WE .
3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle
4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs
remain in a high impedance state.
5. tCW is measured from the later of CE going low to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
(November, 2001, Version 0.0)
7
AMIC Technology, Inc.
LP61L256C Series
AC Test Conditions
Input Pulse Levels
0V to 3.0V
2 ns
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
See Figures 1 and 2
+3.3V
317
W
W
I/O
OUTPUT
RL=50
W
ZO=50
W
5pF*
351
VT=1.5V
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = 0°C to 70°C)
Symbol
Parameter
Min.
Max.
Unit
Conditions
VDR
VCC for Data Retention
2
3.6
V
CE ³ VCC - 0.2V
VCC = 2.0V
CE ³ VCC - 0.2V
VIN ³ VCC - 0.2V or
VIN £ 0.2V
ICCDR
Data Retention Current
-
2
mA
Chip Disable to Data Retention
Time
tCDR
tR
0
-
-
ns
ns
See Retention Waveform
Operation Recovery Time
tRC*
tRC = Read Cycle Time
PRELIMINARY
(November, 2001, Version 0.0)
8
AMIC Technology, Inc.
LP61L256C Series
Low VCC Data Retention Waveform
DATA RETENTION MODE
VCC
CE
3.0V
3.0V
tCDR
tR
VDR
³
2.0V
VIH
VIH
CE
³
VDR - 0.2V
Ordering Information
Part No.
Operating Current
Max. (mA)
Standby Current
Max. (mA)
Access Time (ns)
Package
28L SOJ
28L SOJ
LP61L256CS-12
LP61L256CS-15
12
15
120
120
5
5
PRELIMINARY
(November, 2001, Version 0.0)
9
AMIC Technology, Inc.
LP61L256C Series
Package Information
SOJ 28L Outline Dimensions
unit: inches/mm
28
15
1
14
D
b
b
S
e
e
1
1
y
Seating Plane
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
-
Max
0.140
-
Min
-
Nom
-
Max
3.56
-
A
A1
A2
b1
b
0.027
0.095
-
0.69
2.41
-
0.100
0.028 TYP
0.018 TYP
0.010 TYP
0.710
0.300
0.050 BSC
0.265
0.337
0.087
-
0.105
2.54
2.67
0.71 TYP
0.46 TYP
0.25 TYP
18.03
7.62
C
D
E
-
0.730
0.305
-
18.54
7.75
0.295
7.49
e
1.27 BSC
6.73
e1
HE
L
0.255
0.329
0.077
-
0.275
0.345
0.097
0.045
0.004
6.48
8.36
1.96
-
6.99
8.76
2.46
1.14
0.10
8.56
2.21
S
-
y
-
-
-
-
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
PRELIMINARY
(November, 2001, Version 0.0)
10
AMIC Technology, Inc.
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