LP62S1024AV-70LLI [AMICC]
128K X 8 BIT LOW VOLTAGE CMOS SRAM; 128K ×8位的低电压CMOS SRAM
| 型号： | LP62S1024AV-70LLI |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| 文件： | 总15页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP62S1024A-I Series
Preliminary
128K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
n Power supply range: 2.7V to 3.6V
n Access times: 55/70 ns (max.)
n Current:
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy
Very low power version: Operating:(70NS)30mA(max.)
(55NS)40mA(max.)
Standby: 5uA (max.)
n Full static operation, no clock or refreshing required
application
n Data retention voltage: 2V (min.)
n Available in 32-pin TSOP, TSSOP (8X13.4mm)
packages
General Description
The LP62S1024A-I is a low operating current 1,048,576-
bit static random access memory organized as 131,072
words by 8 bits and operates on a low power voltage:
2.7V to 3.6V. It is built using AMIC's high performance
CMOS process.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
n TSOP/TSSOP
16
1
32
17
Pin No.
1
2
3
4
5
6
7
8
9
10
A16
26
11
A14
27
12
A12
28
13
A7
14
A6
15
A5
16
A4
32
Pin
Name
A11
17
A9
18
A2
A8
19
A1
A13
20
WE
21
CE2
22
A15
VCC
24
NC
25
Pin No.
23
29
30
31
Pin
Name
I/O3
I/O8
A3
A0
I/O1
I/O2
GND
I/O4
I/O5
I/O6
I/O7
CE1
A10
OE
PRELIMINARY (August, 2001, Version 0.1)
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AMIC Technology, Inc.
LP62S1024A-I Series
Block Diagram
A0
VCC
GND
ROW
512 X 2048
A14
A15
A16
DECODER
MEMORY ARRAY
I/O1
COLUMN I/O
INPUT DATA
CIRCUIT
I/O8
CE2
CE1
OE
CONTROL
CIRCUIT
WE
Pin Description – TSOP/TSSOP
Pin No.
Symbol
Description
1 - 4, 7,
10 - 20, 31
A0 - A16
Address Inputs
Write Enable
5
WE
CE2
VCC
NC
6
8
9
Chip Enable
Power Supply
No Connection
21 - 23,
25 - 29
I/O1 - I/O8
Data Input/Outputs
24
30
GND
CE1
OE
Ground
Chip Enable
32
Output Enable
PRELIMINARY (August, 2001, Version 0.1)
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AMIC Technology, Inc.
LP62S1024A-I Series
Recommended DC Operating Conditions
(TA = -40°C to +85°C)
Symbol
VCC
GND
VIH
Parameter
Supply Voltage
Min.
2.7
0
Typ.
Max.
Unit
V
3.0
3.6
Ground
0
-
0
V
Input High Voltage
Input Low Voltage
Output Load
2.0
-0.3
-
VCC + 0.3
V
VIL
-
+0.6
30
1
V
CL
-
pF
-
TTL
Output Load
-
-
PRELIMINARY (August, 2001, Version 0.1)
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AMIC Technology, Inc.
LP62S1024A-I Series
Absolute Maximum Ratings*
*Comments
VCC to GND .............................................. -0.5V to +4.6V
IN, IN/OUT Volt to GND.....................-0.5V to VCC +0.5V
Operating Temperature, Topr ................... -40°C to +85°C
Storage Temperature, Tstg..................... -55°C to +125°C
Temperature Under Bias, Tbias................ -10°C to +85°C
Power Dissipation, PT ...............................................0.7W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -40°C to +85°C, VCC = 2.7V to 3.6V, GND = 0V)
LP62S1024A-55LLI/70LLI
Symbol
Parameter
Unit
Conditions
Min.
Max.
Input Leakage
Current
-
1
VIN = GND to VCC
çILIú
mA
CE1 = VIH or CE2 = VIL
VI/O = GND to VCC
Output Leakage
Current
-
-
1
3
çILOú
ICC
mA
Active Power Supply
Current
CE1 = VIL, CE2 = VIH
II/O = 0mA
mA
-
-
-70NS:30
-55NS:40
Min. Cycle, Duty = 100%
CE1 = VIL, CE2 = VIH
II/O = 0mA
ICC1
ICC2
mA
mA
Dynamic Operating
Current
CE1 = VIL, CE2 = VIH
f = 1 MHZ, II/O = 0mA
-
5
PRELIMINARY (August, 2001, Version 0.1)
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AMIC Technology, Inc.
LP62S1024A-I Series
DC Electrical Characteristics (continued)
LP62S1024A-55LLI/70LLI
Symbol
Parameter
Unit
Conditions
Min.
Max.
ISB
ISB1
ISB2
-
0.5
mA
CE1 = VIH or CE2 =VIL
CE1 ³ VCC - 0.2V , CE2 ³ VCC - 0.2V
VIN ³ VCC - 0.2V or VIN £ 0.2V
Standby Power
Supply Current
-
-
5
5
mA
mA
CE1 £ 0.2V , CE2 £ 0.2V
VIN ³ VCC - 0.2V or VIN £ 0.2V
Output Low
Voltage
VOL
VOH
-
0.4
-
V
V
IOL = 2.1mA
IOH = -1.0mA
Output High
Voltage
2.2
Truth Table
Mode
CE2
I/O Operation
Supply Current
CE1
H
OE
WE
X
X
L
X
X
H
L
High Z
High Z
High Z
DOUT
ISB, ISB1
Standby
X
X
ISB, ISB2
Output Disable
Read
L
L
L
H
H
H
H
ICC, ICC1, ICC2
ICC, ICC1, ICC2
ICC, ICC1, ICC2
H
Write
X
L
DIN
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
6
8
CI/O*
Input/Output Capacitance
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
PRELIMINARY (August, 2001, Version 0.1)
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AMIC Technology, Inc.
LP62S1024A-I Series
AC Characteristics (TA = -40°C to +85°C, VCC = 2.7V to 3.6V)
LP62S1024A-55LLI
LP62S1024A-70LLI
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
Read Cycle
tRC
tAA
Read Cycle Time
55
-
-
70
-
-
ns
ns
ns
Address Access Time
55
55
70
70
tACE1
-
-
CE1
CE2
Chip Enable Access Time
tACE2
tOE
-
-
55
30
-
-
-
70
35
-
ns
ns
ns
Output Enable to Output Valid
Chip Enable to Output in Low Z
tCLZ1
10
10
CE1
CE2
tCLZ2
tOLZ
10
5
-
-
10
5
-
-
ns
ns
ns
Output Enable to Output in Low Z
Chip Disable to Output in High Z
tCHZ1
0
20
0
25
CE1
CE2
tCHZ2
tOHZ
tOH
0
0
5
20
20
-
0
0
25
25
-
ns
ns
ns
Output Disable to Output in High Z
Output Hold from Address Change
10
Write Cycle
tWC
Write Cycle Time
55
50
0
-
-
70
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Chip Enable to End of Write
Address Setup Time
tAS
-
-
tAW
Address Valid to End of Write
Write Pulse Width
50
40
0
-
60
50
0
-
tWP
-
-
tWR
Write Recovery Time
-
-
tWHZ
tDW
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
25
-
0
25
-
25
0
30
0
tDH
-
-
tOW
5
-
5
-
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
PRELIMINARY (August, 2001, Version 0.1)
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AMIC Technology, Inc.
LP62S1024A-I Series
Timing Waveforms
Read Cycle 1 (1, 2, 4)
tRC
Address
tAA
tOH
tOH
DOUT
Read Cycle 2 (1, 3, 4, 6)
CE1
tACE1
5
tCLZ1
5
tCHZ1
DOUT
Read Cycle 3 (1, 4, 7, 8)
CE2
tACE2
5
tCHZ2
5
tCLZ2
DOUT
PRELIMINARY (August, 2001, Version 0.1)
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AMIC Technology, Inc.
LP62S1024A-I Series
Timing Waveforms (continued)
Read Cycle 4 (1)
tRC
Address
tAA
OE
tOE
tOH
5
tOLZ
CE1
tACE1
5
5
tCHZ1
tCLZ1
CE2
5
tACE2
tOHZ
5
tCHZ2
5
tCLZ2
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7. CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
PRELIMINARY (August, 2001, Version 0.1)
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AMIC Technology, Inc.
LP62S1024A-I Series
Timing Waveforms (continued)
Write Cycle 1 (6)
(Write Enable Controlled)
tWC
Address
3
tAW
tWR
5
tCW
(4)
(4)
CE1
CE2
1
2
tAS
tWP
WE
tDW
tDH
DIN
tWHZ
tOW
DOUT
PRELIMINARY (August, 2001, Version 0.1)
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AMIC Technology, Inc.
LP62S1024A-I Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
3
tAW
tWR
5
tCW
CE1
CE2
(4)
(4)
1
tAS
5
tCW
2
tWP
WE
tDW
tDH
DIN
7
tWHZ
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (August, 2001, Version 0.1)
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AMIC Technology, Inc.
LP62S1024A-I Series
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
5 ns
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
See Figures 1 and 2
TTL
TTL
CL
CL
30pF
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = -40°C to 85°C)
Symbol
Parameter
Min.
Max.
Unit
Conditions
CE1 ³ VCC - 0.2V
VDR1
2.0
3.6
V
VCC for Data Retention
VDR2
2.0
3.6
V
CE2 £ 0.2V
VCC = 2V,
ICCDR1
-
3*
mA
CE1 ³ VCC - 0.2V
VIN ³ VCC - 0.2V or VIN £ 0.2V
Data Retention Current
VCC = 2V,
CE2 £ 0.2V
VIN ³ VCC - 0.2V or VIN £ 0.2V
ICCDR2
-
3*
mA
tCDR
tR
Chip Disable to Data Retention Time
Operation Recovery Time
0
5
-
-
ns
See Retention Waveform
ms
*
LP62S1024A-55LLI/70LLI
ICCDR: max. ImA at TA = 0°C to + 40°C
PRELIMINARY (August, 2001, Version 0.1)
11
AMIC Technology, Inc.
LP62S1024A-I Series
Low VCC Data Retention Waveform (1) ( CE1 Controlled)
DATA RETENTION MODE
VCC
CE1
3.0V
3.0V
tCDR
tR
VDR
³ 2V
VIH
VIH
CE1
³ VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE
VCC
CE2
3.0V
3.0V
tCDR
tR
VDR
³ 2V
VIL
VIL
CE2
£ 0.2V
PRELIMINARY (August, 2001, Version 0.1)
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AMIC Technology, Inc.
LP62S1024A-I Series
Ordering Information
Part No.
Operating Current
Max. (mA)
Standby Current
Access Time (ns)
Package
Max. (mA)
LP62S1024AV-55LLI
LP62S1024AX-55LLI
LP62S1024AV-70LLI
LP62S1024AX-70LLI
40
40
30
30
5
5
5
5
32L TSOP
32L TSSOP
32L TSOP
32L TSSOP
PRELIMINARY (August, 2001, Version 0.1)
13
AMIC Technology, Inc.
LP62S1024A-I Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
D
12.0°
GAUGE PLANE
q
L
LE
HD
Detail "A"
Detail "A"
y
S
b
0.10(0.004)
M
Symbol
Dimensions in inches
Dimensions in mm
1.20 Max.
0.10±0.05
1.00±0.05
0.20±0.03
0.15±0.02
18.40±0.10
8.00±0.10
0.50 TYP.
20.00±0.20
0.50±0.10
0.80 TYP.
0.425 TYP.
0.10 Max.
0° ~ 6°
A
A1
A2
b
0.047 Max.
0.004±0.002
0.039±0.002
0.008±0.001
0.006±0.001
0.724±0.004
0.315±0.004
0.020 TYP.
0.787±0.007
0.020±0.004
0.031 TYP.
0.0167 TYP.
0.004 Max.
0° ~ 6°
c
D
E
e
HD
L
LE
S
Y
q
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
PRELIMINARY (August, 2001, Version 0.1)
14
AMIC Technology, Inc.
LP62S1024A-I Series
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
12.0°
GAUGE PLANE
q
L
LE
D1
D
Detail "A"
Detail "A"
0.10MM
S
b
SEATING PLANE
Symbol
Dimensions in inches
Dimensions in mm
1.25 Max.
A
A1
A2
b
0.049 Max.
0.002 Min.
0.05 Min.
0.039±0.002
0.008±0.001
0.006±0.0003
0.315±0.004
0.020 TYP.
0.528±0.008
0.465±0.004
0.02±0.008
0.0266 Min.
0.0109 TYP.
0.004 Max.
0° ~ 6°
1.00±0.05
0.20±0.03
0.15±0.008
8.00±0.10
0.50 TYP.
13.40±0.20
11.80±0.10
0.50±0.20
0.675 Min.
0.278 TYP.
0.10 Max.
c
E
e
D
D1
L
LE
S
y
q
0° ~ 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
PRELIMINARY (August, 2001, Version 0.1)
15
AMIC Technology, Inc.
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