LP62S1024BU-55LLI [AMICC]
128K X 8 BIT LOW VOLTAGE CMOS SRAM; 128K ×8位的低电压CMOS SRAM
| 型号： | LP62S1024BU-55LLI |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| 文件： | 总17页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP62S1024B-I Series
128K X 8 BIT LOW VOLTAGE CMOS SRAM
Document Title
128K X 8 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
1.0
1.1
1.2
Initial issue
May 30, 2002
October 2, 2002
July 18, 2003
June 29, 2004
August 9, 2004
Preliminary
Add 32L Pb-Free TSSOP package type
Final version release
Final
Change ICCDR1, ICCDR2 (max.) from 3μA to 1μA
Add Pb-Free package type for all parts
(August, 2004, Version 1.2)
AMIC Technology, Corp.
LP62S1024B-I Series
128K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
General Description
Power supply range: 2.7V to 3.6V
Access times: 55/70 ns (max.)
Current:
Very low power version: Operating: 30mA(max.)
Standby: 5uA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
The LP62S1024B-I is a low operating current 1,048,576-bit
static random access memory organized as 131,072 words
by 8 bits and operates on a low power voltage: 2.7V to 3.6V.
It is built using AMIC's high performance CMOS process.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included for
Output enable and two chip enable inputs for easy
application
Data retention voltage: 2V (min.)
easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 2V.
Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm)
forward type and 36-pin CSP packages
Product Family
Power Dissipation
Package
Product Family
Operating
Temperature
VCC
Range
Speed
Data Retention
(ICCDR, Typ.)
Standby
Operating
(ICC2, Typ.)
Type
(ISB1, Typ.)
32L SOP
32L TSOP
32L TSSOP
36B µBGA
LP62S1024B
2.7V~3.6V 55ns / 70ns
1.5mA
-40°C ~ +85°C
0.05µA
0.08µA
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
(August, 2004, Version 1.2)
1
AMIC Technology, Corp.
LP62S1024B-I Series
Pin Configurations
SOP
TSOP/TSSOP
CSP (Chip Size Package)
36-pin Top View
1
VCC
A15
CE2
WE
A13
A8
32
31
30
29
28
27
26
NC
A16
A14
16
1
2
3
4
5
6
A12
A7
1
2
3
4
5
6
A8
A0
A1
A2
CE2
WE
A3
A4
A6
A7
A
B
A6
I/O
I/O
5
I/O
I/O
1
A5
A4
A3
A9
7
8
C
D
E
F
6
NC
A5
2
A11
OE
25
24
23
22
9
GND
VCC
VCC
GND
A10
10
11
A2
A1
A0
CE1
I/O
I/O
7
NC
CE1
A11
NC
A16
A12
I/O
I/O
3
I/O
8
12
13
14
15
16
21
20
19
18
17
I/O
I/O
I/O
1
2
3
I/O
I/O
I/O
I/O
7
4
G
H
8
OE
A15
A13
6
5
A9
A10
A14
32
17
GND
4
Pin No.
1
2
3
4
5
6
7
8
9
10
A16 A14
26 27
I/O I/O
11
12
A12
28
13
A7
29
14
A6
30
15
16
Pin
Name
A11
17
A9
18
A2
A8
19
A1
A13
20
WE
21
CE2 A15 VCC NC
A5
31
A4
32
Pin No.
22
I/O
23
24
25
Pin
Name
I/O
3
I/O
8
A3
A0
I/O
1
2
GND I/O
4
5
6
I/O
7
CE1 A10
OE
Block Diagram
A0
VCC
GND
ROW
512 X 2048
MEMORY ARRAY
A14
A15
A16
DECODER
I/O
1
COLUMN I/O
INPUT DATA
CIRCUIT
I/O
8
CE2
CE1
OE
CONTROL
CIRCUIT
WE
(August, 2004, Version 1.2)
2
AMIC Technology, Corp.
LP62S1024B-I Series
Pin Descriptions - SOP
Pin Description – TSOP/TSSOP
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
NC
No Connection
1 - 4, 7,
10 - 20, 31
A0 - A16
Address Inputs
Write Enable
2 - 12, 23,
25 - 28, 31
A0 - A16
Address Inputs
5
WE
CE2
VCC
NC
13 - 15,
17 - 21
6
8
9
Chip Enable
I/O1 - I/O8
Data Input/Outputs
Power Supply
No Connection
16
22
GND
CE1
OE
Ground
Chip Enable
21 - 23,
25 - 29
I/O1 - I/O8
Data Input/Outputs
24
29
Output Enable
Write Enable
24
30
GND
CE1
OE
Ground
WE
CE2
VCC
Chip Enable
30
32
Chip Enable
32
Output Enable
Power Supply
Pin Description - CSP
Symbol
Description
Symbol
Description
A0 - A16
WE
Address Inputs
Write Enable
NC
No Connection
I/O1 - I/O8
Data Input/Output
Power Supply
Ground
Output Enable
Chip Enable
Chip Enable
VCC
GND
--
OE
CE1
CE2
--
(August, 2004, Version 1.2)
3
AMIC Technology, Corp.
LP62S1024B-I Series
Recommended DC Operating Conditions
(TA = -40°C to +85°C)
Symbol
VCC
GND
VIH
Parameter
Supply Voltage
Min.
2.7
0
Typ.
Max.
Unit
V
3.0
3.6
Ground
0
-
0
V
Input High Voltage
Input Low Voltage
Output Load
2.2
-0.3
-
VCC + 0.3
V
VIL
-
+0.6
30
1
V
CL
-
pF
-
TTL
Output Load
-
-
Absolute Maximum Ratings*
*Comments
VCC to GND ...............................................-0.5V to +4.6V
IN, IN/OUT Volt to GND..................... -0.5V to VCC +0.5V
Operating Temperature, Topr ................... -40°C to +85°C
Storage Temperature, Tstg..................... -55°C to +125°C
Temperature Under Bias, Tbias................ -10°C to +85°C
Power Dissipation, PT ............................................... 0.7W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics (TA = -40°C to +85°C, VCC = 2.7V to 3.6V, GND = 0V)
Symbol
Parameter
LP62S1024B-55LLI/70LLI
Unit
Conditions
Min.
Max.
Input Leakage Current
Output Leakage Current
-
1
VIN = GND to VCC
⎜ILI⎥
⎜ILO⎥
ICC
µA
µA
CE1 = VIH or CE2 = VIL
-
-
1
3
or OE = VIH or WE = VIL
VI/O = GND to VCC
Active Power Supply
Current
CE1 = VIL, CE2 = VIH
II/O = 0mA
mA
Min. Cycle, Duty = 100%
CE1 = VIL, CE2 = VIH
II/O = 0mA
-
-
30
3
ICC1
ICC2
mA
mA
Dynamic Operating
Current
CE1 = VIL, CE2 = VIH
VIH = VCC, VIL = 0V
f = 1 MHZ, II/O = 0mA
VCC ≤ 3.3V, CE1 = VIH or CE2 =VIL
ISB
-
-
0.5
5
mA
Standby Power Supply
Current
VCC ≤ 3.3V, CE1 ≥ VCC - 0.2V or
CE2 ≤ 0.2V, VIN ≥ 0V
ISB1
µA
VOL
VOH
Output Low Voltage
Output High Voltage
-
0.4
-
V
V
IOL = 2.1mA
IOH = -1.0mA
2.2
(August, 2004, Version 1.2)
4
AMIC Technology, Corp.
LP62S1024B-I Series
Truth Table
Mode
CE2
I/O Operation
Supply Current
CE1
H
OE
X
WE
X
X
L
High Z
High Z
High Z
DOUT
ISB, ISB1
Standby
X
X
X
ISB, ISB1
Output Disable
L
H
H
H
H
L
H
ICC, ICC1, ICC2
ICC, ICC1, ICC2
ICC, ICC1, ICC2
Read
Write
L
H
L
X
L
DIN
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
6
8
CI/O*
Input/Output Capacitance
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
(August, 2004, Version 1.2)
5
AMIC Technology, Corp.
LP62S1024B-I Series
AC Characteristics (TA = -40°C to +85°C, VCC = 2.7V to 3.6V)
LP62S1024B-55LLI
LP62S1024B-70LLI
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
Read Cycle
tRC
tAA
Read Cycle Time
55
-
-
70
-
-
ns
ns
ns
Address Access Time
55
55
70
70
tACE1
-
-
CE1
CE2
Chip Enable Access Time
tACE2
tOE
-
-
55
30
-
-
-
70
35
-
ns
ns
ns
Output Enable to Output Valid
Chip Enable to Output in Low Z
tCLZ1
10
10
CE1
CE2
tCLZ2
tOLZ
10
5
-
-
10
5
-
-
ns
ns
ns
Output Enable to Output in Low Z
Chip Disable to Output in High Z
tCHZ1
0
20
0
25
CE1
CE2
tCHZ2
tOHZ
tOH
0
0
5
20
20
-
0
0
25
25
-
ns
ns
ns
Output Disable to Output in High Z
Output Hold from Address Change
10
Write Cycle
tWC
Write Cycle Time
55
50
0
-
-
70
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Chip Enable to End of Write
Address Setup Time
tAS
-
-
tAW
Address Valid to End of Write
Write Pulse Width
50
40
0
-
60
50
0
-
tWP
-
-
tWR
Write Recovery Time
-
-
tWHZ
tDW
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
25
-
0
25
-
25
0
30
0
tDH
-
-
tOW
5
-
5
-
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
(August, 2004, Version 1.2)
6
AMIC Technology, Corp.
LP62S1024B-I Series
Timing Waveforms
Read Cycle 1 (1, 2, 4)
t
RC
Address
t
AA
t
OH
t
OH
D
OUT
Read Cycle 2 (1, 3, 4, 6)
CE1
t
ACE1
5
CLZ1
t
5
CHZ1
t
D
OUT
Read Cycle 3 (1, 4, 7, 8)
CE2
t
ACE2
5
CHZ2
t
5
CLZ2
t
D
OUT
(August, 2004, Version 1.2)
7
AMIC Technology, Corp.
LP62S1024B-I Series
Timing Waveforms (continued)
Read Cycle 4 (1)
tRC
Address
OE
tAA
tOE
tOH
tOLZ
5
CE1
tACE1
5
5
tCHZ1
tCLZ1
CE2
5
tACE2
tOHZ
5
tCHZ2
5
tCLZ2
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7. CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
Write Cycle 1 (6)
(Write Enable Controlled)
tWC
Address
3
tAW
tWR
5
tCW
(4)
(4)
CE1
CE2
1
2
tAS
tWP
WE
DIN
tDW
tDH
tWHZ
tOW
DOUT
(August, 2004, Version 1.2)
8
AMIC Technology, Corp.
LP62S1024B-I Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
t
WC
Address
3
tWR
t
AW
5
CW
t
CE1
CE2
(4)
(4)
1
AS
t
5
CW
t
2
t
WP
WE
t
DW
t
DH
D
IN
7
WHZ
t
D
OUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(August, 2004, Version 1.2)
9
AMIC Technology, Corp.
LP62S1024B-I Series
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
5 ns
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
See Figures 1 and 2
TTL
TTL
C
L
CL
30pF
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = -40°C to 85°C)
Symbol
Parameter
Min.
Max.
Unit
Conditions
CE1 ≥ VCC - 0.2V
CE2 ≤ 0.2V,
VDR1
2.0
3.6
V
VCC for Data Retention
VDR2
2.0
3.6
V
VCC = 2V,
ICCDR1
-
1*
µA
CE1 ≥ VCC - 0.2V,
VIN ≥ 0V
Data Retention Current
VCC = 2V,
CE2 ≤ 0.2V,
VIN ≥ 0V
-
1*
µA
ICCDR2
tCDR
tR
Chip Disable to Data Retention Time
Operation Recovery Time
0
5
-
-
ns
See Retention Waveform
ms
*
LP62S1024B-55LLI/70LLI
ICCDR: max. 1µA at TA = 0°C to + 40°C
(August, 2004, Version 1.2)
10
AMIC Technology, Corp.
LP62S1024B-I Series
Low VCC Data Retention Waveform (1) ( CE1 Controlled)
DATA RETENTION MODE
VCC
CE1
3.0V
3.0V
t
CDR
t
R
VDR ≥ 2V
V
IH
VIH
CE1
≥ VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE
VCC
CE2
3.0V
3.0V
t
CDR
t
R
VDR ≥ 2V
VIL
VIL
CE2
≤ 0.2V
(August, 2004, Version 1.2)
11
AMIC Technology, Corp.
LP62S1024B-I Series
Ordering Information
Part No.
Operating Current
Max. (mA)
Standby Current
Access Time (ns)
Package
Max. (µA)
LP62S1024BM-55LLI
LP62S1024BM-55LLIF
LP62S1024BV-55LLI
LP62S1024BV-55LLIF
LP62S1024BX-55LLI
LP62S1024BX-55LLIF
LP62S1024BU-55LLI
LP62S1024BU-55LLIF
LP62S1024BM-70LLI
LP62S1024BM-70LLIF
LP62S1024BV-70LLI
LP62S1024BV-70LLIF
LP62S1024BX-70LLI
LP62S1024BX-70LLIF
LP62S1024BU-70LLI
LP62S1024BU-70LLIF
32L SOP
32L Pb-Free SOP
32L TSOP
32L Pb-Free TSOP
32L TSSOP
55
30
5
32L Pb-Free TSSOP
36L CSP
36L Pb-Free CSP
32L SOP
32L Pb-Free SOP
32L TSOP
32L Pb-Free TSOP
32L TSSOP
70
30
5
32L Pb-Free TSSOP
36L CSP
36L Pb-Free CSP
(August, 2004, Version 1.2)
12
AMIC Technology, Corp.
LP62S1024B-I Series
Package Information
SOP (W.B.) 32L Outline Dimensions
unit: inches/mm
32
17
e
1
L
16
1
b
Detail F
e
1
D
L
E
e
s
y
See Detail F
Seating Plane
Symbol
Dimensions in inches
0.118 Max.
Dimensions in mm
3.00 Max.
A
A1
A2
b
0.004 Min.
0.10 Min.
0.106±0.005
0.016 +0.004
-0.002
2.69±0.13
0.41 +0.10
-0.05
c
0.008 +0.004
-0.002
0.20 +0.10
-0.05
D
E
e
0.805 Typ. (0.820 Max.)
0.445±0.010
0.050 ±0.006
20.45 Typ. (20.83 Max.)
11.30±0.25
1.27±0.15
e
1
0.525 NOM.
0.556±0.010
0.031±0.008
0.055±0.008
0.044 Max.
0.004 Max.
0° ~ 10°
13.34 NOM.
14.12±0.25
0.79±0.20
1.40±0.20
1.12 Max.
0.10 Max.
0° ~ 10°
HE
L
LE
S
y
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(August, 2004, Version 1.2)
13
AMIC Technology, Corp.
LP62S1024B-I Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
D
12.0°
GAUGE PLANE
θ
L
L
E
H
D
Detail "A"
Detail "A"
y
S
b
0.10(0.004)
M
Symbol
Dimensions in inches
Dimensions in mm
1.20 Max.
0.10±0.05
1.00±0.05
0.20±0.03
0.15±0.02
18.40±0.10
8.00±0.10
0.50 TYP.
20.00±0.20
0.50±0.10
0.80 TYP.
0.425 TYP.
0.10 Max.
0° ~ 6°
A
A1
A2
b
0.047 Max.
0.004±0.002
0.039±0.002
0.008±0.001
0.006±0.001
0.724±0.004
0.315±0.004
0.020 TYP.
0.787±0.007
0.020±0.004
0.031 TYP.
0.0167 TYP.
0.004 Max.
0° ~ 6°
c
D
E
e
HD
L
LE
S
Y
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(August, 2004, Version 1.2)
14
AMIC Technology, Corp.
LP62S1024B-I Series
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
12.0°
GAUGE PLANE
θ
L
L
E
D
1
D
Detail "A"
Detail "A"
0.10MM
S
b
SEATING PLANE
Symbol
Dimensions in inches
Dimensions in mm
1.25 Max.
0.05 Min.
A
A1
A2
b
0.049 Max.
0.002 Min.
0.039±0.002
0.008±0.001
0.006±0.0003
0.315±0.004
0.020 TYP.
0.528±0.008
0.465±0.004
0.02±0.008
0.0266 Min.
0.0109 TYP.
0.004 Max.
0° ~ 6°
1.00±0.05
0.20±0.03
0.15±0.008
8.00±0.10
0.50 TYP.
13.40±0.20
11.80±0.10
0.50±0.20
0.675 Min.
0.278 TYP.
0.10 Max.
0° ~ 6°
c
E
e
D
D1
L
LE
S
y
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(August, 2004, Version 1.2)
15
AMIC Technology, Corp.
LP62S1024B-I Series
Package Information
36LD CSP (6 x 8 mm) Outline Dimensions
unit: mm
TOP VIEW
BOTTOM VIEW
Ball#A1 CORNER
S
S
0.10
0.25
C
C A B
Ball*A1 CORNER
b (36X)
6
5 4 3 2 1
1
2 3 4 5 6
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
B
e
D1
A
SIDE VIEW
D
0.20(4X)
C
SEATING PLANE
Dimensions in mm
Symbol
MIN. NOM. MAX.
A
A1
A2
D
1.00
0.16
0.48
5.80
7.80
---
1.10
0.21
0.53
6.00
8.00
3.75
5.25
0.75
0.30
1.20
0.26
0.58
6.20
8.20
---
E
D1
E1
e
---
---
---
---
b
0.25
0.35
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS
OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
4. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE
SOLDER BALL AND THE BODY EDGE.
(August, 2004, Version 1.2)
16
AMIC Technology, Corp.
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