LP62S16256EU-70LLI [AMICC]
256K X 16 BIT LOW VOLTAGE CMOS SRAM; 256K x 16位的低电压CMOS SRAM
| 型号： | LP62S16256EU-70LLI |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 256K X 16 BIT LOW VOLTAGE CMOS SRAM |
| 文件： | 总15页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP62S16256E-I Series
256K X 16 BIT LOW VOLTAGE CMOS SRAM
Document Title
256K X 16 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
2.0
Change VCCmax from 3.3V to 3.6V
January 25, 2002
Add product family and 55ns specification
(January, 2002, Version 2.0)
AMIC Technology, Inc.
LP62S16256E-I Series
256K X 16 BIT LOW VOLTAGE CMOS SRAM
Features
General Description
n Operating voltage: 2.7V to 3.6V
n Access times: 55ns / 70ns (max.)
n Current:
The LP62S16256E-I is a low operating current 4,194,304-bit
static random access memory organized as 262,144 words
by 16 bits and operates on low power voltage from 2.7V to
Very low power version: Operating: 40mA (max.)
3.3V. It is built using AMIC's high performance CMOS
process.
Standby: 10mA (max.)
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output enable
input are included for easy interfacing.
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2.0V (min.)
n Available in 44-pin TSOP and 48-ball CSP (6×8mm)
packages
Data retention is guaranteed at a power supply voltage as
low as 2.0V.
Product Family
Power Dissipation
Package
Operating
Temperature
VCC
Range
Data Retention
(ICCDR, Typ.)
Standby
Operating
(ICC2, Typ.)
Product Family
Speed
Type
(ISB1, Typ.)
44L TSOP
48B CSP
LP62S16256E-I
2.7V~3.6V 55ns / 70ns
5mA
-40°C ~ +85°C
0.08mA
0.3mA
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configurations
n TSOP
n CSP (Chip Size Package)
48-pin Top View
A4
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A3
A2
A1
A0
CE
2
A6
1
2
3
4
5
6
3
A7
4
OE
A
B
C
D
E
F
LB
OE
A0
A1
A2
NC
5
HB
6
LB
I/O
9
HB
A3
A5
A4
A6
I/O
I/O
1
CE
I/O1
I/O2
I/O3
I/O4
7
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O12
I/O11
I/O10
8
I/O10
I/O11
I/O
I/O
I/O
I/O
2
3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC
GND
GND I/O12
A17
NC
A14
A12
A9
A7
4
5
6
VCC
GND
VCC
I/O15
I/O16
NC
I/O13
I/O14
NC
A16
A15
A13
A10
I/O5
I/O6
I/O7
I/O8
I/O
I/O
7
8
I/O
9
G
H
WE
A11
WE
A17
A16
A15
A14
A13
NC
A8
A8
NC
A9
A10
A11
A12
(January, 2002, Version 2.0)
1
AMIC Technology, Inc.
LP62S16256E-I Series
Block Diagram
VCC
GND
A0
512 X 8192
DECODER
MEMORY ARRAY
A16
A17
I/O1
I/O9
COLUMN I/O
INPUT
DATA
INPUT
DATA
CIRCUIT
CIRCUIT
I/O16
I/O8
CE
LB
HB
CONTROL
CIRCUIT
OE
WE
Pin Descriptions -- TSOP
Pin No.
Symbol
Description
1 - 5, 18 - 27,
42 - 44
A0 - A17
Address Inputs
6
Chip Enable Input
CE
7 - 10, 13 - 16,
29 - 32, 35 - 38
I/O1 - I/O16
Data Inputs/Outputs
Write Enable Input
17
39
40
41
WE
LB
Lower Byte Enable Input (I/O1 to I/O8)
Higher Byte Enable Input (I/O9 to I/O16)
Output Enable Input
HB
OE
VCC
GND
NC
11, 33
12, 34
28
Power
Ground
No Connection
(January, 2002, Version 2.0)
2
AMIC Technology, Inc.
LP62S16256E-I Series
Pin Description - CSP
Symbol
Description
Symbol
Description
A0 - A17
Address Inputs
Higher Byte Enable Input
(I/O9 - I/O16)
HB
Chip Enable
Output Enable
CE
OE
I/O1 - I/O16
Data Input/Output
Write Enable Input
VCC
GND
Power Supply
Ground
WE
LB
Byte Enable Input
(I/O1 - I/O8)
NC
No Connection
Recommended DC Operating Conditions
(TA = -40°C to + 85°C)
Symbol
VCC
GND
VIH
Parameter
Supply Voltage
Min.
Typ.
Max.
3.6
0
Unit
V
2.7
0
3
0
Ground
V
Input High Voltage
Input Low Voltage
Output Load
2.2
-0.3
-
-
-
-
-
VCC + 0.3
V
VIL
+0.6
30
1
V
CL
pF
-
TTL
Output Load
-
(January, 2002, Version 2.0)
3
AMIC Technology, Inc.
LP62S16256E-I Series
Absolute Maximum Ratings*
*Comments
VCC to GND ..............................................-0.5V to +4.0V
IN, IN/OUT Volt to GND................... -0.5V to VCC + 0.5V
Operating Temperature, Topr ...................-40°C to +85°C
Storage Temperature, Tstg.....................-55°C to +125°C
Power Dissipation, PT ...................................................................... 0.7W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -40°C to + 85°C, VCC = 2.7V to 3.6V, GND = 0V)
LP62S16256E-55LLI / 70LLI
Symbol
Parameter
Unit
Conditions
Min.
Typ.
Max.
Input Leakage Current
Output Leakage Current
-
-
1
VIN = GND to VCC
½ILI½
mA
mA
CE = VIH
-
1
½ILO½
HB = VIH or OE = VIH or
-
WE = VIH
VI/O = GND to VCC
ICC
Active Power Supply Current
Dynamic Operating Current
-
-
-
5
mA
mA
CE = VIL, II/O = 0mA
Min. Cycle, Duty = 100%
ICC1
25
40
CE = VI, II/O = 0mA
CE = VIL, VIH = VCC,
VIL = 0V, f = 1MHz,
II/O = 0 mA
ICC2
-
5
15
mA
mA
CE = VIH
VCC £ 3.3V
ISB
-
-
-
1
Standby Current
CE ³ VCC - 0.2V,
VCC £ 3.3V
VIN ³ 0V
ISB1
0.3
10
mA
VOL
VOH
Output Low Voltage
Output High Voltage
-
-
-
0.4
-
V
V
IOL = 2.1 mA
IOH = -1.0 mA
2.2
(January, 2002, Version 2.0)
4
AMIC Technology, Inc.
LP62S16256E-I Series
Truth Table
I/O1 to I/O8 Mode
I/O9 to I/O16 Mode
VCC Current
CE
H
OE
X
WE
X
LB
X
H
L
HB
X
H
L
Not selected
High - Z
Read
Not selected
High - Z
Read
ISB1, ISB
X
X
X
ISB1, ISB
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
L
L
L
H
L
L
H
L
Read
High - Z
Read
H
L
High - Z
Write
L
Write
X
L
H
L
Write
High - Z
Write
H
L
High - Z
High - Z
High - Z
L
L
H
H
H
H
X
L
High - Z
High - Z
X
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
6
8
CI/O*
Input/Output Capacitance
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
(January, 2002, Version 2.0)
5
AMIC Technology, Inc.
LP62S16256E-I Series
AC Characteristics (TA = -40°C to +85°C, VCC = 2.7V to 3.6V)
LP62S16256E-55LLI
LP62S16256E-70LLI
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
55
-
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
55
55
55
30
-
70
70
70
35
-
tACE
tBE
Chip Enable Access Time
-
-
Byte Enable Access Time
-
-
tOE
Output Enable to Output Valid
Chip Enable to Output in Low Z
Byte Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Byte Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
-
-
tCLZ
tBLZ
tOLZ
tCHZ
tBHZ
tOHZ
tOH
10
10
5
-
10
10
5
-
-
-
-
-
20
20
20
-
25
25
25
-
-
-
-
-
5
5
Write Cycle
tWC
Write Cycle Time
55
50
50
0
-
-
70
60
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Chip Enable to End of Write
Byte Enable to End of Write
Address Setup Time
tBW
-
-
tAS
-
-
tAW
Address Valid to End of Write
Write Pulse Width
50
40
0
-
60
50
0
-
tWP
-
-
tWR
Write Recovery Time
-
-
tWHZ
tDW
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
-
25
-
-
25
-
25
0
30
0
tDH
-
-
tOW
5
-
5
-
Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
(January, 2002, Version 2.0)
6
AMIC Technology, Inc.
LP62S16256E-I Series
Timing Waveforms
Read Cycle 1(1, 2, 4)
tRC
Address
tAA
tOH
tOH
DOUT
Read Cycle 2(1, 2, 3)
tRC
Address
tAA
CE
tACE
5
tCHZ
5
tCLZ
tBE
HB, LB
5
5
tBLZ
tBHZ
OE
5
tOE
tOHZ
5
tOLZ
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with CE and (HB and, or LB ) transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(January, 2002, Version 2.0)
7
AMIC Technology, Inc.
LP62S16256E-I Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
tWC
Address
3
tWR
tAW
tCW
CE
tBW
HB, LB
1
2
tAS
tWP
WE
tDH
tDW
DATA IN
4
tWHZ
tOW
DATA OUT
(January, 2002, Version 2.0)
8
AMIC Technology, Inc.
LP62S16256E-I Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
tAW
3
tWR
1
2
tAS
tCW
CE
tBW
HB, LB
tWP
WE
tDH
tDW
DATA IN
4
tWHZ
tOW
DATA OUT
(January, 2002, Version 2.0)
9
AMIC Technology, Inc.
LP62S16256E-I Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
tWC
Address
tAW
tCW
CE
3
tWR
1
2
tAS
tBW
HB, LB
tWP
WE
tDH
tDW
DATA IN
4
tWHZ
tOW
DATA OUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and (HB and , or LB ).
3. tWR is measured from the earliest of CE or WE or (HB and , or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(January, 2002, Version 2.0)
10
AMIC Technology, Inc.
LP62S16256E-I Series
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
5 ns
Input Rise And Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
See Figures 1 and 2
TTL
TTL
CL
CL
30pF
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = -40°C to 85°C)
Symbol
Parameter
Min.
Typ. Max.
Unit
Conditions
VDR
VCC for Data Retention
2.0
-
3.6
V
CE ³ VCC - 0.2V
VCC = 2.0V,
CE ³ VCC - 0.2V
VIN ³ 0V
ICCDR
Data Retention Current
-
0.08
3*
mA
tCDR
tR
Chip Disable to Data Retention Time
Operation Recovery Time
0
tRC
5
-
-
-
-
-
-
ns
ns
See Retention Waveform
tVR
VCC Rising Time from Data Retention
Voltage to Operating Voltage
ms
*
LP62S16256E-55LLI / 70LLI
ICCDR: max. 1mA at TA = 0°C to + 40°C
(January, 2002, Version 2.0)
11
AMIC Technology, Inc.
LP62S16256E-I Series
Low VCC Data Retention Waveform
DATA RETENTION MODE
2.7V
2.7V
VCC
tCDR
tR
VDR
³ 2.0V
tVR
VIH
CE
VIH
CE
³ VDR - 0.2V
Ordering Information
Part No.
Access Time (ns)
Operating Current
Standby Current
Package
Max. (mA)
Max. (mA)
LP62S16256EV-55LLI
LP62S16256EU-55LLI
LP62S16256EV-70LLI
LP62S16256EU-70LLI
40
40
40
40
10
10
10
10
44L TSOP
48L CSP
44L TSOP
48L CSP
55
70
(January, 2002, Version 2.0)
12
AMIC Technology, Inc.
LP62S16256E-I Series
Package Information
TSOP 44L TYPE II Outline Dimensions
unit: inches/mm
44
23
L
L1
1
22
D
L1
L
S
B
y
e
Dimension in inch
Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
A
A1
A2
B
-
-
-
0.047
-
-
-
1.20
-
0.002
0.05
-
0.037 0.039 0.041 0.95
0.010 0.014 0.018 0.25
1.00
0.35
0.15
1.05
0.45
-
c
-
0.006
-
-
D
E
0.721 0.725 0.729 18.31 18.41 18.51
0.396 0.400 0.404 10.06 10.16 10.26
e
-
0.031
-
-
0.80
-
HE
L
0.455 0.463 0.471 11.56 11.76 11.96
0.016 0.020 0.024 0.40
0.50
0.60
-
L1
S
-
-
0.031
-
-
-
0.80
-
-
-
0.036
0.004
5°
-
-
-
0.93
0.10
5°
y
-
-
q
0°
0°
Notes:
1. Dimension D&E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
(January, 2002, Version 2.0)
13
AMIC Technology, Inc.
LP62S16256E-I Series
Package Information
48LD CSP ( 6 x 8 mm ) Outline Dimensions
(48TFBGA)
unit: mm
TOP VIEW
BOTTOM VIEW
Ball#A1 CORNER
S
0.10
C
S
0.25 C A B
Ball*A1 CORNER
b (48X)
6
5 4 3 2 1
1
2 3 4 5 6
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
B
e
D
1
A
SIDE VIEW
D
0.20(4X)
C
SEATING PLANE
Dimensions in mm
Symbol
MIN. NOM. MAX.
A
A1
A2
D
1.04
0.20
0.48
5.90
7.90
---
1.14
0.25
0.53
6.00
8.00
3.75
5.25
0.75
0.35
1.24
0.30
0.58
6.10
8.10
---
E
D1
E1
e
---
---
---
---
b
0.30
0.40
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.
4. BALL PAD OPENING OF SUBSTRATE IS F 0.3mm (SMD)
SUGGEST TO DESIGN THE PCB LAND SIZE AS F 0.3mm (NSMD)
(January, 2002, Version 2.0)
14
AMIC Technology, Inc.
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