LP62S1664CU-70LLI [AMICC]
64K X 16 BIT LOW VOLTAGE CMOS SRAM; 64K x 16位的低电压CMOS SRAM
| 型号： | LP62S1664CU-70LLI |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 64K X 16 BIT LOW VOLTAGE CMOS SRAM |
| 文件： | 总15页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP62S1664C Series
Preliminary
64K X 16 BIT LOW VOLTAGE CMOS SRAM
Document Title
64K X 16 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
Initial issue
February 19, 2002
Preliminary
PRELIMINARY
(February, 2002, Version 0.0)
AMIC Technology, Inc.
LP62S1664C Series
Preliminary
64K X 16 BIT LOW VOLTAGE CMOS SRAM
Features
General Description
n Operating voltage: 2.7V to 3.6V
n Access times: 55/70 ns (max.)
n Current:
The LP62S1664C is a low operating current 1,048,576-
bit static random access memory organized as 65,536
words by 16 bits and operates on low power supply
voltage from 2.7V to 3.6V. It is built using AMIC’s high
LP62S1664C-55 series: Operating: 50mA (max.)
performance CMOS process.
Standby:
LP62S1664C-70 series: Operating: 40mA (max.)
Standby: 5mA (max.)
5mA (max.)
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
n Extended operating temperature range : -40°C to 85°C
for -LLI series
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 44-pin TSOP and 48-ball Mini BGA (6X8)
packages.
Product Family
Power Dissipation
Package
Operating
Temperature
VCC
Range
Product
Family
Speed
Data Retention
(ICCDR, Typ.)
Standby
Operating
(ICC2, Typ.)
Type
(ISB1, Typ.)
44L TSOP
48B MBGA
LP62S1664C
2.7V~3.6V 55ns / 70ns
3mA
-40°C ~ +85°C
0.2mA
0.3mA
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configuration
n TSOP (Type II)
n Mini BGA (6X8) Top View
1
2
3
4
5
6
A4
A3
1
2
3
4
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A
B
C
D
E
F
A0
A1
A2
NC
LB
OE
HB
A2
A7
A1
OE
I/O8
A3
A5
A4
A6
I/O0
I/O2
VCC
VSS
I/O6
I/O7
NC
CS
A0
5
HB
CE
6
LB
I/O9
VSS
VCC
I/O14
I/O15
NC
I/O10
I/O1
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
7
I/O15
I/O14
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
8
I/O11
I/O12
I/O13
NC
NC
NC
A14
A12
A9
A7
I/O3
I/O4
I/O5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
A15
A13
A10
G
H
WE
A8
A11
A8
A9
LP62S1664CU
A10
A11
NC
PRELIMINARY
(February, 2002, Version 0.0)
1
AMIC Technology, Inc.
LP62S1664C Series
Block Diagram
VCC
GND
A0
512 X 2048
DECODER
MEMORY ARRAY
A14
A15
I/O
0
I/O8
COLUMN I/O
INPUT
DATA
INPUT
DATA
CIRCUIT
CIRCUIT
I/O15
I/O
7
CE
LB
HB
CONTROL
CIRCUIT
OE
WE
PRELIMINARY (February, 2002, Version 0.0)
2
AMIC Technology, Inc.
LP62S1664C Series
Pin Description - TSOP
Pin No.
Symbol
A0 - A15
CE
Description
1 - 5, 18 - 21,
24 - 27,42 - 44
Address Inputs
6
Chip Enable Input
Data Input/Outputs
7 - 10, 13 - 16,
29 - 32, 35 - 38
I/O0 - I/O15
17
Write Enable Input
WE
LB
39
40
41
Byte Enable Input (I/O0 to I/O7)
Byte Enable Input (I/O8 to I/O15)
Output Enable Input
HB
OE
VCC
GND
NC
11, 33
12, 34
Power
Ground
22 , 23, 28
No Connection
Recommended DC Operating Conditions
(TA = -25°C to + 85°C for –LLT or -40°C to 85°C for -LLI)
Symbol
VCC
GND
VIH
Parameter
Supply Voltage
Min.
2.7
0
Typ.
Max.
Unit
V
3.0
3.6
Ground
0
-
0
V
Input High Voltage
Input Low Voltage
Output Load
2.2
-0.3
-
VCC + 0.3
V
VIL
-
+0.6
30
1
V
CL
-
pF
-
TTL
Output Load
-
-
PRELIMINARY (February, 2002, Version 0.0)
3
AMIC Technology, Inc.
LP62S1664C Series
Absolute Maximum Ratings*
*Comments
VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V
Operating Temperature, Topr . . . . . . . . -40°C to +85°C
Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . 260°C, 10 sec
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics
(TA = -25°C to + 85°C for -LLT or -40°C to + 85°C for -LLI, VCC = 2.7V to 3.6V, GND = 0V)
LP62S1664C-55LLT/LLI LP62S1664C-70LLT/LLI
Unit
Conditions
Symbol
Parameter
Min.
Max.
Min.
Max.
Input Leakage
Current
-
1
-
1
VIN = GND to VCC
½ILI½
mA
mA
CE = VIH or OE = VIH or
LB = HB = VIH or
Output Leakage
Current
-
1
-
1
½ILO½
WE = VIL
VI/O = GND to VCC
Active Power
Supply Current
CE = VIL, II/O = 0mA
ICC
-
-
5
-
-
5
mA
mA
Min. Cycle, Duty = 100%
ICC1
50
40
CE = VIL, II/O = 0mA
Dynamic
Operating
Current
CE = VIL, VIH = VCC,
VIL = 0V, f = 1MHz,
II/O = 0 mA
ICC2
-
5
-
5
mA
ISB
-
-
0.3
5
-
-
0.3
5
mA
CE = VIH
Standby Power
Supply Current
CE ³ VCC - 0.2V
VIN ³ 0V
ISB1
mA
Output Low
Voltage
VOL
VOH
-
0.4
-
-
0.4
-
V
V
IOL = 2.1mA
IOH = -1.0mA
Output High
Voltage
2.2
2.2
PRELIMINARY (February, 2002, Version 0.0)
4
AMIC Technology, Inc.
LP62S1664C Series
Truth Table
I/O0 to I/O7 Mode
I/O8 to I/O15 Mode
VCC Current
CE
OE
WE
LB
X
L
HB
X
L
H
X
X
Not selected
Read
Not selected
Read
ISB1, ISB
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ISB1, ISB
L
L
L
H
L
L
H
L
Read
High - Z
Read
H
L
High - Z
Write
L
Write
X
L
H
L
Write
Not Write/Hi - Z
Write
H
L
Not Write/Hi - Z
High - Z
High - Z
Not selected
X
L
High - Z
High - Z
Not selected
L
H
X
H
X
X
H
X
H
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
-
-
6
8
CI/O*
Input/Output Capacitance
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
PRELIMINARY
(February, 2002, Version 0.0)
5
AMIC Technology, Inc.
LP62S1664C Series
AC Characteristics (TA = -25°C to +85°C for -LLT or -40°C to +85°C for -LLI, VCC = 2.7V to 3.6V)
LP62S1664C-55LLT/LLI LP62S1664C-70LLT/LLI
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
55
-
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
55
55
55
30
-
70
70
70
35
-
tACE
tBE
Chip Enable Access Time
-
-
Byte Enable Access Time
-
-
tOE
Output Enable to Output Valid
Chip Enable to Output in Low Z
Byte Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Byte Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
-
-
tCLZ
tBLZ
tOLZ
tCHZ
tBHZ
tOHZ
tOH
10
5
5
-
10
5
5
-
-
-
-
-
20
20
20
-
25
25
25
-
-
-
-
-
5
10
Write Cycle
tWC
Write Cycle Time
55
50
50
0
-
-
70
60
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Chip Enable to End of Write
Byte Enable to End of Write
Address Setup Time
tBW
-
-
tAS
-
-
tAW
Address Valid to End of Write
Write Pulse Width
50
40
0
-
60
50
0
-
tWP
-
-
tWR
Write Recovery Time
-
-
tWHZ
tDW
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
-
25
-
-
30
-
25
0
30
0
tDH
-
-
tOW
5
-
5
-
Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
PRELIMINARY
(February, 2002, Version 0.0)
6
AMIC Technology, Inc.
LP62S1664C Series
Timing Waveforms
Read Cycle 1(1, 2, 4)
tRC
Address
tAA
tOH
tOH
DOUT
Read Cycle 2(1, 2, 3)
tRC
Address
tAA
CE
tACE
5
tCHZ
5
tCLZ
tBE
HB, LB
5
5
tBLZ
tBHZ
OE
5
tOE
tOHZ
5
tOLZ
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with CE and (HB and, or LB ) transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
(February, 2002, Version 0.0)
7
AMIC Technology, Inc.
LP62S1664C Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
tWC
Address
3
tWR
tAW
tCW
CE
tBW
HB, LB
1
2
tAS
tWP
WE
tDH
tDW
DATA IN
4
tWHZ
tOW
DATA OUT
PRELIMINARY
(February, 2002, Version 0.0)
8
AMIC Technology, Inc.
LP62S1664C Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
tAW
3
tWR
1
2
tAS
tCW
CE
tBW
HB, LB
tWP
WE
tDH
tDW
DATA IN
4
tWHZ
tOW
DATA OUT
PRELIMINARY
(February, 2002, Version 0.0)
9
AMIC Technology, Inc.
LP62S1664C Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
tWC
Address
tAW
tCW
CE
3
tWR
1
2
tAS
tBW
HB, LB
tWP
WE
tDH
tDW
DATA IN
4
tWHZ
tOW
DATA OUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and (HB and, or LB ).
3. tWR is measured from the earliest of CE or WE or (HB and, or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
(February, 2002, Version 0.0)
10
AMIC Technology, Inc.
LP62S1664C Series
AC Test Conditions
Input Pulse Levels
0V to 2.4V
5 ns
Input Rise And Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
See Figures 1 and 2
TTL
TTL
CL
CL
30pF
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = -25°C to 85°C for –LLT or -40°C to 85°C for -LLI)
Symbol
Parameter
VCC for Data Retention
Min.
Max.
Unit
Conditions
VDR
2.0
3.6
V
CE ³ VCC - 0.2V
VCC = 2.0V,
mA
ICCDR
Data Retention Current
-
3*
CE ³ VCC - 0.2V
VIN ³ 0V
tCDR
tR
Chip Disable to Data Retention Time
Operation Recovery Time
0
tRC
5
-
-
-
ns
ns
See Retention Waveform
tVR
VCC Rise Time from Data Retention
Voltage to Operating Voltage
ms
*
LP62S1664C-55/70(LLT/LLI)
ICCDR: max. 1mA at TA = 0°C to + 40°C
PRELIMINARY
(February, 2002, Version 0.0)
11
AMIC Technology, Inc.
LP62S1664C Series
Low VCC Data Retention Waveform
DATA RETENTION MODE
VCC
CE
2.7V
2.7V
tCDR
tR
VDR
³ 2V
tVR
VIH
VIH
CE
³ VDR - 0.2V
Ordering Information
Part No.
Operating Current
Standby Current
Access Time (ns)
Package
Max. (mA)
Max. (mA)
LP62S1664CV-55LLT
LP62S1664CV-55LLI
LP62S1664CU-55LLT
LP62S1664CU-55LLI
LP62S1664CV-70LLT
LP62S1664CV-70LLI
LP62S1664CU-70LLT
LP62S1664CU-70LLI
44L TSOP
44L TSOP
55
50
5
48B Mini BGA
48B Mini BGA
44L TSOP
44L TSOP
70
40
5
48B Mini BGA
48B Mini BGA
LLT : for -25°C ~ 85°C
LLI : for -40°C ~ 85°C
PRELIMINARY
(February, 2002, Version 0.0)
12
AMIC Technology, Inc.
LP62S1664C Series
Package Information
TSOP 44L (Type II) Outline Dimensions
unit: inches/mm
44
q
L
L1
1
D
L
L1
b
e
y
ZD
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
Min
Nom
Max
A
A1
A2
b
-
0.047
0.006
0.041
0.018
0.008
0.730
-
-
1.20
0.15
1.05
0.45
0.21
0.002
0.037
0.012
0.005
0.720
-
0.05
0.95
0.30
0.12
18.28
-
0.039
1.00
-
-
-
-
c
D
ZD
E
0.725
0.032 REF
0.463
0.400
0.023
0.031 REF
0.031 BSC
-
18.41
0.805 REF
11.76
10.16
0.59
18.54
0.455
0.395
0.019
0.471
0.405
0.027
11.56
10.03
0.49
11.96
10.29
0.69
E1
L
L1
e
0.80 REF
0.80 BSC
-
y
-
0.004
5°
-
0.10
5°
0°
-
0°
-
q
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension ZD includes end flash.
PRELIMINARY
(February, 2002, Version 0.0)
13
AMIC Technology, Inc.
LP62S1664C Series
Package Information
Mini BGA 6X8 (48 BALLS) Outline Dimensions
unit : millimeter(mm)
Bottom View
Pin A1 Index
Top View
Pin A1 Index
6
5
4
3 2 1
A
B
C
D
E
F
G
H
A
B
Diameter D
Solder Ball
B1
D
Symbol
Min
Typ
0.75
6.00
3.75
8.00
5.25
0.35
1.10
0.36
0.25
Max
A
B
-
-
5.90
6.10
B1
C
-
-
7.90
8.10
C1
D
-
0.30
1.00
-
-
0.40
1.20
-
E
E1
E2
-
-
PRELIMINARY
(February, 2002, Version 0.0)
14
AMIC Technology, Inc.
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