LP62S4096EXR-70LLI [AMICC]
Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, TSSOP1-32;
| 型号： | LP62S4096EXR-70LLI |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, TSSOP1-32 静态存储器 光电二极管 |
| 文件： | 总16页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP62S4096E-I Series
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Document Title
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
2.0
Change VCCmax from 3.3V to 3.6V
January 25, 2002
Final
Add product family and 55ns specification
Add product family and 32-pin TSSOP reverse type package
Add Pb-Free package type
3.0
3.1
3.2
April 16, 2003
August 9, 2004
March 13, 2006
Delete Tbias absolute maximum ratings
(March, 2006, Version 3.2)
AMIC Technology, Corp.
LP62S4096E-I Series
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
General Description
Power supply range: 2.7V to 3.6V
Access times: 55ns / 70ns (max.)
Current:
The LP62S4096E-I is a low operating current 4,194,304-bit
static random access memory organized as 524,288 words
by 8 bits and operates on a low power supply range: 2.7V to
3.3V. It is built using AMIC's high performance CMOS
process.
Very low power version: Operating: 30mA (max.)
Standby:
10µA (max.)
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and
device enable and an output enable input is included for
easy interfacing.
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Data retention voltage: 2V (min.)
Available in 32-pin TSOP/TSSOP 36-ball CSP package
Data retention is guaranteed at a power supply voltage as
low as 2V.
CE2 pin for CSP package only
Product Family
Power Dissipation
Operating
Temperature
VCC
Range
Product Family
Speed
Package Type
Data
Standby
(ISB1, Typ.)
Operating
(ICC2, Typ.)
Retention
(ICCDR, Typ.)
32L TSOP
32L TSSOP
(Forward type)
32L TSSOP
(Reverse type)
36B CSP
LP62S4096E-I
2.7V~3.6V
55ns /
70ns
5mA
-40°C ~ +85°C
0.08µA
0.3µA
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
(March, 2006, Version 3.2)
1
AMIC Technology, Corp.
LP62S4096E-I Series
Pin Configurations
TSOP/(TSSOP)
(forward type)
TSSOP
(reverse type)
CSP (Chip Size Package)
36-pin Top View
16
1
1
16
1
2
3
4
5
6
A8
A0
A1
A2
CE2
WE
A3
A4
A6
A7
A
B
I/O
I/O
5
I/O
I/O
1
C
D
E
F
6
NC
A5
2
GND
VCC
VCC
GND
I/O
I/O
7
A18
CE1
A11
A17
A16
A12
I/O
I/O
3
4
G
H
8
OE
A15
A13
A9
A10
A14
17
32
32
17
Pin No.
1
2
3
4
5
6
7
8
9
10
A16
26
11
A14
27
12
A12
28
13
A7
29
14
15
A5
16
A4
32
Pin
Name
A11
17
A9
18
A2
A8
19
A1
A13
20
WE
21
A17
22
A15
23
VCC
24
A18
25
A6
30
Pin No.
31
Pin
Name
I/O
3
I/O8
A3
A0
I/O
1
I/O
2
GND
I/O
4
I/O5
I/O6
I/O7
CE1
A10
OE
Block Diagram
A0
VCC
GND
ROW
1024 X 4096
A16
A17
A18
DECODER
MEMORY ARRAY
I/O
1
COLUMN I/O
INPUT DATA
CIRCUIT
I/O
8
CE1
CE2
OE
CONTROL
CIRCUIT
WE
(March, 2006, Version 3.2)
2
AMIC Technology, Corp.
LP62S4096E-I Series
Pin Description
Symbol
Recommended DC Operating Conditions
(TA = -40°C to + 85°C)
Description
Address Inputs
Symbol
VCC
Parameter
Min. Typ.
Max.
3.6
0
Unit
V
A0 - A18
I/O1 - I/O8
GND
Supply Voltage
Ground
2.7
0
3.0
0
Data Input/Outputs
Ground
GND
V
VCC +
0.3
VIH
Input High Voltage
2.2
-
V
Chip Enable
CE1, CE2
OE
VIL
CL
Input Low Voltage
Output Load
-0.3
0
-
+0.6
30
1
V
pF
-
Output Enable
Write Enable
Power Supply
-
-
WE
TTL
Output Load
-
VCC
(March, 2006, Version 3.2)
3
AMIC Technology, Corp.
LP62S4096E-I Series
Absolute Maximum Ratings*
*Comments
VCC to GND ------------------------------------- -0.5V to + 4.0V
IN, IN/OUT Volt to GND--------------- -0.5V to VCC + 0.5V
Operating Temperature, Topr -------------- -40°C to + 85°C
Storage Temperature, Tstg --------------- -55°C to + 125°C
Power Dissipation, PT---------------------------------------- 0.7W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics (TA = -40°C to + 85°C, VCC = 2.7V to 3.6V, GND = 0V)
LP62S4096E-55LLI / 70LLI
Symbol
Parameter
Unit
Conditions
Min.
Typ.
Max.
Input Leakage Current
Output Leakage Current
-
-
1
VIN = GND to VCC
⎜ILI⎥
µA
µA
CE1= VIH , CE2= VIL or
-
1
⎜ILO⎥
-
OE = VIH WE =VIL
VI/O = GND to VCC
ICC
Active Power Supply Current
Dynamic Operating Current
-
-
-
5
mA
mA
CE1= VIL, CE2= VIH II/O = 0mA
Min. Cycle, Duty = 100%,
ICC1
20
30
CE1 = VIL CE2= VIH, II/O = 0mA
CE1= VIL, CE2= VIH, VIH = VCC
VIL = 0V, f = 1MHZ
II/O = 0mA
ICC2
Dynamic Operating Current
-
mA
5
15
VCC ≤ 3.3V
CE1= VIH, CE2= VIL
ISB
Standby Power
Supply Current
-
-
-
1
mA
VCC ≤ 3.3V
CE1≥ VCC - 0.2V, or CE2 ≤ 0.2V
VIN ≤ 0.2V
ISB1
0.3
10
µA
VOL
VOH
Output Low Voltage
Output High Voltage
-
-
-
0.4
-
V
V
IOL = 2.1mA
IOH = -1.0mA
2.2
(March, 2006, Version 3.2)
4
AMIC Technology, Corp.
LP62S4096E-I Series
Truth Table
Mode
I/O Operation
Supply Current
CE1
CE2
OE
X
WE
X
Standby
Standby
H
X
L
L
L
X
L
High Z
High Z
High Z
DOUT
ISB, ISB1
X
X
ISB, ISB1
Output Disable
H
H
H
H
H
ICC, ICC1, ICC2
ICC, ICC1, ICC2
ICC, ICC1, ICC2
Read
Write
L
H
X
L
DIN
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
6
8
CI/O*
Input/Output Capacitance
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = -40°C to + 85°C, VCC = 2.7V to 3.6V)
Symbol
Parameter
LP62S4096E-55LLI LP62S4096E-70LLI
Unit
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
55
-
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
55
55
30
-
70
70
35
-
tACE1, tACE2
tOE
Chip Enable Access Time
-
-
Output Enable to Output Valid
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
-
-
tCLZ1, tCLZ2
tOLZ
10
5
0
0
5
10
5
0
0
5
-
-
tCHZ1, tCHZ2
tOHZ
20
20
-
25
25
-
tOH
(March, 2006, Version 3.2)
5
AMIC Technology, Corp.
LP62S4096E-I Series
AC Characteristics (continued)
LP62S4096E-55LLI
LP62S4096E-70LLI
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
Write Cycle
tWC
Write Cycle Time
55
50
0
-
-
70
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW1
tAS
Chip Enable to End of Write
Address Setup Time
-
-
tAW
Address Valid to End of Write
Write Pulse Width
50
40
0
-
60
50
0
-
tWP
-
-
tWR
Write Recovery Time
-
-
tWHZ
tDW
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
25
-
0
25
-
25
0
30
0
tDH
-
-
tOW
5
-
5
-
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
Timing Waveforms
Read Cycle 1(1)
t
RC
Address
t
AA
OE
t
OE
tOH
CE1
5
OLZ
t
CE2
5
t
OHZ
t
ACE1 , tACE2
t
CHZ1 , CHZ2
t
t
CLZ1 , tCLZ2
D
OUT
(March, 2006, Version 3.2)
6
AMIC Technology, Corp.
LP62S4096E-I Series
Timing Waveforms (continued)
Read Cycle 2 (1, 2, 4)
t
RC
Address
t
AA
t
OH
t
OH
D
OUT
Read Cycle 3 (1, 3, 4)
CS1
CS2
t
ACS1 , tACS2
t
CLZ1 , tCLZ2
t
CHZ1 , tCHZ2
D
OUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, CE1 = VIL or CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low or CE2 transition high.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(March, 2006, Version 3.2)
7
AMIC Technology, Corp.
LP62S4096E-I Series
Timing Waveforms (continued)
Write Cycle 1(6)
(Write Enable Controlled)
tWC
Address
CE1
tAW
3
tWR
tcw1 ,tcw2
(4)
CE2
1
2
tAS
tWP
WE
tDW
tDH
7
tWHZ
DIN
7
tOW
DOUT
Write Cycle 2(6)
(Chip Enable Controlled)
tWC
Address
tAW
3
1
tCW1 , tCW2
tAS
tWR
CE1
(4)
CE2
2
tWP
WE
tDW
tDH
DIN
7
tWHZ
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1 or high CE2 , and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low WE going high to the end of the Write cycle.
4. If the CE1 low or CE2 high transition occurs simultaneously with the WE low transition or after the WE transition ,
outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE level is high or low.
7. Transition is measured ± 500mV from steady state. This parameter is sampled and not 100% tested.
(March, 2006, Version 3.2)
8
AMIC Technology, Corp.
LP62S4096E-I Series
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
5 ns
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
See Figures 1 and 2
TTL
TTL
C
L
C
L
30pF
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ,
tOHZ, tOL, tCHZ, tWHZ, and tOW
Data Retention Characteristics (TA = -40°C to 85°C)
Symbol
Parameter
VCC for Data Retention
Min. Typ. Max. Unit
Conditions
VDR
2.0
-
3.6
V
CE1≥ VCC - 0.2V, or
CE2 ≤ 0.2V
VCC = 2.0V,
CE1≥ VCC - 0.2V, or
CE2 ≤ 0.2V
ICCDR
Data Retention Current
LL-Version
-
0.08
3*
µA
VIN ≤ 0V
tCDR
tR
Chip Disable to Data Retention Time
Operation Recovery Time
0
tRC
5
-
-
-
-
-
-
ns
ns
See Retention Waveform
tVR
VCC Rising Time from Data Retention Voltage to
Operating Voltage
ms
*
LP62S4096E-55LLI / 70LLI
ICCDR: max. 1µA at TA = 0°C to + 40°C
(March, 2006, Version 3.2)
9
AMIC Technology, Corp.
LP62S4096E-I Series
Low VCC Data Retention Waveform (1) (
Controlled)
CE1
DATA RETENTION MODE
VCC
CE1
2.7V
2.7V
t
CDR
tR
V
DR
≥ 2V
t
VR
V
IH
V
IH
CE1
≥ VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE
VCC
CE2
2.7V
2.7V
t
CDR
t
R
VDR ≥ 2V
t
VR
VIL
VIL
CE2 ≤ 0.2V
(March, 2006, Version 3.2)
10
AMIC Technology, Corp.
LP62S4096E-I Series
Ordering Information
Part No.
Access Time Operating Current Standby Current
Package
(ns)
Max.(mA)
Max.(uA)
LP62S4096EV-55LLI
LP62S4096EV-55LLIF
LP62S4096EX-55LLI
LP62S4096EX-55LLIF
LP62S4096EXR-55LLI
LP62S4096EXR-55LLIF
LP62S4096EU-55LLI
LP62S4096EU-55LLIF
LP62S4096EV-70LLI
LP62S4096EV-70LLIF
LP62S4096EX-70LLI
LP62S4096EX-70LLIF
LP62S4096EXR-70LLI
LP62S4096EXR-70LLIF
LP62S4096EU-70LLI
LP62S4096EU-70LLIF
32L TSOP
32L Pb-Free TSOP
32L TSSOP (Forward)
32L Pb-Free TSSOP (Forward)
32L TSSOP (Reverse)
32L Pb-Free TSSOP (Reverse)
36L CSP
55
30
10
36L Pb-Free CSP
32L TSOP
32L Pb-Free TSOP
32L TSSOP (Forward)
32L Pb-Free TSSOP (Forward)
32L TSSOP (Reverse)
32L Pb-Free TSSOP (Reverse)
36L CSP
70
30
10
36LPb-Free CSP
(March, 2006, Version 3.2)
11
AMIC Technology, Corp.
LP62S4096E-I Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
D
12.0
°
GAUGE PLANE
θ
L
L
E
H
D
Detail "A"
Detail "A"
y
S
b
0.10(0.004)
M
Symbol
Dimensions in inches
Dimensions in mm
1.20 Max.
0.10±0.05
1.00±0.05
0.20±0.03
0.15±0.02
18.40±0.10
8.00±0.10
0.50 TYP.
20.00±0.20
0.50±0.10
0.80 TYP.
0.425 TYP.
0.10 Max.
0° ~ 6°
A
A1
A2
b
0.047 Max.
0.004±0.002
0.039±0.002
0.008±0.001
0.006±0.001
0.724±0.004
0.315±0.004
0.020 TYP.
0.787±0.007
0.020±0.004
0.031 TYP.
0.0167 TYP.
0.004 Max.
0° ~ 6°
c
D
E
e
HD
L
LE
S
Y
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(March, 2006, Version 3.2)
12
AMIC Technology, Corp.
LP62S4096E-I Series
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions (Forward Type)
unit: inches/mm
1
32
12.0°
GAUGE PLANE
θ
L
16
17
L
E
D
1
D
Detail "A"
Detail "A"
0.10MM
S
b
SEATING PLANE
Symbol
Dimensions in inches
0.049 Max.
Dimensions in mm
1.25 Max.
0.05 Min.
A
A1
A2
b
0.002 Min.
0.039±0.002
0.008±0.001
0.006±0.0003
0.315±0.004
0.020 TYP.
1.00±0.05
0.20±0.03
0.15±0.008
8.00±0.10
0.50 TYP.
13.40±0.20
11.80±0.10
0.50±0.20
0.675 Min.
0.278 TYP.
0.10 Max.
0° ~ 6°
c
E
e
D
D1
L
0.528±0.008
0.465±0.004
0.02±0.008
LE
S
0.0266 Min.
0.0109 TYP.
0.004 Max.
y
θ
0° ~ 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(March, 2006, Version 3.2)
13
AMIC Technology, Corp.
LP62S4096E-I Series
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions (Reverse Type)
unit: inches/mm
L
E
1
32
L
θ
GAUGE PLANE
12.0°
16
17
Detail "A"
D
1
D
Detail "A"
S
b
SEATING PLANE
0.10MM
Symbol
Dimensions in inches
0.049 Max.
Dimensions in mm
A
A1
A2
b
1.25 Max.
0.05 Min.
1.00±0.05
0.20±0.03
0.15±0.008
8.00±0.10
0.50 TYP.
13.40±0.20
11.80±0.10
0.50±0.20
0.675 Min.
0.278 TYP.
0.10 Max.
0° ~ 6°
0.002 Min.
0.039±0.002
0.008±0.001
0.006±0.0003
0.315±0.004
0.020 TYP.
c
E
e
D
D1
L
0.528±0.008
0.465±0.004
0.02±0.008
LE
S
0.0266 Min.
0.0109 TYP.
0.004 Max.
y
θ
0° ~ 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(March, 2006, Version 3.2)
14
AMIC Technology, Corp.
LP62S4096E-I Series
Package Information
36LD CSP (6 x 8 mm) Outline Dimensions
unit: mm
TOP VIEW
BOTTOM VIEW
Ball#A1 CORNER
S
S
0.10
0.25
C
C A B
Ball*A1 CORNER
b (36X)
6
5 4 3 2 1
1
2 3 4 5 6
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
B
e
D1
A
SIDE VIEW
D
0.20(4X)
C
SEATING PLANE
Dimensions in mm
Symbol
MIN. NOM. MAX.
A
A1
A2
D
1.00
0.16
0.48
5.80
7.80
---
1.10
0.21
0.53
6.00
8.00
3.75
5.25
0.75
0.30
1.20
0.26
0.58
6.20
8.20
---
E
D1
E1
e
---
---
---
---
b
0.25
0.35
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS
OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE
SOLDER BALL AND THE BODY EDGE.
4. BALL PAD OPENING OF SUBSTRATE IS Φ 0.25mm (SMD)
SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.25mm (NSMD)
(March, 2006, Version 3.2)
15
AMIC Technology, Corp.
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