13715-201 [AMI]
Clock Generator, 300MHz, CMOS, PDSO16, 5.30 MM, SSOP-16;
| 型号： | 13715-201 |
| 厂家： | 
AMI SEMICONDUCTOR |
| 描述： | Clock Generator, 300MHz, CMOS, PDSO16, 5.30 MM, SSOP-16 光电二极管 |
| 文件： | 总15页 (文件大小：1031K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
1.0 Features
2.0 Description
• Extremely flexible and low-jitter phase-locked loop (PLL)
frequency synthesis
The FS7140 / FS7145 is a monolithic CMOS clock gen-
erator/regenerator IC designed to minimize cost and
component count in a variety of electronic systems. Via the I2C-
bus interface, the FS714x can be adapted to many clock
generation requirements.
• No external loop filter components needed
• 150MHz CMOS or 340MHz PECL outputs
• Completely configurable via I2C™-bus
• Up to four FS7140 or FS7145 can be used on a single
I2C-bus
• 3.3V operation
• Independent on-chip crystal oscillator and external
reference input
The length of the reference and feedback dividers, their fine
granularity, and the flexibility of the post divider make the
FS714x the most flexible stand-alone phase-locked loop (PLL)
clock generator available.
• Very low "cumulative" jitter
3.0 Applications
SCL
SDA
1
2
3
4
5
6
7
8
16 CLKN
15 CLKP
14 VDD
SCL
SDA
1
2
3
4
5
6
7
8
16 CLKN
15 CLKP
• Precision frequency synthesis
• Low-frequency clock multiplication
• Video line-locked clock generation
• Laser beam printers (FS7145)
ADDR0
VSS
14
ADDR0
VSS
VDD
13
13
n/c
SYNC
XIN
12 REF
11 VSS
10 n/c
XIN
12 REF
11 VSS
10 n/c
XOUT
ADDR1
VDD
XOUT
ADDR1
VDD
9
9
IPRG
IPRG
Figure 1: Pin Configuration:
16-pin (0.150”) SOIC, 16-pin (5.3mm) SSOP
Sync
SYNC
Control
(FS7145 only)
IPRG
XIN
Loop
Filter
Crystal
Oscillator
XOUT
REF
UP
Reference
Divider
(NR)
CLKP
CLKN
Phase-
Frequency
Detector
Voltage
Controlled
Oscillator
Post
Divider
(NPx)
Charge
Pump
DOWN
CMOS/PECL
Output
ADDR[1:0]
Feedback
Divider (NF)
SCL
SDA
I2C
Interface
Registers
FS7140 / FS7145
Figure 2: Device Block Diagram
AMI Semiconductor
www.amis.com
1
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 1: FS7140 Pin Descriptions
Pin
1
Type
DI
Name
SCL
Description
Serial Interface Clock (requires an external pull-up)
Serial Interface Data Input/Output (requires an external pull-up)
Address Select Bit "0"
Ground
2
DIO
SDA
D
DI
3
ADDR0
VSS
4
P
AI
5
XIN
Crystal Oscillator Feedback
Crystal Oscillator Drive
Address Select Bit "1"
Power Supply (+3.3V nominal)
PECL Current Drive Programming
No Connection
6
AO
XOUT
ADDR1
VDD
IPRG
n/c
D
DI
7
8
P
AI
-
9
10
11
12
13
14
15
16
P
DIU
VSS
Ground
REF
Reference Frequency Input
No Connection
-
n/c
P
VDD
CLKP
CLKN
Power Supply (+3.3V nominal)
Clock Output
DO
DO
Inverted Clock Output
D
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DI = Input with Internal Pull-Down; DIO = Digital Input/Output;
DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
Table 2: FS7145 Pin Descriptions
Pin
1
Type
DI
Name
SCL
Description
Serial Interface Clock (requires an external pull-up)
Serial Interface Data Input/Output (requires an external pull-up)
Address Select Bit "0"
2
DIO
SDA
D
DI
3
ADDR0
VSS
4
P
AI
Ground
5
XIN
Crystal Oscillator Feedback
Crystal Oscillator Drive
6
AO
XOUT
ADDR1
VDD
D
DI
7
Address Select Bit "1"
8
P
AI
Power Supply (+3.3V nominal)
PECL Current Drive Programming
No Connection
9
IPRG
n/c
10
11
12
13
14
15
16
-
P
VSS
Ground
DIU
DIU
P
REF
Reference Frequency Input
Synchronization Input
SYNC
VDD
Power Supply (+3.3V nominal)
Clock Output
DO
DO
CLKP
CLKN
Inverted Clock Output
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DI = Input with Internal Pull-Down; DIO = Digital Input/Output;
DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
D
AMI Semiconductor
www.amis.com
2
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
modulus. Selected moduli below 12 are also permitted.
Moduli of: 4, 5, 8, 9, and 10 are also allowed (4 and 5 are not
available on date codes prior to 0108).
4.0 Functional Block Description
4.1 Phase Locked Loop (PLL)
The phase locked loop is a standard phase- and frequency-
locked loop architecture. The PLL consists of a reference
divider, a phase-frequency detector (PFD), a charge pump, an
internal loop filter, a voltage-controlled oscillator (VCO), a
feedback divider, and a post divider.
4.1.3 Post Divider
The post divider consists of three individually programmable
dividers, as shown in Figure 3.
The reference frequency (generated by either the on-board
crystal oscillator or an external frequency source), is first
reduced by the Reference Divider. The integer value that the
frequency is divided by is called the modulus and is denoted as
NR for the reference divider. This divided reference is then fed
into the PFD.
POST1[3:0]
POST2[3:0]
POST3[1:0]
Post
Divider 1
Post
Divider 2
Post
Divider 3
(NP3)
f
fCLK
VCO
(NP1
)
(NP2
)
POST DIVIDER (N
)
Px
The VCO frequency is fed back to the PFD through the
feedback divider (the modulus is denoted by NF).
Figure 3: Post Divider
The PFD will drive the VCO up or down in frequency until the
divided reference frequency and the divided VCO frequency
appearing at the inputs of the PFD are equal. The input/output
relationship between the reference frequency and the VCO
frequency is then:
P1
P2
The moduli of the individual dividers are denoted as N , N
P3
Px
and N , and together they make up the array modulus N .
NPx = NP × NP × NP
1
2
3
The post divider performs several useful functions. First, it
allows the VCO to be operated in a narrower range of speeds
compared to the variety of output clock speeds that the device
is required to generate. Second, the extra integer in the
denominator permits more flexibility in the programming of the
loop for many applications where frequencies must be
achieved exactly.
fVCO
NF
fREF
NR
=
This basic PLL equation can be rewritten as
NF
NR
fVCO
= fREF
A post-divider (actually a series combination of three post
dividers) follows the PLL and the final equation for device
output frequency is:
Note that a nominal 50/50 duty factor is always preserved
(even for selections which have an odd modulus).
See Table 8 for additional information.
NF
1
fCLK = fREF
NR NPx
4.1.4 Crystal Oscillator
The FS7140 is equipped with a Pierce-type crystal oscillator.
The crystal is operated in parallel resonant mode. Internal
load capacitance is provided for the crystal. While a
recommended load capacitance for the crystal is specified,
crystals for other standard load capacitances may be used if
great precision of the reference frequency (100ppm or less) is
not required.
4.1.1 Reference Divider
The reference divider is designed for low phase jitter. The
divider accepts the output of either the crystal oscillator circuit
or an external reference frequency. The reference divider is a
12 bit divider, and can be programmed for any modulus from 1
to 4095 (divide by 1 not available on date codes prior to 0108).
4.1.5 Reference Divider Source MUX
4.1.2 Feedback Divider
The source of frequency for the reference divider can be
chosen to be the device crystal oscillator or the REF pin by the
REFDSRC bit.
The feedback divider is based on a dual-modulus divider (also
called dual-modulus prescaler) technique. It permits division
by any integer value between 12 and 16383. Simply program
the FBKDIV register with the binary equivalent of the desired
When not using the crystal oscillator, it is preferred to connect
AMI Semiconductor
www.amis.com
3
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
IN
SS
OUT
X to V . Do not connect to X
.
Then:
When not using the REF input, it is preferred to leave it floating
R1 (from CLKP and CLKN output to VDD) =
DD
LOAD
DD
HI
or connected to V .
R
* V / V =
75 * 3.3 / 2.4 =
103 ohms
4.1.6 Feedback Divider Source MUX
The source of frequency for the feedback divider may be
selected to be either the output of the post divider or the output
of the VCO by the FBKDSRC bit.
R2 (from CLKP and CLKN output to GND) =
LOAD
DD
DD
HI
R
* V / (V - V ) =
75 * 3.3 / (3.3 - 2.4) =
275 ohms
Ordinarily, for frequency synthesis, the output of the VCO is
used. Use the output of the post divider only where a
deterministic phase relationship between the output clock and
reference clock are desired (line-locked mode, for example).
Rprgm (from VDD to IPRG pin) =
DD
LOAD
HI
LO
26 * (V * R ) / (V - V ) / 3 =
26 * (3.3 * 75) / (2.4 - 1.6) / 3 =
2.68 Kohms
4.1.7 Device Shutdown
Two bits are provided to effect shutdown of the device if
desired, when it is not active. SHUT1 disables most externally
4.3 SYNC Circuitry
observable device functions.
quiescent current to absolute minimum values. Normally, both
bits should be set or cleared together.
SHUT2 reduces device
The FS7145 supports nearly instantaneous adjustment of the
output CLK phase by the SYNC input. Either edge direction of
SYNC (positive-going or negative-going) is supported.
Serial communications capability is not disabled by either
SHUT1 or SHUT2.
Example (positive-going SYNC selected): Upon the negative
edge of SYNC input, a sequence begins to stop the CLK
output. Upon the positive edge, CLK resumes operation,
synchronized to the phase of the SYNC input (plus a
deterministic delay). This is performed by control of the device
post-divider. Phase resolution equal to ½ of the VCO period
can be achieved (approximately down to 2ns).
4.2 Differential Output Stage
The differential output stage supports both CMOS and pseudo-
ECL (PECL) signals. The desired output interface is chosen via
the programming registers.
5.0 I2C-bus Control Interface
If a PECL interface is used, the transmission line is usually
terminated using a Thévenin termination. The output stage can
only sink current in the PECL mode, and the amount of sink
current is set by a programming resistor on the LOCK/IPRG
pin. The ratio of output sink current to IPRG current is 13:1.
Source current for the CLKx pins is provided by the pull-up
resistors that are part of the Thévenin termination.
This device is a read/write slave device meeting all
Philips I2C-bus specifications except a "general
call." The bus has to be controlled by a master
device that generates the serial clock SCL,
controls bus access and generates the START
and STOP conditions while the device works as a slave. Both
master and slave can operate as a transmitter or receiver, but
the master device determines which mode is activated. A
device that sends data onto the bus is defined as the
transmitter, and a device receiving data as the receiver.
4.2.1 Example
Assume that it is desired to connect a PECL-type fanout buffer
right next to the FS7140.
I2C-bus logic levels noted herein are based on a percentage of
Further assume:
DD
· V = 3.3V
DD
the power supply (V ). A logic-one corresponds to a nominal
HI
· desired V = 2.4V
DD
SS
voltage of V , while a logic-zero corresponds to ground (V ).
LO
· desired V = 1.6V
LOAD
· equivalent R
= 75 ohms
AMI Semiconductor
www.amis.com
4
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
5.1 Bus Conditions
5.2 I2C-bus Operation
Data transfer on the bus can only be initiated when the bus is
not busy. During the data transfer, the data line (SDA) must
remain stable whenever the clock line (SCL) is high. Changes
in the data line while the clock line is high will be interpreted by
the device as a START or STOP condition. The following bus
conditions are defined by the I2C-bus protocol.
All programmable registers can be accessed randomly or
sequentially via this bi-directional two wire digital interface. The
crystal oscillator does not have to run for communication to
occur.
The device accepts the following I2C-bus commands:
5.1.1 Not Busy
5.2.1 Slave Address
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
After generating a START condition, the bus master broadcasts
a seven-bit slave address followed by a R/W bit. The address
of the device is:
5.1.2 START Data Transfer
A6
A5
A4
A3
A2
A1
A0
A high to low transition of the SDA line while the SCL input is
high indicates a START condition. All commands to the device
must be preceded by a START condition.
1
0
1
1
0
X
X
where X is controlled by the logic level at the ADDR pins. The
selectable ADDR bits allow four different FS7140 devices to
exist on the same bus. Note that every device on an I2C-bus
must have a unique address to avoid pos-sible bus conflicts.
5.1.3 STOP Data Transfer
A low to high transition of the SDA line while SCL is held high
indicates a STOP condition. All commands to the device must
be followed by a STOP condition.
5.2.2 Random Register Write Procedure
Random write operations allow the master to directly write to
any register. To initiate a write procedure, the R/W bit that is
transmitted after the seven-bit device address is a logic-low.
This indicates to the addressed slave device that a register
address will follow after the slave device acknowledges its
device address. The register address is written into the slave's
address pointer. Following an acknowledge by the slave, the
master is allowed to write eight bits of data into the addressed
register. A final acknowledge is returned by the device, and the
master generates a STOP condition.
5.1.4 Data Valid
The state of the SDA line represents valid data if the SDA line
is stable for the duration of the high period of the SCL line after
a START condition occurs. The data on the SDA line must be
changed only during the low period of the SCL signal. There is
one clock pulse per data bit.
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data bytes
transferred between START and STOP conditions is
determined by the master device, and can continue indefinitely.
However, data that is overwritten to the device after the first
eight bytes will overflow into the first register, then the second,
and so on, in a first-in, first-overwritten fashion.
If either a STOP or a repeated START condition occurs during
a register write, the data that has been transferred is ignored.
5.2.3 Random Register Read Procedure
Random read operations allow the master to directly read from
any register. To perform a read procedure, the R/W bit that is
transmitted after the seven-bit address is a logic-low, as in the
register write procedure. This indicates to the addressed slave
device that a register address will follow after the slave device
acknowledges its device address. The register address is then
written into the slave's address pointer.
5.1.5 Acknowledge
When addressed, the receiving device is required to generate
an acknowledge after each byte is received. The master device
must generate an extra clock pulse to coincide with the
acknowledge bit. The acknowledging device must pull the SDA
line low during the high period of the master acknowledge
clock pulse. Setup and hold times must be taken into account.
Following an acknowledge by the slave, the master generates
a repeated START condition. The repeated START terminates
the write procedure, but not until after the slave's address
pointer is set. The slave address is then resent, with the R/W
bit set this time to a logic-high, indicating to the slave that data
will be read. The slave will acknowledge the device address,
and then transmits the eight-bit word. The master does not
The master must signal an end of data to the slave by not
generating and acknowledge bit on the last byte that has been
read (clocked) out of the slave. In this case, the slave must
leave the SDA line high to enable the master to generate a
STOP condition.
AMI Semiconductor
www.amis.com
5
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
acknowledge the transfer but does generate a STOP condition.
5.2.5 Sequential Register Read Procedure
Sequential read operations allow the master to read from each
register in order. The register pointer is automatically
incremented by one after each read. This procedure is more
efficient than the random register read if several registers must
be read.
5.2.4 Sequential Register Write Procedure
Sequential write operations allow the master to write to each
register in order. The register pointer is automatically
incremented after each write. This procedure is more efficient
than the random register write if several registers must be
written.
To perform a read procedure, the R/W bit that is transmitted
after the seven-bit address is a logic-low, as in the register
write procedure. This indicates to the addressed slave device
that a register address will follow after the slave device
acknowledges its device address. The register address is then
written into the slave's address pointer.
To initiate a write procedure, the R/W bit that is transmitted
after the seven-bit device address is a logic-low. This indicates
to the addressed slave device that a register address will follow
after the slave device acknowledges its device address. The
register address is written into the slave's address pointer.
Following an acknowledge by the slave, the master is allowed
to write up to eight bytes of data into the addressed register
before the register address pointer overflows back to the
beginning address.
Following an acknowledge by the slave, the master generates
a repeated START condition. The repeated START terminates
the write procedure, but not until after the slave's address
pointer is set. The slave address is then resent, with the R/W
bit set this time to a logic-high, indicating to the slave that data
will be read. The slave will acknowledge the device address,
and then transmits all eight bytes of data starting with the initial
addressed register. The register address pointer will overflow if
the initial register address is larger than zero. After the last byte
of data, the master does not acknowledge the transfer but
does generate a STOP condition.
An acknowledge by the device between each byte of data must
occur before the next data byte is sent.
Registers are updated every time the device sends an
acknowledge to the host. The register update does not wait for
the STOP condition to occur. Registers are therefore updated
at different times during a sequential register write.
AMI Semiconductor
www.amis.com
6
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
S
DEVICE ADDRESS
W
A
REGISTER ADDRESS
A
DATA
A P
7-bit Receive
Device Address
Register Address
Acknowledge
Data
Acknowledge
STOP Condition
Acknowledge
START
Command
WRITE Command
From bus host
to device
From device
to bus host
Figure 4: Random Register Write Procedure
S
DEVICE ADDRESS
W
A
REGISTER ADDRESS
A
S
DEVICE ADDRESS
R
A
DATA
A P
7-bit Receive
Device Address
7-bit Receive
Device Address
Register Address
Acknowledge
Data
Acknowledge
STOP Condition
NO Acknowledge
Repeat START
START
Command
WRITE Command
Acknowledge
READ Command
From bus host
to device
From device
to bus host
Figure 5: Random Register Read Procedure
S
DEVICE ADDRESS
W
A
REGISTER ADDRESS
A
DATA
A
DATA
A
DATA
A P
7-bit Receive
Device Address
Register Address
Acknowledge
Data
Data
Data
Acknowledge
Acknowledge
Acknowledge
Acknowledge
START
Command
WRITE Command
STOP Command
From bus host
to device
From device
to bus host
Figure 6: Sequential Register Write Procedure
S
DEVICE ADDRESS
W
A
REGISTER ADDRESS
A
S
DEVICE ADDRESS
R
A
DATA
A
DATA
A P
7-bit Receive
Device Address
7-bit Receive
Device Address
Register Address
Acknowledge
Data
Data
Acknowledge
Acknowledge
NO Acknowledge
Repeat START
START
Command
WRITE Command
Acknowledge
READ Command
STOP Command
From bus host
to device
From device
to bus host
Figure 7: Sequential Register Read Procedure
AMI Semiconductor
www.amis.com
7
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
6.0 Programming Information
All register bits are cleared to zero on power-up. All register
bits may be read back as written.
Table 3: FS7140 Register Map
ADDRESS
BYTE 7
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
(Bit 63)
(Bit 62)
(Bit 61)
(Bit 60)
(Bit 59)
(Bit 58)
(Bit 57)
(Bit 56)
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
RESERVED
RESERVED
SHUT2
(Bit 53)
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
(Bit 55)
(Bit 54)
(Bit 52)
(Bit 51)
(Bit 50)
(Bit 49)
(Bit 48)
BYTE 6
BYTE 5
0 = Normal
1 = Powered Down
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
RESERVED
LC
(Bit 46)
LR[1]
(Bit 45)
LR[0]
(Bit 44)
RESERVED
RESERVED
CP[1]
(Bit 41)
CP[0]
(Bit 40)
(Bit 47)
(Bit 43)
(Bit 42)
Loop Filter Cap
Select
Must be set to “0”
Loop Filter Resistor Select
Must be set to “0”
Must be set to “0”
Charge Pump Current Select
CMOS
(Bit 39)
FBKDSRC
(Bit 38)
FBKDIV[13]
FBKDIV[12]
FBKDIV[11]
FBKDIV[10]
FBKDIV[9]
(Bit 33)
FBKDIV[8]
(Bit 32)
(Bit 37)
(Bit 36)
(Bit 35)
(Bit 34)
BYTE 4
0 = VCO Output
1 = Post Divider
Output
8192
4096
2048
1024
512
256
0 = PECL
1 = CMOS
See Section 4.1.2 for disallowed FBKDIV values
FBKDIV[7]
(Bit 31)
FBKDIV[6]
(Bit 30)
FBKDIV[5]
(Bit 29)
FBKDIV[4]
(Bit 28)
FBKDIV[3]
(Bit 27)
FBKDIV[2]
(Bit 26)
FBKDIV[1]
(Bit 25)
FBKDIV[0]
(Bit 24)
BYTE 3
BYTE 2
128
64
32
16
8
4
2
1
See Section 4.1.2 for disallowed FBKDIV values
POST2[3]
(Bit 23)
POST2[2]
(Bit 22)
POST2[1]
(Bit 21)
POST2[0]
(Bit 20)
POST1[3]
(Bit 19)
POST1[2]
(Bit 18)
POST1[1]
(Bit 17)
POST1[0]
(Bit 16)
Modulus = N+1 (N=0 to 11)
See Table 8
Modulus = N+1 (N=0 to 11)
See Table 8
POST3[1]
(Bit 15)
POST3[0]
(Bit 14)
SHUT1
(Bit 13)
REFDSRC
(Bit 12)
REFDIV[11]
REFDIV[10]
REFDIV[9]
REFDIV[8]
(Bit 11)
(Bit 10)
(Bit 9)
(Bit 8)
BYTE 1
BYTE 0
Modulus = 1, 2, 4, or 8
See Table 8
0 = Normal
1 = Powered Down
0 = Crystal Oscillator
1 = REF Pin
2048
1024
512
256
REFDIV[7]
REFDIV[6]
REFDIV[5]
REFDIV[4]
REFDIV[3]
REFDIV[2]
REFDIV[1]
REFDIV[0]
(Bit 7)
(Bit 6)
(Bit 5)
(Bit 4)
(Bit 3)
(Bit 2)
(Bit 1)
(Bit 0)
128
64
32
16
8
4
2
1
AMI Semiconductor
www.amis.com
8
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 4: FS7145 Register Map
ADDRESS
BYTE 7
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
(Bit 63)
(Bit 62)
(Bit 61)
(Bit 60)
(Bit 59)
(Bit 58)
(Bit 57)
(Bit 56)
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
RESERVED
RESERVED
SHUT2
(Bit 53)
RESERVED
RESERVED
RESERVED
SYNCPOL
(Bit 49)
SYNCEN
(Bit 48)
(Bit 55)
(Bit 54)
(Bit 52)
(Bit 51)
(Bit 50)
BYTE 6
BYTE 5
0 = Normal
1 = Powered Down
“0” = negative
“1” = positive
“0” = negative
“1” = positive
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
RESERVED
LC
(Bit 46)
LR[1]
(Bit 45)
LR[0]
(Bit 44)
RESERVED
RESERVED
CP[1]
(Bit 41)
CP[0]
(Bit 40)
(Bit 47)
(Bit 43)
(Bit 42)
Loop Filter Cap
Select
Must be set to “0”
Loop Filter Resistor Select
Must be set to “0”
Must be set to “0”
Charge Pump Current Select
CMOS
(Bit 39)
FBKDSRC
(Bit 38)
FBKDIV[13]
FBKDIV[12]
FBKDIV[11]
FBKDIV[10]
FBKDIV[9]
(Bit 33)
FBKDIV[8]
(Bit 32)
(Bit 37)
(Bit 36)
(Bit 35)
(Bit 34)
BYTE 4
0 = VCO Output
1 = Post Divider
Output
8192
4096
2048
1024
512
256
0 = PECL
1 = CMOS
See Section 4.1.2 for disallowed FBKDIV values
FBKDIV[7]
(Bit 31)
FBKDIV[6]
(Bit 30)
FBKDIV[5]
(Bit 29)
FBKDIV[4]
(Bit 28)
FBKDIV[3]
(Bit 27)
FBKDIV[2]
(Bit 26)
FBKDIV[1]
(Bit 25)
FBKDIV[0]
(Bit 24)
BYTE 3
BYTE 2
128
64
32
16
8
4
2
1
See Section 4.1.2 for disallowed FBKDIV values
POST2[3]
(Bit 23)
POST2[2]
(Bit 22)
POST2[1]
(Bit 21)
POST2[0]
(Bit 20)
POST1[3]
(Bit 19)
POST1[2]
(Bit 18)
POST1[1]
(Bit 17)
POST1[0]
(Bit 16)
Modulus = N+1 (N=0 to 11)
See Table 8
Modulus = N+1 (N=0 to 11)
See Table 8
POST3[1]
(Bit 15)
POST3[0]
(Bit 14)
SHUT1
(Bit 13)
REFDSRC
(Bit 12)
REFDIV[11]
REFDIV[10]
REFDIV[9]
REFDIV[8]
(Bit 11)
(Bit 10)
(Bit 9)
(Bit 8)
BYTE 1
BYTE 0
Modulus = 1, 2, 4, or 8
See Table 8
0 = Normal
1 = Powered Down
0 = Crystal Oscillator
1 = REF Pin
2048
1024
512
256
REFDIV[7]
REFDIV[6]
REFDIV[5]
REFDIV[4]
REFDIV[3]
REFDIV[2]
REFDIV[1]
REFDIV[0]
(Bit 7)
(Bit 6)
(Bit 5)
(Bit 4)
(Bit 3)
(Bit 2)
(Bit 1)
(Bit 0)
128
64
32
16
8
4
2
1
AMI Semiconductor
www.amis.com
9
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 5: Device Configuration Bits
Table 9: Post Divider Control Bits
Name
Description
Name
Description
REFerence Divider SouRCe
[0] = Crystal Oscillator / [1] = REF Pin
FeedB ack Divider SouRCe
[0] = VCO Output / [1] = Post Divider Output
SHUTdown1
[0] = Normal / [1] = Powered Down
SHUTdown2
[0] = Normal / [1] = Powered Down
CLKP/CLKN Output Mode
[0] = PECL Output / [1] CMOS Output
P1
POST Divider #1 (N ) Modulus
REFDSRC
[0000]
[0001]
[0010]
[0011]
[0100]
[0101]
[0110]
[0111]
[1000]
[1001]
[1010]
[1011]
[1100]
[1101]
1
2
3
4
5
6
7
8
9
FBKDSRC
SHUT1
SHUT2
CMOS
POST1[3:0]
10
11
12
Table 6: Main Loop Tuning Bits
Name
Description
Charge Pump Current
Do not use
[1110]
[1111]
[00]
[01]
2.0µA
4.5µA
CP[1:0]
P2
POST Divider #2 (N ) Modulus
[10]
[11]
11.0µA
22.5µA
[0000]
[0001]
[0010]
[0011]
[0100]
[0101]
[0110]
[0111]
[1000]
[1001]
[1010]
[1011]
[1100]
[1101]
[1110]
[1111]
1
2
3
4
5
6
7
8
9
Loop Filter Resistor Select
[00]
[01]
[10]
400KΩ
133KΩ
30KΩ
LR[1:0]
LC
[11]
12KΩ
Loop Filter Capacitor Select
POST2[3:0]
[0]
[1]
185pF
500pF
10
11
12
Table 7: PLL Divider Control Bits
NAME
DESCRIPTION
Do not use
R
REFerence DIVider (N )
REFDIV[11:0]
FBKDIV[13:0]
R
FeedBacK DIVider (N )
P3
POST Divider #3 (N ) Modulus
[00]
[01]
[10]
[11]
1
2
4
8
POST3[1:0]
Table 8: SYNC Control Bits (FS7145 only)
Name
Description
SYNC Enable
[0] = Disabled / [1] = Enabled
SYNC POLarity
SYNCEN
SYNCPOL
[0] = Negative Edge / [1] = Positive Edge
AMI Semiconductor
www.amis.com
10
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
7.0 Electrical Specifications
Table 10: Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
V
4.5
SS
DD
V
SS
Supply Voltage, dc (V = ground)
V -0.5
Input Voltage, dc
V
1
V
SS
DD
V -0.5
V +0.5
Output Voltage, dc
V
O
SS
DD
V
V -0.5
V +0.5
-50
-50
-65
-55
50
50
mA
mA
°C
°C
°C
I
I
DD
IK
Input Clamp Current, dc (V < 0 or V > V )
I
I
I
DD
OK
Output Clamp Current, dc (V < 0 or V > V )
Storage Temperature Range (non-condensing)
Ambient Temperature Range, Under Bias
I
150
125
150
S
T
A
T
Junction Temperature
J
T
Per IPC/JEDEC
J-STD-020B
Reflow Solder Profile
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
2
kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only and functional operation of the
device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect
device performance, functionality and reliability.
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a
high-energy electrostatic discharge.
Table 11: Operating Conditions
Parameter
Symbol Conditions/Description
Min.
3.0
0
Typ.
Max.
3.6
Units
Supply Voltage
3.3
V
DD
V
Ambient Operating Temperature Range
70
°C
A
T
AMI Semiconductor
www.amis.com
11
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 12: DC Electrical Specifications
Parameter
Overall
Symbol Conditions/Description
Min.
Typ.
Max.
Units
XTAL
VCO
CMOS mode; F
= 15MHz; F = 400MHz;
DD
I
I
Supply Current, Dynamic
35
mA
CLK
F
= 200MHx; does not include load current
DDL
Supply Current, Static
SHUT1, SHUT2 bit both “1”
400
700
µA
Serial Communication I/O (SDA, SCL)
High-Level Input Voltage
IH
DD
V
V
V
0.8*V
V
IL
DD
0.2*V
+10
Low-Level Input Voltage
V
hys
DD
0.33*V
14
Hysteresis Voltage
V
I
I
Input Leakage Current
SDA, SCL in read condition
-10
5
µA
mA
OL
SDA
I
SDA in acknowledge condition; V = 0.4V
Low-Level Output Sink Current (SDA)
Address Select Input (ADDR0, ADDR1)
High-Level Input Voltage
IH
IL
VDD
V
V
V
-1.0
-1.0
-1.0
V
Low-Level Input Voltage
0.8
1
V
IH
ADDRx
ADDRx
DD
I
I
V
= V
High-Level Input Current (pull-down)
Low-Level Input Current
30
µA
µA
IL
V
= 0V
-1
Reference Frequency Input (REF)
High-Level Input Voltage
IH
VDD
V
V
V
V
IL
Low-Level Input Voltage
0.8
1
V
IH
IL
REF
V
DD
= V
I
I
High-Level Input Current
-1
µA
µA
REF
V
= 0V
Low-Level Input Current (pull-down)
Sync Control Input (SYNC)
High-Level Input Voltage
-30
-30
IH
VDD
V
V
V
V
IL
Low-Level Input Voltage
0.8
1
V
IH
REF
REF
DD
I
I
V
= V
High-Level Input Current
-1
µA
µA
IL
V
= 0V
Low-Level Input Current (pull-down)
Crystal Oscillator Input (XIN)
Threshold Bias Voltage
TH
DD
V /2
V
V
IH
XIN
XIN
I
V
= VDD
= GND
High-Level Input Current
40
µA
µA
MHz
pF
IL
I
V
Low-Level input Current
-40
X
F
Crystal Frequency
Fundamental mode
35
10
L(XTAL)
C
Recommended Crystal Load Capacitance*
Crystal Oscillator Output (XOUT)
High-Level Output Source Current
Low-Level Output Sink Current
PECL Current Program I/O (IPRG)
Low-Level Input Current
For best matching with internal crystal oscillator load
16-18
OH
XOUT
V
I
I
= 0
-8.5
11
mA
mA
OL
XOUT
IPRG
O
V
= VDD
IL
I
V
= 0V; PECL Mode
-10
µA
Clock Outputs, CMOS Mode (CLKN, CLKP)
High-Level Output Source Current
Low-Level Output Sink Current
Clock Outputs, PECL Mode (CLKN, CLKP)
OH
OL
I
I
V = 2.0V
19
mA
mA
O
V = 0.4V
-35
IPRG
V
will be clamped to this level when a resistor is
IPRG
V
IPRG Bias Voltage
VDD/3
13
V
connected from VDD to IPRG
IPRG
IPRG
I
VDD
IPRG
SET
I
- (V - V ) / R
IPRG Bias Current
Sink Current to IPRG Current Ratio
Tristate Output Current
DD
3.5
10
mA
Z
I
-10
µA
A
Unless otherwise stated, V = 3.3V ± 10%, no load on any output, and ambient temperature range T = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data
and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
AMI Semiconductor
www.amis.com
12
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 13: AC Timing Specifications
Clock
(MHz)
Parameter
Overall
Symbol
Conditions/Description
Min. Typ.
Max.
Units
CMOS outputs
PECL outputs
0
0
150
300
400
O(max)
f
Output Frequency*
MHz
VCO
f
VCO Frequency*
40
MHz
ns
r
t
L
C = 7pF
CMOS Mode Rise Time*
CMOS Mode Fall Time*
PECL Mode Rise Time*
PECL Mode Fall Time*
Reference Frequency Input (REF)
Input Frequency
1
f
L
t
C = 7pF
1
ns
r
t
L
L
C = 7pF; R = 65 ohm
1
ns
f
L
L
t
C = 7pF; R = 65 ohm
1
ns
REF
F
80
MHz
ns
REHF
t
Reference High Time
3
3
REFL
t
Reference Low Time
ns
Sync Control Input (SYNC)
Sync High Time
SYNCH
CLK
t
T
for orderly CLK stop/start
for orderly CLK stop/start
3
3
SYNCL
CLK
t
T
Sync Low Time
Clock Output (CLKP, CLKN)
Duty Cycle (CMOS Mode)*
Duty Cycle (PECL Mode)*
Measured at 1.4V
50
50
%
%
CLKP
CLKN
Measured at zero crossings of (V -V
)
For valid programming solutions. Long-term (or cumulative) jitter specified is RMS
position error of any edge compared with an ideal clock generated from the same
reference frequency. It is measured with a time interval analyzer using a 500
microsecond window, using statistics gathered over 1000 samples.
ps
FREF/NREF > 1000kHz
FREF/NREF ~= 500kHz
FREF/NREF ~= 250kHz
FREF/NREF ~= 125kHz
FREF/NREF ~= 62.5kHz
FREF/NREF ~= 31.5kHz
40MHz < VCO Frequency < 100MHz
VCO Frequency > 100MHz
25
50
ps
ps
ps
ps
ps
ps
ps
ps
j(LT)
Jitter, Long Term (σ
γ
(τ))∗
t
100
190
240
300
75
j(∆P)
t
Jitter, Period (peak-peak)*
50
DD
A
Unless otherwise stated, V = 3.3V ± 10%, no load on any output, and ambient temperature range T = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data
and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
Table 14: Serial Interface Timing Specifications
Fast Mode
Parameter
Symbol
Conditions/Description
Units
Min.
0
Max.
SCL
f
Clock Frequency
SCL
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUF
t
Bus Free Time Between STOP and START
Setup Time, START (repeated)
Hold Time, START
1300
600
600
100
0
su:STA
t
hd:STA
t
su:DAT
t
Setup Time, Data Input
Hold Time, Data Input
SDA
SDA
hd:DAT
t
AA
t
Output Data Valid From Clock
Rise Time, Data and Clock
Fall Time, Data and Clock
High Time, Clock
900
300
300
R
t
SDA, SCL
SDA, SCL
SCL
F
t
HI
t
600
1300
600
LO
t
Low Time, Clock
SCL
su:STO
t
Setupt Time, STOP
DD
A
Unless otherwise stated, V = 3.3V ± 10%, no load on any output, and ambient temperature range T = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data
and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
AMI Semiconductor
www.amis.com
13
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
SCL
thd:STA
tsu:STA
tsu:STO
SDA
ADDRESS OR
DATA VALID
DATA CAN
CHANGE
START
STOP
Figure 8: Bus Timing Data
tHI
tR
tF
tLO
SCL
tsu:STA
thd:STA
tsu:STO
tsu:DAT
thd:DAT
SDA
IN
tBUF
tAA
tAA
SDA
OUT
Figure 9: Data Transfer Sequence
8.0 Package Information for ‘Green’ (FS7140) and ‘Non-Green’ (FS7140 & FS7145)
Table 15: 16-pin SOIC (0.150”) Package Dimensions
Dimensions
16
Inches
Min.
Millimeters
Max.
0.068
0.0098
0.061
0.019
0.0098
0.393
0.157
Min.
Max.
1.73
0.249
1.55
0.49
0.249
9.98
3.99
A
A1
A2
B
0.061
0.004
0.055
0.013
0.0075
0.386
0.150
1.55
0.102
1.40
E
H
0.33
C
D
E
0.191
9.80
1
ALL RADII:
0.005" TO 0.01"
h x 45°
7° typ.
B
e
3.81
e
0.050 BSC
1.27 BSC
C
A2
A
H
h
0.230
0.010
0.016
0°
0.244
0.016
0.035
8°
5.84
0.25
0.41
0°
6.20
0.41
0.89
8°
D
L
θ
A1
L
BASE PLANE
SEATING PLANE
Θ
AMI Semiconductor
www.amis.com
14
Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 16: 16-pin SOIC (0.150”) Package Characteristics
Parameter
Symbol
Conditions/Description
Air flow = 0 ft./min.
Corner lead
Typ.
108
2.5
Units
°CW
nH
JA
Θ
Thermal Impedance, Junction to Free-Air
11
L
Lead Inductance, Self
Center lead
1.2
nH
Table 17: 16-pin 5.3mm (0.209”) SSOP Package Dimensions
16
Dimensions
Millimeters
Inches
Min.
Max.
0.078
0.008
0.070
0.015
0.008
0.249
0.212
Min.
1.73
0.05
1.68
0.25
0.13
6.07
5.20
Max.
1.99
0.21
1.78
0.38
0.20
6.33
5.38
A
A1
A2
B
0.068
0.002
0.066
0.010
0.005
0.239
0.205
E
H
C
D
1
B
e
E
e
0.0256 BSC
0.65 BSC
C
A2
A
H
0.301
0.022
0
0.311
0.037
8
7.65
0.55
0
7.90
0.95
8
D
L
θ
A1
L
Θ
BASE PLANE
SEATING PLANE
Table 18: 16-pin 5.3mm (0.208”) SSOP Package Characteristics
Parameter
Symbol
Conditions/Description
TYP.
UNITS
Thermal Impedance, Junction to Free-Air
16-pin 0.150” SOIC
JA
Θ
Air flow = 0ms
90
°C/W
Corner lead
Center lead
2.3
1
nH
nH
11
L
Lead Inductance, Self
9.0 Ordering Information
Ordering Code
Device Number
Package Type
Operating Temperature Range
Shipping Configuration
13715-802
13715-201
13715-102
13715-202
FS7140-01
FS7140-01
FS7145
16-pin (0.150”) SOIC
16-pin (5.3mm) SSOP
16-pin (0.150”) SOIC
16-pin (5.3mm) SSOP
0°C to 70°C (commercial)
0°C to 70°C (commercial)
0°C to 70°C (commercial)
0°C to 70°C (commercial)
Tape and reel/tubes (please specify)
Tape and reel/tubes (please specify)
Tape and reel/tubes (please specify)
Tape and reel/tubes (please specify)
FS7145
16-pin (5.3mm) SSOP
‘green’ or lead-free packaging
13715-805
FS7140-01g
0°C to 70°C (commercial)
Tape and reel/tubes (please specify)
AMI Semiconductor
www.amis.com
15
© 2004 AMI Semiconductor, Inc.
AMI Semiconductor makes no warranty for the use of its products, other than those expressly contained in the company’s standard warranty contained in AMI Semiconductor’s Terms and Conditions. The company
assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to
update the information contained herein. No licenses to patents or other intellectual property of AMI Semiconductor are granted by the company in connection with the sale of AMI Semiconductor products, expressly or
by implication. I2C is a licensed trademark of Philips Electronics, N.V. AMI Semiconductor reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
IM
相关型号：
©2020 ICPDF网 联系我们和版权申明