FS6205-01 [AMI]

Clock Generator, 74.5808MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8;
FS6205-01
型号: FS6205-01
厂家: AMI SEMICONDUCTOR    AMI SEMICONDUCTOR
描述:

Clock Generator, 74.5808MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

时钟 光电二极管 外围集成电路 晶体
文件: 总8页 (文件大小:138K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
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1.0 Features  
2.0 Description  
The FS6205 is a monolithic CMOS clock generator IC  
designed to minimize cost and component count in digital  
video/audio systems.  
On-chip tunable voltage-controlled crystal oscillator  
circuitry (VCXO) allows precise system frequency  
tuning (pull range typically 300ppm)  
An on-chip voltage-controlled crystal oscillator (VCXO)  
permits the reference frequency (or output frequency) to  
be tuned to match other frequencies present in the sys-  
tem.  
Uses inexpensive fundamental-mode crystals  
Integrated phase-locked loops (PLL) multiply VCXO  
frequency to the higher system frequencies needed  
3.3V or 5V supply voltage available  
Phase-locked loops are used to generate precise output /  
reference frequency ratios. See Table 1 for information  
on the frequency ratios programmed into each version of  
the FS6205.  
Small circuit board footprint (8-pin 0.150SOIC)  
Custom frequency selections available - contact your  
local AMI Sales Representative for more information  
Table 1: Version Information  
Figure 1: Pin Configuration  
DEVICE  
VDD  
(nom)  
FREF  
(MHz)  
FS  
MS  
CLK  
(MHz)  
1
8
7
6
5
XIN  
XOUT  
MS  
27.000  
(REF * 2)  
F
0
0
1
1
0
1
0
1
S
13.500  
2
VDD  
6
74.175824175…  
(REF * 500 / 91)  
025  
3
4
XTUNE  
VSS  
FS  
FS6205-01  
3.3  
27.027  
(REF * 2)  
CLK  
13.5135  
74.580835443…  
(REF * 436 / 79)  
8-pin (0.150) SOIC  
NOTE: Contact AMI for custom versions  
Figure 2: Block Diagram  
XIN  
VCXO  
PLL A  
PLL B  
XOUT  
MUX  
CLK  
XTUNE  
FS  
MS  
FS6205  
American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
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Table 2: Pin Descriptions  
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,  
DO = Digital Output; P = Power/Ground; # = Active Low pin  
PIN  
TYPE  
NAME  
DESCRIPTION  
1
2
3
4
5
6
7
8
AI  
P
XIN  
VDD  
XTUNE  
VSS  
CLK  
VCXO Crystal Feedback  
Power Supply (+3.3V or +5V) – see Version Information  
AI  
VCXO Tune  
P
Ground  
DO  
DIU  
DIU  
AO  
Clock Output  
FS  
Frequency Select Input (changes PLL Frequencies)  
Multiplexer Select Input (chooses PLL A or PLL B)  
VCXO Crystal Drive  
MS  
XOUT  
the oscillator circuit. The actual amount that changing the  
load capacitance alters the oscillator frequency will be  
dependent on the characteristics of the crystal as well as  
the oscillator circuit itself.  
3.0 Functional Block Description  
3.1  
Phase-Locked Loops (PLL)  
Specifically, the motional capacitance of the crystal (usu-  
ally referred to by crystal manufacturers as C1), the static  
capacitance of the crystal (C0), and the load capacitance  
(CL) of the oscillator determine the “warping” or “pulling”  
capability of the crystal in the oscillator circuit.  
The on-chip PLLs are a standard frequency- and phase-  
locked loop architecture. The PLL multiplies the reference  
oscillator to the desired frequency by a ratio of integers.  
The frequency multiplication is exactly that specified by  
the integer ratios.  
A simple formula to obtain the pulling capability of a  
crystal oscillator is:  
3.2  
Voltage-Controlled Crystal  
Oscillator (VCXO)  
6
×
(
+
)
×
C1 CL2 CL1 10  
2×  
f (ppm) =  
(
)
×
(
+
)
C0 CL2 C0 CL1  
where CL1 and CL2 are the two extremes of the applied  
load capacitance.  
The VCXO provides a tunable, low-jitter frequency refer-  
ence for the rest of the FS6109 system components.  
Loading capacitance for the crystal is internal to the  
FS6205. No external components (other than the crystal  
resonator itself) are required for operation of the VCXO.  
EXAMPLE: A crystal with the following parameters is  
used. With C1 = 0.02pF, C0 = 5pF, CL1 = 13pF, and CL2  
=
35pF, the tuning range between extreme settings of  
XTUNE voltage is:  
Continuous fine-tuning of the VCXO frequency is accom-  
plished by varying the voltage on the XTUNE pin. The  
total change (from one extreme to the other) in effective  
loading capacitance is 12pF nominal (i.e from 35pF to  
13pF).  
6
0.02×  
(
35 13  
)
×
10  
.
306ppm  
f =  
2×  
(
5 + 35  
)
×
(
5 +13  
)
The oscillator operates the crystal resonator in the paral-  
lel-resonant mode. Crystal warping, or the “pulling” of the  
crystal oscillation frequency, is accomplished by altering  
the effective load capacitance presented to the crystal by  
2
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4.0 Electrical Specifications  
Table 3: Absolute Maximum Ratings  
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at  
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,  
functionality, and reliability.  
PARAMETER  
SYMBOL  
MIN.  
MAX.  
UNITS  
Supply Voltage (VSS = ground)  
Input Voltage, dc  
VDD  
VI  
VSS-0.5  
VSS-0.5  
VSS-0.5  
-50  
7
VDD+0.5  
VDD+0.5  
50  
V
V
Output Voltage, dc  
VO  
IIK  
V
Input Clamp Current, dc (VI < 0 or VI > VDD  
)
mA  
mA  
°C  
°C  
°C  
°C  
kV  
Output Clamp Current, dc (VI < 0 or VI > VDD  
)
IOK  
TS  
TA  
TJ  
-50  
50  
Storage Temperature Range (non-condensing)  
Ambient Temperature Range, Under Bias  
Junction Temperature  
-65  
150  
-55  
125  
125  
Lead Temperature (soldering, 10s)  
260  
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)  
2
CAUTION: ELECTROSTATIC SENSITIVE DEVICE  
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-  
trostatic discharge.  
Table 4: Operating Conditions  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
SEE NOTE 1  
MIN.  
TYP.  
MAX.  
UNITS  
Supply Voltage (3.3 volt system)  
Supply Voltage (5.0 volt system)  
Ambient Operating Temperature Range  
Crystal Resonator Frequency  
VDD  
VDD  
TA  
3.0  
4.5  
0
3.3  
5.0  
3.6  
5.5  
70  
V
V
SEE NOTE 1  
SEE NOTE 1  
°C  
fXTAL  
Fundamental Mode  
5
18  
MHz  
NOTE 1: These specifications represent generic FS6205 device capability. Device specifications for a particular version (i.e. FS6205-xx) are guaranteed only with the operating voltage and refer-  
ence frequency specified in Version Information.  
3
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Table 5: DC Electrical Specifications (VDD = 3.3V nominal)  
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization  
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
MIN.  
TYP.  
MAX.  
UNITS  
Overall  
Supply Current, Dynamic, with Loaded  
Outputs  
IDD  
fXTAL = 13.5MHz; CL = 10pF, VDD = 3.3V  
t.b.d.  
mA  
Crystal Oscillator  
As seen by a crystal connected to XIN and  
XOUT (@VXTUNE=mid-scale)  
Crystal Loading Capacitance  
CL(xtal)  
20  
pF  
RXTAL=20;  
Crystal Drive Level  
200  
uW  
Clock Outputs (CLKx)  
High-Level Output Source Current *  
Low-Level Output Sink Current *  
IOH  
IOL  
VO = 2.0V  
-40  
17  
25  
25  
-55  
55  
mA  
mA  
VO = 0.4V  
zOH  
zOL  
IOSH  
IOSL  
VO = 0.1VDD; output driving high  
VO = 0.1VDD; output driving low  
VO = 0V; shorted for 30s, max.  
VO = 3.3V; shorted for 30s, max.  
Output Impedance *  
Short Circuit Source Current *  
Short Circuit Sink Current *  
mA  
mA  
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Table 6: DC Electrical Specifications (VDD = 5V nominal)  
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization  
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
MIN.  
TYP.  
MAX.  
UNITS  
Overall  
Supply Current, Dynamic, with Loaded  
Outputs  
IDD  
fXTAL = 13.5MHz; CL = 10pF, VDD = 5.0V  
mA  
Crystal Oscillator  
As seen by a crystal connected to XIN and  
XOUT  
Crystal Loading Capacitance  
CL(xtal)  
pF  
RXTAL=20;  
Crystal Drive Level  
uW  
Clock Outputs (CLKx)  
High-Level Output Source Current *  
Low-Level Output Sink Current *  
IOH  
IOL  
VO = 2.0V  
mA  
mA  
VO = 0.4V  
zOH  
zOL  
IOSH  
IOSL  
VO = 0.1VDD; output driving high  
VO = 0.1VDD; output driving low  
VO = 0V; shorted for 30s, max.  
VO = 5V; shorted for 30s, max.  
Output Impedance *  
Short Circuit Source Current *  
Short Circuit Sink Current *  
mA  
mA  
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Table 7: AC Timing Specifications (VDD = 3.3V nominal)  
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization  
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.  
CLOCK  
(MHz)  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
MIN.  
TYP.  
MAX.  
UNITS  
Overall  
Synthesis Error  
(unless otherwise noted in Frequency Table)  
0
ppm  
Clock Output (CLKx)  
Ratio of high pulse width (as measured from rising edge  
to next falling edge at VDD/2) to one clock period  
Duty Cycle *  
45  
55  
%
From rising edge to next rising edge at  
tj(P)  
tj(LT)  
Jitter, Period (peak-peak) *  
390  
155  
ps  
V
DD/2, CL = 10pF  
From 0-500µs at VDD/2, CL = 10pF  
compared to ideal clock source  
Jitter, Long Term (σy(τ)) *  
ps  
Rise Time *  
Fall Time *  
tr  
tf  
VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF  
VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF  
1.7  
1.7  
ns  
ns  
Table 8: AC Timing Specifications (VDD = 5V nominal)  
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization  
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.  
CLOCK  
(MHz)  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
MIN.  
TYP.  
MAX.  
UNITS  
Overall  
Synthesis Error  
(unless otherwise noted in Frequency Table)  
0
ppm  
Clock Output (CLKx)  
Ratio of high pulse width (as measured from rising edge  
to next falling edge at VDD/2) to one clock period  
Duty Cycle *  
45  
55  
%
From rising edge to next rising edge at  
VDD/2, CL = 10pF  
tj(P)  
tj(LT)  
Jitter, Period (peak-peak) *  
390  
155  
ps  
From 0-500µs at VDD/2, CL = 10pF  
compared to ideal clock source  
Jitter, Long Term (σy(τ)) *  
ps  
Rise Time *  
Fall Time *  
tr  
tf  
VDD = 5V; VO = 0.5V to 4.5V; CL = 10pF  
VDD = 5V; VO = 4.5V to 0.5V; CL = 10pF  
1.0  
1.0  
ns  
ns  
6
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5.0 Package Information  
Table 9: 8-pin SOIC (0.150") Package Dimensions  
8
DIMENSIONS  
INCHES  
MILLIMETERS  
MIN.  
MAX.  
MIN.  
MAX.  
A
A1  
A2  
B
0.061  
0.004  
0.055  
0.013  
0.068  
0.0098  
0.061  
0.019  
1.55  
0.102  
1.40  
1.73  
0.249  
1.55  
E
H
R
0.33  
0.49  
1
C
D
E
0.0075 0.0098  
0.191  
4.80  
0.249  
4.98  
ALL RADII:  
0.005" TO 0.01"  
0.189  
0.150  
0.196  
0.157  
h x 45°  
7° typ.  
3.81  
3.99  
B
e
e
0.050 BSC  
1.27 BSC  
C
A2  
A
H
h
0.230  
0.010  
0.016  
0°  
0.244  
0.016  
0.035  
8°  
5.84  
0.25  
0.41  
0°  
6.20  
0.41  
0.89  
8°  
L
D
θ
A1  
L
BASE  
PLANE  
SEATING  
PLANE  
Θ
Table 10: 8-pin SOIC (0.150") Package Characteristics  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
Air flow = 0 m/s  
TYP.  
UNITS  
Thermal Impedance, Junction to Free-Air  
8-pin 0.150” SOIC  
ΘJA  
110  
°C/W  
Corner lead  
2.0  
1.6  
Lead Inductance, Self  
L11  
nH  
Center lead  
Lead Inductance, Mutual  
Lead Capacitance, Bulk  
L12  
Any lead to any adjacent lead  
Any lead to VSS  
0.4  
nH  
pF  
C11  
0.27  
7
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6.0 Ordering Information  
OPERATING  
SHIPPING  
CONFIGURATION  
ORDERING CODE  
DEVICE NUMBER  
PACKAGE TYPE  
TEMPERATURE RANGE  
0°C to 70°C (Commercial)  
0°C to 70°C (Commercial)  
8-pin (0.150”) SOIC  
(Small Outline Package)  
11640-t.b.d.  
11640-t.b.d.  
FS6205-01  
Tape and Reel  
Tubes  
8-pin (0.150”) SOIC  
(Small Outline Package)  
FS6205-01  
Copyright © 1999 American Microsystems, Inc.  
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI  
makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom  
of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-  
serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are  
intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-  
ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom-  
mended without additional processing by AMI for such applications.  
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,  
WWW Address: http://www.amis.com E-mail: tgp@amis.com  
8
6.1.99  
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