概述
规格参数
数据手册N08M1618L1AD-85I 概述
Standard SRAM, 512KX16, 85ns, CMOS, DIE SRAM
N08M1618L1AD-85I 规格参数
| 生命周期： | Transferred | 包装说明： | DIE |
| Reach Compliance Code： | unknown | 风险等级： | 5.79 |
| 最长访问时间： | 85 ns | JESD-30 代码： | X-XUUC-N |
| 内存密度： | 8388608 bit | 内存集成电路类型： | STANDARD SRAM |
| 内存宽度： | 16 | 功能数量： | 1 |
| 字数： | 524288 words | 字数代码： | 512000 |
| 工作模式： | ASYNCHRONOUS | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 组织： | 512KX16 |
| 封装主体材料： | UNSPECIFIED | 封装代码： | DIE |
| 封装形状： | UNSPECIFIED | 封装形式： | UNCASED CHIP |
| 并行/串行： | PARALLEL | 认证状态： | Not Qualified |
| 最大供电电压 (Vsup)： | 2.2 V | 最小供电电压 (Vsup)： | 1.4 V |
| 标称供电电压 (Vsup)： | 1.8 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子形式： | NO LEAD | 端子位置： | UPPER |
| Base Number Matches： | 1 |
N08M1618L1AD-85I 数据手册
通过下载N08M1618L1AD-85I数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载AMI Semiconductor, Inc.
ULP Memory Solutions
N08M1618L1A
670 North McCarthy Blvd. Suite 220
Milpitas, CA 95035
Advance Information
PH: 408-935-7777, FAX: 408-935-7770
8Mb Ultra-Low Power Asynchronous Medical CMOS SRAM
512K × 16 bit
Overview
Features
The N08M1618L1A is an integrated memory
device intended for non life-support medical
applications. This device is a 8 megabit memory
organized as 524,288 words by 16 bits. The device
is designed and fabricated using AMI
• Dual voltage for Optimum Performance:
Vccq - 2.3 to 3.6 Volts
Vcc - 1.4 to 2.2 Volts
• Very low standby current
0.5µA at 1.8V and 37 deg C
Semiconductor’s advanced CMOS technology with
reliability inhancements for medical users. The
device operates with two chip enable (CE1 and
CE2) controls and output enable (OE) to allow for
easy memory expansion. Byte controls (UB and
LB) allow the upper and lower bytes to be
• Very low operating current
1.0mA at 1.8V and 1µs (Typical)
• Very low Page Mode operating current
0.5mA at 1.8V and 1µs (Typical)
• Simple memory control
accessed independently and can also be used to
deselect the device. This device is optimal for
various applications where low-power is critical
such as battery backup and hand-held devices.
The device can operate over a very wide
Dual Chip Enables (CE1 and CE2)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Low voltage data retention
Vcc = 1.2V
o
o
temperature range of -40 C to +85 C and is
• Special Processing to reduce Soft Error Rate
available in a JEDEC standard BGA package.
(SER)
• Automatic power down to standby mode
Product Family
Standby
Operating
Current (Icc),
Max
Operating
Power
Current (ISB),
Part Number
N08M1618L1AB
N08M1618L1AW
Package Type
48 - BGA
Wafer
Speed
Temperature
Supply
Max
2.3V-3.6V(VCCQ
1.4V-2.2V(VCC) 150ns @ 1.4V
)
85ns @ 1.7V
2.5 mA @
1MHz
-40oC to +85oC
20 µA
Pin Configuration
Pin Descriptions
1
2
3
A0
A3
4
5
A2
6
Pin Name
A0-A18
WE
CE1, CE2
OE
LB
UB
I/O0-I/O15
Pin Function
A1
A4
A6
A7
LB
OE
CE2
A
B
C
D
E
F
Address Inputs
Write Enable Input
Chip Enable Input
I/O8
I/O0
UB
CE1
I/O9 I/O10 A5
VSS I/O11 A17
I/O1 I/O2
I/O3 VCC
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
VCCQ I/O12
I/O14 I/O13 A14
A16 I/O4 VSS
A15 I/O5 I/O6
NC
I/O15
A18
A12
A9
A13
A10
I/O7
NC
NC
A8
WE
A11
G
H
VCC
VSS
Power
Ground
48 Pin BGA (top)
8 x 10 mm
VCCQ
NC
Power I/O pins only
Not Connected
Stock No. 23211-03 9/21/06
ADVANCE INFORMATION
1
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
N08M1618L1A
AMI Semiconductor, Inc.
Functional Block Diagram
Advance Information
Word
Address
Inputs
Address
Decode
Logic
A0 - A3
Input/
Page
32K Page
x 16 word
x 16 bit
Address
Inputs
Output
Address
Decode
Logic
I/O0 - I/O7
Mux
A4 - A18
and
RAM Array
Buffers
I/O8 - I/O15
CE1
CE2
WE
OE
Control
Logic
UB
LB
Functional Description
1
CE1
CE2
WE
OE
UB
LB
MODE
POWER
I/O0 - I/O15
Standby2
Standby2
Standby2
Write3
H
X
X
L
X
L
X
X
X
L
X
X
X
X3
L
X
X
X
X
High Z
High Z
Standby
Standby
X
H
H
H
H
H
High Z
Standby
L1
L1
L1
L1
L1
L1
Active -> Standby4
Active -> Standby4
Standby4
Data In
Data Out
High Z
L
H
H
Read
Active
L
H
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from
any expernal influence.
1
Capacitance
Item
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN = 0V, f = 1 MHz, TA = 25oC
VIN = 0V, f = 1 MHz, TA = 25oC
Input Capacitance
I/O Capacitance
CI/O
8
pF
1. These parameters are verified in device characterization and are not 100% tested
Stock No. 23211-03 9/21/06
ADVANCE INFORMATION
2
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
N08M1618L1A
AMI Semiconductor, Inc.
Advance Information
1
Absolute Maximum Ratings
Item
Symbol
VIN,OUT
VCC
Rating
–0.3 to VCC+0.3
–0.3 to 4.5
500
Unit
V
Voltage on any pin relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
V
PD
mW
oC
oC
oC
TSTG
Storage Temperature
–40 to 125
TA
Operating Temperature
-40 to +85
240oC, 10sec(Lead only)
TSOLDER
Soldering Temperature and Time
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Typ1
Item
Symbol
Test Conditions
Min.
Max
Unit
VCC
VCCQ
VDR
VIH
Core Supply Voltage
I/O Supply Voltage
1.4
2.3
1.8
2.2
3.6
V
V
VCCQ > or = VCC
Chip Disabled3
Data Retention Voltage
Input High Voltage
1.2
VCCQ-0.6
V
VCCQ+0.3
0.6
V
VIL
Input Low Voltage
–0.3
V
VOH
VOL
ILI
IOH = 0.2mA
IOL = -0.2mA
VCCQ–0.2
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
V
0.2
0.1
0.1
V
VIN = 0 to VCC
µA
µA
ILO
OE = VIH or Chip Disabled
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
Read/Write Operating Supply Current
ICC1
ICC2
1.5
2.5
mA
mA
@ 1 µs Cycle Time2
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
Read/Write Operating Supply Current
10.0
13.0
@ 85 ns Cycle Time2
Page Mode Operating Supply Current
@ 85 ns Cycle Time2 (Refer to Power
Savings with Page Mode Operation
diagram)
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
ICC3
3.5
1
mA
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0,
f = 0
Read/Write Quiescent Operating Sup-
ply Current3
ICC4
µA
VIN = VCC or 0V
Standby Current3
Chip Disabled
ISB1
0.5
0.1
20.0
1.0
µA
µA
tA= 85oC, VCC = 2.2 V
VCC = 1.2V, VIN = VCC or 0
Chip Disabled, tA= 85oC
Data Retention Current3
IDR
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested.
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all
inputs must be within 0.2 volts of either VCC or VSS.
Stock No. 23211-03 9/21/06
ADVANCE INFORMATION
3
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
N08M1618L1A
AMI Semiconductor, Inc.
Power Savings with Page Mode Operation (WE = V )
Advance Information
IH
Page Address (A4 - A18)
Word Address (A0 - A3)
Open page
...
Word 16
Word 1
Word 2
CE1
CE2
OE
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 8-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Stock No. 23211-03 9/21/06
ADVANCE INFORMATION
4
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
N08M1618L1A
AMI Semiconductor, Inc.
Timing Test Conditions
Advance Information
Item
0.1VCC to 0.9 VCC
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
5ns
0.5 VCC
CL = 30pF
-40 to +85 oC
Operating Temperature
Timing V
> or = V
CCQ
CC
VCC = 1.4 - 2.2 V
VCC = 1.7 - 2.2 V
Item
Symbol
Units
Min.
Max.
Min.
Max.
tRC
tAA
Read Cycle Time
150
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Address Access Time (Page Mode)
Chip Enable to Valid Output
150
30
85
30
85
40
85
tAAP
tCO
tOE
150
50
Output Enable to Valid Output
Byte Select to Valid Output
t
LB, tUB
tLZ
150
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
20
20
20
0
10
5
tOLZ
tLBZ, tUBZ
tHZ
10
0
30
30
30
15
15
15
tOHZ
0
0
t
LBHZ, tUBHZ
tOH
0
0
20
10
tWC
tCW
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
150
75
75
75
50
0
85
50
50
50
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAW
tLBW, tUBW
tWP
tAS
Address Setup Time
tWR
Write Recovery Time
0
0
tWHZ
tDW
Write to High-Z Output
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
30
15
50
0
40
0
tDH
tOW
10
5
ns
Stock No. 23211-03 9/21/06
ADVANCE INFORMATION
5
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
N08M1618L1A
AMI Semiconductor, Inc.
Timing of Read Cycle (CE1 = OE = V , WE = CE2 = V )
Advance Information
IL
IH
t
RC
Address
t
AA
t
OH
Previous Data Valid
Data Valid
Data Out
Timing Waveform of Read Cycle (WE=V )
IH
t
RC
Address
t
AA
t
HZ(1,2)
CE1
CE2
t
CO
t
LZ(2)
t
OHZ(1)
t
OE
OE
t
OLZ
t
t
LB, UB
LB, UB
t
t
t
t
LBLZ, UBLZ
LBHZ, UBHZ
High-Z
Data Valid
Data Out
Stock No. 23211-03 9/21/06
ADVANCE INFORMATION
6
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
N08M1618L1A
AMI Semiconductor, Inc.
Timing Waveform of Page Mode Read Cycle (WE = V )
Advance Information
IH
t
RC
Page Address (A4 - A18)
Word Address (A0 - A3)
t
AAP
t
AA
t
HZ
CE1
CE2
t
CO
t
OHZ
t
OE
OE
t
OLZ
t
t
LB, UB
LB, UB
t
t
t
t
LBHZ, UBHZ
LBLZ, UBLZ
High-Z
Data Out
Stock No. 23211-03 9/21/06
ADVANCE INFORMATION
7
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
N08M1618L1A
AMI Semiconductor, Inc.
Advance Information
Timing Waveform of Write Cycle (WE control)
t
WC
Address
t
WR
t
AW
CE1
CE2
t
CW
t
, t
LBW UBW
LB, UB
WE
t
t
AS
WP
t
t
DH
DW
High-Z
Data Valid
Data In
Data Out
t
WHZ
t
OW
High-Z
Stock No. 23211-03 9/21/06
ADVANCE INFORMATION
8
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
N08M1618L1A
AMI Semiconductor, Inc.
Advance Information
Timing Waveform of Write Cycle (CE1 Control)
t
WC
Address
t
t
AW
WR
t
CE1
CW
(for CE2 Control, use
inverted signal)
t
AS
t
, t
LBW UBW
LB, UB
WE
t
WP
t
t
DH
DW
Data Valid
Data In
t
LZ
t
WHZ
High-Z
Data Out
Stock No. 23211-03 9/21/06
ADVANCE INFORMATION
9
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
N08M1618L1A
AMI Semiconductor, Inc.
Ball Grid Array Package
Advance Information
0.20±0.05
1.10±0.10
D
A1 BALL PAD
CORNER (3)
1. 0.30±0.05 DIA.
E
2. SEATING PLANE - Z
0.15
Z
0.05
Z
TOP VIEW
SIDE VIEW
1. DIMENSION IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER.
PARALLEL TO PRIMARY Z.
A1 BALL PAD
CORNER
SD
2. PRIMARY DATUM Z AND SEATING
PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE
SOLDER BALLS.
e
SE
3. A1 BALL PAD CORNER I.D. TO BE
MARKED BY INK.
K TYP
J TYP
e
BOTTOM VIEW
Dimensions (mm)
e = 0.75
BALL
D
E
MATRIX
TYPE
SD
SE
J
K
8±0.10
10±0.10
0.375
0.375
2.125
2.375
FULL
Stock No. 23211-03 9/21/06
ADVANCE INFORMATION
10
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
N08M1618L1A
AMI Semiconductor, Inc.
Ordering Information
Advance Information
N08M1618L1AX-XX X
I = Industrial, -40°C to 85°C
Temperature
85 = 85ns @ 1.7V
Performance
B = 48-ball BGA
Package Type
D = Known Good Die
Revision History
Revision #
01
Date
Change Description
11/01/02
Initial Release
General Update:
Updated ICC4 typical and ISB1 typical value
Updated Block Diagram, Functional Description Table.
Added tAAP, tLB, tUB, tLBZ, tUBZ, tLBHZ, tUBHZ, tLBW, tUBW timing parameters.
Added Page Mode Read Timing Waveform
02
3/03/05
Updated BGA 8X10 Package Drawing
Updated VccQ range on DC Parameters Table
03
9/21/2006
Converted to AMI Semiconductor
© 2006 AMI Semiconductor, Inc. All rights reserved.
AMI Semiconductor, Inc. ("AMIS") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice.
AMIS does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration pur-
poses only and they vary depending upon specific applications.
AMIS makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does AMIS assume any liability arising out of the application or use of
any product or circuit described herein. AMIS does not authorize use of its products as critical components in any application in which the failure of the AMIS product may be
expected to result in significant injury or death, including life support systems and critical medical instruments.
Stock No. 23211-03 9/21/06
ADVANCE INFORMATION
11
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
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