AS1116_12 [AMSCO]
64 LED Dr iver wi th Detai led Er ror Detect ion; 64 LED医生艾弗的Wi日德泰主导尔ROR离子检测
| 型号： | AS1116_12 |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | 64 LED Dr iver wi th Detai led Er ror Detect ion |
| 文件： | 总24页 (文件大小：2482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Datasheet
AS1116
64 LED Driver with Detailed Error Detection
1 General Description
The AS1116 is a compact LED driver for 64 single LEDs or 8 digits of
7ꢀsegments. The devices can be programmed via an SPI compatible
3ꢀwire interface.
2 Key Features
ꢀ
10MHz SPIꢀCompatible Interface
Open and Shorted LED Error Detection
ꢀ Global or Individual Error Detection
Hexadecimalꢀ or BCDꢀCode for 7ꢀSegment Displays
200nA LowꢀPower Shutdown Current (typ; data retained)
Individual Digit Brightness Control
Digital and Analog Brightness Control
Display Blanked on PowerꢀUp
Drive CommonꢀCathode LED Displays
Supply Voltage Range: 2.7 to 5.5V
Software Reset
Optional External Clock
Package:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Every segment can be individually addressed and updated sepaꢀ
rately. Only one external resistor (RSET) is required to set the curꢀ
rent. LED brightness can be controlled by analog or digital means.
The devices include an integrated BCD codeꢀB/HEX decoder, multiꢀ
plex scan circuitry, segment and display drivers, and a 64ꢀbit memꢀ
ory. Internal memory stores the shift register settings, eliminating the
need for continuous device reprogramming.
Additionally the AS1116 offers a diagnostic mode for easy and fast
production testing and allows the use of the AS1116 for critical appliꢀ
cations. The diagnostic allows to detect individual open or shorted
LEDs.
ꢀ QSOP24 and TQFN(4x4)ꢀ24
The AS1116 features a low shutdown current of typically 200nA, and
an operational current of typically 350ꢁA. The number of digits can
be programmed, the devices can be reset by software, and an exterꢀ
nal clock is also supported.
3 Applications
The AS1116 is ideal fsevenꢀsegment or dot matrix displays in pubꢀ
lic information disays at subway, train or bus stations, at airports
and also at dplays public transportation like buses or trains
mobile pho, personal electronic and toys.
The device is available in a QSOPꢀ24 and TQFN(4x4)ꢀ24 pakage.
Figure 1. AS1116 - Typical Application Diagram
8
SEGA to G,
SEG DP
DIG0 to
DIG7
V
DD
8
8
8
8
2.7V to 5.5V
9.53kΩ
GND
IET
SDI
AS1116
AS1116
AS1116
SDO
SDO
SDO
SDI
SDI
I/O
LD
LD
LD
SCL
SCL
SCL
I/O
µP
I/O
I/O
Diagnostic readback: open & shorted LEDs
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Revision 1.08
1 ꢀ 23
AS1116
Datasheet ꢀ Pinout
4 Pinout
Pin Assignments
Figure 2. Pin Assignments (Top View)
24 23 22 21 20 19
DIG2
DIG3
GND
DIG4
DIG5
N/C
1
2
3
4
5
6
18 SEG E
17 SEGC
16 VDD
AS1116
AS1116
15 SEGG
14 SGB
13 EG
7
8
9
10 11 12
Pin Descriptions
Table 1. Pin Descriptions
Pin Name
QSOP-24
TQFN(4x4)-24
Description
Seri-Data Input. Data oaded into the internal 16ꢀbit shift register on the rising edge
opin SCL.
1
22
SDI
1, 2, 4, 5, 78, 23
4
2ꢀ5, 7ꢀ10
Digit Drive Lines. ight digit drive lines that sink current from the display cathode.
DIG0:DIG7
GND
6
3
9
6
Ground.
Load. Serial is loaded into the shift register while this pin is low. The last 16 bits of
seriadata re latched on the rising edge of this pin.
Not Connected.
11
12
LD
N/C
Set Segment Current. Connect to VDD or a reference voltage through RSET to set the
pak segment current (see Selecting RSET Resistor Value and Using
External Drivers on page 17).
Serial-Clock Input. 10MHz maximum rate. Data is shifted into the internal shift register
on the rising edge of this pin. Data is clocked out of pin SDO on the rising edge of this
pin.
13
14
10
11
ISET
SCL
Seven Segment and Decimal Point Drive Lines. 8 sevenꢀsegment drives and
decimal point drive that source current to the display.
SEGA:SEGG,
SEGDP
15ꢀ18,
20ꢀ23
12ꢀ15,
17ꢀ20
19
16
Positive Supply Voltage. Connect to +2.7 to +5.5V supply.
VDD
Serial-Data Output. The data into pin SDI is valid at pin SDO 16 clock cycles later. This
pin is used to daisyꢀchain several devices and is never highꢀimpedance.
Exposed Pad. This pin also functions as a heat sink. Solder it to a large pad or to the
circuitꢀboard ground plane to maximize power dissipation.
2
21
SDO
Exposed Pad
ꢀ
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Revision 1.08
2 ꢀ 23
AS1116
Datasheet ꢀ Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Section 6 Electrical Characteristics on page 4 is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Min
Max
Units
Notes
Electrical Parameters
VDD to GND
ꢀ0.3
ꢀ0.3
7
V
V
Input Voltage Range
7 or
VDD + 0.3
All other pins to GND
DIG0:DIG7 Sink Current
SEGA:SEGG, SEGDP
500
100
mA
mA
mA
Current
Input Current (latchꢀup immunity)
±100
Norm: JEDE78
Electrostatic Discharge
Electrostatic Discharge
Thermal Information
Digital outputs
All other pins
1000
000
V
V
Norm: MI833 E method 3015
88
ºC/W
ºC/W
on PCB, QSOPꢀ24 package
Thermal Resistance ΘJA
30.5
on PCB, TQFN(4x4)ꢀ24 package
Temperature Ranges and Storage Conditions
Junction Temperature
+150
+10
C
ºC
Storage Temperature
ꢀ55
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020 “Moisture/Reflow
Sensitivity Classification for Non-Hermetic
Solid State Surface Mount Devices”.
The lead finish for Pbꢀfree leaded packages
is matte tin (100% Sn).
Package Body Temperature
260
85
ºC
Humidity nonꢀcondensing
5
%
%
%
QSOPꢀ24 package
Moisture Sensitive Level
1
3
Represents a max. floor life time of unlimited
Represents a max. floor life time 168h
TQFN(4x4)ꢀ24 acge
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Revision 1.08
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AS1116
Datasheet ꢀ Electrical Characteristics
6 Electrical Characteristics
VDD = 2.7 to 5.5V, RSET = 9.53kΩ, Typical values are at TAMB = +25°C, VDD = 5.0V (unless otherwise specified). All limits are guaranteed. The
parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods.
Table 3. Electrical Characteristics
Symbol
TAMB
TJ
Parameter
Conditions
Min
ꢀ40
ꢀ40
2.7
Typ
Max
+85
+125
5.5
Unit
°C
°C
V
Operating Temperature Range
Operating Junction Temperature
Operating Supply Voltage
VDD
All digital inputs at VDD or GND,
TAMB = +25ºC
0.2
0.35
335
0.8
2
A
IDDSD
Shutdown Supply Current
RSET = open circuit.
0.6
IDD
Operating Supply Current
mA
All segments and decimal point on;
ISEG = ꢀ40mA.
0.6
320
ꢀ37
2
ꢀ47
47
kHz
mA
mA
%
fOSC
IDIGIT
ISEG
Display Scan Rate
8 digits scanned
Digit Drive Sink Current
VOUT = 0.65V
ꢀ42
3
Segment Drive Source Current
Segment Drive Current Matching
Segment Drive Source Current
VDD = 5.0V, OUT = DD ꢀ1V)
∆ISEG
ISEG
mA
age Current
Table 4. Logic Inputs/Outputs Characteristics
Symbol
Parameter
Conditions
VIN = 0V or V
4.5V < VDD < 5.5V
2.7V < VD < 4.5V
VD = 5.0V
Min
ꢀ1
Typ
Max
Unit
ꢁA
V
IIH, IIL
Input Current SDI, SCL, LD
1
0.6 x VDD
0.7 x VDD
VIH
VIL
Logic High Input Voltag
Logic Low Input Voe
V
0.8
0.6
V
V
VDD = 3.0V
SDO, ISOURCE = ꢀ1mA,
VDD = 5.0V
VDD ꢀ 1
VOH
Output High Voltage
SDO, ISOURCE = ꢀ1mA,
VDD = 3.0V
VDD ꢀ 0.5
VOL
∆VI
Output Low Voltag
Hysteresis Voltage
0.4
V
V
SDO, ISINK = 1mA
1
SDI, SCL, LD
0.7x
0.75x
0.8x
V
V
Open Detection Leel Theshold
Short Detectin Level Threshold
VDD
VDD
VDD
0.1x
VDD
0.15x
VDD
0.05x VDD
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Revision 1.08
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AS1116
Datasheet ꢀ Electrical Characteristics
Table 5. SPI Timing Characteristics
Symbol
tCP
Parameter
Conditions
Min
100
20
20
25
10
0
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
SCL Clock Period
tCH
SCL Pulse Width High
SCL Pulse Width Low
tCL
tCSS
tCSH
tDS
LD to SCL Rise Setup Time
SCL Rise to LD Rise Hold Time
SDI Setup Time
tDH
SDI Hold Time
5
tDO
Output Data Propagation Delay
LD Rising Edge to SCL Rising Edge
Minimum LD Pulse High
DataꢀtoꢀSegment Delay
CLOAD = 50pF
25
tLDCK
tCSW
tDSPD
20
20
2.25
See Figure 19 on page 10 for more information.
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Revision 1.08
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AS1116
Datasheet ꢀ Typical Operating Characteristics
7 Typical Operating Characteristics
RSET = 9.53kΩ, VRset = VDD;
Figure 3. Display Scan Rate vs. Supply Voltage;
Figure 4. Display Scan Rate vs. Temperature;
980
980
960
940
920
900
960
940
920
900
880
Vdd =2.7V
880
Tamb = - 40°C
Vdd =4V
Tamb = +25°C
Vdd =5V
860
860
Vdd =5.5V
Tamb = +85°C
840
80
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-40
-15
10
5
60
85
Vdd (V)
Tamb (°C)
Figure 5. Segment Current vs. Temperature;
re 6. Segment Current v. RSET;
60
50
Vseg = 4V; Vdd =5V
Vseg = 3V; Vdd =5V
Vseg = 2V; Vdd =5V
Vseg = 1.7V; Vdd =2.7V
50
40
30
40
30
20
10
0
20
Vseg = 1.7V; Vdd = 2.7V
Vseg = 1.7V; Vdd = 5V
10
Vseg = 3V; Vdd = 5V
Vseg = 4V; Vdd = 5V
0
-40
-15
10
35
85
0
10 20 30 40 50 60 70 80 90
Rset (kOhm)
Tamb (°)
Figure 7. Segment Current vs. Supply oltage;
Figure 8. Segment Current vs. VDD; VRset = 2.8V
60
50
Vseg =1.7V
45
40
35
30
25
20
15
10
5
Vseg =2V
Vseg =2.3V
Vseg =3.1V
50
40
30
20
10
0
Vseg = 1.7V
Vseg = 3V
Vseg = 4V
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3
3.3
3.6
3.9
4.2
Vdd (V)
Vdd (V)
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Revision 1.08
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AS1116
Datasheet ꢀ Typical Operating Characteristics
Figure 9. VDIGIT vs. IDIGIT
Figure 10. Input High Level vs. Supply Voltage
0.4
3.5
3
2.5
2
0.3
0.2
0.1
0
1.5
1
Vdd = 2.7V
Vdd = 3.3V
Vdd = 4V
Vdd = 5V
0.5
0
Vdd = 5.5V
2.7
3.1
3.5
3.9
Vdd (V)
4.3
4.7
5.1
5.5
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35
Idig (A)
Figure 11. ISEG vs. VSEG; VDD = 5V
Figure 12. ISEG vs. VSEG; VDD = 4V
50
50
Rext =10k
Rext =13k
Rext =18k
Rext =30k
Rext =56k
Rext =8k2
Rext =10k
Rext =13k
Rext =18k
Rext =30k
45
40
35
30
25
20
15
10
5
5
40
35
30
25
20
10
5
0
0
2
2.5
3
3.5
Vseg (V)
4
4.5
5
1
1.5
2
2.5
Vseg (V)
3
3.5
4
Figure 13. ISEG vs. VSEG; VDD = 3.3V
Figure 14. ISEG vs. VSEG; VDD = 2.7V
50
50
Rext =6k8
Rext =8k2
Rext =10k
Rext =13k
Rext =18k
Rext =4k7
Rext =5k6
Rext =6k8
Rext =10k
Rext =13k
45
40
35
30
25
20
1
10
5
45
40
35
30
25
20
15
10
5
0
0
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6
Vseg (V)
Vseg (V)
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Revision 1.08
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AS1116
Datasheet ꢀ Detailed Description
8 Detailed Description
Block Diagram
Figure 15. Block Diagram (QSOP-24 Package)
Open/Short
Detection
VDD
+
–
SET
19
+
–
VDD
13
Oszillator
SET
8
15-18, 20-23
SEGA-G,
SEGDP
Digital Cotrol
Logic
8
2-5, 7-10
DIG0 to DIG7
(PWM, Debunce,....)
11
LD
1
SDI
14
Registers
SPI
Interface
6
SCL
Data - Regiser
Contr- Registers
Scn - Registers
GND
24
SDO
AS1116
Figure 16. ESD Struue
valid for the pins:
- SDI
VDD
VDD
- SCL
- SDO
- LD
- ISET
valid for the pins:
- DIG0 to DIG7
- SEGA-G, SEGDP
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Revision 1.08
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AS1116
Datasheet ꢀ Detailed Description
Serial Interface
The AS1116 contains a 16bit SPI interface to access the internal data and control registers of the device (see Digit- and Control-Registers
on page 11). The SPI interface is driven with the rising edge of SCL. A falling edge on LD signal indicates the beginning of an access on the
SPI interface, the rising edge on LD determines an access on SPI. An access must consist of exactly 16bits for write operation and 8bits for read
operation. Timing restrictions on the SPI interface pins are defined in Figure 19.
Table 6 shows the structure of the 16bit command word for writing data. The bits D0 to D7 are the data information, bits D8 to D12 are the
address bits, D13 is set to ‘0’, bit D14 is defining the read (D14 = ‘1’) or the write (D14 = ‘0’) configuration and bit D15 is a don’t care bit.
In Table 7 on page 11 the 8bit command word for the read operation can be found.
Bit D0 (write operation) or bit D8 (read operation) is the first bit to shift into the SPI interface after the falling edge of LD. Bit D15 is the last bit t
write to SPI before rising edge of LD.
At a read operation an 8bit operation is executed (see Figure 18). At the first rising edge of SCL after the rising edge of LD D7 of addrese
register is written to SDO pin. At the next rising edge of SCL D6 is written to SDO pin. LD must be kept high during reading data from a inter
data or control register of AS1116.
Table 6. 16-Bit Serial Data Format
D0
D1
D2
D3
Data
D4
D5
D6
D7
D8
D9
D10
D11
D12
13
D14
D15
LSB
MSB
Register Address (see Table 7)
0
R/W
X
Figure 17. Write operation
16
1
8
9
SCL
LD
SDI
D0
D0
D1 D2 D3 D4 D5 D7
D1 D2 D3 D4 D5 D6 D7
D8
D8
D9 D10 11 DD1D14 D15
D9 D10 11 D12 D13 D14 D15
SDO
Figure 18. Read operation
16
1
8
SCL
LD
SDI
D8
D9 D10 11 2 D13 D14 D15
SDO
D7
D6 D5 D4 D3 D2 D1 D0
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Revision 1.08
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AS1116
Datasheet ꢀ Detailed Description
Figure 19. Interface Timing
LD
tCSW
tCSH
tCP
tCSS
tLDCK
tCL
tCH
SCL
SDI
t
DH
t
DS
D0
D1
D14
D15
tDO
SDO
Initial Power-Up
On initial powerꢀup, the AS1116 registers are reset to their default valudisplay is blanked, and the device goes into shutdown mode. At
this time, all registers should be programmed for normal operation.
Note: The default settings enable only scanning of one digit; the internal decoder is disabd and he Intensity Control Register (see page
15) is set to the minimum values.
Shutdown Mode
The AS1116 devices feature a shutdown mode, whre theconsume only 200n(typ) current. Shutdown mode is entered via a write to the Shutꢀ
down Register (see Table 8). For the AS1116, t that point, all segment cuent sorces and digital drivers are switched off, so that all segments
are blanked.
Note: During shutdown mode the DigitꢀRegisters maintain their d
Shutdown mode can either be used as a means to reduce poer cosumption or for generating a flashing display (repeatedly entering and leavꢀ
ing shutdown mode). For minimum supply current in shutdown mode, logic input should be at GND or VDD (CMOS logic level).
When entering or leaving shutdown mode, the FeaRegister is reset to its default values (all 0s) when Shutdown Register bit D7 (page 12) =
0.
Note: When Shutdown Register D7 = 1, the Feature Register is left unchanged when entering or leaving shutdown mode. If the AS1116
is used with an external ock, hutdown Register bit D7 should be set to 1 when writing to the Shutdown Register.
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Revision 1.08
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AS1116
Datasheet ꢀ Detailed Description
Digit- and Control-Registers
The AS1116 devices contain 8 DigitꢀRegisters,11 controlꢀregisters and 8 diagnosticꢀregisters, which are listed in Table 7. All registers are
selected using a 8ꢀbit address word, and communication is done via the serial interface.
ꢀ
ꢀ
Digit Registers – These registers are realized with an onꢀchip 64ꢀbit memory. Each digit can be controlled directly without rewriting the
whole register contents.
Control Registers – These registers consist of decode mode, display intensity, number of scanned digits, shutdown, display test and feaꢀ
tures selection registers.
Table 7. Register Address Map
Address
Register
Page
D15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D14 D13 D12 D11 D10
D9
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D7:D0
NoꢀOp
Digit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
16
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12
Digit 1
Digit 2
(see Table 10 on pae 12,
Table 11 n pae 13 and
Table 12 n pag13)
Digit 3
Digit 4
Digit 5
Digit 6
Digit 7
DecodeꢀMode
Global Intensity
Scan Limit
(se Table 9 on page 12)
(ee Table 16 on page 15)
(see Table 18 on page 15)
(see Table 8 on page 12)
15
15
Shutdown
12
Not Used
N/A
16
Feature
(see Table 19 on page 16)
(see Table 13 on page 14)
(see Table 17 on page 15)
(see Table 17 on page 15)
(see Table 17 on page 15)
(see Table 17 on page 15)
Display Test Mode
DIG0:DIG1 Intensity
DIG2:DIG3 Intensity
DIG4:DIG5 Intensity
DIG6:DIG7 Intensity
Diagnostic Digit 0
Diagnostic Digit 1
Diagnostic Digit 2
Diagnostic Digit 3
Diagnostic Digit 4
Diagnostic Digit 5
Diagnostic Dg6
Diagnostic Digit
12
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Note: Wrieration: D14=0; Read operation: D14=1.
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AS1116
Datasheet ꢀ Detailed Description
The Shutdown Register controls AS1116 shutdown mode.
Table 8. Shutdown Register Format (Address (HEX) = 0x0C))
Register Data
HEX
Code
Mode
D7 D6 D5 D4 D3 D2 D1 D0
Shutdown Mode, Reset Feature Register to Default Settings
Shutdown Mode, Feature Register Unchanged
0x00
0x80
0x01
0x81
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
Normal Operation, Reset Feature Register to Default Settings
Normal Operation, Feature Register Unchanged
Decode Enable Register (0x09)
The Decode Enable Register sets the decode mode. BCD/HEX decoding (either BCD code – characters 0:9, E, H, L, P, and ꢀ, or HEX code –
characters 0:9 and A:F) is selected by bit D2 (page 16) of the Feature Register. The Decode Enable Register is used to select the decoe mo
or noꢀdecode for each digit. Each bit in the Decode Enable Register corresponds to its respective display digit (i.e., bit D0 corresponds to igit 0,
bit D1 corresponds to digit 1 and so on). Table 10 lists some examples of the possible settings for the Decode Enable Rgister bits.
Note: A logic high enables decoding and a logic low bypasses the decoder altogether.
When decode mode is used, the decoder looks only at the lowerꢀnibble (bits D3:D0of the data in the DigitꢀRegis, diegarding bits D6:D4.
Bit D7 sets the decimal point (SEG DP) independent of the decoder and is poive loi(bit D7 = 1 turns the decimpoint on). Table 10 lists
the codeꢀB font; Table 11 lists the HEX font.
When noꢀdecode mode is selected, data bits D7:D0 of the DigitꢀRegiscorrespond to the segment lines of the AS1116. Table 12 shows the
1:1 pairing of each data bit to the appropriate segment line.
Table 9. Decode Enable Register Format Examples
Register Data
HEX
Code
Decode Mode
D7 D6 D5 D4 D3 D2 D1 D0
No decode for digit7
0x00
0x01
0x07
0x3F
0x25
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
CodeꢀB/HEX decode for digit 0. Ndecodfor digits 7:1
CodeꢀB/HEX decode for digit 0:No dcode for digits 7:3
CodeꢀB/HEX decode for digits o decode for digit
CodeꢀB/HEX decode for digits 0,2,5. No decode for digits , 7
Table 10. Code-B Font
Register Data
D7 D6:D4
Register Data
D6: D4 D3 D2 D1 D0
Register Data
D6:D4 D3 D2 D1 D0
Char-
acter
Chr-
acter
Char-
acter
D7
D7
D3 D2 D1 D0
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
X
X
X
X
X
X
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
X
X
X
X
X
1
1
1
1
X
1
1
1
1
X
0
0
1
1
X
0
1
0
1
X
1*
* The decimal point can be enabled with every character by setting bit D7 = 1.
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Revision 1.08
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AS1116
Datasheet ꢀ Detailed Description
Table 11. HEX Font
Register Data
D6:D4 D3 D2 D1 D0
Register Data
Register Data
Char-
acter
Char-
acter
Char-
acter
D7
D7
D7
D6: D4 D3 D2 D1 D0
D6:D4 D3 D2 D1 D0
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
X
X
X
X
X
X
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
X
X
X
X
X
1
1
1
1
X
1
1
1
1
X
0
0
1
X
0
1
0
1
X
1*
* The decimal point can be enabled with every character by setting bi= 1.
Table 12. No-Decode Mode Data Bits and Corresponding Segment Lines
D7
D6
D5
D4
D3
D2
D1
D0
Corresponding Segment Line
DP
A
B
D
E
F
G
Figure 20. Standard 7-Segment LED
F
A
B
C
DP
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Revision 1.08
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AS1116
Datasheet ꢀ Detailed Description
Display-Test Mode
The AS1116 can detect open or shorted LEDs. Readout of either open LEDs (D2=1) or short LEDs (D1=1) is possible, as well as a OR relation of
open and short (D1=D2=1). After a diagnostic run bit D4 can be read to clarify if an error occurred before reading out detailed diagnostic data.
Note: All settings of the digitꢀ and controlꢀregisters are maintained.
Table 13. Testmode Register Summary
D7
D6
D5
D4
D3
D2
D1
D0
X
REXT_short
REXT_open
LED_global
LED_test
LED_open
LED_short
DISP_test
Table 14. Testmode Register Bit Description (Address (HEX) = 0x0F))
Addr: 0x0F
Address
Bit
Bit Name
Default
Access
D7:D0
Optical display test. (Testmode for external visual test.)
D0
DISP_test
0
W
0: Normal operation; 1: Run display test (All digits are tested independtly
from scan limit & shutdown register.)
Starts a test for shorted LEDs. (Can be set together witD2)
0: Normal operation; 1: Activate testmode
D1
D2
D3
D4
D5
LED_short
LED_open
LED_test
0
0
0
0
0
W
W
R
Starts a test fr open LEDs. (Can be set togethewith D)
0: Normal oration; 1Activate testmode
Indicates an onging open/short LED test
0: No LED test; 1: LED st in progress
Indicatthat the last open/short LEtest has detected an error
0: No error detected; 1: Errodeteted
LED_global
REXT_open
REXT_short
R
Cecks if external resistor RET is open
0: REXT correct; 1: T is open
R
Checks if externresistor REXT is shorted
0: REXT corrt; 1: REXT is shorted
D6
D7
0
0
R
ꢀ
Not used
LED Diagnostic Registers
These eight registers contain the result of the LED open/shortest fthe individual LED of each digit.
Table 15. LED Diagnostic Register Address
Register
HEX
Address
Segme
Register
HEX
Address
Segment
Digit D7 D6 D5 D4 DD2 D1 D0
Digit D7 D6 D5 D4 D3 D2 D1 D0
DIG0
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
DP
A
B
C
D
E
F
G
DP
A
B
C
D
E
F
G
Note: If more than 2 horts occure in the LED array, detection of individual LED fault could become limited to blocs.
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Revision 1.08
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AS1116
Datasheet ꢀ Detailed Description
Intensity Control Register (0x0A)
The brightness of the display can be controlled by digital means using the Intensity Control Registers and by analog means using RSET (see
Selecting RSET Resistor Value and Using External Drivers on page 17). The intensity can be controlled globally for all digits, or
for each digit individually. The global intensity command will write intensity data to all four individual brightness registers, while the individual
intesity command will only write to the associated individual intensity register.
Display brightness is controlled by an integrated pulseꢀwidth modulator which is controlled by the lowerꢀnibble of the Intensity Control Register.
The modulator scales the average segmentꢀcurrent in 16 steps from a maximum of 15/16 down to 1/16 of the peak current set by RSET.
Table 16. Intensity Register Format
Register Data
Register Data
Duty Cycle
HEX Code
Duty Cycle
HEX Code
MSB
D2
0
D1
0
LSB
0
1
0
1
0
1
0
1
MSB
D2
0
D1
0
LSB
0
0
1
0
1
0
1
1/16 (min on)
2/16
0xX0
0xX1
0xX2
0xX3
0xX4
0xX5
0xX6
0xX7
0
0
0
0
0
0
0
0
9/16
10/16
11/16
12/16
13/16
0xX8
0xX9
0xXA
0xXB
0xXC
0xXD
0xXE
0xXF
1
1
1
1
1
1
0
0
0
0
3/16
4/16
5/16
6/16
7/16
8/16
0
1
0
1
0
1
0
1
1
0
1
0
1
0
14/16
15/16
1
0
1
1
1
1
1
1
15/6 (max on)
1
1
Table 17. Intensity Register Address
ister Data
Register HEX Address
Type
Global
Digit
Digit
Digit
D7:D4
X
Digit 1 Intensity
Digit 3 Inity
DigInteity
Digit 7 Itensity
D3:D0
0x0A
0x10
0x11
0x12
0x13
Global Intensity
Digit 0 Intensity
Digit 2 Intensity
Digit 4 Intensity
Digit 6 Intensity
Dig
Scan-Limit Register (0x0B)
The ScanꢀLimit Register controls which of the digits are to be displaen all 8 digits are to be displayed, the update frequency is typically
0.8kHz. If the number of digits displayed is reduced, the updae frequency is increased. The frequency can be calculated using 8fOSC/N, where
N is the number of digits. Since the number of displayed digitinfluces the brightness, RSET should be adjusted accordingly.
Note: To avoid differences in brightness this registeshould not be used to blank parts of the display (leading zeros).
Table 18. Scan-Limit Register Format (Address (H= 0x0B))
gister Data
Register Data
HEX
Cod
HEX
Code
Scan Limit
Scan Limit
DD3 D2 D1 D0
D7:D3 D2 D1 D0
Display digit 0 only
Display digits 0:1
Display digits 0:2
Display dig03
00
0xX1
0xX2
0xX3
X
X
X
X
0
0
0
0
0
0
1
1
0
1
0
1
Display digits 0:4
Display digits 0:5
Display digits 0:6
Display digits 0:7
0xX4
0xX5
0xX6
0xX7
X
X
X
X
1
1
1
1
0
0
1
1
0
1
0
1
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Revision 1.08
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AS1116
Datasheet ꢀ Detailed Description
Feature Register (0x0E)
The Feature Register is used for enabling various features including switching the device into external clock mode, applying an external reset,
selecting codeꢀB or HEX decoding, enabling or disabling blinking, enabling or disabling the SPIꢀcompatible interface, setting the blinking rate,
and resetting the blink timing.
Note: At powerꢀup the Feature Register is initialized to 0.
Table 19. Feature Register Summary
D7
D6
D5
D4
D3
D2
D1
D0
blink_start
sync
blink_freq_sel
blink_en
NU
decode_sel
reg_res
clk_en
Table 20. Feature Register Bit Descriptions (Address (HEX) = 0xXE)
Feature Register
Addr: 0xXE
Enables and disables various device features.
Bit
Bit Name
Default
Access
Bit Description
External clock active.
D0
clk_en
0
R/W
0 = Internal oscillator is used for system clock.
1 = Pin CLK of the serial interface operates as system clock inut.
Resets all control registrs except the Feature Register.
0 = Reset Disabled. Nmal opetion.
D1
reg_res
0
0
R/W
R/W
1 = All control registers ae rest to default state (exet thFeature Register)
identically after rꢀup.
Note: The DiRegisters maintain teir data.
Selects display deoding for the selected igits (Table 9 on page 12).
0 = Enable CodeꢀB decoding (see Tale 10 on page 12).
1 = Eable EX decoding (see le 1on page 13).
Noused
Enables blinking.
0 = Disable blinking. 1 = nable blinking.
Sets blink with low fquency (with the internal oscillator enabled):
0 = Blink periicallis 1 second (0.5s on, 0.5s off).
1 = Blink peseconds (1s on, 1s off).
D2
decode_sel
D3
D4
NU
blink_en
0
0
R/W
D5 blink_freq_sel
Synchonizes blinking on the rising edge of pin LD. The multiplex and blink timing
countis clared on the rising edge of pin LD. By setting this bit in multiple devices, the
blink timing can be synchronized across all the devices.
tart Blinking with display enabled phase. When bit D4 (blink_en) is set, bit D7
determines how blinking starts.
D6
D7
sync
0
0
R/W
RW
blink_start
0 = Blinking starts with the display turned off.
1 = Blinking starts with the display turned on.
No-Op Register (0xX0)
The NoꢀOp Register is used whn multiple AS1116 devices are cascaded in order to support displays with more than 8 digits. The cascading
must be done in suca way at all SDO pins are connected to SDI of the next AS1116 (see Figure 21 on page 18). The LD and SCL sigꢀ
nals are connected to aldevices.
For example, if fe devces are cascaded, in order to perform a write operation to the fifth device, the writeꢀcommand must be followed by four
noꢀoperation commands. When the LD signal goes high, all shift registers are latched. The first four devices will receive noꢀoperation commands
and only ifth device will receive the intended operation command, and subsequently update its register.
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Revision 1.08
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AS1116
Datasheet ꢀ Typical Application
9 Typical Application
Selecting RSET Resistor Value and Using External Drivers
Brightness of the display segments is controlled via RSET. The current that flows between VDD and ISET defines the current that flows through
the LEDs.
Segment current is about 200 times the current in ISET. Typical values for RSET for different segment currents, operating voltages, and LED voltꢀ
age drop (VLED) are given in Table 21 & Table 22. The maximum current the AS1116 can drive is 47mA. If higher currents are needed, exterꢀ
nal drivers must be used, in which case it is no longer necessary that the devices drive high currents.
Note: The display brightness can also be logically controlled (see Intensity Control Register (0x0A) on page 15).
Table 21. RSET vs. Segment Current and LED Forward Voltage, VDD = 2.7V & 3.3V & 3.6V
VLED
VLED
2.0V
VLED
ISEG (mA)
1.5V
5kΩ
2.0V
4.4kΩ
5.9kΩ
9.6kΩ
20.7kΩ
1.5V
6.7kΩ
9.1kΩ
13.9kΩ
28.8kΩ
2.5V
5.7kΩ
8.1kΩ
12.6kΩ
26kΩ
1.5V
7.5kΩ
2.0V
2.5V
.6kΩ
9.2Ω
13kΩ
29.5kΩ
0V
5.5kΩ
7.5kΩ
13kΩ
40
30
20
10
6.4kΩ
8.8kΩ
7.2kΩ
9.8kΩ
15kΩ
3
6.9kΩ
10.7kΩ
22.2kΩ
10.18kΩ
15.6kΩ
31.9kΩ
13.3kΩ
27.7kΩ
27.3kΩ
Table 22. RSET vs. Segment Current and LED Forward Voltage, VDD = 4.0V 5.0V
VLED
2.5V
VLED
2.5V
ISEG
(mA)
1.5V
2.0V
3.0V
7.6kΩ
9.9kΩ
3.5V
5.2kΩ
7.8kΩ
1.5V
2.0V
3.0V
3.5V
4.0V
40
30
20
10
8.6kΩ
11.6kΩ
17.7kΩ
8.3kΩ
11.2kΩ
17.3kΩ
7.9kΩ
11.35kΩ 11.12Ω 10.84kΩ 10.49kΩ 10.2kΩ 9.9kΩ
10.8kΩ
15.4kΩ
23.6kΩ
48.Ω
15.1Ω
.1kΩ
47.kΩ
14.7kΩ
22.6kΩ
46.9kΩ
14.4kΩ 13.6kΩ 13.1kΩ
22kΩ 21.1kΩ 20.2kΩ
16.6kΩ 15.6kΩ 13.6kΩ
34.5kΩ 32.5Ω 29.1kΩ
36.89kΩ 35.7kΩ
45.4kΩ 43.8kΩ 42kΩ
Calculating Power Dissipation
The upper limit for power dissipation (PD) for tAS1116 is determithe following equation:
PD = (VDD x 5mA) + VDD - VLED)(DUTY x ISEG x N)
(EQ 1)
Where:
VDD is the supply voltage.
DUTY is the duty cycle set by intensity register pa15).
N is the number of segments driven (worst case is
VLED is the LED forward voltage
ISEG = segment current set by RSET
Dissipation Example:
IEG = 40mA, N = 8, DUTY = 15/16, VLED = 2.2V at 40mA, VDD = 5V
PD = 5V(5mA) + (5V - 2.2V)(15/16 x 40mA x 8) = 0.865W
(EQ 2)
(EQ 3)
Thus, for a QSOꢀ24 pckage ΘJA = +88°C/W, the maximum allowed TAMB is given by:
TJ,MAX = TAMB + PD x
Θ
JA = 150°C = TAMB + 0.865W x 88°C/W
(EQ 4)
In thiexample the maximum ambient temperature must stay below 73.88°C.
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Revision 1.08
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AS1116
Datasheet ꢀ Typical Application
8x8 Dot Matrix Mode
The application example in Figure 21 shows the AS1116 in the 8x8 LED dot matrix mode.
The LED columns have common cathodes and are connected to the DIG0:7 outputs. The rows are connected to the segment drivers. Each of
the 64 LEDs can be addressed separately. The columns are selected via the digits as listed in Table 7 on page 11.
The Decode Enable Register (see page 12) must be set to ‘00000000’ as described in Table 9 on page 12. Single LEDs in a column can
be addressed as described in Table 12 on page 13, where bit D0 corresponds to segment G and bit D7 corresponds to segment DP.
Note: For a multipleꢀdigit dot matrix, multiple AS1116 devices can be cascaded easily.
Figure 21. Application Example as LED Dot Matrix Driver
DIG0 to
DIG7
V
DD
2.7 to 5V
9.53kΩ
SEG A to G
SEP DP
I
SET
SDI
AS1116
I/O
SCL
LD
Diode Arngemnt
I/O
I/O
µP
SDO
I/O
GND
Diagnostic
readback: open
& shorted LEDs
Supply Bypassing and Wiring
In order to achieve optimal performance the AS1116 should be placclose to the LED display to minimize effects of electromagnetic interꢀ
ference and wiring inductance.
Furthermore, it is recommended to connect a 10ꢁF electrolytiand a 0.1ꢁF ceramic capacitor between pins VDD and GND to avoid power supꢀ
ply ripple (see Figure 21 on page 18).
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AS1116
Datasheet ꢀ Package Drawings and Markings
10 Package Drawings and Markings
Figure 22. QSOP-24 Marking
Figure 23. TQFN(4x4)-24 Marking
Table 23. Packaging Code
YY
WW
R / X
ZZ
manufacring eek
last two digits of the current year
plant identifier
free choice / traceability code
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Revision 1.08
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AS1116
Datasheet ꢀ Package Drawings and Markings
Figure 24. QSOP-24 Package
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Revision 1.08
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AS1116
Datasheet ꢀ Package Drawings and Markings
Figure 25. TQFN(4x4)-24 Package
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Revision 1.08
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AS1116
Datasheet ꢀ Ordering Information
11 Ordering Information
The devices are available as the standard products shown in Table 24.
Table 24. Ordering Information
Ordering Code
AS1116ꢀBSST
AS1116ꢀBQFT
Marking
AS1116
ASR9
Description
Delivery Form
Tape and Reel
Tape and Reel
Package
QSOPꢀ24
64 LED Driver with Detailed Error Detection
64 LED Driver with Detailed Error Detection
TQFN(4x4)ꢀ24
Note: All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
Technical Support is found at http://www.austriamicrosystems.com/TechnicalꢀSupport
For further information and requests, please contact us mailto:sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
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AS1116
Datasheet
Copyrights
Copyright © 1997ꢀ2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, AustriaꢀEurope. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and pries
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG fo
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature rage,
unusual environmental requirements, or high reliability applications, such as military, medical lifeꢀsupport or lifeꢀsustaining equipment ar
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamirosysms AG shall not
be liable to recipient or any third party for any damages, including but not limiteto personal injury, property dam, loss f profits, loss of use,
interruption of business or indirect, special, incidental or consequential damags, of any nd, in connection with or aring out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recipnt or any third party shall rie oflow out of
austriamicrosystems AG rendering of technical or other services.
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Tobelbaderstrasse 30
Aꢀ8141 Unterpremstaten, Astria
Tel: +43 (0) 3136 500 0
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