AS1118 [AMSCO]
64 LED Dr iver for Mobi le Appl ications wi th Er ror Detect ion; 64 LED医生艾弗的牧高笛乐APPL ications的Wi日尔ROR离子检测
| 型号： | AS1118 |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | 64 LED Dr iver for Mobi le Appl ications wi th Er ror Detect ion |
| 文件： | 总21页 (文件大小：1779K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Datasheet
AS1118
64 LED Driver for Mobile Applications with Error Detection
1 General Description
2 Key Features
ꢀ
10MHz SPI-Compatible Interface
The AS1118 is a compact LED driver for 64 single LEDs
or 8 digits of 7-segments. The devices can be pro-
grammed via an SPI compatible 3-wire interface. Every
segment can be individually addressed and updated
separately. Only one external resistor (RSET) is required
to set the current. LED brightness can be controlled by
analog or digital means. The devices include an inte-
grated BCD code-B/HEX decoder, multiplex scan cir-
cuitry, segment and display drivers, and a 64-bit
memory. Internal memory stores the shift register set-
tings, eliminating the need for continuous device repro-
gramming.
ꢀ
Open and Shorted LED Error Detection
- Global or Individual Error Detection
ꢀ
ꢀ
Hexadecimal- or BCD-Code for 7-Segment Display
200nA Low-Power Shutdown Current (typ; data
retained)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Individual Digit Brightness Control
Digital and Analog Brightness Control
Display Blanked on Power-Up
Drive Common-Cathode LED Dislays
Supply Voltage Range: 2.7V to .5V
Softre and Hardware Rest
Optional External Clock
Table 1. Available Products
Devices
AS1115
AS1116
AS1117
AS1118
RESET Input
Interfaces
I²C
no
no
Package: TQFN(4x4)-24
SPI
yes
yes
I²C
3 Applications
SPI
The AS18 is ideal for seven-segment or dot matrix dis-
plays mobile applications, public information displays
at sbway, train or bus stations, at airports and also at
isplas in public transportation like buses or trains, per-
soal electronic and toys.
,
Additionally the AS1118 offers a detailed errodiagostic
mode for easy and fast production testing n crical
applications. The AS1118 features a low shtdown cur-
rent of typically 200nA, and an operaticurrent of
typically 350µA. The number of digits n be pro-
grammed, the devices can be reset by software, and an
external clock is also supported. The device is avalable
in a TQFN(4x4)-24 package.
Figure 1. AS1118 - Typical Application Diagra
8
DIG0to
SGA-DP
VDD
DIG7
V
DD
8
8
8
8
2.7V to 5V
9.53kΩ
GND
ISET
SDI
AS1118
AS1118
AS1118
SDI
SDO
SDO
SDO
SDI
I/O
LD
LD
LD
SCL
RESETN
RESETN
RESETN
SCL
SCL
I/O
µP
I/O
I/O
I/O
Diagnostic readback: open & shorted LEDs
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Revision 1.01
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AS1118
Datasheet - Pinout
4 Pinout
Pin Assignments
Figure 2. Pin Assignments (Top View)
24 23 22 21 20 19
DIG2
DIG3
GND
DIG4
DIG5
1
2
3
4
5
6
18 SEG E
17 SEGC
16 VDD
AS1118
15 SEGG
14 SEGB
13 SEGF
RESETN
7
8
9
10 11 12
Pin Descriptions
Table 2. Pin Descriptions
Pin Name
TQFN(4x4)-24
scription
Serial-ata Iput. Data is loed into the internal 16-bit shift register on the
risinedgof pin SCL.
22
SDI
Dgit Drive Lines. Eighdigit rive lines that sink current from the display
cde.
1, 2, 4, 5, 7, 8, 23,
24
DIG0:DIG7
GND
3
Ground.
Load. Serial Data is laded into the shift register while this pin is low. The last
16 bits of seral daa are latched on the rising edge of this pin.
ReseInput. Pull this pin to low to resest all registers (set to default values) and
to put te device into shutdown.
9
LD
6
RESETN
Set gment Current. Connect to VDD or a reference voltage through RSET to
set tpeak segment current (see Selecting RSET Resistor Value and Using
External Drivers on page 15).
10
ISET
Srial-Clock Input. 10MHz maximum rate. Data is shifted into the internal shift
register on the rising edge of this pin. Data is clocked out of pin SDO on the
rising edge of this pin.
11
SCL
Seven Segment and Decimal Point Drive Lines. 8 seven-segment drives and
decimal point drive that source current to the display.
SEGA:SEGG,
SEGDP
1215,
17-20
Positive Supply Voltage. Connect to +2.7V to +5.5V supply. Bypass this pin to
GND with a 10µF and a 0.1µF capacitor to avoid power supply ripple.
16
VDD
Serial-Data Output. The data into pin SDI is valid at pin SDO 16 clock cycles
later. This pin is used to daisy-chain several devices and is never high-
impedance.
21
S
Exposed Pad. This pin also functions as a heat sink. Solder it to a large pad or
to the circuit-board ground plane to maximize power dissipation.
Exposed Pad
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Revision 1.01
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AS1118
Datasheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Section 6 Electrical
Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 3. Absolute Maximum Ratings
Parameter
Min
Max
Units
Notes
Electrical Parameters
VDD to GND
-0.3
-0.3
7
V
V
Input Voltage Range
7 or
VDD + 0.3
All other pins to GND
DIG0:DIG7 Sink Current
SEGA:SEGG, SEGDP
500
100
mA
mA
mA
Current
Input Current (latch-up immunity)
±100
Norm: JEEC 7
Norm: MIL 833 E method 3015
on PCB
Electrostatic Discharge
Electrostatic Discharge
Thermal Information
Digital outputs
All other pins
000
100
V
V
Thermal Resistance ΘJA
30.5
ºC/W
Temperature Ranges and Storage Conditions
Junction Temperature
+150
+150
°C
ºC
Storage Temperature
-55
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020 “Moisture/Reflow
Sensitivity Classification for Non-Hermetic
Solid State Surface Mount Devices”.
The lead finish for Pb-free leaded packages
is matte tin (100% Sn).
Package Body Temperatur
+260
85
ºC
Humidity non-condensing
Moisture Sensitive Level
5
%
%
3
Represents a max. floor life time of 168h
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Revision 1.01
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AS1118
Datasheet - Electrical Characteristics
6 Electrical Characteristics
VDD = 2.7V to 5.5V, RSET = 9.53k
Ω, TAMB = -40°C to +85°C, typ. values @ TAMB = +25ºC and VDD = 5.0V (unless oth-
erwise specified).
Table 4. Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ Max
Unit
2.7
5.5
V
VDD
Operating Supply Voltage
Shutdown Supply Current
All digital inputs at VDD or
GND, TAMB = +25ºC
0.2
0.35
335
0.8
2
µA
IDDSD
RSET = open circuit.
0.6
IDD
Operating Supply Current
mA
All segments and decimal
point on; ISEG = -40mA.
0.6
320
-37
1.2
-7
47
Hz
mA
mA
%
fOSC
IDIGIT
ISEG
Display Scan Rate
8 digits scanned
VOUT = 0.65V
Digit Drive Sink Current
-42
Segment Drive Source Current
Segment Drive Current Matching
Segment Drive Source Current
VDD = 5.0V, VOUT = (VDD -1V)
Averge Crnt
∆ISEG
ISEG
mA
Table 5. Logic Inputs/Outputs Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IIH, IIL
Input Current SDI, SCL, LD
-1
1
µA
VIN = 0V or VDD
Logic High Input Voltage
SDI, SCL, LD, RESETN
VIH
VIL
1.26
V
V
Logic Low Input Voltage
SDI, SCL, LD, RESETN
0.54
0.4
SDO, ISOUE = -1mA,
VD = 5.0V
VDD - 1
VOH
Output High Vol
V
SOURCE = -1mA,
VDD = 3.0V
VDD - 0.5
VOL
Output Low Voltage
Hysteresis Voltage
V
V
SDO, ISINK = 1mA
SDI, SCL, LD
∆VI
1
0.7x
VDD
0.75x 0.8x
V
V
Open Detection Level Threshd
Short Detection Level Thhold
VDD
VDD
0.1x 0.15x
0.05x VDD
VDD
VDD
Table 6. SPI Timing Characteriscs
Symbol
tCP
Parameter
Conditions
Min
100
20
20
25
10
0
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
SCL Clock Period
SCL Pulse Width High
SCL Pulse Width Low
LD to SCL Rise Setup Time
tCH
tCL
tCSS
tCS
tDS
SCL Rise to LD Rise Hold Time
SDI Setup Time
H
SDI Hold Time
5
tDO
Output Data Propagation Delay
LD Rising Edge to SCL Rising Edge
Minimum LD Pulse High
Data-to-Segment Delay
CLOAD = 50pF
25
tLDCK
tCSW
tDSPD
20
20
2.25
See Figure 18 on page 8 for more information.
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Revision 1.01
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AS1118
Datasheet - Typical Operating Characteristics
7 Typical Operating Characteristics
RSET = 9.53kΩ, VRset = VDD;
Figure 3. Display Scan Rate vs. Supply Voltage;
Figure 4. Display Scan Rate vs. Temperature;
980
980
960
940
920
900
880
860
80
960
940
920
900
880
Vdd =2.7V
Vdd =4V
Vdd =5V
Tamb = - 40°C
Tamb = +25°C
860
Vdd =5.5V
Tamb = +85°C
840
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-40
-15
10
5
60
85
Vdd (V)
Tamb (°C)
Figure 5. Segment Current vs. Temperature;
ure 6. Segment Curent vs. RSET;
60
50
Vseg = 4V; Vdd =5V
Vseg = 3V; Vdd =5V
Vseg = 2V; Vdd =5V
Vseg = 1.7V; Vdd =2.7V
50
40
30
40
30
20
10
0
20
Vseg = 1.7V; Vdd = 2.7V
Vseg = 1.7V; Vdd = 5V
10
Vseg = 3V; Vdd = 5V
Vseg = 4V; Vdd = 5V
0
-40
-15
10
35
85
0
10 20 30 40 50 60 70 80 90
Rset (kOhm)
Tamb (°)
Figure 7. Segment Current vs. upply Voltage;
Figure 8. Segment Current vs. VDD; VRset = 2.8V
60
50
Vseg =1.7V
45
Vseg =2V
50
40
30
20
Vseg =2.3V
40
Vseg =3.1V
35
30
25
20
15
10
5
Vseg = 1.7V
Vseg = 3V
Vseg = 4V
10
0
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3
3.3
3.6
3.9
4.2
Vdd (V)
Vdd (V)
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Revision 1.01
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AS1118
Datasheet - Typical Operating Characteristics
Figure 9. VDIGIT vs. IDIGIT
Figure 10. Input High Level vs. Supply Voltage
0.4
3.5
3
2.5
2
0.3
0.2
1.5
1
Vdd = 2.7V
0.1
0
Vdd = 3.3V
Vdd = 4V
Vdd = 5V
0.5
0
Vdd = 5.5V
2.7
3.1
3.5
3.9
Vdd (V)
4.3
4.7
5.1
5.5
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35
Idig (A)
Figure 11. ISEG vs. VSEG; VDD = 5V
Figur12. ISG vs. VSEG; VDD = 4V
50
50
Rext =10k
Rext =13k
Rext =18k
Rext =30k
Rext =56k
Rext =8k2
Rext =10k
Rext =13k
Rext =18k
Rext =30k
45
40
35
30
25
20
15
10
5
5
40
35
30
25
20
10
5
0
0
2
2.5
3
3.5
4
4.5
5
1
1.5
2
2.5
3
3.5
4
Vseg (V)
Vseg (V)
Figure 13. ISEG vs. VSEG; VDD = 33V
Figure 14. ISEG vs. VSEG; VDD = 2.7V
50
50
Rext =6k8
Rext =8k2
Rext =10k
Rext =13k
Rext =18k
Rext =4k7
Rext =5k6
Rext =6k8
Rext =10k
Rext =13k
45
40
35
30
25
20
1
10
5
45
40
35
30
25
20
15
10
5
0
0
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6
Vseg (V)
Vseg (V)
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AS1118
Datasheet - Detailed Description
8 Detailed Description
Block Diagram
Figure 15. AS1118 - Block Diagram
Open/Short
Detection
16
VDD
RSET
VDD
+
–
100nF
+
–
10
Oszillator
ISET
12-15, 17-20
6
SEGA-G,
SEGDP
Digital Control
Logic
RESETN
8
2-5, 7-10
DIG0 to DIG7
(PWM, Dboune,....)
9
LD
22
SDI
11
Registers
SPI
Interface
3
SCL
Data - Regsters
Conrol - Registers
Scan Registers
GND
21
SDO
AS1118
Figure 16. ESD Structure
valid for the pins:
- SDI
VDD
VDD
- SCL
- SDO
- LD
- ISET
valid for the pins:
- DIG0 to DIG7
- SEGA-G, SEGDP
- RESETN
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Revision 1.01
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AS1118
Datasheet - Detailed Description
Serial-Addressing Format
The AS1118 contains a 16bit SPI interface to access the internal data and control registers of the device (see Digit-
and Control-Registers on page 9). The SPI interface is driven with the rising edge of SCL. A falling edge on LD signal
indicates the beginning of an access on the SPI interface, the rising edge on LD determines an access on SPI. An
access must consist of exactly 16bits for write operation and 8bits for read operation. Timing restrictions on the SPI
interface pins are defined in Figure 18.
Table 7 shows the structure of the 16bit command word for writing data, Table 8 the 8bit command word for read oper-
ation.
D0 (write operation) / D8 (read operation) is the first bit to shift into the SPI interface after the falling edge of LD, is the
last bit to write to SPI before rising edge of LD.
At a read operation an 8bit operation is executed. At the first rising edge of SCL after the rising edge of LD D7 of
addressed register is written to SDO pin. At the next rising edge of SCL D6 is written to SDO pin. LD must be kept hi
during reading data from a internal data or control register of AS1118.
Table 7. 16-Bit Serial Data Format
D0
D1
D2
D3
Data
D4
D5
D6
D7
D8
D9
D10
D11
D12 D13 D14 D15
R/W
LSB
MSB
Register Address (see Table 8)
0
X
Figure 17. Read operation
16
1
8
9
10
SCL
LD
SDO
D
D6 D5 D4 D3 D1 D0
Figure 18. Interface Timing
LD
tCSW
tCSH
tCP
tCSS
tLDCK
tCL
tC
SCL
SDI
t
DH
t
DS
D
D1
D14
D15
tDO
SDO
Initial Power-Up
On inital power-up, the AS1118 registers are reset to their default values, the display is blanked, and the device goes
into shutdown mode. At this time, all registers should be programmed for normal operation.
Note: The default settings enable only scanning of one digit; the internal decoder is disabled and the Intensity Control
Register (see page 13) is set to the minimum values.
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AS1118
Datasheet - Detailed Description
Shutdown Mode
The AS1118 devices feature a shutdown mode, where they consume only 200nA (typ) current. Shutdown mode is
entered via a write to the Shutdown Register (see Table 9) or via pulling the pin RESTEN to logic low. When pin
RESETN is set to logic low an according write to the Shutdown Register is done internally.
For the AS1118, at that point, all segment current sources and digital drivers are switched off, so that all segments are
blanked. During shutdown mode the Digit-Registers maintain their data.
Note: When pin RESETN is pulled to logic high again, a write to the Shutdown Register in necessary to leave the
shutdown mode.
Shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display
(repeatedly entering and leaving shutdown mode). For minimum supply current in shutdown mode, logic input shoul
be at GND or VDD (CMOS logic level).
When entering or leaving shutdown mode, the Feature Register is reset to its default values (all 0s) when Shutdwn
Register bit D7 (page 10) = 0.
Note: When Shutdown Register bit D7 = 1, the Feature Register is left unchanged when entering oleaving shut-
down mode. If the AS1118 is used with an external clock, Sutdown Register bit D7 oulbe set to 1 when
writing to the Shutdown Register.
Digit- and Control-Registers
The AS1118 devices contain 8 Digit-Registers,11 control-reers and 8 diagnosregisters, which are listed in Table
8. All registers are selected using a 8-bit address word, and ommunication is done vthe serial interface.
ꢀ
Digit Registers – These registers are realized with an on-chip 64-bit meory. Each digit can be controlled directly
without rewriting the whole register contents.
ꢀ
Control Registers – These registers consst f decode mode, isplaintnsity, number of scanned digits, shut-
down, display test and features selection egisters.
Table 8. Register Address Map
Address
D15 D14 D13 D12 D110 D9
Register
Page
D8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D7:D0
No-Op
Digit 0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
14
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
10
Digit 1
0
Digit 2
0
(see Table 11 on page 11,
Table 12 on page 11 and
Table 13 on page 11)
Digit 3
0
Digit 4
0
Digit 5
0
Digit 6
0
Digit 7
0
Decode-Moe
Global ntensity
Scan imit
hudown
0
(see Table 10 on page 10)
(see Table 17 on page 13)
(see Table 19 on page 13)
(see Table 9 on page 10)
0
13
0
13
0
9
Not Used
0
N/A
14
Feature
0/1
0
(see Table 20 on page 14)
(see Table 14 on page 12)
(see Table 18 on page 13)
(see Table 18 on page 13)
(see Table 18 on page 13)
(see Table 18 on page 13)
Display Test Mode
DIG0:DIG1 Intensity
DIG2:DIG3 Intensity
DIG4:DIG5 Intensity
DIG6:DIG7 Intensity
10
0
0
0
0
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AS1118
Datasheet - Detailed Description
Table 8. Register Address Map
Address
D15 D14 D13 D12 D11 D10 D9
Register
Page
D8
0
D7:D0
Diagnostic Digit 0
Diagnostic Digit 1
Diagnostic Digit 2
Diagnostic Digit 3
Diagnostic Digit 4
Diagnostic Digit 5
Diagnostic Digit 6
Diagnostic Digit 7
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/
1
0
1
0
1
0
1
Note: Write operation: D14=0; Read operation: D14=1.
The Shutdown Register controls AS1118 shutdown mode.
Table 9. Shutdown Register Format (Address (HEX) = 0x0C))
Rester Data
HEX
ode
Mode
D7 D6 D5 D4 D3 D2 D1 D0
Shutdown Mode, Reset Feature Register to Default ttings
Shutdown Mode, Feature Register Unchanged
0x00
0x80
0x01
0x8
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
Normal Operation, Reset Feature Register to Default Stings
Normal Operation, Feature Register Unchanged
Decode Enable Register (0x09)
The Decode Enable Register sets the decode mode. BCD/HEX decoing (either BCD code – characters 0:9, E, H, L,
P, and -, or HEX code – characters 0:9 anA:F) is selected by bit 2 (page 14) of the Feature Register. The Decode
Enable Register is used to select thdode mode or no-decde for each digit. Each bit in the Decode Enable Regis-
ter corresponds to its respective displigit (i.e., bit D0 esponds to digit 0, bit D1 corresponds to digit 1 and so
on). Table 11 lists some examples of the possible settinhe Decode Enable Register bits.
Note: A logic high enables decoding and a logic ow bpasses the decoder altogether.
When decode mode is used, the decoder loks only at the lower-nibble (bits D3:D0) of the data in the Digit-Registers,
disregarding bits D6:D4. Bit D7 sets the deciml point (SEG DP) independent of the decoder and is positive logic (bit
D7 = 1 turns the decimal point on). Tabe 1ists the code-B font; Table 12 lists the HEX font.
When no-decode mode is selected, data s D7:D0 of the Digit-Registers correspond to the segment lines of the
AS1118. Table 13 shows the 1:1 piring of each data bit to the appropriate segment line.
Table 10. Decode Enable Rgistr Format Examples
Register Data
HEX
Code
Decode Mode
D7 D6 D5 D4 D3 D2 D1 D0
No decode for digits 7:0
0x00
0x01
0x07
0x3F
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
CodeB/HEX decode for digit 0. No decode for digits 7:1
Code-BHEX decode for digit 0:2. No decode for digits 7:3
C-B/HEX decode for digits 0:5. No decode for digits 7:6
ode-BEX decode for digits 0,2,5. No decode for digits 1, 3, 4, 6, 7 0x25
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Revision 1.01
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AS1118
Datasheet - Detailed Description
Table 11. Code-B Font
Register Data
Char-
Register Data
Register Data
Char-
acter
Char-
acter
acter
D7
D7
D7
D6:D4 D3 D2 D1 D0
D6:D4 D3 D2 D1 D0
D6:D4 D3 D2 D1 D0
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
X
X
X
X
X
X
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
X
X
X
X
X
1
1
1
1
X
1
1
1
1
X
0
0
1
X
0
1
0
1
X
1*
* The decimal point can be enabled with every character etting bit D7 = 1.
Table 12. HEX Font
Register Data
Regiter Data
Register Data
D6:D4 D3 D2 D1 D0
Char-
acter
Char-
acter
Car-
acter
D7
D7
D7
D6:D4 D3 D2 D1 D0
D6:D4 D3 D2 D1 D0
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
X
X
X
X
X
X
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
1
0
1
0
1
X
X
X
X
X
1
1
1
1
X
1
1
1
1
X
0
0
1
1
X
0
1
0
1
X
1*
* The decimal pnt cabe enabled with every character by setting bit D7 = 1.
Table 13. NoDecode Mode Data Bits and Corresponding Segment Lines
D7
D6
D5
D4
D3
D2
D1
D0
Correonng Segment Line
DP
A
B
C
D
E
F
G
Figure 19. Standard 7-Segment LED
F
A
G
B
E
C
D
DP
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AS1118
Datasheet - Detailed Description
Display-Test Mode
The AS1118 can detect open or shorted LEDs. Readout of either open LEDs (D2=1) or short LEDs (D1=1) is possible,
as well as a OR relation of open and short (D1=D2=1). After a dignostic run bit D4 can be read to clearify if an error
occurred before reading out detailed diagnostic data.
Note: All settings of the digit- and control-registers are maintained.
Table 14. Testmode Register Summary
D7
D6
D5
D4
D3
D2
D1
D0
X
REXT_short REXT_open
LED_global
LED_test
LED_open
LED_short
DISP_test
Table 15. Testmode Register Bit Description (Address (HEX) = 0x0F))
Addr: 0x0F
Address
Bit
Bit Name
Default Access
D7:D0
Optical display test. (Testmode for external visual test.)
0: Normal operation; 1: Run display test (All digts are tested
independently from scan limit & shutdown reister)
D0
DISP_test
0
W
Starts a test for shorted LEDs. (Can be set ogeer with D2)
0: Normal operation; 1: Activate testme
D1
D2
D3
D4
D5
LED_short
LED_open
LED_test
0
0
0
0
0
W
W
R
Starts a tet for opn LEDs. (Can be set toether with D1)
0: Normal oeraton; 1: Activate tetmoe
Indin ongoing openshort LED test
0: No ngoing LED test; 1: LD test in progress
Indicates that the last openhort LED test has detected an error
0: No error detected; 1: rror detected
LED_global
REXT_open
REXT_short
R
Checks if externsistor REXT is open
0: REXT corrt; 1: RXT is open
R
Checks if ternresistor REXT is shorted
0: REXT orret; 1: REXT is shorted
D6
D7
0
0
R
-
Nod
LED Diagnostic Registers
These eight registers contain the result of he LED open/short test for the individual LED of each digit.
Table 16. LED Diagnostic Register Address
Register
HEX
Address
Segme
Register
HEX
Address
Segment
Digit D7 D6 D5 D4 D3 D2 D1 D0
Digit D7 D6 D5 D4 D3 D2 D1 D0
DIG0
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
DP
A
B
C
D
E
F
G
DP
A
B
C
D
E
F
G
Note: If morthan 2 shorts occure in the LED array, detection of individual LED fault could become limited to blocs.
Intensitontrol Register (0x0A)
Te brignes of the display can be controlled by digital means using the Intensity Control Registers and by analog
mens using RSET (see Selecting RSET Resistor Value and Using External Drivers on page 15). The intensity can be
controed globally for all digits, or for each digit individually. The global intensity command will write intensity data to all
four individual brightness registers, while the individual intesity command will only write to the associated individual
intensity register.
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AS1118
Datasheet - Detailed Description
Display brightness is controlled by an integrated pulse-width modulator which is controlled by the lower-nibble of the
Intensity Control Register. The modulator scales the average segment-current in 16 steps from a maximum of 15/16
down to 1/16 of the peak current set by RSET.
Table 17. Intensity Register Format
Register Data
MSB D2 D1 LSB
Register Data
MSB D2 D1 LSB
Duty Cycle
HEX Code
Duty Cycle
HEX Code
1/16 (min on)
2/16
0xX0
0xX1
0xX2
0xX3
0xX4
0xX5
0xX6
0xX7
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
9/16
10/16
11/16
12/16
13/16
0xX8
0xX9
0xXA
0xXB
0xXC
0xXD
0xXE
0xXF
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3/16
4/16
5/16
6/16
7/16
8/16
14/16
15/16
15/16 (max on)
Table 18. Intensity Register Address
Register Data
Register HEX Address
Type
Global
Digit
Digit
Digit
D7:4
D3:D0
0x0A
0x10
0x11
0x12
0x13
X
Global Intensity
Digit 0 Intensity
Digit 2 Intensity
Digit 4 Intensity
Digit 6 Intensity
Digit tensity
it 3 Intensity
Digit 5 Intensity
Digit 7 Intensity
Digit
Scan-Limit Register (0x0B)
The Scan-Limit Register controls which of thdigitare to be disped. When all 8 digits are to be displayed, the
update frequency is typically 0.8kHz. If thnumber of digits displyed reduced, the update frequency is increased.
The frequency can be calculated using 8fOSC/N, where N is te nuber of digits. Since the number of displayed digits
influences the brightness, RSET should adjusted accordingly.
Note: To avoid differences in brightness this register snot be used to blank parts of the display (leading zeros).
Table 19. Scan-Limit Register Format (Address (HEX) 0x0B))
Rgister Data
Register Data
HEX
Code
HEX
Code
Scan Limit
Scan Limit
D7:D3 D2 D1 D0
D7:D3 D2 D1 D0
Display digit 0 only
Display digits 0:1
Display digits 0:2
Display digits 0:3
0xX0
0xX1
0xX
0X3
X
X
X
0
0
0
0
0
0
1
1
0
1
0
1
Display digits 0:4
Display digits 0:5
Display digits 0:6
Display digits 0:7
0xX4
0xX5
0xX6
0xX7
X
X
X
X
1
1
1
1
0
0
1
1
0
1
0
1
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Revision 1.01
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AS1118
Datasheet - Detailed Description
Feature Register (0x0E)
The Feature Register is used for enabling various features including switching the device into external clock mode,
applying an external reset, selecting code-B or HEX decoding, enabling or disabling blinking, enabling or disabling the
SPI-compatible interface, setting the blinking rate, and resetting the blink timing.
Note: At power-up the Feature Register is initialized to 0.
Table 20. Feature Register Summary
D7
D6
D5
D4
D3
D2
D1
D0
blink_
start
blink_
freq_sel
sync
blink_en
NU
decode_sel
reg_res
clk_en
Table 21. Feature Register Bit Descriptions (Address (HEX) = 0xXE)
Feature Register
Addr: 0xXE
Enables and disables various device features.
Bit
Bit Name
Default
Access
Bit Description
External clock active.
0 = Internal oscillator is used for system clock.
D0
clk_en
0
R/W
1 = Pin CLK of the serial interface operates as stem clock input.
Resets all control gistrs xcept the Feature Reser.
0 = Reset DisabledNorml operation.
D1
reg_res
0
0
R/W
R/W
1 = All contrgisters are reset to default state (except the Feature
Register) idelly after power-up
Note: The DigRegisters maintan thedata.
Selects display decoding for thseleted digits (Table 10 on page 10).
0 = nablCode-B decoding (seTable 11 on page 11).
1 Enable HEX decodinee Table 12 on page 11).
Not sed
Eables blinking.
0 = Disable blinng. 1 = Enable blinking.
Sets blink wlow requency (with the internal oscillator enabled):
0 = Blink ypically is 1 second (0.5s on, 0.5s off).
1 = Blink period is 2 seconds (1s on, 1s off).
D2
decode_sel
D3
D4
NU
blink_en
0
0
R/W
R/W
D5 blink_freq_sel
Synrones blinking on the rising edge of pin LD. The multiplex and
blink timing counter is cleared on the rising edge of pin LD. By setting
his bit in multiple devices, the blink timing can be synchronized across
althe devices.
Start Blinking with display enabled phase. When bit D4 (blink_en) is set,
bit D7 determines how blinking starts.
D6
D7
sync
0
0
R/W
R/W
blink_start
0 = Blinking starts with the display turned off.
1 = Blinking starts with the display turned on.
No-Op Register (0xX0)
The No-Op Registeis used when multiple AS1118 devices are cascaded in order to support displays with more than 8
digits. The cascading must be done in such a way that all SDO pins are connected to SDI of the next AS1118 (see Fig-
ure 20 on pag16The LD and SCL signals are connected to all devices.
For exae, if five devices are cascaded, in order to perform a write operation to the fifth device, the write-command
mst be fllowed by four no-operation commands. When the LD signal goes high, all shift registers are latched. The
first our devices will receive no-operation commands and only the fifth device will receive the intended operation com-
mand, and subsequently update its register.
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AS1118
Datasheet - Typical Application
9 Typical Application
Selecting RSET Resistor Value and Using External Drivers
Brightness of the display segments is controlled via RSET. The current that flows between VDD and ISET defines the
current that flows through the LEDs.
Segment current is about 200 times the current in ISET. Typical values for RSET for different segment currents, operat-
ing voltages, and LED voltage drop (VLED) are given in Table 22 & Table 23. The maximum current the AS1118 can
drive is 47mA. If higher currents are needed, external drivers must be used, in which case it is no longer necessary
that the devices drive high currents.
Note: The display brightness can also be logically controlled (see Intensity Control Register (0x0A) on page 12).
Table 22. RSET vs. Segment Current and LED Forward Voltage, VDD = 2.7V & 3.3V & 3.6V
VLED
VLED
2.0V
VLED
ISEG (mA)
1.5V
5kΩ
2.0V
4.4kΩ
5.9kΩ
9.6kΩ
20.7kΩ
1.5V
2.5V
5.7kΩ
8.1kΩ
2.6kΩ
26kΩ
1.5V
2.0V
2.5V
6.6Ω
2kΩ
14.3kΩ
3.0V
40
30
20
10
6.7kΩ
9.1kΩ
13.9kΩ
28.8kΩ
6.4kΩ
8.8kΩ
7.5kΩ
7.2kΩ
9.8kΩ
1Ω
31kΩ
5.5kΩ
7.5kΩ
13kΩ
6.9kΩ
10.18kΩ
15.6kΩ
31.9kΩ
10.7kΩ
22.2kΩ
13.3kΩ
27.7kΩ
29.5kΩ 27.3kΩ
Table 23. RSET vs. Segment Current and LED Forward Vge, VDD = 4.0V & 5.0V
VLED
2.5V
VLED
2V
ISEG
(mA)
1.5V
2.0V
3.0V
3.5V
1.5V
2.0
3.0V
3.5V
4.0V
40
30
20
10
8.6kΩ
8.3kΩ
7.9kΩ
7.6kΩ 5.2kΩ
11.35kΩ 11.1kΩ 10.84kΩ 10.49kΩ 10.2kΩ 9.9kΩ
15.4kΩ .1kΩ 14.7kΩ 14.4kΩ 13.6kΩ 13.1kΩ
11.6kΩ 11.2kΩ 10.8kΩ 9.9kΩ 7.8k
17.7kΩ 17.3kΩ 16.6kΩ 15.6kΩ 13.6kΩ
36.89kΩ 35.7kΩ 34.5kΩ 32.5kΩ 29.1kΩ
23.kΩ 3.kΩ 22.6kΩ
22kΩ 21.1kΩ 20.2kΩ
48.9k47.8kΩ 46.9kΩ 45.4kΩ 43.8kΩ 42kΩ
Calculating Power Dissipan
The upper limit for power dissipation (PD) for the AS1118 etermined from the following equation:
PD = (VDD x 5mA) + (D- VLED)(DUTY x ISEG x N)
(EQ 1)
Where:
VDD is the supply voltage.
DUTY is the duty cycle set by intensity reer (page 13).
N is the number of segments drivn (worst case is 8)
VLED is the LED forward voltage
ISEG = segment current set by RET
Dissipation Example:
ISE= 40mA, N = 8, DUTY = 15/16, VLED = 2.2V at 40mA, VDD = 5V
PD = 5V(5mA) + (5V - 2.2V)(15/16 x 40mA x 8) = 0.865W
(EQ 2)
(EQ 3)
Thus, foSOP-24 package ΘJA = +88°C/W, the maximum allowed TAMB is given by:
TJ,MAX = TAMB + PD x
Θ
JA = 150°C = TAMB + 0.865W x 88°C/W
(EQ 4)
In this example the maximum ambient temperature must stay below 73.88°C.
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AS1118
Datasheet - Typical Application
8x8 Dot Matrix Mode
The application example in Figure 20 shows the AS1118 in the 8x8 LED dot matrix mode.
The LED columns have common cathodes and are connected to the DIG0:7 outputs. The rows are connected to the
segment drivers. Each of the 64 LEDs can be addressed separately. The columns are selected via the digits as listed
in Table 8 on page 9.
The Decode Enable Register (see page 10) must be set to ‘00000000’ as described in Table 10 on page 10. Single
LEDs in a column can be addressed as described in Table 13 on page 11, where bit D0 corresponds to segment G and
bit D7 corresponds to segment DP.
Note: For a multiple-digit dot matrix, multiple AS1118 devices can be cascaded easily.
Figure 20. Application Example as LED Dot Matrix Driver
V
DD
VDD
2.7V to 5V
DIG0 to
DIG7
9.53kΩ
SEG A to G
SEP DP
ISET
SDI
AS1118
I/O
I/O
I/O
SCL
LD
DArrangement
µP
SDO
I/O
GN
Diagnostic
readback: open
& shorted LEDs
RESETN
Supply Bypassing and Wiring
In order to achieve optimal performance the AS111should be placed very close to the LED display to minimize effects
of electromagnetic interference and wiring inductace.
Furthermore, it is recommended to connect 10µF electrolytic and a 0.1µF ceramic capacitor between pins VDD and
GND to avoid power supply ripple (see Figure 5 on page 7).
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AS1118
Datasheet - Package Drawings and Markings
10 Package Drawings and Markings
Figure 21. TQFN(4x4)-24 Marking
Table 24. Packaging Code YYWWIZZ
YY
WW
X
ZZ
manufacturing wek
last two digits of the current year
plant identifier
free chice / traceability code
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AS1118
Datasheet - Package Drawings and Markings
Figure 22. TQFN(4x4)-24 Package
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AS1118
Datasheet - Ordering Information
11 Ordering Information
The devices are available as the standard products shown in Table 25.
Table 25. Ordering Information
Ordering Code
Marking
Desciption
Delivery Form
Package
64 LED Driver for Mobile
Applications with Error Detection
AS1118-BQFT
ASSX
Tape and Reel
TQFN(4x4)-24
Note: All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
Technical Support is found at http://www.austriamicrosystems.com/Technical-Support
For further information and requests, please contact us mailto:sales@austriamicrosystems.cm
or find your local distributor at http://www.austriamicrosystems.com/distributor
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AS1118
Datasheet
Copyrights
Copyright © 1997-2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement.
austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice.
Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG f
current information. This product is intended for use in normal commercial applications. Applications requiring
extended temperature range, unusual environmental requirements, or high reliability applications, sucas military,
medical life-support or life-sustaining equipment are specifically not recommended without additionl prcessing by
austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing ow might show
deviations from the standard production flow, such as test flow or tet location.
The information furnished here by austriamicrosystems AG is bieved tbe correct and accurat. However,
austriamicrosystems AG shall not be liable to recipient or any thirpartfor any damags, incuding but not limited to
personal injury, property damage, loss of profits, loss of uinterruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or ng out of the furning, performance or use of the
technical data herein. No obligation or liability to recipient or ny third party shall arisor flow out of
austriamicrosystems AG rendering of technical or other services.
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