AS3418-EWLM [AMSCO]
Low Noise ANC Solution;
| 型号： | AS3418-EWLM |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | Low Noise ANC Solution |
| 文件： | 总77页 (文件大小：1373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
DS000507
AS3418
Low Noise ANC Solution
v4-00 • 2020-Jan-23
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AS3418
Content Guide
Content Guide
6.8
6.9
6.10
6.11
6.12
Operation Modes ....................................... 33
VNEG Charge Pump .................................... 38
EEPROM.................................................... 39
Production Trimming Interface................... 41
I2C Interface ............................................... 42
1
General Description....................... 3
1.1
1.2
1.3
Key Benefits & Features .............................. 3
Applications.................................................. 4
Block Diagram.............................................. 4
2
3
Ordering Information..................... 5
Pin Assignment ............................. 6
7
Register Description ................... 47
7.1
7.2
Register Overview...................................... 47
Detailed Register Description .................... 49
3.1
3.2
Pin Diagram.................................................. 6
Pin Description ............................................. 6
8
Application Information .............. 70
4
5
6
Absolute Maximum Ratings.......... 9
Electrical Characteristics............ 10
Functional Description................ 12
8.1
8.2
Schematic .................................................. 70
External Components ................................ 72
9
Package Drawings & Markings... 74
Revision Information................... 76
Legal Information ........................ 77
10
11
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Audio Line Input ......................................... 12
Microphone Inputs...................................... 13
Microphone Supply .................................... 19
Headphone Amplifier.................................. 21
Music Bypass Switch ................................. 25
Operational Amplifier.................................. 28
System ....................................................... 30
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AS3418
General Description
1 General Description
The AS3418 speaker driver with Ambient Noise Cancelling function for headsets, headphones or ear
pieces. They are intended to improve quality of e.g. music listening, a phone conversation etc. by
reducing background ambient noise.
The fully analog implementation allows the lowest power consumption, lowest system BOM cost and
most natural received voice enhancement otherwise difficult to achieve with DSP implementations.
The device is designed to be easily applied to existing architectures.
An internal EEPROM can be optionally used to store the microphones gain calibration settings. The
AS3418 can be used in different configurations for best trade-off of noise cancellation, required
filtering functions and mechanical designs.
The AS3418 targeting feed-forward topology is used to effectively reduce frequencies typically up to 2-
3 kHz. The typical bandwidth for a feed-forward system is from 20Hz up to 3 kHz which is lower than
the feed-forward systems.
The filter loop for the system is determined by measurements, for each specific headset individually,
and depends very much on mechanical designs. The gain and phase compensation filter network is
implemented with cheap resistors and capacitors for lowest system costs.
1.1
Key Benefits & Features
The benefits and features of AS3418, Low Noise ANC Solution, are listed below:
Figure 1:
Added Value of Using AS3418
Benefits
Features
Low Noise Floor
Low Noise Amplifiers
Integrated Music Bypass Switch
Depletion mode transistors for passive music
bypass
Smallest ANC form factor
WL-CSP package 2.645mm x 2.545mm; 0.4mm
pitch
Reprogrammable ANC settings
EEPROM Memory for system settings
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AS3418
General Description
1.2
1.3
Applications
●
●
●
●
●
Ear Pieces
Headsets
Hands-Free Kits
Mobile Phones
Voice Communicating Devices
Block Diagram
The functional blocks of this device are shown below:
Figure 2 :
Functional Blocks of AS3418
CFLY
CVNEG
Left ANC Filter
VNEG
CACL
VBAT
VMIC
VBAT
Charge Pump
CMICL
MICL
BPL
CVBAT
Left ANC
Microphone
RMICL
Music Bypass
LINL
MUTE
AS3418
HPL
Speaker Left
TRSDA
TRSCL
ANC
Processing
AGND
HPR
EEPROM
Music Input
Speaker Right
VBAT
LINR
MUTE
ILED
VMIC
BPR
Music Bypass
CMICR
MICR
I2C
MSUP
Right ANC
Microphone
RMICR
On/Off/Monitor/PBO
CMSUP
VMIC
CMICS
CACR
Right ANC Filter
Button Control or
I2C Communication
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AS3418
Ordering Information
2 Ordering Information
Ordering Code
Package
Marking
Delivery Form Delivery Quantity
AS3418-EWLT
AS3418-EWLM
WL-CSP
WL-CSP
AS3418
AS3418
Tape & Reel
Tape & Reel
6500 pcs/reel
500 pcs/reel
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AS3418
Pin Assignment
3 Pin Assignment
3.1
Pin Diagram
Figure 3 :
Pin Assignment AS3418
A1
A2
A3
A4
A5
A6
IOP1R
QMICR
MICR
VNEG
GND
VBAT
B1
B2
B3
B4
B5
B6
BPR
HPR
MICACR
CPN
LINR
LINL
C5
ANC/
CSDA
C6
MODE/
CSCL
C1
VNEG
C2
QOP1R
C3
QOP1L
C4
CPP
D1
D2
D3
D4
D5
D6
BPL
HPL
MICACL
TRSDA
AGND
TRSCL
E1
E2
E3
E4
E5
E6
IOP1L
QMICL
MICL
MICS
MSUP
ILED
3.2
Pin Description
Figure 4:
Pin Description of AS3418
Pin Number Pin Name Pin Type(1)
Description
A1
A2
A3
IOP1R
QMICR
MICR
ANA IN
ANC filter OPAMP1 input - right channel.
ANA OUT
ANA IN
ANC microphone preamplifier output - right channel.
ANC microphone preamplifier input - right channel.
VNEG charge pump output terminal. This output
provides the negative amplifier supply voltage for all
OPAMPs and the headphone amplifier.
A4
VNEG
SUP OUT
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AS3418
Pin Assignment
Pin Number Pin Name Pin Type(1)
Description
A5
A6
GND
ANA IN
SUP IN
VNEG charge pump ground terminal.
Positive supply terminal of AS3418.
VBAT
Right audio bypass switch input. This pin features a
music bypass function for the right audio channel in
off mode operation in order to replace and external
analog switch.
B1
BPR
ANA IN
B2
B3
HPR
ANA OUT
ANA OUT
Headphone amplifier output - right channel.
Microphone preamplifier AC coupling ground
terminal. This pin requires a typ. 10µF capacitor
connected to AGND pin.
MICACR
VNEG charge pump negative terminal for flying
capacitor
B4
CPN
ANA OUT
B5
B6
LINR
LINL
ANA IN
ANA IN
Line input - right channel.
Line input - left channel.
VNEG charge pump output terminal. This output
provides the negative amplifier supply voltage for all
OPAMPs and the headphone amplifier.
C1
VNEG
SUP OUT
C2
C3
QOP1R
QOP1L
ANA OUT
ANA OUT
ANC filter OPAMP1 output - right channel
ANC filter OPAMP1 output - left channel
VNEG charge pump positive terminal for flying
capacitor
C4
C5
CPP
ANA OUT
Serial interface data signal line for I2C interface and
alternatively ANC control to enable/disable ANC.
ANC/
DIG IN/OUT
CSDA
Serial Interface clock signal line for I2C interface and
alternatively control pin for power up/down and
Monitor mode.
MODE/
CSCL
C6
D1
DIG IN
ANA IN
Left audio bypass switch input. This pin features a
music bypass function for the left audio channel in
off mode operation in order to replace and external
analog switch.
BPL
D2
D3
HPL
ANA OUT
ANA OUT
Headphone amplifier output - left channel.
Microphone preamplifier AC coupling ground
terminal. This pin requires a typ. 10µF capacitor
connected to AGND pin.
MICACL
Data input for production trimming. Can be
connected to LINL pin to enable production trimming
via 3.5mm audio jack.
D4
D5
TRSDA
AGND
ANA IN
ANA IN
Analog reference ground. Do not connect this pin to
power or digital ground plane.
Clock input for production trimming. Can be
connected to LINR pin to enable production
trimming via 3.5mm audio jack.
D6
E1
TRSCL
IOP1L
ANA IN
ANA IN
ANC filter OPAMP1 input - left channel
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AS3418
Pin Assignment
Pin Number Pin Name Pin Type(1)
Description
E2
E3
QMICL
MICL
ANA OUT
ANA IN
ANC microphone preamplifier output - left channel
ANC microphone preamplifier input - left channel
Microphone Supply output to source analog ECM
via a bias resistor or MEMs microphones. This pin
needs an output blocking capacitor with 4.7µF.
E4
MICS
SUP OUT
In default configuration a charge pump output that
provides the power for the low noise microphone
supply LDO. The internal charge pump can also be
disabled the MSUP serves as a supply input
terminal to source the low noise microphone supply
LDO.
E5
MSUP
SUP IN/OUT
Current sink input for on-indication LED. The
Cathode of an LED can be directly connected to this
terminal without the need of an external current
limitation resistor.
E6
ILED
ANA IN
(1)
Explanation of abbreviations:
ANA IN
Analog Input
Analog Output
Digital Input
ANA OUT
DIG IN
SUP IN/OUT
SUP IN
Supply input or supply output pad
Supply input terminal
SUP OUT
Supply output terminal
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AS3418
Absolute Maximum Ratings
4 Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to
the device. These are stress ratings only. Functional operation of the device at these or any other
conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Figure 5
Absolute Maximum Ratings of AS3418
Symbol
Parameter
Min
Max
Unit
Comments
Electrical Parameters
VSUP_MAX
VGND_MAX
VNEG_MAX
VCP_MAX
Supply Voltage to Ground
-0.5
2
V
V
V
V
Applicable for pin VBAT
Applicable for pin AGND
and GND
Ground Terminals
-0.5
+0.5
Negative Terminals
Charge Pump Terminals
-2.0
0.5
Applicable for pin VNEG
Applicable for pins CPN
and CPP
VNEG - 0.5
VPOS + 0.5
Applicable for pins HPR
and HPL
VHP_MAX
Headphone Pins
VNEG - 0.5
VPOS + 0.5
V
Applicable for pins LINL,
LINR, MICL/R, HPR, HPL,
QMICL/R, IOP1x, QOP1x,
CPP, CPN, TRSCL, BPR,
TRSDA, BPL, MICACL
and MICACR
VANA_MAX
Analog Pins
VNEG - 0.5
VPOS + 0.5
V
Applicable for pins
ANC/CSDA and
MODE/CSCL
VCON_MAX
Control Pins
Other Pins
VNEG - 0.5
VNEG - 0.5
5
5
V
Applicable for pins MICS
and MICFB
VOTHER_MAX
ISCR
V
Input Current (latch-up
immunity)
± 100
mA
Class II JEDEC JESD78D
Electrostatic Discharge
ESDHBM
Electrostatic Discharge HBM
± 2000
85
V
Norm: JS-001-2014
Temperature Ranges and Storage Conditions
TJ
Operating Junction Temperature
Storage Temperature Range
Package Body Temperature
°C
°C
°C
TSTRG
TBODY
- 55
5
125
260
85
IPC/JEDEC J-STD-020 (1)
Unlimited floor lifetime
Relative Humidity (non-
condensing)
RHNC
MSL
%
Moisture Sensitivity Level
1
(1)
The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.” The lead finish for Pb-
free leaded packages is “Matte Tin” (100% Sn)
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AS3418
Electrical Characteristics
5 Electrical Characteristics
VBAT = 1.4V to 1.8V, TA = -20ºC to 85ºC. Typical values are at VBAT = 1.6V, TA = 25ºC, unless
otherwise specified. All limits are guaranteed. The parameters with Min and Max values are
guaranteed with production tests or SQC (Statistical Quality Control) methods.
Figure 6:
Electrical Characteristics of AS3418
Symbol Parameter
Conditions
Min
Typ
Max Unit
Ambient Temperature
Range
TA
-20
85
°C
Supply Voltages
GND
VBAT
VNEG
Reference Ground
0
0
V
V
V
Battery Supply Voltage
Charge Pump Voltage
Normal Operation
1.4
-1.8
1.6
1.8
-1.2
To achieve good performance, the
negative supply terminals should be
connected to a low impedance ground
plane.
Difference of Ground
Supplies GND, AGND
VDELTA
-0.1
0.1
V
Other Pins
VMICS
Microphone Supply Voltage
Analog Pins
Applicable to MICS pin
0
3.6
V
V
MICACL, MICACR,LINR, LINL, HPR,
HPL, QMICL, QMICR, IOP1x, and
QOP1x
VANALOG
VNEG
VBAT
Applicable to MODE/CSCL and
ANC/CSDA pins
VCONTROL
VCP
Control Pins
0
3.7
V
V
Charge Pump Pins
Applicable to CPN and CPP pins
VNEG
VBAT
VNEG
0.3
or -1.8
-
VBAT
+0.5
or 1.8
VTRIM
Application Trim Pins
Applicable to TRSCL and TRSDA pins
V
VNEG
0.3
or -1.8
-
VBAT
+0.5
or 1.8
VBYP
Bypass Pins
Applicable to BPR and BPL pins
Applicable to MICL and MICR pins.
V
V
VMIC
Microphone Inputs
VNEG
VBAT
Block Power Requirements
IOFF
Off mode current
MODE/CSCL pin low, device switched off
1
5
µA
VBAT = 1.8V; Bias generation, oscillator,
POR and VNEG
1.45
mA
ISYS
Reference supply current
VBAT = 1.4V; Bias generation, oscillator,
POR and VNEG
1
mA
mA
mA
mA
VBAT = 1.8V; no signal, stereo, High
quality mode
0.97
0.68
0.92
Microphone gain stage
current
VBAT = 1.8V; no signal, stereo, ECO
mode
IMIC
VBAT = 1.4V; no signal, stereo, High
quality mode
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AS3418
Electrical Characteristics
Symbol Parameter
Conditions
Min
Typ
Max Unit
VBAT = 1.4V; no signal, stereo, ECO
mode
0.63
mA
VBAT = 1.8V; no signal, high quality mode
VBAT = 1.8V; no signal, ECO mode
VBAT = 1.4V; no signal, high quality mode
VBAT = 1.4V; no signal, ECO mode
2.9
mA
mA
mA
mA
2.4
IHP
Headphone stage current
2.78
2.32
VBAT = 1.8V; OP1L and OP1R enabled,
High quality mode
1
mA
mA
mA
mA
VBAT = 1.8V; OP1L and OP1R enabled,
ECO mode
0.7
0.95
0.65
IOP1
ANC Filter OPAMP current
VBAT = 1.8V; OP1L and OP1R enabled,
High quality mode
VBAT = 1.8V; OP1L and OP1R enabled,
ECO mode
VBAT = 1.8V; no load; high quality mode
VBAT = 1.4V; no load; high quality mode
VBAT = 1.8V; no load; ECO mode
VBAT = 1.4V; no load; ECO mode
VBAT = 1.8V; no load
0.69
0.67
0.33
0.32
0.3
mA
mA
mA
mA
mA
mA
Microphone low noise LDO
supply current
IMICS
Microphone supply charge
pump current
IMICS_CP
VBAT = 1.4V; no load
0.26
Typical System Power Consumption
VBAT = 1.8V; OP1L, OP1R enabled,
250µA microphone load; all amplifiers in
high quality mode
15
mW
mW
mW
mW
Typical power consumption
feed forward application in
high quality mode
PFF
VBAT = 1.4V; OP1L, OP1R enabled,
250µA microphone load; all amplifiers in
high quality mode
configuration
10.7
12.4
8.8
VBAT = 1.8V; OP1L, OP1R enabled,
250µA microphone load; all amplifiers in
ECO mode
Typical power consumption
feed forward application in
ECO mode configuration
PFF_ECO
VBAT = 1.4V; OP1L, OP1R enabled,
250µA microphone load; all amplifiers in
ECO mode
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AS3418
Functional Description
6 Functional Description
This section provides a detailed description of the device related components.
6.1
Audio Line Input
The chip features one stereo line input for music playback. In monitor mode the line inputs can also be
muted in order to interrupt the music playback and increase speech intelligibility.
Figure 7:
Stereo Line Input
to left
headphone
LINL
Music Left
MUTE
MUTE
amplifier
RLIN
CLIN
to right
headphone
amplifier
LINR
Music Right
RLIN
CLIN
If there is a high pass function desired in an application, to block very low frequencies that could harm
the speaker or eliminate little offset voltages, a series capacitor CLIN can support this function. The
implementation is shown in Figure 7. The correct capacitor value for the desired cut-off frequency can
be calculated with the following formula:
Equation 1:
1
퐶퐿퐼푁
=
2 ∗ 휋 ∗ 푅퐿퐼푁 ∗ 푓
푐푢푡−표ꢀꢀ
A typical cut-off frequency in an audio application is 20Hz. With an input impedance RLIN of typ. 1kΩ
and a desired cut off frequency of 20Hz the input capacitor should be bigger than 8µF. Therefore a
typical value of 10µF is recommended.
6.1.1
Parameter
VBAT=1.65V, TA= 25ºC unless otherwise specified.
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AS3418
Functional Description
Figure 8:
Parameter of Line Input
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VBAT
0.9
*
VLIN
Input Signal Level
VBAT
VPEAK
RLIN
Input Impedance
Mute Attenuation
1
kΩ
AMUTE
100
dB
6.2
Microphone Inputs
The AS3418 offers two low noise microphone inputs with full digital control and a dedicated DC offset
cancellation pin for each microphone input. In total each gain stage offers up to 63 gain steps of 0.5dB
resulting in a gain range from 0dB to +31dB. The microphone gain is stored digitally during production,
in an EEPROM memory on the ANC chip. Besides the standard microphone gain register for left and
right channel, the chip features also four additional microphone gain registers for Monitor- and
Playback Only operation mode. Thus, in Monitor/Playback Only mode, a completely different gain
setting for left and right microphone can be selected to implement voice filter functions in order to
amplify the speech band for better intelligibility.
Figure 9:
Stereo Microphone Inputs
MUTE
MICL
AGC
QMICL
DISCHARGE
MICACL
MICACR
DISCHARGE
AGC
QMICR
MICR
MUTE
To avoid unwanted start-up pop noise, a soft-start function is implemented for an automatic gain
ramping of the device. In case of an overload condition on the microphone input (e.g. high sound
pressure level) there is also an automatic gain control (AGC) function available which reduces the gain
to a moderate level. For some designs it might be useful to switch off this feature. Especially in feed-
back systems infrasound can cause an overload condition of the microphone preamplifier that results
in low frequency noise which can be avoided by disabling the AGC.
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AS3418
Functional Description
6.2.1
Input Capacitor Selection
The microphone preamplifier needs a bias resistor (RBias) per channel as well as DC blocking
capacitors (CMIC). The capacitors CAC are DC blocking capacitors to avoid DC amplification of the non-
inverting microphone preamplifier. This capacitor has an influence on the frequency response because
the internal feedback resistors create a high pass filter. The typical application circuit is shown in
Figure 10 with all necessary components.
Figure 10:
Microphone Capacitor Selection Circuit
MICS
RBIAS
CMIC
MUTE
MICL
AGC
QMICL
R2
DISCHARGE
ANC Microphone
RMICIN
CAC
R1
MICACL
MICACR
CAC
RMICIN
R1
R2
ANC Microphone
DISCHARGE
MUTE
CMIC
QMICR
AGC
MICR
MICS
RBIAS
The corner frequency of this high pass filter is defined with the capacitor CAC and the gain of the
headphone amplifier. Figure 11 shows an overview of typical cut-off frequencies with different
microphone gain settings.
Figure 11:
Microphone Cut-Off Frequency Overview
Microphone Gain
R1
R2
fcut-off
22.2kΩ
15716Ω
11126Ω
7877Ω
5576Ω
3948Ω
0Ω
1.7Hz
1.9Hz
2.2Hz
2.7Hz
3.5Hz
4.5Hz
0dB
6484Ω
11074Ω
14323Ω
16623Ω
18252Ω
3dB
6dB
9dB
12dB
15dB
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AS3418
Functional Description
Microphone Gain
R1
R2
fcut-off
2795Ω
1979Ω
1400Ω
992Ω
19405Ω
20221Ω
20800Ω
21208Ω
21498Ω
6.1Hz
18dB
21dB
24dB
27dB
30dB
8.4Hz
11.5Hz
16.3Hz
22.7Hz
702Ω
It is important when doing the ANC filter simulations to include all microphone filter components to
incorporate the gain and phase influence of these components. In the cut-off frequency overview,
capacitor CAC was defined as 10µF which results in a rather low cut-off frequency for best ANC filter
design. If a different capacitor value is desired in the application, the following formula defines the
transfer function of the high pass circuit of the microphone preamplifier:
Equation 2:
ꢃ
ꢃ
√4 ∗ 퐶ꢁꢂ ∗ 푓 ∗ 푅ꢄ + 푅ꢃ ꢃ ∗ 휋ꢃ + 1
(
)
|퐴| =
√4 ∗ 퐶ꢁꢃꢂ ∗ 푓ꢃ ∗ 푅ꢄꢃ ∗ 휋ꢃ + 1
The simplified transfer function does not include the high pass filter defined by CMIC and RMICIN.
With the recommended values of 2.2µF for CMIC and 22kΩ for RMICIN this filter can be neglected
because of the very low cut-off frequency of 1.5Hz. The cut-off frequency for this filter can be
calculated with the following formula:
Equation 3:
1
푓
=
푐푢푡−표ꢀꢀ
2 ∗ 휋 ∗ 푅푀퐼ꢂ퐼푁 ∗ 퐶푀퐼ꢂ
The simulated frequency response for the microphone preamplifier with the recommended component
values is shown in Figure 12.
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AS3418
Functional Description
Figure 12 :
Simulated Microphone Frequency Response
35
30
25
20
15
10
5
30dB
24dB
18dB
12dB
6dB
0dB
0
-5
10
100
1k
10k
f [Hz]
In applications with PCB space limitations it is also possible to remove the capacitors CAC and connect
MICACL and MICACR pins directly to AGND. In this configuration AC coupling of the QMICR and
QMICL signals is recommended.
6.2.2
Parameter
VBAT=1.8V, TA= 25ºC , CAC=10µF, CMIC=4.7µF and RMICIN=2.2kΩ unless otherwise specified.
Figure 13:
Microphone Parameter
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Preamplifier gain=0dB, THD <
0.1%
VMICIN_0
1050
mVRMS
Typical maximum
Input Signal Level
Preamplifier gain=20dB, THD <
0.1%
VMICIN_0
110
119
109
106
117
108
mVRMS
dB
0dB gain, High quality mode,
AGC disabled
10dB gain, High quality mode,
AGC disabled
dB
Signal to Noise
Ratio
20dB gain, High quality mode,
AGC disabled
SNR
dB
0dB gain, ECO mode, AGC
disabled
dB
10dB gain, ECO mode, AGC
disabled
dB
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AS3418
Functional Description
Symbol Parameter
Conditions
Min
Typ
Max
Unit
20dB gain, ECO mode, AGC
disabled
105
dB
0dB gain, 20Hz – 20kHz
bandwidth, high quality
1.3
4.5
13.7
1.4
5
µV
µV
µV
µV
µV
µV
10dB gain, 20Hz – 20kHz
bandwidth, high quality
20dB gain, 20Hz – 20kHz
bandwidth, high quality
A-weighted output
noise floor
VNOISE-A
0dB gain, 20Hz – 20kHz
bandwidth, ECO mode
10dB gain, 20Hz – 20kHz
bandwidth, ECO mode
20dB gain, 20Hz – 20kHz
bandwidth, ECO mode
15.7
1
VBAT = 1.8V; no signal, stereo,
normal mode
mA
VBAT = 1.8V; no signal, stereo,
ECO mode
0.7
0.9
0.6
mA
mA
mA
dB
Block Current
Consumption
IMIC
VBAT = 1.4V; no signal, stereo,
normal mode
VBAT = 1.4V; no signal, stereo,
ECO mode
Programmable
Gain
AMIC
0
31
0.5
dB
dB
Gain Step Size
0.2
Gain Step Precision
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AS3418
Functional Description
Figure 14 :
Microphone Frequency Response (MICACx grounded; CMIC=10µF)
35
30dB
30
25
20dB
20
15
10dB
10
5
0dB
0
-5
10
100
1k
10k
100k
f [Hz]
Figure 15:
Microphone THD+N vs. Vinput High Quality Mode (A-weighted)
1
0,1
0,01
0,001
0,0001
10
100
Vinput [mV]
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AS3418
Functional Description
Figure 16:
Microphone THD+N vs. Vinput ECO Mode (A-weighted)
1
0,1
0,01
0,001
0,0001
10
100
Vinput [mV]
6.3
Microphone Supply
The AS3418 features an integrated microphone supply voltage regulator and a charge pump to source
the microphone LDO even with a 1.4V chip supply voltage in order to increase the sensitivity of the
microphone. The microphone supply charge pump is in default configuration enabled and can be
controlled in ANC and Monitor operation mode with register ANCMON_MICS_CP_ON bit. For PBO
operation mode there is a dedicated control bit PBO_MICS_CP_ON.
The output of the charge pump is directly connected to an internal microphone supply ultra-low noise
voltage regulator. This low dropout (LDO) regulator is in default configuration enabled and can be
controlled with ANCMON_MICS_ON bit. The default output voltage of the regulator is 2.9V. If there is
a lower output voltage desired in an application the voltage level can be changed via register
MICS_V_SEL register.
If the AS3418 is connected to a 1.5V battery the input voltage will of course drop during operation
because the battery is discharging during operation. In order to make sure the microphone supply
LDO has enough headroom to regulate properly the device features an automatic output voltage
adjustment feature. This function makes sure the voltage regulator has enough headroom and adjusts
the output voltage of the LDO accordingly.
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AS3418
Functional Description
Figure 17:
Microphone Supply
ANCMON_MICS_CP_BYP_EN
MICS_V_SEL<3:0>
MICS_V_LEV<3:0>
ANCMON_
MICS_ON
ANCMON_MICS_CP_ON
MIC
Charge
Pump
VBAT
to microphone
BIAS resistors
MICS
LDO
CMICS
CMSUP
The microphone supply charge pump is also used to switch off the integrated music bypass switch of
the AS3418 in active mode. Therefore, during normal operation the microphone supply must not be
switched off if the BPL and BPR pins are in use.
6.3.1
Parameter
VBAT=1.8V, TA= 25ºC, CMSUP = 4.7µF and CMICS = 4.7µF unless otherwise specified.
Figure 18:
Microphone Supply Parameter
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VBAT= 1.8V; no load; charge
pump activated
2.9
V
Microphone supply
LDO output voltage
VMICS
VMSUP
VNoise-A
IMICS
VBAT=1.4V; no load; charge
pump activated
2.5
V
VBAT= 1.8V; no load; MICS
voltage regulator off
3.15
2.7
V
Microphone supply
charge pump
output voltage
VBAT= 1.4V; no load; MICS
voltage regulator off
V
High quality mode enabled; 1mA
load; A-weighted
1.7
µV
µV
mA
mA
Microphone Supply
Noise at MICS
output
High quality mode disabled;
1mA load; A-weighted
2.2
VBAT = 1.8V; no load;
HIQ_EN_MICS_LDO = 1
Current
0.69
0.67
consumption low
noise voltage
regulator
VBAT = 1.4V; no load;
HIQ_EN_MICS_LDO = 1
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AS3418
Functional Description
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VBAT = 1.8V; no load;
HIQ_EN_MICS_LDO = 0
0.33
mA
VBAT = 1.4V; no load;
HIQ_EN_MICS_LDO = 0
0.32
0.3
mA
mA
mA
mA
VBAT= 1.8V; MICS voltage
regulator off; no load
VBAT= 1.8V; MICS voltage
regulator off; 1mA load
Current
3.5
consumption
microphone supply
IMICS_CP
VBAT= 1.4V; MICS voltage
regulator off; no load
0.26
charge pump
VBAT= 1.4V; MICS voltage
regulator off; 1mA load
3.33
2
mA
mA
IOUT
Output current
Charge pump activated
Figure 19:
Microphone Supply Load Characteristic
3
2
1
0
VBAT=1,4V
VBAT=1.8V
1
2
3
4
Iload [mA]
6.4
Headphone Amplifier
The headphone amplifier is a true ground output using VNEG as negative supply. It is designed to
feature an output power of 2x34mW @ 32Ωload. For higher output requirements, the headphone
amplifier is also capable of operating in bridged mode. In this mode the left output is carrying the
inverted signal of the right output shown in Figure 21. With a VBAT voltage of 1.8V, a maximum output
power of 100mW can be achieved. This is necessary for over- and on ear headsets with higher output
power requirements. The amplifier itself features various input sources. The line input signal is directly
connected to the headphone amplifier. The input multiplexer supports three different input signals
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AS3418
Functional Description
which can be configured according in the ANC_HPH_MUX, MON_HPH_MUX and PBO_HPH_MUX
registers independently for each operation mode. The “Open” setting is being used to disable the
active noise cancelling function.
Figure 20:
Headphone Amplifier Single Ended
XXX_HPH_MUX
QMICR
1kΩ
1kΩ
QOP1R
open
LINE_MUTE
1kΩ
LINR
AGND
LINL
HPR
HPL
RLI N
RLI N
LINE_MUTE
1kΩ
QMICL
QOP1L
1kΩ
1kΩ
open
XXX_HPH_MUX
Figure 21:
Headphone Amplifier Differential
XXX_HPH_MUX
QMICL
QOP1L
1k ꢀ
1k ꢀ
open
LINE_MUTE
1k ꢀ
LINR
HPR
HPL
RLI N
AGND
1k ꢀ
1k ꢀ
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AS3418
Functional Description
6.4.1
Parameter
VBAT =1.8V, TA= 25ºC, unless otherwise specified.
Figure 22:
Microphone Supply Parameter
Symbol Parameter
RL_HP Load Impedance
CL_HP
Conditions
Min
Typ
Max
Unit
Stereo Operation Mode
Mono Operation Mode
Per channel
16
32
32
Ω
Ω
Load Capacitance
100
pF
VBAT= 1.8V; 32Ω load;
THD<0.1%
35
mW
mW
mW
mW
mW
mW
mA
mA
mA
mA
dB
VBAT= 1.4V; 32Ω load;
THD<0.1%
20
Nominal Output
Power Stereo Mode
PHP
VBAT= 1.8V; 16Ω load;
THD<0.1%
55
VBAT= 1.4V; 16Ω load;
THD<0.1%
30
VBAT= 1.8V; 32Ω load;
THD<0.1%
130
75
Nominal Output
Power Differential
Mode
PBRIDGE
VBAT= 1.4V; 32Ω load;
THD<0.1%
VBAT = 1.8V; no input signal,
normal mode
2.9
2.4
2.8
2.3
100
VBAT = 1.8V; no input signal,
ECO mode
IHPH
Supply Current
VBAT = 1.4V; no input signal,
normal mode
VBAT = 1.4V; no signal, ECO
mode
Power Supply
Rejection Ratio
PSRRHP
1kHz
High Quality Mode, Line Input -
> HPH stereo in phase test
signal; 32Ω load; VBAT = 1.8V;
A-weighted
117
dB
dB
dB
High Quality Mode, Line Input -
> HPH stereo out of phase test
signal; 32Ω load; VBAT = 1.8V;
A-weighted
Signal to Noise
Ratio
SNR
117.5
114
ECO Mode, Line Input -> HPH
stereo in phase test signal;
32Ω load; VBAT = 1.8V; A-
weighted
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AS3418
Functional Description
Symbol Parameter
Conditions
Min
Typ
Max
Unit
ECO Mode, Line Input -> HPH
stereo out of phase test signal;
32Ω load; VBAT = 1.8V; A-
weighted
114.5
dB
ACHANNEL Channel Separation 32Ω load
93
dB
µV
High Quality Mode; 32Ω load;
HP_MUX = nc; LINx
1.5
connected to ground
A-Weighted Output
Noise Floor
VNOISE-A
ECO Mode; 32Ω load;
HP_MUX = nc; LINx
connected to ground
2.1
µV
Figure 23:
Figure 24:
Headphone THD+N vs. Output Power 32Ω
Headphone THD+N vs. Output Power 32Ω
Stereo – ECO Mode
Stereo – High Quality Mode
1
1
Vbat = 1.8V
Vbat = 1.8 ECO
Vbat = 1.4V
Vbat = 1.4V ECO
0,1
0,1
0,01
0,01
0,001
0,001
1
10
100
1
10
100
Pout [mW]
Pout [mW]
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AS3418
Functional Description
Figure 25:
Figure 26:
Headphone THD+N vs. Output Power 16Ω
Headphone THD+N vs. Output Power 16Ω
Stereo – ECO Mode
Stereo – High Quality Mode
1
1
Vbat = 1.8 ECO
Vbat = 1.8V
Vbat = 1.4V ECO
Vbat = 1.4V
0,1
0,1
0,01
0,001
0,01
1
10
100
1
10
100
Pout [mW]
Pout [mW]
Figure 27:
Figure 28:
Headphone THD+N vs. Output Power 32Ω
Headphone THD+N vs. Output Power 32Ω
MONO – High Quality Mode (1.8//1.4V)
MONO –ECO Mode (1.8//1.4V)
1
1
Vbat = 1.8 ECO
Vbat = 1.8V
Vbat = 1.4V ECO
Vbat = 1.4V
0,1
0,1
0,01
0,01
1
10
100
1k
1
10
100
1k
Pout [mW]
Pout [mW]
6.5
Music Bypass Switch
If the AS3418 is switched off, the device features a unique feature, which are integrated music bypass
switches. These switches can be used to replace a mechanical switch to bypass the music signal in
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AS3418
Functional Description
off mode or if the headset runs out of battery. Figure 29 shows the basic music playback path of the
AS3418 with a full battery. In this mode the line input signal is feed to the headphone amplifier. The
integrated bypass switches are automatically disabled in this operation mode.
Figure 29:
Bypass Mode Inactive
100%
BPL
Music Bypass
LINL
AGND
LINR
HPL
HPR
3.5mm audio jack
BPR
Music Bypass
Figure 30 shows the AS3418 in off mode with an empty battery. This is basically the same use case
as no battery at all. In this mode the internal bypass switch becomes active. The headphone amplifier
is not powered because the headset has run out of battery and the bypass switch becomes active.
Thus the music signal coming from the 3.5mm audio jack is routed through the ANC chip, without any
power source connected to the device, to the speakers. The integrated bypass switch works even
without any battery connected to the device. It helps to reduce BOM costs and PCB area. Furthermore
it facilitates new industrial designs to ANC solutions.
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AS3418
Functional Description
Figure 30:
Bypass Mode Active
BPL
Music Bypass
0%
LINL
HPL
HPR
AGND
3.5mm audio jack
LINR
BPR
Music Bypass
6.5.1
Parameter
VBAT =0V, TA= 25ºC, unless otherwise specified.
Figure 31:
Bypass Switch Parameter
Symbol Parameter
Conditions
Min
Typ
Max
Unit
RSWITCH
THD
Switch resistance
Power down
1.2
-85
-79
Ω
0dBV input signal, 32Ω load
0dBV input signal, 16Ω load
dB
dB
Total Harmonic
Distortion
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Functional Description
Figure 32 :
Bypass THD+N vs. Output Power 32Ω Load
0,1
32 Ohm
0,01
0,001
0,0001
1
10
100
Pout [mW]
6.6
Operational Amplifier
The AS3418 offers one general purpose operational amplifier for feed-forward ANC. The amplifier is
used to develop the gain- and phase compensation filter for the ANC signal path.
Figure 33:
Operational Amplifier
OP1L
QOP1L
AGND
QOP1R
OP1R
6.6.1
Parameter
VBAT =1.8V, TA= 25ºC, Rinput = RFB = 1kΩ unless otherwise specified.
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Functional Description
Figure 34:
Operational Amplifier Parameter
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VIN
Input Signal Level
Gain=0dB
0.9*VBAT VBAT
VPEAK
10k load Gain = 0dB (1)
VBAT=1.8V,
,
,
,
,
114.5
dB
dB
dB
dB
High Quality Mode
10k load Gain = 0dB (1)
VBAT=1.4V
111.4
113.3
110
High Quality Mode
Signal to Noise
Ratio
SNR
10k load Gain = 0dB (1)
VBAT=1.8V,
ECO Mode
10k load Gain = 0dB (1)
VBAT=1.4V,
ECO Mode
VBAT = 1.8V; OP1L and
OP1R enabled; normal mode
1
mA
mA
mA
mA
VBAT = 1.8V; OP1L and
OP1R enabled; ECO mode
0.7
0.95
0.65
Block Current
Consumption
IOP1
VBAT = 1.4V; OP1L and
OP1R enabled; normal mode
VBAT = 1.4V; OP1L and
OP1R enabled; ECO mode
Input Referred
Noise Floor A-
Weighted
2.2
2.6
µV
µV
High Quality Mode
ECO Mode
VNOISE-A
VOFFSET
CL
DC offset voltage
Load Capacitance
Load Impedance
Open Loop Gain
500
100
µV
pF
kΩ
dB
Gain=0dB
RL
1
ALOOP
120
100MHz
(1)
SNR figure measured with 20dB gain to minimize audio analyzer noise floor
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AS3418
Functional Description
Figure 35 :
Operational Amplifier Frequency Response
1
ECO Mode
HighQ Mode
0,8
0,6
0,4
0,2
0
-0,2
-0,4
-0,6
-0,8
-1
10
100
1k
f [Hz]
10k
100k
Figure 36 :
OPAMP THD+N vs. Frequency
1
HighQ Mode
ECO Mode
0,1
0,01
0,001
0,0001
10
100
1k
10k
100k
f [Hz]
6.7
System
This chapter describes the power up and power down conditions of AS3418. Furthermore the Start-up
sequence of the device is also described in more detail.
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Functional Description
Figure 37:
Power Up Conditions
#
Source
Description
Depending on the operation mode the power up/down pin
MODE/CSCL pin behaves differently:
Slider Mode: Mode pin has to be driven high turn on the device. Since
the timing can be programmed the value depends also on
POWER_UP_BUT_TIME register setting. With default configuration of
POWER_UP_BUT_TIME register typ. button press time is ~16ms.
Full Slider Mode: Mode pin has to be driven high turn on the device.
Since the timing can be programmed the value depends also on
POWER_UP_BUT_TIME register setting. With default configuration of
POWER_UP_BUT_TIME register typ. button press time is ~16ms.
1
MODE/CSCL pin
Push Button Mode: Mode pin has to be driven high turn on the device.
Since the timing can be programmed the value depends also on
POWER_UP_BUT_TIME register setting. With default configuration of
POWER_UP_BUT_TIME register typ. button press time is ~16ms.
In I2C mode, an I2C start condition turns on the device. For this startup
function I2C_MODE bit must be set in the EEPROM register.
2
I2C start condition
The chip automatically powers down if one of the following conditions arises:
Figure 38:
Power Down Conditions
#
Source
Description
Depending on the operation mode the power MODE/CSCL pin
behaves differently:
Slider Mode: Mode pin has to be driven low for min. 10ms to turn off
the device
1
MODE/CSCL pin
Full Slider Mode: Mode pin has to be driven low for min. 10ms to turn
off the device
Push Button Mode: Mode pin has to be high for the time defined in
PWR_DOWN_BUT_TIME register to turn off the device.
Power down by serial interface is initiated by clearing the PWR_HOLD
bit. (Please mind that the I2C_MODE bit has to be set before clearing
the PWR_HOLD bit to enable the I2C power down mode)
I2C power down
command
2
3
VNEG over current
Power down if VNEG is higher than the VNEG off-threshold.
6.7.1
Start-Up Sequence
The AS3418 has a defined startup sequence. Once the AS3418 MODE pin is pulled high, the device
initiates the automatic startup sequence shown in Figure 39 or Figure 40 depending on the operation
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Functional Description
mode. In case the I2C_MODE bit is set the device behaves differently during startup compared to
normal operation with external slide switch or push button.
Figure 39:
Normal Start-Up Sequence
VBAT
min. 1.4V
min. 70% VBAT
MODE/CSCL
don‘t care
VOL/CSDA
BIAS & OSC ON
~10ms
VNEG OK
START EEPROM DOWNLOAD
~1ms
EEPROM READY
PWR_UP_BUT_TIME
(5ms-2500ms)
Enable MICS charge pump (MSUP)
Enable OPAMPs and MIC Amplifiers
MICS LDO Chargepump OK
~5ms
MICS LDO OK
31ms timeout
~40µs masking
Enable Line Zero Cross Comparator
Right Zero Cross Detect
Left Zero Cross Detect
Enable Right Music Bypass
Enable Left Music Bypass
Enable Headphone Right
Enable Headphone Left
not connected b‘11‘
ANC_HPH_MUX<1:0>
Configure HPH_MUX
PWRUP COMPLETE
FADE IN MIC GAIN
MUTE
OFF
ANC_MICx_GAIN<6:0>
ANC Operation
Fade in MIC Gain
Operating State
Time Axis
START_RAMP_TIME
typ. 52
0
11
t
[ms]
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Functional Description
Figure 40:
I2C Start-Up Sequence
VBAT
min. 1.4V
PWRUP_HOLD = 1
min. 70% VBAT
MODE/CSCL
VOL/CSDA
PWRUP_HOLD = 1
BIAS & OSC ON
~10ms
VNEG OK
START EEPROM DOWNLOAD
EEPROM READY
~1ms
I2C_MODE
I2C_TIMEOUT = 8ms
PWR_HOLD
Enable MICS charge pump (MSUP)
Enable OPAMPs and MIC Amplifiers
MICS LDO Chargepump OK
MICS LDO OK
~5ms
31ms timeout
~40µs masking
Enable Line Zero Cross Comparator
Right Zero Cross Detect
Left Zero Cross Detect
Enable Right Music Bypass
Enable Left Music Bypass
Enable Headphone Right
Enable Headphone Left
Configure HPH_MUX
PWRUP COMPLETE
not connected b‘11‘
ANC_HPH_MUX<1:0>
FADE IN MIC GAIN
MUTE
OFF
ANC_MICx_GAIN<6:0>
ANC Operation
Fade in MIC Gain
Operating State
Time Axis
START_RAMP_TIME
typ. 55
0
11
t
[ms]
6.8
Operation Modes
If the AS3418 is in stand-alone mode (no I2C control), the device can work in different operation
modes. An overview of the different operation modes is shown in Figure 41.
Figure 41:
Operation Modes
MODE
Description
OFF
ANC
Chip is turned off.
Chip is turned on and active noise cancellation is enabled.
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MODE
Description
In Monitor Mode, a different (normally higher) microphone preamplifier gain can be
configured to get an amplification of the ambient noise. To get rid of the low pass
filtering needed for the noise cancellation, the headphone input multiplexer can be
set to a different (normally to MIC) source to increase speech intelligibility. In
addition, the Line Input signal can be muted for further improved intelligibility. If the
device is operated in I2C mode, it is also possible to enter the monitor mode by
setting the MON_MODE_EN bit in register 0x03.
MONITOR
The Playback Only mode is a special mode that disables the noise cancelling
function and just keeps e.g. line input amplifier or headphone amplifier active.
Certainly this operation mode can also be used as an alternative Monitor or ANC
mode with different gain settings.
PBO
With the AS3418 design engineers have different options to enter the described operation modes
shown in Figure 41. In addition to the different user interface modes described in the following three
chapters, it is also important to configure the device accordingly. Figure 42 shows the required register
configuration settings to enable the different AS3418 control modes.
Figure 42:
User Interface Control Modes
MODE
Register UI_MODE<1:0>
Button Mode
Slider Mode
Full Slider Mode
Do not use
0
0
1
1
0
1
0
1
6.8.1
Full Slider Mode
Full Slider Mode enables the AS3418 to be connected to two slide switches for Power, ANC and
Monitor Mode control. To enable this operation mode register UI_MODE has to be set to ‘d2’. The
typical connection of the slide switches is shown in Figure 43.
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Figure 43:
Full Slider Mode
VBAT
MODE/CSCL
ANC/CSDA
22kΩ
Control Logic
22kΩ
1MΩ
S1
S2
OFF ON MON
ANC PBO
In Full Slider Mode the MODE/CSCL pin can detect three different input levels to distinguish between
the different operating modes On, Off and Monitor mode. The timing diagram with all relevant
information is shown in Figure 44.
Figure 44:
Full Slider Timing Diagram
OFF
ON
MONITOR
ON
OFF
Operation Mode
MODE/CSCL Pin
VBAT
>=1.65V
45% - 55% VBAT
> PWR_UP_BUT_TIME
> MON_TIME
> MON_TIME
> SHUTDOWN_DELAY
6.8.2
Slider Mode
Slider Mode is similar to Full Slider Mode with the only difference that it is possible to use a push
button (S3) to enable and disable the Monitor Mode. In order to enable this operation mode, register
UI_MODE has to be set to ‘d1’. The typical connection of the slide switches and push button is shown
in Figure 45.
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Figure 45:
Slider Mode
VBAT
MODE/CSCL
ANC/CSDA
Control Logic
22kΩ
S2
S1
S3
22kΩ
MONITOR
ANC PBO
ON OFF
The advantage of this mode compared to Full Slider Mode is the automatic hold function of the
Monitor Mode. Once the push button S3 is pressed, the device enters monitor mode. This mode stays
active until the user pushes the button again.
Figure 46:
Slider Mode Timing Diagram
OFF
ON
MONITOR
ON
OFF
Operation Mode
MODE/CSCL Pin
VBAT
>=1.65V
45% - 55% VBAT
<0.3V
> SHUTDOWN_DELAY
> PWR_UP_BUT_TIME
> MON_TIME
> MON_TIME
6.8.3
Push Button Mode
Push Button mode allows the user to control the device with a single normally open (NO) push button.
A simple key press (>PWR_UP_BUT_TIME) powers up the AS3418. Once the device is running, a
long key press (>PWR_DOWN_BUT_TIME) the device down. The device features two configuration
registers (PWR_UP_BUT_TIME and PWR_DOWN_BUT_TIME) that allows the user to re-configure
the power up- and power down button press time. Monitor Mode can be activated with a second, short
key press. To avoid unwanted change of operation mode it is also possible to configure the button
press time (MON_TIME) to enter monitor mode. A timing diagram of this function is shown in Figure
48. If the monitor mode function is not desired, it is possible to deactivate the monitor mode by
clearing the bit MON_EN in register 0x0F. The typical connection of the push button to the AS3418 is
shown in Figure 47.
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AS3418
Functional Description
Figure 47:
Push Button Mode
VBAT
MODE/CSCL
ANC/CSDA
Control Logic
S2
S4
22k ꢀ
ANC PBO
ON/OFF/MONITOR
Figure 48:
Push Button Timing Diagram
OFF
ANC
MONITOR
ANC
OFF
Operation Mode
>65% VBAT
MODE/CSCL Pin
<35% VBAT
> MON_TIME
>PWR_DOWN_BUT_TIME
> MON_TIME
> PWR_UP_BUT_TIME
6.8.4
Playback Only Mode
The active noise cancelling feature of the AS3418 can also be disabled with the ANC/CSDA pin. The
ANC/CSDA pin has to be pulled high to enable the ANC function during startup (ANC MODE). If the
pin is connected to ground, the chip enters playback only mode (PBO MODE) in which the ANC
function can be disabled or an alternative monitor/ANC mode is configured. The functional blocks in
this operation mode can be controlled in registers PBO_MODE0 and PBO_MODE1. Typically only the
line input amplifiers and the headphone amplifier are enabled in the playback only mode. If this
function is not desired you just need to pull the pin high with an external 22kΩ resistor.
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AS3418
Functional Description
Figure 49:
Playback Only Mode Timing Diagram
ANC ON
Operation Mode
Playback Only Mode
ANC ON
>65% VBAT
ANC/CSDA Pin
<35% VBAT
200-400ms
200-400ms
6.9
VNEG Charge Pump
The VNEG charge pump uses one external 2.2µF ceramic capacitor (CFLY) to generate a negative
supply voltage out of the input voltage to supply all audio related blocks. This allows a true-ground
headphone output with no need of external DC-decoupling capacitors.
Figure 50:
VNEG Charge Pump
CFLY
VBAT
VBAT
VNEG
Charge Pump
CVNEG
VNEG
CVBAT
Connection to audio blocks
The charge pump typically requires an input capacitor CVBAT with 4.7µF, an output capacitor CVNEG with
a capacity of typ. 10µF and a flying capacitor CFLY with 2.2µF.
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AS3418
Functional Description
6.9.1
Parameter
VBAT =1.8V, TA= 25ºC, unless otherwise specified.
Figure 51:
VNEG Charge Pump Parameter
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VIN
Input Voltage
VBAT
VNEG
1.4
1.6
1.8
-1
V
V
VOUT
Output Voltage
-1.8
VBAT input
capacitor
CVBAT
Effective capacitive value
1.6
4.7
5.46
µF
VNEG output
capacitor
CVNEG
CFLY
Effective capacitive value
Effective capacitive value
3.4
10
12
µF
µF
Flying capacitor
0.97
2.2
2.86
6.10
EEPROM
The AS3418 features an integrated EEPROM that stores the system configuration data like
microphone gain settings and configuration of the different operation modes during power down
operation mode. Because the EEPROM is not bit addressable the AS3418 has an additional register
bank in parallel to the EEPROM that is loaded with the EEPROM content during startup of the device.
Each time AS3418 is powered up the EEPROM content is loaded to the register bank (0x00 – 0x1D)
to configure the AS3418 according to the application requirements. The registers can be accessed via
the I2C interface for embedded applications and system evaluation purpose. For non-embedded
systems were no MCU is in place to configure the device there are two dedicated production trimming
signal lines available that allow access to the AS3418 registers and upload/download function of the
EEPROM.
Figure 52:
Register Access
MODE/CSCL
WRITE
AS3418 Register
ANC/CSDA
0x00 – 0x1D
READ
TRSDA
WRITE
EEPROM
Memory
READ
TRSCL
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AS3418
Functional Description
The EEPROM supports three operation modes:
●
●
Upload Operation - The Upload function copies the register content of register 0x01 – 0x1D
and stores it permanently to the EEPROM.
Download Operation - The Download function copies the permanently stored EEPROM
content to the registers of AS3418 and overwrites the existing register content with the
EEPROM values like it happens during startup of the device.
●
TEST UPLOAD - The Test Upload function is a feature to trigger a test EEPROM upload.
During this test the device does not write the EEPROM settings, instead it just tries if it would be
possible to write the EEPROM successfully. It is recommended to perform this test each time
before a real EEPROM upload is triggered.
6.10.1
EEPROM Download Function
In order to trigger an EEPROM Download function (copy EEPROM content to AS3418 system
registers) the EEPROM_DOWNLOAD bit has to be set in register 0x34. Once the bit is set via I2C
interface or the production trimming interface the EE_READY bit in register 0x01 can be checked if
the download of the EEPROM content is finished. As long as the EE_READY bit is zero the download
process is ongoing. Once the bit is set the download process is completed. A flow chart of the
download is shown in Figure 53.
Figure 53:
EEPROM Download Flow Chart
Set bit
Check
EE_READY bit
in register 0x01
EEPROM Download
complete
EE_READY = 1
EEPROM_DOWNLOAD in
register 0x34
EE_READY = 0
6.10.2
EEPROM Upload Function
An EEPROM Upload function can be simply triggered by setting the EEPROM_UPLOAD bit in register
0x34. Once the bit is set, the EE_READY bit has to be monitored to check the status of the EEPROM.
If the Upload function is completed the EE_READY bit is set and the next step in the upload sequence
is to check the EE_WR_OK bit in the same register 0x01. If the upload process was successfully
completed the bit is set to ‘1’. In case the upload failed the bit is set to ‘0’. The flow chart for the
EEPROM Upload sequence is shown in Figure 54.
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AS3418
Functional Description
Figure 54:
EEPROM Upload Flow Chart
Check
EE_READY bit
in register 0x01
Check
EE_WR_OK bit
in register 0x01
Set bit EEPROM_UPLOAD
EEPROM Upload
EE_READY = 1
EE_WR_OK = 1
in register 0x34
complete
EE_READY = 0
EE_WR_OK = 0
EEPROM Upload
failed
6.10.3
EEPROM Upload Test Function
Before an EEPROM Upload function is started it is recommended to do first an Upload Test. During
this test the device does not write the EEPROM settings, instead it just tries if it would be possible to
write the EEPROM successfully. It is checked if the power supply is sufficient to trigger a real
EEPROM Upload.
Figure 55:
EEPROM Upload Test Function
Set bit
Check
EE_READY bit
in register 0x01
Check
EE_WR_OK bit
in register 0x01
EEPROM Upload Test
complete
EE_READY = 1
EE_WR_OK = 1
EEPROM_UPLOAD_TEST
in register 0x34
EE_READY = 0
EE_WR_OK = 0
EEPROM Upload Test
failed
The sequence for the Upload test function is similar to the real Upload. The only difference is that the
EEPROM_UPLOAD_TEST bit has to be set to start the upload test instead of the
EEPROM_UPLOAD bit. The flow chart for the Upload test sequence is shown in Figure 55.
6.11
Production Trimming Interface
In addition to option programming the AS3418 via I2C interface, the AS3418 features a second unique
trimming mechanism. This very special mode enables the analog music inputs of the AS3418 to
become a digital production trimming input.
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AS3418
Functional Description
Figure 56:
Production Trim Box
LINL
to HPH
MUTE
TRSDA
TRSCL
EEPROM
AS3418
Application Trim Box
LINR
to HPH
MUTE
With this new system, there is no need for mechanical potentiometers any more. Up to now, operators
in production used to use screw drivers to fine tune the ANC performance of each headset. The
disadvantage of this is reliability and cost of potentiometers. Additionally, operators are not always
precise in their work, thus yielding inconsistent results. With the production trimming system from ams
there are no mechanical potentiometers required. The operator connects a 3.5mm audio jack to a
trimming box and this box enables the audio input of the headset to become the ANC tuning input.
This new feature also helps industrial designers of headset because there are no more considerations
concerning leakage holes for the old mechanical trimming. Thus, the headset can be fully assembled
and ready for the ANC test system at the end of the manufacturing process. The trim box can be
easily controlled with an USB interface so it is also possible to create fully automated trimming
systems. For further details please contact our local sales office; they can provide you with source
code examples and application notes.
6.12
I2C Interface
In order to configure the device using the evaluation software or a MCU the AS3418 features a serial
two wire interface. The I²C address for the device can be found in Figure 57.
Figure 57:
I2C Slave Address
7 bit I2C address
8 Bit read address
8 Bit write address
0x47
0x8F
0x8E
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AS3418
Functional Description
6.12.1
Protocol
Figure 58:
I2C Serial Interface Symbol Definition
Symbol
Definition
RW
Note
S
Start condition after stop
Repeated start
R
R
R
R
R
W
R
R
W
R
R
1 bit
1 bit
Sr
DW
DR
Device address for write
Device address for read
Word address
1000 1110b (8Eh)
1000 1111b (8Fh)
WA
A
8 bit
Acknowledge
1 bit
N
No Acknowledge
1 bit
reg_data
data (n)
P
Register data/write
8 bit
Register data/read
8 bit
Stop condition
1 bit
WA++
Increment word address internally
AS3418 (=slave) transmits data
AS3418 (=slave) receives data
during acknowledge
Figure 59:
Byte Write
S
DW
A
WA
A
reg_data
A P
WA++
Figure 60:
Page Write
S
DW
A
WA
A
reg_data 1
A
reg_data 2
A
...
reg_data n A P
WA++
WA++
WA++
Byte Write and Page Write formats are used to write data to the slave. The transmission begins with
the START condition, which is generated by the master when the bus is in IDLE state (the bus is free).
The device-write address is followed by the word address. After the word address any number of data
bytes can be sent to the slave. The word address is incremented internally, in order to write
subsequent data bytes to subsequent address locations.
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AS3418
Functional Description
For reading data from the slave device, the master has to change the transfer direction. This can be
done either with a repeated START condition followed by the device-read address, or simply with a
new transmission START followed by the device-read address, when the bus is in IDLE state. The
device-read address is always followed by the 1st register byte transmitted from the slave. In Read
Mode any number of subsequent register bytes can be read from the slave. The word address is
incremented internally.
Figure 61:
Random Read
S
DW
A
WA
A Sr
DR
A
data N P
RA++
Random Read and Sequential Read are combined formats. The repeated START condition is used to
change the direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is
idle. The START condition is followed by the device-write address and the word address.
In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after
the acknowledge bit of the word address transfer. After the reception of the device-read address, the
slave becomes the transmitter. In this state the slave transmits register data located by the previous
received word address vector. The master responds to the data byte with a not-acknowledge, and
issues a STOP condition on the bus.
Figure 62:
Sequential Read
S
DW
A
WA
A Sr
DR
A
reg_data 1
A
reg_data 2
A
...
reg_data n
N P
RA++
RA++
RA++
Sequential Read is the extended form of Random Read, as more than one register-data bytes are
transferred subsequently. Different from the Random Read, for a sequential read, the transferred
register-data bytes are responded with an acknowledge from the master. The number of data bytes
transferred in one sequence is unlimited (consider the behavior of the word-address counter). To
terminate the transmission the master has to send a not-acknowledge following the last data byte and
then generate the STOP condition.
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AS3418
Functional Description
Figure 63:
Current Address Read
S
DR
A
data
A
reg_data 2
A
...
reg_data n
N P
RA++
RA++
RA++
To keep the access time as short as possible, this format allows a read access without the word
address transfer in advance to the data transfer. The bus is idle and the master issues a START
condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is
terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an
unlimited number of data bytes can be transferred, where the data bytes have to be responded with an
acknowledge from the master. For termination of the transmission, the master sends a not-
acknowledge following the last data byte and a subsequent STOP condition.
6.12.2
Parameter
VBAT =1.8V, TA=25ºC, unless otherwise specified.
Figure 64:
I2C Serial Timing
SU
H
HD
L
PD
TS
T
T
T
T
T
MODE/CSCL
ANC/CSDA
1-7
8
9
1-7
8
9
1-7
8
9
Start
Condition
Address
R/W
ACK
Data
ACK
Data
ACK
Stop
Condition
Figure 65:
I2C Serial Interface Parameter
Symbol Parameter
Conditions
Min
Typ
Max
0.42
Unit
CSCL, CSDA Low
VCSL
(max 30% VBAT
)
0
-
V
Input Level
CSCL, CSDA High
Input Level
VCSH
CSCL, CSDA (min 70% VBAT
)
1.16
-
V
CSCL, CSDA Input
Hysteresis
HYST
450
mV
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AS3418
Functional Description
Symbol Parameter
Conditions
Min
Typ
Max
Unit
CSDA Low Output
Level
VOL
at 3mA
-
-
0.4
-
V
Tsp
TH
Spike insensitivity
Clock high time
Clock low time
50
100
ns
ns
ns
max. 400kHz clock speed
max. 400kHz clock speed
500
500
TL
CSDA has to change Tsetup
before rising edge of CSCL
TSU
THD
250
0
-
-
-
-
ns
ns
No hold time needed for CSDA
relative to rising edge of CSCL
CSDA H hold time relative to
CSDA edge for
start/stop/rep_start
TS
200
-
-
ns
ns
CSDA prop delay relative to low
going edge of CSCL
TPD
50
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AS3418
Register Description
7 Register Description
7.1
Register Overview
Figure 66:
Register Overview
Addr
Name
<D7>
<D6>
<D5>
<D4>
<D3>
<D2>
<D1>
<D0>
System Registers
0x00
0x01
ID
DESIGN_VERSION<3:0>
CHIP_ID<3:0>
EE_RE
EE_WR
_TEST_
OK
PWRUP
_COMP
LETE
PWR_H
OLD
SYSTEM_STATUS
-
-
-
LOBAT
ADY
NO_LO
BAT_O
FF
EN_ZE
RO_CR
OSS
DELAY
_HPH_
MUX
MICS_
DC_EN
HPH_M
ODE
I2C_MO
DE
0x02
0x03
0x04
MODE_REG0
MODE_REG1
MICS_VOLTAGE
UI_MODE<1:0>
ANCMO
ANCMO ANCMO
PBO_M
ODE_E
N
MON_M
ODE_E
N
N_MIC
S_CP_
BYP_E
N
ANCMO ANCMO
N_MIC_ N_HPH
ON
N_MIC
S_CP_
ON
N_MIC
S_LDO
_ON
-
_ON
MICS_L MICS_L
DO_CV
_MODE
DO_CD
_MODE
-
-
MICS_V_SEL<3:0>
PWR_DOWN_BUT_TIME<2:0
>
0x05
0x06
PUSH_DELAY
ON_DELAY
-
-
-
-
PWR_UP_BUT_TIME<2:0>
ON_DELAY<2:0>
LDO_BOOST<2:0>
HIQ_EN
_MICS_
LDO
HIQ_EN
HIQ_EN HIQ_EN
_OPAM
HIQ_ECO_PRESE
T<1:0>
0x07
HIQ_MODE_REG
-
-
-
_HPH
_MIC
P
0x08
0x09
LED_MON
LED_ANC
-
-
-
MON_LED_MODE<2:0>
MON_ILED<1:0>
ANC_ILED<1:0>
PBO_LED_MODE<
1:0>
ANC_LED_MODE<
1:0>
-
ANC Mode Control Registers
ANC_O
P1L_O
N
ANC_O
P1R_O
N
ANC_HPH_MUX<1
:0>
LIN_MU
TE
0x0A
ANC_MODE_REG
-
-
-
ANC_MIC_LEFT_GAI
N
0x0B
0x0C
-
-
ANC_MIC_LEFT_GAIN<6:0>
ANC_MIC_RIGHT_GAIN<6:0>
ANC_MIC_RIGHT_G
AIN
Monitor Mode Control Registers
MON_LI
MON_M
MON_O MON_O
MON_E
N
0x0D
0x0E
MONITOR_MODE0
MONITOR_MODE1
0
-
N_MUT
E
0
-
0
-
P1L_O
N
P1R_O
N
IX_EN
MON_HPH_MUX<
1:0>
-
MON_TIME<1:0>
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Register Description
Addr
Name
<D7>
<D6>
<D5>
<D4>
<D3>
<D2>
<D1>
<D0>
MON_MIC_LEFT_GA
IN
0x0F
-
MON_MIC_LEFT_GAIN<6:0>
MON_MIC_RIGHT_GAIN<6:0>
MON_MIC_RIGHT_G
AIN
0x10
-
PBO Mode Control Registers
PBO_LI
PBO_M
PBO_O
P1L_O
N
PBO_O
P1R_O
N
PBO_E
N
0x11
0x12
PBO_MODE0
PBO_MODE1
-
N_MUT
E
-
-
IX_EN
HPH_O
N/DIS_
BYPAS
S
PBO_M
ICS_CP
_BYP_
EN
PBO_HPH_MUX
<1:0>
PBO_M
ICS_LD
O_ON
PBO_M
ICS_CP
_ON
PBO_M
IC_ON
-
PBO_MIC_LEFT_GAI
N
0x13
0x14
-
-
PBO_MIC_LEFT_GAIN<6:0>
PBO_MIC_RIGHT_GAIN<6:0>
PBO_MIC_RIGHT_G
AIN
AGC Control Registers
ZERO_
CROSS
_EN
AGC_M
UTE_E
N
AGC_ATTACK_LE
VEL<1:0>
AGC_RELEASE_L
EVEL<1:0>
NEG_A
TT_EN
AGC_E
N
0x15
0x16
AGC_CONTROL0
AGC_ATTACK_RELE
ASE_TIME
AGC_RELEASE_TIME<3:0>
ZERO_TIMEOUT<3:0>
AGC_ATTACK_TIME<3:0>
HOLD_TIME<3:0>
0x17
0x18
AGC_HOLD
AGC_START_TIME
-
-
-
-
-
-
START_RAMP_TIME<2:0>
Operation Mode Control Register
GAIN_J
GAIN_J
UMP_U
P_EN
MODE_SWITCH_CO
NTROL
SHUTDOWN_DEL
AY<1:0>
MODE_SWITCH_D
ELAY<1:0>
UMP_D
OWN_E
N
0x1A
-
EEPROM Control Register
EEPRO
M_UPL
OAD_T
EST
EEPRO
M_DO
WNLOA
D
EEPRO
M_UPL
OAD
0x34
EEPROM_CONTROL
-
-
-
-
-
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AS3418
Register Description
7.2
Detailed Register Description
7.2.1
System Registers
Figure 67:
ID Register Description
Addr: 0x00
ID
Bit Bit Name
Default
Access Bit Description
Design version number to identify the design version
of the AS3418.
DESIGN_VER
SION
7:4
0110
0001
R
R
0110: Chip Version 3.0
This register represents the chip ID number of
AS3418.
3:0 CHIP_ID
0001: AS3418
Figure 68:
SYSTEM_STATUS Register Description
Addr: 0x01
SYSTEM_STATUS
Bit Bit Name
Default
Access Bit Description
This register reports if an EEPROM upload test was
successfully finished. This bit is also used for the
EEPROM-Program-Test (together with
EEPROM_UPLOAD_TEST), where a “dummy-write”
can be initialized to check the power-supply
EE_WR_TEST
_OK
4
3
-
R
R
0: EEPROM upload TEST failed
1: EEPROM upload TEST successful
This registers indicates the status after a read/write
command of the EEPROM.
EE_READY
-
0: EEPROM busy
1: EEPROM ready
This bit indicates the Power-Up sequencer status of
AS3418. The signal goes high after all amplifiers are
enabled but before the microphone signal is faded in.
PWRUP_COM
PLETE
1
0
1
1
R
0: Power-up sequence incomplete
1: Power-up sequence completed
This bit allows an MCU, using the I2C interface, to
power down the AS3418. A start condition on the I2C
interface will wake up the device again. This function
PWR_HOLD
R/W
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AS3418
Register Description
Addr: 0x01
SYSTEM_STATUS
Bit Bit Name
Default
Access Bit Description
works only if the I2C_MODE bit is set. In case
I2C_MODE is low, the register content is ignored.
0: Power up hold is cleared and chip powers down
1: Device remains powered on
Figure 69:
MODE_REG0 Register Description
Addr: 0x02
MODE_REG0
Bit
Bit Name
Default
Access Bit Description
This bit activates zero cross detection while switching
between music bypass switch and headphone
amplifier.
EN_ZERO_C
ROSS
6
1
R/W
R/W
0: Zero cross detection is disabled.
1: Zero cross detection is enabled.
This register controls the startup delay setting before
the ANC_HPH_MUX setting is applied to the system.
This function can help to reduce pop noise during
startup of the device especially if there are
components with long charging times involved. This
bit is only valid during initial startup.
DELAY_HPH_
MUX
5
0
0: Headphone MUX delay disabled
1: Headphone MUX delay enabled
This register defines the user interface operation
mode of AS3418. For a detailed description of the
different user interface modes please refer to chapter
Operation Modes.
4:3 UI_MODE
01
R/W
00: Push Button Operation Mode
01: Slider Operation Mode
10: Full Slider Operation
11: Do not use
This bit enables the internal microphone supply
discharge function if the microphone supply is
switched off. The MICS_LDO pin is discharged within
~10ms.
2
1
MICS_DC_EN
1
0
R/W
R/W
0: MICS_LDO discharge disabled
1: MICS_LDO discharge enabled
This register controls the operation mode of the
headphone amplifier. The headphone amplifier
supports single ended mode and differential mode. In
differential output mode the right audio signal path is
the active input signal for the headphone amplifier.
HPH_MODE
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AS3418
Register Description
Addr: 0x02
MODE_REG0
Bit
Bit Name
Default
Access Bit Description
0: Stereo single ended mode
1: Mono differential mode
All registers can be read and written by the I2C
interface independent on the level of I2C_MODE bit
but I2C_MODE controls whether the main modes of
AS3418 (MON/ANC/PBO/ON/OFF) are controlled by
the MON_MODE_EN, PBO_MODE_EN bits and
SYSTEM_STATUS registers or by the buttons and
switches. Once the bit is set and the system powers
up because there’s an I2C start condition applied to
the CSCL and CSDA pins, the user has to write the
PWR_HOLD bit within SHUTDOWN_DELAY,
otherwise AS3418 powers down again.
0
I2C_MODE
0
R/W
This can be done either over the CSDA/CSCL or
over the application trimming interface.
0: I2C mode control functions disabled
1: I2C mode control functions enabled
Figure 70:
MODE_REG1 Register Description
Addr: 0x03
MODE_REG1
Bit
Bit Name
Default
Access Bit Description
In case I2C_MODE bit is not set, the register content
is ignored but can be read and written. In case
I2C_MODE bit is set, this bit controls the operation
mode of AS3418 (ANC, MON, PBO). In case the
PBO_MODE_EN is 1, MON_MODE_EN has to be 0.
PBO_MODE_
EN
7
0
R/W
0: ANC Mode
1: PBO Mode
In case I2C_MODE bit is not set, the register content
is ignored but can be read and written. In case
I2C_MODE bit is set, this bit controls the operation
mode of AS3418 (ANC, MON, PBO). In case the
PBO_MODE_EN is 1, MON_MODE_EN has to be 0.
MON_MODE_
EN
6
4
0
0
R/W
R/W
0: ANC Mode
1: MON Mode
This bit enables the automatic VBAT to MICS bypass
function when the microphone supply charge pump is
switched off. This function has to be activated in case
the microphone supply voltage regulator is supplied
externally via MICS_CP pin.
ANCMON_MI
CS_BYP_EN
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AS3418
Register Description
Addr: 0x03
MODE_REG1
Bit
Bit Name
Default
Access Bit Description
0: MIC charge pump bypass function disabled
1: MIC charge pump bypass function enabled
This bit controls the microphone supply charge
pump. The microphone charge pump has a second
function besides the bias voltage generation for
microphones. It is also used to disable the integrated
music bypass switch if the AS3418 is active. In case
the integrated bypass switch is used in an application
this bit must not be set to ‘0’.
ANCMON_MI
CS_CP_ON
3
1
R/W
0: Microphone supply charge pump disabled
1: Microphone supply charge pump enabled
WARNING: Microphone supply is also used for
disabling the Bypass switch. If Microphone supply is
disabled an external supply is required.
This bit controls the microphone supply. In case this
bit is set to ‘1’ the microphone supply voltage
regulator (MICS output pin) is powered up.
ANCMON_MI
CS_LDO_ON
2
1
1
1
R/W
R/W
0: Microphone supply switched off
1: Microphone supply switched on
This bit powers up the microphone preamplifier.
0: Microphone preamplifier disabled
ANCMON_MI
C_ON
1: Microphone preamplifier enabled
This bit allows the user to power down headphone
amplifier in case it is not used in the final application
in order to save system power.
ANCMON_HP
H_ON
0
1
R/W
0: Headphone amplifier disabled
1: Headphone amplifier enabled
Figure 71:
MICS_VOLTAGE Register Description
Addr: 0x04
MICS_VOLTAGE
Bit
Bit Name
Default
Access Bit Description
Signals if the MICS_LDO is in constant voltage
mode.
MICS_LDO_C
V_MODE
7
-
R
R
1: Constant voltage mode active
0: Constant voltage mode inactive
Signals if the microphone supply is in constant drop
mode
MICS_LDO_C
D_MODE
6
-
1: Constant drop mode active
0: Constant drop mode inactive
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AS3418
Register Description
Addr: 0x04
MICS_VOLTAGE
Bit
Bit Name
Default
Access Bit Description
This register controls the output voltage of the
integrated microphone supply regulator.
0000: 1.6V
0001: 1.7V
0010: 1.8V
0011: 1.9V
0100: 2.0V
0101: 2.1V
0110: 2.2V
0111: 2.3V
3:0 MICS_V_SEL
1011
R/W
1000: 2.4V
1001: 2.5V
1010: 2.6V
1011: 2.7V(default)
1100: 2.8V
1101: 2.9V
1110: Do not use
…
1111: Do not use
Figure 72:
PUSH_DELAY Register Description
Addr: 0x05
PUSH_DELAY
Bit
Bit Name
Default
Access Bit Description
This register controls the hold time for the push
button in order to power down the AS3418.
Depending on the register setting the power down
push button time can be programmed accordingly.
This delay is applied for button, slider and full slider
mode.
000: 5ms
PWR_DOWN_
BUT_TIME
001: 500ms
010: 1000ms
011: 1500ms
100: 2000ms
101: 2500ms
110: 2500ms
111: 2500ms
5:3
111
R/W
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AS3418
Register Description
Addr: 0x05
PUSH_DELAY
Bit
Bit Name
Default
Access Bit Description
This register controls the hold time for the push
button in order to power up the AS3418. Depending
on the register setting the power up push button time
can be programmed accordingly. This delay is
applied for button, slider and full slider mode.
000: 5ms
001: 500ms
010: 1000ms
011: 1500ms
100: 2000ms
101: 2500ms
110: 2500ms
111: 2500ms
PWR_UP_BU
T_TIME
2:0
000
R/W
Figure 73:
ON_DELAY Register Description
Addr: 0x06
ON_DELAY
Bit
Bit Name
Default
Access Bit Description
This register controls the pre-charge time of the
microphone supply LDO. LDO_BOOST is effective
not only during startup but also whenever the LDO is
enabled after startup.
000: 0ms
001: 150ms
010: 400ms
011: 600ms
100: 800ms
101: 1000ms
110: 1200ms
111: 1500ms
5:3 LDO_BOOST
001
R/W
This register controls the power on delay setting. If
this register is set, the device powers up but stays in
a Mute mode with the integrated bypass switches
deactivated to block unwanted noise at the line input.
000: 0ms
2:0 ON_DELAY
000
R/W
001: 200ms
010: 400ms
011: 600ms
100: 800ms
101: 1200ms
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AS3418
Register Description
Addr: 0x06
ON_DELAY
Default
Bit
Bit Name
Access Bit Description
110: 1600ms
111: 2000ms
Figure 74:
ECO_MODE_REG Register Description
Addr: 0x07
ECO_MODE_REG
Bit
Bit Name
Default
Access Bit Description
This register allows the device to achieve best offset
performance. Depending on the quality settings of
headphone amplifier, microphone pre-amplifier and
OP1 the correct preset from the table below has to
be configured to ensure lowest offset values.
HIQ_ECO_PR
ESET
7:6
00
R/W
00: HPH->HIQ; MIC->HIQ; OP1->HIQ
01: HPH->HIQ; MIC->ECO; OP1->ECO
10: HPH->HIQ; MIC->HIQ; OP1->ECO
11: HPH->ECO; MIC->ECO; OP1->ECO
This bit enables the high quality mode of the
microphone LDO.
HIQ_EN_MIC
S_LDO
3
2
1
0
1
1
1
1
R/W
R/W
R/W
R/W
0: High quality function disabled
1: High quality function enabled
This bit enables the high quality mode of the
headphone amplifier.
HIQ_EN_HPH
HIQ_EN_MIC
0: High quality function disabled
1: High quality function enabled
This bit enables the high quality mode of the
microphone amplifier.
0: High quality function disabled
1: High quality function enabled
This bit enables the high quality mode of the
operational amplifier amplifiers for ANC filter design.
HIQ_EN_OPA
MP
0: High quality function disabled
1: High quality function enabled
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AS3418
Register Description
Figure 75:
LED_MON Register Description
Addr: 0x08
LED_MON
Default
Bit
Bit Name
Access Bit Description
This register controls blinking time of LED in MON
mode.
000: LED always on
001: 80ms PWM active / 80ms off
010: 80ms PWM active / 160ms off
011: 80ms PWM active / 240ms off
100: 80ms PWM active / 320ms off
101: 80ms PWM active / 400ms off
110: 80ms PWM active / 480ms off
111: 80ms PWM active / 560ms off
MON_LED_M
ODE
4:2
000
R/W
This register controls the integrated LED driver
current sink of the AS3418 in Monitor operation
mode.
00: ILED current sink switched off
01: 25% duty cycle (4µs on/ 14µs off)
10: 50% duty cycle (9µs on/ 9µs off)
11: 100% duty cycle (18µs on/ 0µs off)
1:0 MON_ILED
00
R/W
Figure 76:
LED_ANC Register Description
Addr: 0x09
LED_ANC
Default
Bit
Bit Name
Access Bit Description
Defines the blinking scheme if PBO mode is active.
Please note that PBO mode has not an individual
LED control register. Therefore this setting uses
hardcoded 25% PWM duty cycle for brightness.
PBO_LED_M
ODE
00: LED always off
6:5
00
R/W
01: Blinking scheme as in ANC mode
10: Blinking scheme as in MON mode
11: LED always on (=PWM always active)
This register controls the different LED effects for
ANC mode with various on/off times as well as
different flash frequencies.
ANC_LED_M
ODE
3:2
00
R/W
00: LED always on
01: 80ms on / 1s off
10: 80ms on / 1.5s off
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AS3418
Register Description
Addr: 0x09
LED_ANC
Default
Bit
Bit Name
Access Bit Description
11: 80ms on / 2.5s off
This register controls the integrated LED driver
current sink of the AS3418 in ANC operation mode.
The typical PWM frequency is 1/18µs=55.6kHz.
00: ILED current sink switched off
01: 25% duty cycle (4µs on/ 14µs off)
10: 50% duty cycle (9µs on/ 9µs off)
11: 100% duty cycle (18µs on/ 0µs off)
1:0 ANC_ILED
00
R/W
7.2.2
ANC Mode Control Registers
Figure 77:
ANC_MODE_REG Register Description
Addr: 0x0A
ANC_MODE_REG
Bit
Bit Name
Default
Access Bit Description
This register selects the ANC input source for the
headphone amplifier in ANC mode. Depending on
the register, setting different outputs are routed to the
headphone amplifier input. It is also possible to
disconnect all ANC input sources which is sometimes
desired in monitor mode.
ANC_HPH_M
UX
7:6
11
R/W
00: QMIC outputs are connected to HPH input
01: OP1 outputs are connected to HPH input
10: Do not use this setting
11: Nothing connected to HPH input except line
input in case it is enabled.
This bit mutes the line input signal. If the bit is set the
line input signal is disconnected from the headphone
amplifier in ANC operation mode.
5
LIN_MUTE
0
R/W
0: Line input signal enabled
1: Line input signal muted
This register enables the left channel of OPAMP 1 in
ANC operation mode.
ANC_OP1L_O
N
1
0
0
0
R/W
R/W
0: Left OP1 is switched off
1: Left OP1 is switched on
This register enables the right channel of OPAMP 1
in ANC operation mode.
ANC_OP1R_
ON
0: Right OP1 is switched off
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AS3418
Register Description
Addr: 0x0A
ANC_MODE_REG
Bit
Bit Name
Default
Access Bit Description
1: Right OP1 is switched on
Figure 78:
ANC_MIC_LEFT_GAIN Register Description
Addr: 0x0B
ANC_MIC_LEFT_GAIN
Bit
Bit Name
Default
Access Bit Description
Volume settings for left microphone input, adjustable
in 63 steps of 0.5dB for ANC operation mode.
000 0000: 0dB
000 0001: 0.5dB gain
000 0010: 1.0dB gain
000 0011: 1.5dB gain
…
ANC_MIC_LE
FT_GAIN
101
0111
6:0
R/W
011 1110: 31dB gain
011 1111: Do not use
101 0111: MUTE (Mute code if NEG_ATT_EN bit
set)
111 1111: MUTE (Mute code if NEG_ATT_EN bit
not set)
Figure 79:
ANC_MIC_RIGHT_GAIN Register Description
Addr: 0x0C
ANC_MIC_RIGHT_GAIN
Bit
Bit Name
Default
Access Bit Description
Volume settings for right microphone input,
adjustable in 63 steps of 0.5dB for ANC operation
mode.
000 0000: 0dB
000 0001: 0.5dB gain
000 0010: 1.0dB gain
000 0011: 1.5dB gain
…
ANC_MIC_RI
GHT_GAIN
101
0111
6:0
R/W
011 1110: 31dB gain
011 1111: Do not use
101 0111: MUTE (Mute code if NEG_ATT_EN bit
set)
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AS3418
Register Description
Addr: 0x0C
Bit Bit Name
ANC_MIC_RIGHT_GAIN
Default
Access Bit Description
111 1111: MUTE (Mute code if NEG_ATT_EN bit
not set)
7.2.3
Monitor Mode Control Registers
Figure 80:
MONITOR_MODE0 Register Description
Addr: 0x0D
MONITOR_MODE0
Bit
Bit Name
Default
Access Bit Description
This bit disables the monitor mode function in all
operation modes.
7
MON_ EN
1
R/W
R/W
R/W
R/W
0: Monitor mode disabled
1: Monitor mode enabled
This bit enables mute function for the line input in
monitor more.
MON_LIN_MU
TE
5
1
0
1
0
0
0: Line input enabled in Monitor mode
1: Line input muted in Monitor mode
This register enables the left channel of OPAMP 1 in
MON operation mode.
MON_OP1L_
ON
0: Left OP1 is switched off
1: Left OP1 is switched on
This register enables the right channel of OPAMP 1
in MON operation mode.
MON_OP1R_
ON
0: Right OP1 is switched off
1: Right OP1 is switched on
Figure 81:
MONITOR_MODE1 Register Description
Addr: 0x0E
MONITOR_MODE1
Bit
Bit Name
Default
Access Bit Description
Time needed to press the monitor switch until
monitor mode is activated.
00: 25ms
MON_TIME<1:
0>
5:4
00
R/W
01: 200ms
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AS3418
Register Description
Addr: 0x0E
MONITOR_MODE1
Bit
Bit Name
Default
Access Bit Description
10: 400ms
11: 600ms
This register selects the ANC input source for the
headphone amplifier in Monitor mode. Depending on
the register setting different outputs are routed to the
headphone amplifier input. It is also possible to
disconnect all ANC input sources which is sometimes
desired in monitor mode.
MON_HPH_M
UX<1:0>
1:0
00
R/W
00: QMIC outputs are connected to HPH input
01: OP1 outputs are connected to HPH input
10: Do not use (reserved for OP2)
11: QMIC, OP1 are disconnected from HPH
Figure 82:
MON_MIC_LEFT_GAIN Register Description
Addr: 0x0F
MON_MIC_LEFT_GAIN
Default Access Bit Description
Volume settings for left microphone input, adjustable
Bit
Bit Name
in 63 steps of 0.5dB for Monitor operation mode.
000 0000: 0dB
000 0001: 0.5dB gain
000 0010: 1.0dB gain
000 0011: 1.5dB gain
…
MON_MIC_LE 101
FT_GAIN 0111
6:0
R/W
011 1110: 31dB gain
011 1111: Do not use
101 0111: MUTE (Mute code if NEG_ATT_EN bit
set)
111 1111: MUTE (Mute code if NEG_ATT_EN bit
not set)
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AS3418
Register Description
Figure 83:
MON_MIC_RIGHT_GAIN Register Description
Addr: 0x10
MON_MIC_RIGHT_GAIN
Bit
Bit Name
Default
Access Bit Description
Volume settings for right microphone input,
adjustable in 63 steps of 0.5dB for Monitor operation
mode.
000 0000: 0dB
000 0001: 0.5dB gain
000 0010: 1.0dB gain
000 0011: 1.5dB gain
…
MON_MIC_RI
GHT_GAIN
101
0111
6:0
R/W
011 1110: 31dB gain
011 1111: do not use
101 0111: MUTE (Mute code if NEG_ATT_EN bit
set)
111 1111: MUTE (Mute code if NEG_ATT_EN bit
not set)
7.2.4
PBO Mode Control Registers
Figure 84:
PBO_MODE0 Register Description
Addr: 0x11
PBO_MODE0
Bit
Bit Name
Default
Access Bit Description
This bit disables the Playback Only mode function in
all modes. No external pull up resistor is required on
ANC / CSDA pin if this bit is set to ‘0’.
7
PBO_EN
1
R/W
0: Playback only mode disabled
1: Playback only mode enabled
This bit mutes the line input in Playback Only
operation mode.
PBO_LIN_MU
TE
5
1
0
0
R/W
R/W
0: Line input enabled
1: Line input muted
This register enables the left channel of OPAMP 1 in
playback only mode.
PBO_OP1L_O
N
0: Left OP1 is switched off
1: Left OP1 is switched on
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AS3418
Register Description
Addr: 0x11
PBO_MODE0
Bit
Bit Name
Default
Access Bit Description
This register enables the right channel of OPAMP 1
in playback only mode.
PBO_OP1R_
ON
0
0
R/W
0: Right OP1 is switched off
1: Right OP1 is switched on
Figure 85:
PBO_MODE1 Register Description
Addr: 0x12
PBO_MODE1
Bit
Bit Name
Default
Access Bit Description
0
This register disables the headphone amplifier in
Playback Only mode and enables the integrated
music bypass switch.
HPH_ON/DIS_
BYPASS
6
R/W
R/W
0: Headphone amplifier disabled/ Bypass enabled
1: Headphone amplifier enabled
0
1
This bit disables the automatic charge pump bypass
function if the microphone supply charge pump is in
off mode.
PBO_MICS_C
P_BYP_EN
5
4
0: Charge Pump bypass disabled
1: Charge Pump bypass enabled
This bit enables the microphone LDO in Playback
Only operation mode.
PBO_MICS_L
DO_ON
0: Microphone Supply voltage LDO regulator
disabled
R/W
R/W
1: Microphone Supply voltage LDO regulator
enabled
1
This bit controls the microphone supply charge
pump. Please mind that disabling the charge pump
automatically activates the integrated music bypass
switch.
PBO_MICS_C
P_ON
3
0: Microphone supply charge pump disabled
1: Microphone supply charge pump enabled
0
This register controls the microphone preamplifier in
Playback Only operation mode.
2
PBO_MIC_ON
R/W
R/W
0: Microphone preamplifier disabled
1: Microphone preamplifier enabled
11
This register selects the input source of the
headphone amplifier in Playback Only operation
mode. Depending on register setting the microphone
PBO_HPH_M
UX
1:0
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AS3418
Register Description
Addr: 0x12
PBO_MODE1
Default
Bit
Bit Name
Access Bit Description
preamplifier or OPAMP1 can be connected to the
headphone amplifier input.
00: QMIC outputs are connected to HPH input
01: OP1 outputs are connected to HPH input
10: Do not use
11: Nothing connected to HPH input except line
input.
Figure 86:
PBO_MIC_LEFT_GAIN Register Description
Addr: 0x13
PBO_MIC_LEFT_GAIN
Bit
Bit Name
Default
Access Bit Description
Volume settings for left microphone input, adjustable
in 63 steps of 0.5dB for PBO operation mode.
000 0000: 0dB
000 0001: 0.5dB gain
000 0010: 1.0dB gain
000 0011: 1.5dB gain
…
PBO_MIC_LE
FT_GAIN
101
0111
6:0
R/W
011 1110: 31dB gain
011 1111: do not use
101 0111: MUTE (Mute code if NEG_ATT_EN bit
set)
111 1111: MUTE (Mute code if NEG_ATT_EN bit
not set)
Figure 87:
PBO_MIC_RIGHT_GAIN Register Description
Addr: 0x14
PBO_MIC_RIGHT_GAIN
Bit
Bit Name
Default
Access Bit Description
Volume settings for right microphone input,
adjustable in 63 steps of 0.5dB for PBO operation
mode.
PBO_MIC_RI
GHT_GAIN
101
0111
6:0
R/W
000 0000: 0dB
000 0001: 0.5dB gain
000 0010: 1.0dB gain
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AS3418
Register Description
Addr: 0x14
Bit Bit Name
PBO_MIC_RIGHT_GAIN
Default
Access Bit Description
000 0011: 1.5dB gain
…
011 1110: 31dB gain
011 1111: do not use
101 0111: MUTE (Mute code if NEG_ATT_EN bit
set)
111 1111: MUTE (Mute code if NEG_ATT_EN bit
not set)
7.2.5
AGC Control Registers
Figure 88:
AGC_CONTROL0 Register Description
Addr: 0x15
AGC_CONTROL0
Bit
Bit Name
Default
Access Bit Description
This register disables the zero cross detection
function of the AGC.
ZERO_CROS
S_EN
7
0
R/W
R/W
0: Zero cross detection disabled
1: Zero cross detection enabled
This register controls the attack level threshold
voltage of the AGC.
00: 0.277* VBAT attack level
01: 0.333* VBAT attack level
10: 0.395* VBAT attack level
11: 0.463* VBAT attack level
ATTACK_LEV
EL
6:5
0
This register controls the release level threshold
voltage of the AGC.
00: 0.200* VBAT release level
01: 0.250* VBAT release level
10: 0.304* VBAT release level
11: 0.364* VBAT release level
RELEASE_LE
VEL
4:3
00
R/W
R/W
This bit enables the mute function for the automatic
gain control.
AGC_MUTE_
EN
2
0
0: AGC mute function disabled
1: AGC mute function enabled
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AS3418
Register Description
Addr: 0x15
AGC_CONTROL0
Bit
Bit Name
Default
Access Bit Description
This bit enables negative the negative gain option for
the microphone preamplifier in case of a microphone
overload condition. The gain can go down to -40dB.
In case the AGC_MUTE_EN bit is not. If the
AGC_MUTE_EN bit is set the preamplifier goes to -
40dB and eventually mutes the output.
NEG_ATTEN_
EN
1
0
R/W
R/W
0: Negative attenuation disabled
1: Negative attenuation enabled
This bit enables/disabled the automatic gain control
function of AS3418. This setting is valid for ANC,
Monitor and PBO operation mode.
0
AGC_EN
0
0: AGC disabled
1: AGC enabled
Figure 89:
AGC_ATTACK_RELEASE_TIME Register Description
Addr: 0x16
AGC_ATTACK_RELEASE_TIME
Bit
Bit Name
Default
Access Bit Description
This register controls the AGC release time.
0000: 0ms
0001: 0.5ms
0010: 1ms
0011: 2ms
0100: 4ms
0101: 8ms
0110: 10ms
0111: 12ms
1000: 16ms
1001: 20ms
1010: 24ms
1011: 28ms
1100: 32ms
1101: 64ms
1110: 128ms
1111: 256ms
AGC_RELEAS
E_TIME
7:4
0001
R/W
This register controls the AGC attack time.
0000: 0.5µs
0001: 1µs
0010: 2µs
AGC_ATTACK
_TIME
3:0
0000
R/W
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AS3418
Register Description
Addr: 0x16
AGC_ATTACK_RELEASE_TIME
Bit
Bit Name
Default
Access Bit Description
0011: 4µs
0100: 8µs
0101: 12µs
0110: 16µs
0111: 24µs
1000: 32µs
1001: 64µs
1010: 128µs
1011: 256µs
1100: 512µs
1101: 1000µs
1110: 2000µs
1111: 4000µs
Figure 90:
AGC_HOLD Register Description
Addr: 0x17
AGC_HOLD
Bit
Bit Name
Default
Access Bit Description
This register controls the timeout of the zero cross
detection.
0000: 0 (no timeout)
0001: 20ms
0010: 40ms
0011: 80ms
0100: 120ms
0101: 160ms
0110: 240ms
0111: 320ms
1000: 400ms
1001: 480ms
1010: 560ms
1011: 640ms
1100: 800ms
1101: 960ms
1110: 1120ms
1111: 1280ms
ZERO_TIMEO
UT
7:4
0000
R/W
This register controls the AGC hold time.
3:0 HOLD_TIME
0000
R/W
0000: 0 (no hold time)
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AS3418
Register Description
Addr: 0x17
AGC_HOLD
Bit
Bit Name
Default
Access Bit Description
0001: 20ms
0010: 40ms
0011: 80ms
0100: 120ms
0101: 160ms
0110: 240ms
0111: 320ms
1000: 400ms
1001: 480ms
1010: 560ms
1011: 640ms
1100: 800ms
1101: 960ms
1110: 1120ms
1111: 1280ms
Figure 91:
AGC_START_TIME Register Description
Addr: 0x18
AGC_START_TIME
Bit
Bit Name
Default
Access Bit Description
This register controls the AGC gain ramp up step
time only during startup of the device.
000: 1ms/step
001: 2ms/step
010: 4ms/step
START_RAM
P_TIME<2:0>
2:0
000
R/W
011: 8ms/step
100: 16ms/step
101: 32ms/step
110: 64ms/step
111: 128ms/step
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AS3418
Register Description
7.2.6
Operation Mode Control Register
Figure 92:
MODE_SWITCH_CONTROL Register Description
Addr: 0x1A
MODE_SWITCH_CONTROL
Bit
Bit Name
Default
Access Bit Description
This register controls the shutdown delay function of
AS3418.
00: 10ms(default after reset)
01: 80ms
SHUTDOWN_
DELAY
6:5
00
R/W
10: 200ms
11: 400ms
Defines the time switching from ANC to PBO and
PBO to MONITOR operation mode. During this mode
switching delay the headphone amplifier multiplexer
is not connected to any source.
MODE_SWIT
CH_DELAY
3:2
11
R/W
00: 5ms
01: 100ms
10: 200ms
11: 400ms
This bit is independent of AGC_EN bit. The gain after
a gain register write is not immediately set but is
stepped up from old to new value if it is lower than
the old gain setting. Gain change will follow
AGC_RELEASE_TIME register setting.
GAIN_JUMP_
UP_EN
1
0
R/W
0: Gain Jump up disabled
1: The gain is immediately set after a gain register
write if it is higher than the old gain setting
This bit is independent of AGC_EN bit. The gain after
a gain register write is not immediately set but is
stepped down from old to new value if it’s lower than
the old gain setting. Gain change will follow
AGC_ATTACK_TIME register setting.
GAIN_JUMP_
DOWN_EN
0
0
R/W
0: Gain Jump down disabled
1: Gain jump down enabled
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AS3418
Register Description
7.2.7
EEPROM Control Registers
Figure 93:
EEPROM_CONTROL Register Description
Addr: 0x34
EEPROM_CONTROL
Bit
Bit Name
Default
Access Bit Description
The register bit supports an EEPROM upload test
function which simulates an EEPROM write without
executing the actual write in order to check if the
supply voltage is high enough for proper EEPROM
programming. Once the bit is set, the test is started
automatically and cleared after the test in finished.
The result, if the test was positive, can be read out in
register EE_WR_TEST_OK.
EEPROM_UP
LOAD_TEST
2
0
R/W
0: EEPROM upload test disabled
1: EEPROM upload test started
This register triggers the EEPROM upload function
which copies all register content of AS3418 to the
AS3418 to store it permanently to the device. Once
the upload is completed the bit is cleared
automatically. The success of the EEPROM upload
can be read out in register EE_READY.
EEPROM_UP
LOAD
1
0
R/W
0: EEPROM upload function disabled
1: EEPROM upload function started
This register triggers the EEPROM download
function which copies all EEPROM content to the
AS3418 configuration regsiters. Once the download
is completed the bit is cleared automatically. The
success of the EEPROM download can be read out
in register EE_READY.
EEPROM_DO
WNLOAD
0
0
R/W
0: EEPROM upload function disabled
1: EEPROM upload function started
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AS3418
Application Information
8 Application Information
The following chapters provide application specific information like schematic examples and a
summary of external components.
8.1
Schematic
Figure 94 shows an example of a Feed Forward ANC headset in Push Button operation mode.
Figure 94:
Push Button Operation Mode – Application Example
Left
ANC
Filter
MICS
R1
2k2
C1
C2
2.2µF
MIC1
VNEG
VNEG
C3
1uF
10µF
Left ANC MIC
C4
10uF
R2
2k2
GND
C6
VBAT
AGND
GND
AGND
AGND
U1
C5
E3
D1
B6
D4
D6
B5
B1
A3
B4
C4
A6
D2
D5
B2
E5
E4
2.2µF
4.7µF
MICL
CPN
CPP
VBAT
HPL
BPL
U2
C7
C8
4.7µF
4.7µF
L
3
LINL
GND
Speaker Left
AS3418
TRSDA
TRSCL
LINR
BPR
WL-CSP
AGND
HPR
R
2
1
R3
150
R4
150
GND
MSUP
MICS
Music Line Input
AGND
MICR
C9
Speaker Right
MICS
4.7µF
VBAT
AGND
AGND
AGND
R5
10k
C11
10uF
AGND
GND
C12
4.7µF
MICS
Right
ANC
R6
2k2
Filter
MIC2
AGND
C13
1uF
VBAT
Right ANC MIC
R7
2k2
S1
Push Button
AGND
AGND
On / Off / Monitor
Figure 95 shows an application example of a Feed Forward ANC headset in Slider operation mode.
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AS3418
Application Information
Figure 95:
Slider Operation Mode – Application Example
Left
ANC
Filter
MICS
R1
2k2
C1
C2
MIC1
VNEG
VNEG
C3
1uF
10µF
2.2µF
Left ANC MIC
C4
10uF
R2
2k2
GND
C6
VBAT
AGND
GND
AGND
AGND
U1
C5
E3
D1
B6
D4
D6
B5
B1
A3
B4
C4
A6
D2
D5
B2
E5
E4
2.2µF
4.7µF
MICL
CPN
CPP
VBAT
HPL
BPL
U2
C7
C8
4.7µF
4.7µF
L
3
LINL
GND
Speaker Left
AS3418
TRSDA
TRSCL
LINR
BPR
WL-CSP
AGND
HPR
R
2
1
R3
150
R4
150
GND
MSUP
MICS
Music Line Input
AGND
MICR
C9
Speaker Right
MICS
4.7µF
VBAT
AGND
AGND
AGND
R5
10k
C11
10uF
AGND
GND
C12
4.7µF
MICS
Right
ANC
Filter
R6
2k2
MIC2
AGND
C13
1uF
Right ANC MIC
R7
VBAT
2k2
R8
22k
R9
AGND
AGND
S2
S3
GND
GND
ON OFF
Figure 96 shows an application example of a Feed Forward ANC headset in Full Slider operation
mode.
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AS3418
Application Information
Figure 96:
Full Slider Operation Mode – Application Example
Left
ANC
Filter
MICS
R1
2k2
C1
C2
MIC1
VNEG
VNEG
C3
1uF
10µF
2.2µF
Left ANC MIC
C4
10uF
R2
2k2
GND
C6
VBAT
AGND
GND
AGND
AGND
U1
C5
E3
D1
B6
D4
D6
B5
B1
A3
B4
C4
A6
D2
D5
B2
E5
E4
2.2µF
4.7µF
MICL
CPN
CPP
VBAT
HPL
BPL
U2
C7
C8
4.7µF
4.7µF
L
3
LINL
GND
Speaker Left
AS3418
TRSDA
TRSCL
LINR
BPR
WL-CSP
AGND
HPR
R
2
1
R3
150
R4
150
GND
MSUP
MICS
Music Line Input
AGND
MICR
C9
Speaker Right
MICS
4.7µF
VBAT
AGND
AGND
AGND
R5
10k
C11
10uF
AGND
GND
C12
4.7µF
MICS
Right
ANC
Filter
R6
2k2
MIC2
AGND
C13
1uF
Right ANC MIC
VBAT
R7
R8
22k
2k2
R9
22k
R10
1M
AGND
AGND
GND
GND
OFF ON MON
8.2
External Components
This chapter provides detailed information about recommended external components.
Figure 97:
Useful Caption
Min.
Rated
Voltage
Min. Nominal
Capacitance /
Resistance
Temp.
Characteristic
Max.
Tolerance
Recommended typ.
Component Value
Symbol
Parameter
Capacitors
CVBAT
Input Capacitor
Y5R; X5R
Y5R; X5R
4V
4V
±20%
±20%
1.6µF
4.7µF
2.2µF
VNEG charge pump
flying capacitor
CFLY
0.97µF
CACR, CACL
CVNEG
AC coupling capacitor
Output Capacitor
Y5R; X5R
Y5R; X5R
4V
4V
±10%
±20%
5.6µF
3.4µF
10µF
10µF
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AS3418
Application Information
Min.
Rated
Voltage
Min. Nominal
Capacitance /
Resistance
Temp.
Characteristic
Max.
Tolerance
Recommended typ.
Component Value
Symbol
Parameter
Output Capacitor
microphone supply
CMICS
Y5R; X5R
4V
±20%
±20%
0.94µF
0.94µF
4.7µF
4.7µF
Output Capacitor
microphone charge
pump
CMSUP
Y5R; X5R
AC coupling capacitor;
CMICL, CMICR value depends on
ANC filter design
Y5R; X5R
Y5R; X5R
±10%
±10%
-
-
-
-
ANC filter related
CFILTER
capacitors
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AS3418
Package Drawings & Markings
9 Package Drawings & Markings
Figure 98:
WL-CSP Package Outline Drawing
0 4 c c c
0 8
0 5 4
5 1 ± 0 0 4
5 1 ± 0 0 4
5 1 ± 0 0 4
0 5 4
5 1 ± 0 0 4
0 0 6 1
0 0 5 2
Green
RoHS
(1)
(2)
(3)
(4)
All dimensions are in µm. Angles in degrees.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
This package contains no lead (Pb).
This drawing is subject to change without notice.
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AS3418
Package Drawings & Markings
Figure 99:
Package Marking/Code
AS3418
XXXXX
XXXXX Encoded Tracecode
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AS3418
Revision Information
10 Revision Information
Document Status
Product Status
Definition
Product Preview
Pre-Development Information in this datasheet is based on product ideas in the planning phase
of development. All specifications are design goals without any warranty and
are subject to change without notice
Preliminary Datasheet
Datasheet
Pre-Production
Information in this datasheet is based on products in the design, validation or
qualification phase of development. The performance and parameters shown
in this document are preliminary without any warranty and are subject to
change without notice
Production
Information in this datasheet is based on products in ramp-up to full production
or full production which conform to specifications in accordance with the terms
of ams AG standard warranty as given in the General Terms of Trade
Datasheet
(discontinued)
Discontinued
Information in this datasheet is based on products which conform to
specifications in accordance with the terms of ams AG standard warranty as
given in the General Terms of Trade, but these products have been
superseded and should not be used for new designs
Changes from previous version to current revision v4-00
Page
Figure 94 update of ball number of pin QOP1L
Figure 95 update of ball number of pin QOP1L
Figure 96 update of ball number of pin QOP1L
70
71
72
●
●
Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
Correction of typographical errors is not explicitly mentioned.
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Legal Information
11 Legal Information
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved.
The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the
copyright owner.
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams
AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this
product into a system, it is necessary to check with ams AG for current information. This product is intended for use in
commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high
reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended
without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or
implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are
disclaimed.
ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability
to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
RoHS Compliant & ams Green Statement
RoHS Compliant: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our
semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per
amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where
designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br/Cl): ams Green defines that in addition to RoHS compliance, our products are free
of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material).
Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that
it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or
warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG
has taken and continues to take reasonable steps to provide representative and accurate information but may not have
conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers
consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
Headquarters
Please visit our website at www.ams.com
ams AG
Buy our products or get free samples online at www.ams.com/Products
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Provide feedback about this document at www.ams.com/Document-Feedback
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Tel: +43 (0) 3136 500 0
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