AS3607-BQFP-FF [AMSCO]
System PMU with HV Back Light Driver; PMU系统与高压背光驱动器型号: | AS3607-BQFP-FF |
厂家: | AMS(艾迈斯) |
描述: | System PMU with HV Back Light Driver |
文件: | 总71页 (文件大小:5062K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ams AG
The technical content of this austriamicrosystems datasheet is still valid.
Contact information:
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8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
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Data Sheet
AS3606 AS3607
System PMU with HV Back Light Driver
HV Backlight Driver
1 General Description
The AS3606/07 is an ultra compact System PMU with integrated
battery charger and HV back light driver.
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Step up for 30V backlight with internal transistor
Voltage control mode and over-voltage protection
2 programmable current sink (max. 38mA)
Max. 20mA@50V (with ext. transistor) or 500mA@5V
Possible external PWM dimming input
The device offers advanced power management functions. All
necessary ICs and peripherals in a battery powered mobile device
are supplied by the AS3606/07. It features 3 DCDC converters as
well as 5 low noise LDOs. The different regulated supply voltages
are programmable via the serial control interface.
Battery Charger
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Prog. trickle charging (25-265mA)
The step-up converter for the backlight can operate up to 30V. Both
constant voltage (OLED supply) as well as constant current (white
LED backlight) operations with 2 current sinks are possible. An
internal voltage protection is limiting the output voltage in the case of
external component failures.
Prog. constant current charging (94-1060m
Prog. constant voltage charging (3.9V-4.2V)
Charger time-out and temperatusupeision
Selectae current limitation for USB ode
Inegrated battery switch & ideal dode
AS3606/07 also contains a Li-Ion battery charger with constant
current and constant voltage. The maximum charging current is 1A.
An integrated battery switch and an optional external switch are
separating the battery during charging or whenever an external
power supply is present. With this switch it is also possible to operate
with no or deeply discharged batteries. A programmable current limit
can be used to control the maximum current used from a US
supply.
External battery sh control output
General
Battery aemperature Supervisor
The single supply voltage may vary from 2.7V to 5.5V.
2 or General Purpose IOs
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10bit eneral purpose ADC input
PWM dimming input or wake-up input
2 Key Features
Power Management
Voltage Generation
Status output for: charger, low battery, power good and power-
up key
OTP Programmable BOOT Sequence
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Programmable regulator default voltages
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3 DCDC step down regulators
Programmable start-up sequence
- DVM (0.61V-3.3V, 700mA)
- 50µA quiescent current
Applicable for LDO 1-4 and DCDC 1-3
Control Interface
- Selectable switching frequency (2 r 1MHz)
- 1.4A with combined DCDC 2 &
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I2C control lines, including watchdog
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1 LDO low noise 2.7V (2.33.5V, 100mA
3 or 4 LDOs low noise
Power-Up input
Interrupt output
Bidirectional reset, with selectable delay
Low power standby mode, 160µA with LDO5 on
- 1.2-3.5V; 150/25mA
- 30µA quiecent current (low power mode)
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Power supplsupervision (LDO5)
4sec d 8sec emergency shut-down
Hibernation function
Power-On Reset Circuit
Packaging
QFN32 5x5mm or QFN36 6x6mm, 0.5mm pitch
3 Application
The devices are ideal for Portable Media Players and Portable
Navigation Devices, e-Books, Tablet PCs, etc
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AS3606 AS3607 2v2
Data Sheet - Application
Figure 1. AS3606 Block Diagram
Figure 2. AS3607 Block Diagram
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AS3606 AS3607 2v2
Data Sheet - Contents
Contents
1 General Description ..................................................................................................................................................................
2 Key Features.............................................................................................................................................................................
3 Application ................................................................................................................................................................................
4 Pin Assignments .......................................................................................................................................................................
4.1 Pin Descriptions....................................................................................................................................................................................
5 Absolute Maximum Ratings ......................................................................................................................................................
6 Electrical Characteristics...........................................................................................................................................................
1
1
1
5
6
8
9
7 Typical Operating Characteristics ...........................................................................................................................................
8 Detailed Description - Power Management Functions..........................................................................................................
8.1 Low Drop Out Regulators............................................................................................................................................................... 12
8.1.1 LDO5 ...................................................................................................................................................................................... 12
8.1.2 LDO 1, LDO2, LDO3 & LDO4................................................................................................................................................ 13
8.1.3 Parameter.............................................................................................................................................................................. 13
8.2 DCDC Step-Down Converter....................................................................................................................................................... 15
8.2.1 Functional Description ....................................................................................................................................................... 16
8.2.2 Parameter.............................................................................................................................................................................. 17
8.3 30V Step-Up DCDC Converter........................................................................................................................................ 19
8.3.1 Voltage Feedback and OV Protection ................................................................................................................................ 19
8.3.2 Voltage Feedback................................................................................................................................................................. 19
8.3.3 DLS & Dimming ........................................................................................................................................................... 20
8.3.4 Current Sinks................................................................................................................................................................. 20
8.3.5 Parameter............................................................................................................................................................................ 20
8.4 Charger......................................................................................................................................................................................... 22
8.4.1 Soft Charge/Trickle Charge ............................................................................................................................................... 23
8.4.2 End of Charge Detection ........................................................................................................................................ 23
8.4.3 VSUPSW and Temperature Supervision............................................................................................................................. 23
8.4.4 Battery Temperature Supervision......................................................................................................................................... 23
8.4.5 No Battery Detection................................................................................................................................................................ 23
8.4.6 Charger Modes ....................................................................................................................................................................... 24
8.4.7 Parameter .......................................................................................................................................................................... 24
9 Detailed Description - SYSTEM Functions ............................................................................................................................ 26
9.1 SYSTEM ....................................................................................................................................................................................... 26
9.1.1 Power Up/Down Condions ....................................................................................................................................................... 26
9.1.2 Start-up Sequence ................................................................................................................................................................... 26
9.2 Hibernation ....................................................................................................................................................................................... 27
9.3 Supervisor ...................................................................................................................................................................................... 27
9.3.1 VSUP Supervision ..................................................................................................................................................................... 27
9.3.2 DD7 Supervision ................................................................................................................................................................... 27
.3 Junction Temperature Supervision ............................................................................................................................................ 27
93.4 Power Rail Monitoring ................................................................................................................................................................ 27
94 Interrupt Generation ........................................................................................................................................................................... 28
9.4.1 IRQ Source Interpretation .......................................................................................................................................................... 28
9.4.2 Interrupt Sources ....................................................................................................................................................................... 28
9.5 10-Bit ADC ......................................................................................................................................................................................... 29
9.5.1 Input Sources ............................................................................................................................................................................. 29
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AS3606 AS3607 2v2
Data Sheet - Contents
9.5.2 Parameter .................................................................................................................................................................................. 29
9.6 GPIO Pins .......................................................................................................................................................................................... 30
9.7 2-Wire-Serial Control Interface ........................................................................................................................................................... 31
9.7.1 Protocol ...................................................................................................................................................................................... 31
9.7.2 Parameter .................................................................................................................................................................................. 34
10 Register Definition ................................................................................................................................................................ 35
11 Application Information ......................................................................................................................................................... 62
11.1 Pad Cells .......................................................................................................................................................................................... 62
11.2 Application Schematics .................................................................................................................................................................... 63
12 Package Drawings and Markings .........................................................................................................................................
13 Ordering Information ..........................................................................................................................................................
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AS3606 AS3607 2v2
Data Sheet - Pin Assignments
4 Pin Assignments
Figure 3. Pin Assignments (Top View)
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AS3606 AS3607 2v2
Data Sheet - Pin Assignments
4.1 Pin Descriptions
Note: Pin description may change in preliminary data sheets.
Table 1. Pin Description for AS3606/07
Pin Number
Pin Name
Type
Description
if not used
AS3606 AS3607
Battery Switch Terminal to be connected to the Li-Ion battery
Battery Switch Terminal to be connected to system supplies VSUPx
Charger or USB Bus Power Input
Li-Ion Charger Battery Temp. Sensor Input
External Battery Switch Gate Driver Output
LDO5 Output default 2.7V
VBATSW
VSUPSW
VUSB
-
1
SUP IO
SUP IO
SUP IN
ANA IO
ANA OUT
SUP IO
ANA OUT
SUP IN
ANA OUT
ANA OUT
ANA OUT
SUP IN
SUP IN
DIG OUT
ANA IN
ANA IO
ANA IO
DIG
ANA IN
ANA IO
ANA IO
ANA IO
ANA IO
DIG IN
open
always needed
open
1
2
2
3
BATTEMP
EXTBATSW
VDD27
PVDD4
VSUP5
PVDD3
PVDD2
PVDD1
VSUP4
VSUP1
LXC1
4
4
open
3
5
ope
5
6
always neded
open
LDO4 Output
-
7
LDO3/4 & LDO5 Pos. Supply Terminal, connect to VSUPSW
LDO3 Output
6
8
always needed
open
7
9
LDO2 Output
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
7
28
29
30
31
32
33
open
LDO1 Output
9
open
LDO1/2 Pos. Superminal
CVDD1 Step Down Pos. Supply Terminl
CVDDStep Down Switch Output to Co
CVD1 and Feedback Pin
10
11
12
13
14
15
16
17
-
always needed
always needed
open
CVDD1
CURR2
CURR1
LXSU
open
oad Current Sink2 Termina
Load Current Sink1 Termil
DCDC Step-Up Switch utput to Coil
DCDC Step--Back
open
open
open
FBSU
open
GenerPurpose IO 4
GPIO4
GPIO2
GPIO1
GPIO3
CSCL
open
General Purpose IO 2
18
19
-
open
eneral Purpose IO 1
open
General Purpose IO 3
open
2-wire SERIF Clock Input
20
21
22
23
25
2
27
28
29
open
2-wire SERIF Data I/O
CSDA
IG IO
open
Power Up Input
PWRUP
XIRQ
DIG IN
open
Interrupt Request Output
DIG OUT
DIG IO
open
Reset Output
XRES
open
Digital Periphery Pos. Supply Terminal
CVDD3 Step Down Pos. Supply Terminal
CVDD3 Step Down Switch Output to Coil
CVDD3 and Feedback Pin
DVDD
SUP IN
SUP IN
DIG OUT
ANA IN
ANA IN
always needed
VSUPx
open
VSUP3
LXC
CVDD3
CVDD2
open
CVDD2 and Feedback Pin
open
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AS3606 AS3607 2v2
Data Sheet - Pin Assignments
Table 1. Pin Description for AS3606/07
Pin Number
Pin Name
Type
Description
if not used
AS3606 AS3607
CVDD2 Step Down Switch Output to Coil
LXC2
VSUP2
VBATSW
VSS
30
31
32
33
34
35
36
37
DIG OUT
SUP IN
SUP IO
SUP IO
open
CVDD2 Step Down Pos. Supply Terminal
always needed
open
Battery Switch Terminal to be connected to the Li-Ion battery
Exposed Pad: Neg. Supply Terminal for all blocks
always needed
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AS3606 AS3607 2v2
Data Sheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 9 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. The device should be operated under recommended operating
conditions.
Table 2. Absolute Maximum Ratings
Parameter
Min
Max
Units
Comments
Applicable for pins VBATSW, VSUPSW, VSUP1/
2/3/4/5, PWRUP, GPIO1/2/3/4, VBUS
5V pins
-0.5
7.0
V
3V pins
-0.5
-0.5
5.0
32
V
V
Applicable for pins DVDD
30V pins
Applicable for pin LXSU, CURR1
7.0
VSUPx+0.5
5V pins with protection to VSUPx
3V pins with protection to VDD27
3V pins with protection to DVDD
3V pins with protection to VSUPx
-0.5
-0.5
-0.5
V
V
V
Applicable for pins EXTBATSW, FBS
Applicable for pinBATEMP
5.0
VDD27
5.0
DVDD+0.5
Applicable for pins RQ, XRES, CSCL, CSDA
5.0
VS0.5
Applicablfr ps PVDD1/2/3/4, VDD27,
CVDD1/2/3, LXC1,/2/3
-0.5
V
Input Current (latch-up immunity)
-100
1
mA
Norm: JEDEC 78
Continuous Power Dissipation (TA = +85ºC)
1
Continuous power dissipation
1
PT for QFN32/36 package (RTH ~ 30K/W)
Electrostatic Discharge
Electrostatic Discharge HBM
Temperature Ranges and Storage Condio
Junction Temperature
±1.5
kV
Norm: JEDEC JESD22-A114C
+125
85
ºC
ºC
%
Storage Temperature Range
Humidity non-condensing
-55
5
Temperature (soldering)
Norm IPC/JEDEC J-STD-0202
The lead finish for Pb-free leaded packages is
matte tin (100% Sn)
Package Body Temperature
260
ºC
Moisture Sensitive Level
3
Represents a max. floor live time of 168h
1. Depending on actual PCB lyout ad PCB used
2. The reflow peak solderitemerature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Classification for Nohermec Solid State Surface Mount Devices”
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AS3606 AS3607 2v2
Data Sheet - Electrical Characteristics
6 Electrical Characteristics
VSUPx=+2.7V...+5.5V, TA =-40ºC...+85ºC. Typical values are at VSUPx=+3.6V, TA=+25ºC, unless otherwise specified.
Table 3. Electrical Characteristics
Symbol
Parameter
Condition
Min
0
Typ
3.6
3.6
Max
5.5
Unit
V
operation, VBUS > 2.7V
operation from battery
Battery Supply Voltage
VBATSW
2.7
5.5
V
Supply Voltage
VSUPSW, VSUP1/2/3/4/5
VSUPx
VBUS
2.7
3.6
5.5
V
operating, VSUP5 > 2.7V
charging
0
5.0
5.0
5.5
5.5
3.6
3.5
0
V
V
USB VBUS Voltage
4.5
1.8
2.6
Digital Periphery Supply Voltage
Analog Supply Voltage
DVDD
V
VDD27
2.7
V
VDELTA
TAMB
ISD
+
Difference of Positive Supplies
Operating Temperature Range
Shut-down current
VDD27-VSUPx
V
-40
+85
ºC
nA
@ VBATSW 4.2V
600
160
All regulators of
refereDO5 on
Iq
Quiescent current
µA
IO Pins
3.6V or
DVDD
+0.5
3V digital input pins
XRES, CSCL, CSDA
VID3V
0
V
3.6V or
VDD27
+0.5
3V input pin
BATTEMP
VIA3V
VI5V
0
0
0
0
V
V
V
V
5V input pins
GPIO1/2/3/4
5.5V
5.5V or
VSUP5
+0.5
5V input pin
FBSU
VI5V
20V analiog input pins
LXSU, CURR1/2
VI30V
30
POR & Watchdog
Power-on Reset activation level when
VDD27 decreases
VPOR_ON
Power-on Reset Activaon Leel
2.15
V
Power-on Reset release when VDD27
increases
VPOR_OFF
Power-on ReseReleae Level
Power-on Hysteresis
2.0
V
VPOR_HY
PWRUP
100
mV
tON_DELAY
VPWRU
Delay Time of pin PWRUP
Input Level LOW
Minimum key press time
Pin PWRUP, VSUP5>3V
Pin PWRUP, VSUP5>3V
Pin PWRUP, VSUP5<=3V
Pin PWRUP; @2.7V
60
ms
V
0.5
30
VSUP5/3
V
WRUP_H
IPWRUP
Input Level HIGH
1
V
Internal Pull-down Current Source
10
20
µA
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AS3606 AS3607 2v2
Data Sheet - Electrical Characteristics
Table 3. Electrical Characteristics (Continued)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Digital Inputs/Outputs
Digital Output Driver Capability
(drive LOW)
Pins XRES, XIRQ, GPIOx @ 6mA, open
drain mode
20%
VDO_DL
IPU
V
DVDD
Pins XIRQ @ 0V
Pins CSDA, CSCL @ 0V
Pins GPIOx @ 2.7V
13
100
13
µA
µA
µA
Internal Pull-up Current Source
Internal Pull-down Current Source
Digital Input Level LOW
IPD
8
20
30%
DVDD
VDI_L
Pin GPIOx
Pin GPIOx
V
V
70%
DVDD
VDI_H
Digital Input Level HIGH
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AS3606 AS3607 2v2
Data Sheet - Typical Operating Characteristics
7 Typical Operating Characteristics
VSUPx = +3.6V, TA = +25ºC, unless otherwise specified.
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AS3606 AS3607 2v2
Data Sheet - Detailed Description - Power Management Functions
8 Detailed Description - Power Management Functions
8.1 Low Drop Out Regulators
These LDOs are designed to supply sensitive analog circuits, audio devices, AD and DA converters, micro-controller and other peripheral
devices. The design is optimized to deliver the best compromise between quiescent current and regulator performance for battery powered
devices.
Stability is guaranteed with ceramic output capacitors of 1µF ±20% (X5R) or 2.2µF +100/-50% (Z5U). The low ESR of these caps ensures low
output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the power transistor has to
operate in linear mode. Power supply rejection is high enough to suppress high ripple on the battery at the output. The low noise performance
allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of the power device enables the
device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance.
Figure 4. LDO Block Diagram
8.1.1 LDO5
This LDO generates the digital supplvoltae used for the PMU itself.
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Input Voltage is VSUP5
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Output Voltage is VDD27 (p. 2.7V), this LDO always starts at the beginning of the start-up sequence as it is needed for all further
operation. The efault vltage cannot be changed in the boot ROM.
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Driver strength: 100A, can be programmed to 200mA
It is set to a defalt outut voltage of 2.7V, 100mAmax. It supplies the analog and digital part of the PMU. Additional external loads are possible
but must nceed the supply ratings in total together with the operating internal blocks. Further, the external load must not induce noise to the
VDD27.
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AS3606 AS3607 2v2
Data Sheet - Detailed Description - Power Management Functions
8.1.2 LDO 1, LDO2, LDO3 & LDO4
These LDOs can be used to generate the periphery voltage for the digital processor or other external components (e.g. ext. DAC, USB-PHY, SD-
Cards, NAND-Flashes, FM-Tuner …). LDO4 is only available on AS3607.
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Input Voltage VSUP5 for LDO3 and LDO4, and VSUP4 for LDO2 and LDO1
Output Voltage is PVDD1, PVDD2, PVDD3 & PVDD4 (1.2V to 3.5V)
Default value at start-up is defined by the boot ROM, when the boot ROM is not programmed the LDOs will not start-up
Driver strength: 150mA, can be programmed to 250mA
8.1.3 Parameter
VSUPx=3.6V, TA= 25ºC, unless otherwise specified.
Table 4. LDO Parameter
Symbol
Parameter
Condition
Min
Typ
Max
Unit
RON
On resistance
1
Ω
f=1kHz
70
4
Power supply rejection ratio
Shut down current
PSRR
IOFF
dB
f=100kHz
100
50
nA
μA
withouoad
IVDD
Supply current
low powbled, without load
10Hf < 100kHz
32
μA
Output noise
Startup time
Noise
tstart
50
µVrms
µs
200
Vout_tol
Output voltage tolerance
minimum ±50mV
Stati
-2.5%
2.5%
mV
<1
<10
<1
VLineReg
VLoadReg
ILIMIT
Line regulation
Load regulation
Current limitation
mV
mV
mA
Transient; Slope: tr=0µs
atic
TrSlope: tr=10µs
default
<10
190
350
has o be enabled via register
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AS3606 AS3607 2v2
Data Sheet - Detailed Description - Power Management Functions
Figure 5. LDO Characteristics
Output Noise
Load Regulation
transient load: 1mA – 100mAslope: 1µs
Output load50m
oad Regulation
Load Regulation
output load: 1mA
output load: 150mA
transient input voltagripple: 500mV
transient input voltage ripple: 500mV
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AS3606 AS3607 2v2
Data Sheet - Detailed Description - Power Management Functions
8.2 DCDC Step-Down Converter
These converters are meant to convert the battery voltage down to voltages which fit to the core and peripheral supply voltage requirements for
microprocessors.
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Input Voltage VSUP1/2/3 (usually connected to VSUPSW)
Output Voltage CVDD1 & CVDD2 & CVDD3
Output voltage levels can be programmed independently form 0.61V to 3.35V
The default value at start-up is defined by the boot ROM
DVM for all three outputs with selectable timings
Driver strength 700mA, DCDC2 & 3 can be combined together to double the output current
Under- and over-voltage detection
High efficiency current force mode
1MHz or 2MHz switching frequency
Fast regulation mode
Figure 6. DCDC Step-Down Block Diagram
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AS3606 AS3607 2v2
Data Sheet - Detailed Description - Power Management Functions
8.2.1 Functional Description
The step-down converter is a high efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches
efficiency up to 97% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The
unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to an output current
of 700mA, with an output capacitor of only 10µF. The implemented current limitation protects the DCDC and the coil during overload condition.
To achieve optimized performance in different applications, adjustable settings allow to compromise between high efficiency and low input,
output ripple:
Low Ripple, Low Noise Operation (current force mode = OFF). In this mode there is no minimum coil current necessary before
switching off the PMOS. As result, the ON time of the PMOS will be reduced down to tmin_on at no or light load conditions, even if the coil
current is very small or the coil current is inverted. This results in a very low ripple and noise, but decreased efficiency, at light loads, especially at
low input to output voltage differences. In the case of an inverted coil current the regulator will not operate in pulse skip mode.
Figure 7. DCDC Buck with Disabled Current Force / Pulse Skip Mode
1: LXC1 voage
2Coil current (1mV=1mA)
3: Ouut voltage
High Efficiency Operation (current force mode = ON). In the, there is a minimum coil current necessary before switching off the
PMOS. As result, fewer pulses at low output loads are necesry, and therefore the efficiency at low output load is increased. On the other hand
the output voltage ripple increases, and the noisy pulse skip oeratin is on up to a higher output current.
Figure 8. DCDC Buck with Enabled Current Force / Pule Skip Mode
1: LXC1 voltage
2: Coil current (1mV=1mA)
3: Output voltage
It’s also possible to switch between these two modes dynamically during operation.
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AS3606 AS3607 2v2
Data Sheet - Detailed Description - Power Management Functions
DVM (Dynamic Voltage Management). To minimize the over-/undershoot during a change of the output voltage, the DVM can be enabled.
With DVM the output voltage will ramp up/down with a selectable slope after the new value was written to the registers. Without DVM the slew
rate of the output voltage is only determined by external components like the coil and load capacitor as well as the load current.
Fast Regulation Mode. This mode can be used to react faster on sudden load changes and thus minimize the over-/undershoot of the output
voltage. FRM needs an 22uF output capacitor instead the 10uF one to guarantee the stability of the regulator.
Low Frequency Operation. Especially for very low load conditions, e.g. during a sleep mode of a processor, the switching frequency can be
reduced to achieve a higher efficiency.
100% PMOS ON Mode for Low Dropout Regulation. For low input to output voltage difference the DCDC converter can use 100% du
cycle for the PMOS transistor, which is than in LDO mode.
8.2.2 Parameter
VSUP=3.6, TA= 25ºC, unless otherwise specified.
Table 5. DCDC Parameter
Symbol
VIN
Parameter
Input voltage
Condition
Min
Ty
Max
Unit
VSUPx
2.7
5.5
V
0.6125
-3%
3.35
3%
V
mV
mA
mA
Ω
VOUT
VOUT_tol
Iload
Regulated output voltage
Output voltage tolerance
Maximum Load current
Current limit
minimum ±50mV
600
1000
0.5
0.5
1/2
0.6
10
700
ILIMIT
RPSW
RNSW
fSW
VSUPx=3.0V
VSUPx=3.0V
0.7
0.7
P-Switch ON resistance
N-Switch ON resistance
Switching frequency
Switching frequency
Output capacitor
Ω
depending on DCD_Cntr ttings
in shortcut cas
MHz
MHz
µF
µH
%
fSWsc
Cout
Ceramic, 10% tolerance
tolerance
2.2
97
Inductor
Lx
Iout0mA, Vout=3.0V
ηeff
Efficiency
Opeting current without load
Shutdown current
65
0.1
µA
IVDD
Current consumption
80
40
ns
ns
tMIN_ON
Minimum on time
Minimum off time
tMIN_OFF
Static
2
mV
Line regultion
Lad reulation
VLineReg
Transient; Slope: tr=10µs, 100mV step, 200mA
load
10
Static
5
mV
VLoadReg
Transient; Slope: tr=10µs,
100mA step
50
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Data Sheet - Detailed Description - Power Management Functions
Figure 9. DCDC Step-down Performance Characteristics
DCDC buck Efficiency @2MHz, 3.6V VSUPx
100,00
95,00
90,00
85,00
80,00
75,00
70,00
CVDD1 @ 1,2V Vout
CVDD1 @ 1,8V Vout
CVDD1 @ 3V Vout
65,00
60,00
1
10
100
1000
Output Current [mA]
Output voltage vs. Output Current
ine Regulation
1,225
1,215
1,205
1,195
1,185
1,175
1,215
,21
1,205
1,2
IOUT=0mA
IOUT=125mA
IOUT=250mA
VOUT=1.2V
VIN=3.6V
1,195
0
50
100
150
00
250
3
3,4
3,8
4,2
4,6
5
OUTPUT CURRENT [mA]
INPUT VOLTAGE [V]
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Data Sheet - Detailed Description - Power Management Functions
8.3 30V Step-Up DCDC Converter
The integrated Step-Up DC/DC Converter is a high efficiency current-mode PWM regulator, providing an output voltage up to 30V. A constant
switching-frequency results in a low noise on supply and output voltages.
It has two programmable high voltage current sinks (0 to 38.25mA) for driving e.g. white LEDs as back-light. It can drive also unbalanced strings
due to the internal automatic feedback selection.
A voltage feedback mode allows generating constant supply voltages for e.g. OLEDs. The output voltage is set by an external resistor divider
and an internal current sink.
An internal protection circuit will shut down the regulator if the voltage on FBSU exceeds the over voltage threshold. No more external protection
has to be used to avoid an exceeding of the operation conditions in a no load situation.
Figure 10. DCDC15 Block Diagram
8.3.1 Voltage Feedback
Setting bit SU_CURR_FB = 0 enaes voltage feedback at pin FBSU.
The output voltage is regulated ta constant value, given by (Bit SU_GAIN should be set to 1 in this configuration)
UStep up_out = (R1+R2)/R2 *1.25 + IFB * R1
If R2 is not used, he outpuvoltage is by (Bit SU_GAIN should be set to 0 in this configuration)
UStep up_out = 1.25 + IFB * R1
(EQ 1)
(EQ 2)
Where:
UStep up_out = Step Up DC/DC Converter output voltage
R1 = Feedback resistor R1
R2 = Feedback resistor R2
IFB = Tuning current at pin FBSU; 0 to 31µA
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Data Sheet - Detailed Description - Power Management Functions
Table 6. Voltage Feedback Example Values
UStep up_out
UStep up_out
IDCDC_FB
µA
0
R1 = 1MΩ, R2 not used
R1 = 500kΩ, R2 = 50kΩ
-
13.75
14.25
14.75
15.25
15.75
16.25
16.75
1.25
17.75
18.2
18.75
19.25
19.75
20.25
20.75
21.25
…
1
-
2
-
3
-
4
-
5
6.25
7.25
8.25
9.25
10.25
11.25
15
13
14.2
15.25
16.25
…
6
7
8
9
10
11
12
13
14
15
…
30
31
31.25
28.75
29.25
Note: The voltage on CURR1 and CURR2 must not exced 30V.
8.3.2 Over Voltage Protection (OVP)
Setting bit SU_CURR_FB = 1 enables feedback via the urrent sink pins. The voltage on the current sink pin is regulated to VCURR. The
selection of the current sink with the larger load s dautomatically. The pin FBSU acts as an overvoltage protection in this mode. Please be
sure to set the voltage to a higher level than needo drive the longer LED string. the calculation of the resistor can be done the same as
described in the chapter above.
8.3.3 DLS & Dimming
AS3606/07 feature external diming iputs via CURR1, CURR2, GPIO1 or GPIO2 by directly connecting a PWM output of e.g. the display
controller for DLS (dynamiluminnce scaling). Manual dimming can be done at any time by setting the sink current via I2C commands.
8.3.4 Current Sinks
The current sinkwork ndependent from each other and can also be used without the booster, or can act as a dimming input if they are not
needed as a sink.
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Data Sheet - Detailed Description - Power Management Functions
8.3.5 Parameter
VSUPx=3.6V, TA= 25ºC, unless otherwise specified.
Table 7. DCDC Parameter
Symbol
VSW
Parameter
Condition
Pin FBSU
Min
Typ
Max
Unit
V
High Voltage Pin
Quiescent Current
0
30
IVDD
Pulse Skipping mode
Pin CURR1 or CURR2
Pin FBSU
140
µA
V
0
0
30
5
VFB
Feedback Voltage, Transientt
V
Feedback Voltage, for voltage
regulation
VFBSU
VCURR
Pin FBSU
1.2
0.4
1.25
0.5
1.3
0.6
V
V
Feedback Voltage, for current sink
regulation
Pin CURR1 or CURR2
Additional Tuning Current at Pin
DCDC_FB and over voltage
protection
Adjustable by software using Register DCDC
control1
0
31
6
µA
%
1µA step size (0-31µA)
IDCDC_FB
V
PROTECT = 1.25V +
IDCDC_FB * R1
Accuracy of Feedback Current at
full scale
-6
RSW
ILOAD
FSW
Switch Resistance
Load Current
1
Ω
@ V output voltage
SREQU = 0
0
50
mA
Fixed Switching Frequency
1
MHz
Ceramic, ±20%. Usnominal 4.7µF caacitrs
to obtain at least 0.7µF under all conitions
voagdependence of capitors)
COUT
Output Capacitor
Inductor
0.7
7
4.7
µF
µH
Use nductors with small CARAIC 100pF)
for high efficincy
L
10
13
Minimum On-Time
tMIN_ON
MDC
Guaranteed pr design
Guaranteeper design
100
90
190
ns
%
Maximum Duty Cycle
84
Figure 11. 30V Step-Up Performance Characteristics
DCDC Boost 6 LEDs
90,00
850
00
75,00
70,00
65,00
60,00
55,00
1
10
100
Output Current [mA]
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Data Sheet - Detailed Description - Power Management Functions
8.4 Charger
This block can be used to charge a 4V Li-Ion accumulator. It supports constant current and constant voltage charging modes with adjustable
charging currents (94 to 1000mA) and maximum charging voltage (3.9 to 4.25V).
The charger consists basically of a pre-regulator, which limits the current from e.g. the USB input and provides a constant VSUP after reaching
EOC (end of charge) and the battery switch, which is controlling the current into the battery.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Input Voltage of the pre-regulator: VUSB
Output of the pre-regulator and input for the battery switch and system supply: VSUPSW
Output of the battery switch and battery terminal: VBATSW
CVM (constant voltage), CCM (constant current) and trickle charging
Adjustable EOC voltage and EOC current limit
Selectable input -, trickle- and charging-current limit
Auto-resume with selectable resume voltage level
Charger time-out supervision with selectable time-out setting
Battery temperature supervision supporting two levels (45 or 50ºC) and 100k or 10k NTC types
No battery detection
Status register and interrupt generation
Per default the USB current limit is set to 470mA and the charger is swtched off.
The current battery and charger input voltage can be measured with the ral purpose ADC.
Figure 12. Charger Block Diagram
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Data Sheet - Detailed Description - Power Management Functions
Figure 13. Charger States
8.4.1 Soft Charge/Trickle Charge
If the battery and therefore VBATSW is below 3the charger is working in fixed soft charge mode with a smaller trickle charging current of 24-
265mA. After reaching the 3V level the chargetches to the constancurremode with the programmed charging current.
8.4.2 End of Charge Detection
For the EOC level 4 presets can be selected. This makes it pssible o monitor the charging progress also during constant voltage mode. If the
EOC level is reached an interrupt can be generatedbut it is also possible to poll the charger status bits at any time.
8.4.3 VSUPSW and Temperature Superviion
The charger will automatically reduce the charging ent if VSUPSW drops below the selected level. It will automatically stop charging when
the chip temperature gets too to hot. The harger will return to normal operation as defined in the charger registers if VSUPSW and the chip
temperature return to their normal operatig rane.
8.4.4 Battery Temperature Supervision
This charger block also featurea supply for an external NTC resistor to measure the battery temperature while charging. If the temperature is
too high (voltage on ATTEP pin is below VBATTEMP_ON) the charger will stop operation. If needed an interrupt can be generated based on
this event. When the baery temperature drops the charger the voltage on BATTEMP pin will rise above VBATTEMP_OFF and the charger will
start charging agin. This iforming a temperature hysteresis of about 3 to 5°C to avoid an oscillation of the charger.
The levels for swihinoff the charger (45ºC or 55ºC) as well as the type of NTC (10k or 100k) can be selected via register settings. The battery
temperatupervision via the NTC can be switched off (NTC_ON = 0).
hsupply for the NTC will be only on when a charger is detected and NTC_ON bit is set.
8.4.5 No Battery Detection
If the charger state machine reaches EOC 2 times within a very short period it assumes that there is no battery connected to the VBATSW
terminal.
After this a sensing current of 1uA is applied to the BATTEMP pin to detect if a battery is reconnected.
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Data Sheet - Detailed Description - Power Management Functions
8.4.6 Charger Modes
Figure 14. Charger Modes
8.4.7 Parameter
VDD27=2.7, TA= 25ºC, unless otherwispecified.
Table 8. Charger Parameter
Symbol
Prameter
Condition
Min
Typ
Max
Unit
INOM
-8%
INOM
+8%
ICHG (0-7)
Charging Current
INOM
@ 470mA
mA
VNOM
-50mV
VNOM
+33mV
VCHG (0)
Charging Voltage
VNOM
end of charge is true
V
rising edge on VUSB start
rising edge on VUSB end
VUSB-VBATSW
0.8
V
V
ON_ABS
3.5V
Charger On Voltage Detection
VON_REL
170
50
240
mV
mV
VOFF_REL
VUSB-VBATSW
Battery Temp. high level
(45 or 55ºC)
VSUP >3V
NTCbeta=4200
610 or
400
VBATTEMP_ON
mV
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Data Sheet - Detailed Description - Power Management Functions
Table 8. Charger Parameter
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Battery Temp. low level
(42 or 50ºC)
VSUP >3V
NTCbeta=4200
700 or
500
VBATTEMP_OFF
mV
100k
10k
15
IBATTEMP
NTC Bias Current
µA
mA
150
8%
10%
15%
20%
INOM
ICHG_OFF
End Of Charge current level
VSUP >3V
IREV_OFF
Reverse current shut down
Battery Switch On-resistance
VSUPSW = 5V, VUSB open
<1
µA
RON_BATSW
0.15
Ω
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Data Sheet - Detailed Description - SYSTEM Functions
9 Detailed Description - SYSTEM Functions
9.1 SYSTEM
The system block handles the power up, power down and regulator voltage settings of the PMU.
9.1.1 Power Up/Down Conditions
The chip powers up when one of the following conditions is true:
Table 9. Power UP Conditions
#
1
2
Source
Description
ON_KEY High Level at PWRUP pin of >= 1/3 VBATSW
PWRUP PwUp
VBUS PwUp
USB Plug-In …. High level at VBUS pin of >= 4.5V and >2.7V on VSUP5
The chip automatically shuts off if one of the following conditions arises:
Table 10. Power DOWN Conditions
#
Source
Description
Power-Down by SERIF writing 0h to reister 20h
1
SERIF MAJOR PwDn
Power-Down if PWRUP pin is HIGH r 8sec.
This has to be enabled in register 21h, pr defult a reset cycle is iniaed. t can also be changed to 4s.
2
3
Emergency PwDn
write 3h to reg. 20h … enable atch-dog
Power-Down if no SERIF read ieen for 500ms.
SERIF Watch-Dog PwDn
Power-Down if junction temperature rises up to 140dgC.
This threshold can bloweed with bits <4:0> in reg 21.
This supervisor can be disabled with bit 2 in r0h.
4
Junction-Temp PwDn
Power-Down VDD7 LDO5 has 10% er-voltage for more than 680µs.
This supeisor cn get disabled with bt 6 in rg. 21h.
5
6
7
8
9
VDD27 LOW PwDn
CVDD1 LOW PwDn
CVDD2 LOW PwDn
CVDD3 LOW PwDn
VSUP LOW PwDn
Powerown if enabled with bit 7 ireg. 23h and
CVDDCDC has 10% undtage for more than 680µs.
Power-Down if enabled witn reg. 23h and
CVDD2 DCDC has 1% under-voltage for more than 680µs.
Power-Down if enablewth bit 3 in reg. 23h and
CVDD3 DCDhas 10% under-voltage for more than 680µs.
Power-oif VSUPx goes below the defined level in Reg22h (bits <3:1>)
This super has to be enabled with bit 4 in reg. 22h.
9.1.2 Start-up Sequence
The start-up sequence is defined ithe bot ROM and will be fixed during the production test.
The sequence and voltage of tregulators can be freely chosen for the start-up sequence with the following limitations:
ꢀ
ꢀ
ꢀ
VDD27 will alws tartp, after a ~5ms delay the sequencer will start-up the other chosen regulators with either 0, 1 or 4ms delay each.
A maximum of 6 regators (no matter of DCDC or LDO) or 5 regulators and a changed GPIO configuration can be chosen for the start-up.
On a 7th tim-slot VDD2 can be started-up, but has reduced setting on the output voltage
PWRGOill be activated ~3ms after the last regulator.
XRS will be released 10ms to 110ms (set in the boot ROM) after the last regulator started up.
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Data Sheet - Detailed Description - SYSTEM Functions
9.2 Hibernation
Hibernation allows shutting down a part or the complete system. Hibernation can be terminated by every possible interrupt of the PMU. The
interrupt has to be enabled before going to hibernation.
Table 11. Hibernation
State
Description
To enter hibernation mode the following settings have to be done:
- Enable just these IRQ sources which should lead to leave hibernation mode.
- Make sure that IRQ is inactive (IRQ flags get cleared by Reg 23h-26h readings.
- Set the GPIO to input
- Select the GPIO for hibernation control (GPIO_DIMM_HBN_SEL <1:0>)
- Enable hibernation via GPIO (GPIO_HBN_ON)
Enter via GPIO
- Define which regulators should be kept powered and enter hibernation by writing to Reg 1Ch_0x04 + Re
17h-4. This register MUST NOT be read back!!!
- Drive the selected GPIO to LOW.
Note that hibernation will shutdown regulators which are not in the keep list of the mentioned Re17h-4 writing and
are part of the power-up sequence.
To enter hibernation mode the following settings have to be done:
- Enable just these IRQ sources which shoullead to leave hibernation mode.
- Make sure that IRQ is inactive (IRQ flags t cleared y Reg 23h-26h readings.
- Set a delay for entering hibernation if needed BN_DELAY<1:0>)
- Define which regulators should be wered and enter hibrnation by writing to Reg 1Ch_0x04 + Reg
17h-4. This register MUST NOT be rback.!!!
Enter via SW
Note that hibernation will shutdown regulators which are not in the kelist of the mentioned Reg 17h-4 writing and
are part of the power-up sequence.
VDD27 chip supply is kept ON
All other regulators are swtcheOFF dependent ote KP-its
XRES goes active (cabe isabled in the boot ROM) ad PWRGOOD goes inactive
Hibernation
Leave
The chip will come out oHibernation with
- IRQ actvatir
- GPIO cont
Start-Up sequence is provided defined bboot ROM.
9.3 Supervisor
This supervisor function can be used for automatic detetion of VSUP brown out or junction over-temperature condition.
9.3.1 VSUP Supervision
The VSUP supervision has a selectable vel. If the shutdown is not enabled an interrupt can be generated.
9.3.2 VDD27 Supervision
If VDD27 reaches the “programed lvel of VDD27” -10% for typ. 3ms, the PMU shuts down automatically. If the shutdown is not enabled an
interrupt can be generated.
9.3.3 Junction Temerature Supervision
The temperature supersion level can also be set by 5 bits (120 to –15ºC). If the temperature reaches this level, an interrupt can be generated.
The over-temperatre shutdown level is always 20ºC higher. This shutdown can be disabled in Reg. 20h.
9.4 Power Rail Monitoring
The 3 CDC regulators have an extra monitor which observes the output voltage of the regulators. This power rail monitors are independent
from the 10bit ADC. To activate these please see related registers. For a shut down the voltage of the regulator has to be 10% or more below the
programmed value for more than 3ms.
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Data Sheet - Detailed Description - SYSTEM Functions
9.4 Interrupt Generation
All interrupt sources can get enabled or disabled by corresponding bits in the 4 IRQ-bytes. By default no interrupt source is enabled.
The XIRQ pin can be configured to operate in push/pull (2 different driver strengths), open-drain mode or to be tri-state. The signal polarity can
be defined as active-low or active-high. Default state is open-drain active-low.
9.4.1 IRQ Source Interpretation
There are 3 different modules to process interrupt sources:
LEVEL. The IRQ output is kept active as long as the interrupt source is present and this IRQ-Bit is enabled.
EDGE. The IRQ gets active with a high going edge of this source. The IRQ stays active until the corresponding IRQ-Register gets read.
STATUS CHANGE. The IRQ gets active when the source-state changes. The change bit and the status can be read to notice which interru
was the source. The IRQ stays active until the corresponding interrupt register gets read.De-bouncer
There is a de-bounce function implemented, a de-bounce time of 3ms is selected per default in the IRQ_ENRD_3 register (26h).
9.4.2 Interrupt Sources
These IRQ events will activate the XIRQ pin:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
10bit ADC end of conversion
Charger end of charge, connect/disconnect, no battery
Battery temperature high (at 45ºC or 50ºC with 100/10kΩ NTC)
Junction temperature high
Battery low (Brown-out voltage reached)
Power-up key (pin PWRUP) pressed
Current sink low voltage
Power rail monitor: over-voltage CVDD1, CVDD2, VDD3
Power rail monitor: under-voltage CVDD1, CVD2, CVDD3, VDD27
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Data Sheet - Detailed Description - SYSTEM Functions
9.5 10-Bit ADC
This general purpose ADC can be used for measuring several voltages and currents to perform functions like battery monitor, temperature
supervision, button press detection, etc.
9.5.1 Input Sources
Table 12. ADC10 Input Sources
#
0
1
2
3
4
5
6
7
8
9
A
B
Source
VSUP
Range
5.120V
5.120V
5.120V
5.120V
5.120V
5.120V
2.048V
5.120V
5.120V
5.120V
LSB
5mV
5mV
5mV
5mV
5mV
5mV
2mV
5mV
5mV
5mV
2mV
2mV
Description
check main system supply voltage
GPIO3
GPIO4
VBATSW
VUSB
check battery voltage of 4V Li-Ion accumulator
check USB/charger input voltage
Source defined by DC_TEST in regiser 18h
check battery charging temperure
BATTEMP
GPIO1
GPIO2
PWRUP
reserved
reserved
measuring basis-mitter oltage of temperature sense transistor;
T= (674 - ADC10<9:0>) / 2
C
D
VBE_1µA
VBE_2µA
1.024
1.024
1mV
mV
measuring sis-mitter voltage of temperature sense transistor;
Tj = (694 - ADC10<9:0>) / 2
E
F
1mV
1mV
reserved
reserved
9.5.2 Parameter
VDD27=2.7, TA= 25ºC, unless otherwise specified.
Table 13. ADC10 Parameter
Symbol
ADCFS
TCON
Parameter
Condition
Min
Typ
2.16
34
Max
Unit
V
ADC Full Scale Range
Conversion me
-
50
µs
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Data Sheet - Detailed Description - SYSTEM Functions
9.6 GPIO Pins
AS3607 features 4 GPIO pins, AS3606 has 2 GPIO pins.
If not re-configured in the start-up sequence GPIO1, GPIO3 and GPIO4 are input per default.GPIO2 is set to output and the pin is driven to low
right at the beginning of the startup sequence. GPIO3/4 have one state defined as input and three states as output. The following table shows
the different input/output options.
Table 14. GPIO Configuration
GPIO1
xCharging (1Hz pulses)
xVSUP_low
GPIO2
LOW
GPIO4/3
HiZ / HiZ (input)
00
01
10
11
xVSUP_low
HIGH
xVSUP_low / xCharging (1Hz pulses)
xPWRUP / PWRGOOD
xEOC / xCharger_active
xPWRUP
PWRGOOD
xCharging (1Hz pulses)
When configured as input the following functionality is available:
ꢀ
ꢀ
ꢀ
ꢀ
ADC input, to measure external voltage sources
Wake-up input to return from hibernation
Hibernation enable input (GPIO1/2/3 only)
PWM dimming input (GPIO1/2/3 only)
GPIO pins have a 200kOhm pull-down resistor activated when they aras an input. (HiZ-mode).
Table 15. GPIO Output Functions
Function
Descrptio
The output will bhih hen the charger is no activThe output toggles between high and low as
long as the charging is on going. If EOC, a eout or overtempertur event stops the charger the
output stos toging.
xCharging (1Hz pulses)
The oput wibe high when the chrger ino active or in EOC; it will be low if the charger is active.
xCharger_active
xEOC
The utput will be high when thcharger active; it will be low if the charger is has reached EOC.
Ttput will return baigh the charger enters resume state.
The output will get low if WRUP pin is high.
xPWRUP
The output will bhigh bout 3ms after the start-up seuence is finished. It will be low during the
sequence. Please be sure to configure the GPIO before the pull-up voltage, otherwise the output
will be higas long as the GPIOs are default inputs.
PWRGOOD
The ouut will get low if the VSUP undervoltage level is reached.
The ot will be high.
xVSUP_low
HIGH
The output will be low.
LOW
Please note that all GPIO pins re oen-drain outputs. They can only output a logic “high” if a pull-up and the corresponding pull-up voltage is
present.
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Data Sheet - Detailed Description - SYSTEM Functions
9.7 2-Wire-Serial Control Interface
There is an I2C slave block implemented to have access to 64 byte of setting information.
The I2C address is: Adr_Group8 - audio processors
ꢀ
ꢀ
8Ch_write
8Dh_read
9.7.1 Protocol
Table 16. 2-Wire Serial Symbol Definition
Symbol
Definition
Start condition after stop
Repeated start
RW
R
Note
S
Sr
1 bit
R
1 bit
DW
DR
Device address for write
Device address for read
Word address
R
1000 1100b (8Ch)
R
1000 110b (8Dh)
WA
R
bit
A
Acknowledge
W
R
1 bit
N
No Acknowledge
Register data/write
Register data/read
Stop condition
1 bit
reg_data
data (n)
P
R
8 bit
8 bit
W
R
1 bit
WA++
Increment word address internally
AS3606 AS3607 (=slave) receives data
AS3606 AS3607 (=sve) tansmits data
R
during acknowledge
Figure 15. Byte Write
S
A
WA
A
reg_data
A P
write register
WA++
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AS3606 AS3607 2v2
Data Sheet - Detailed Description - SYSTEM Functions
Figure 16. Page Write
S
DW
A
WA
A
reg_data 1
A
reg_data 2
A
...
reg_data n
A
P
write register
WA++
write register
WA++
write register
WA++
Byte Write and Page Write formats are used to write data to the slave.
The transmission begins with the START condition, which is generated by the mster when the bus is in IDLE stathe bs is free). The device-
write address is followed by the word address. After the word address any nuber odabytes can be sent to the slve. The word address is
incremented internally, in order to write subsequent data bytes on subsequent adress cations.
For reading data from the slave device, the master has to change the trdirection. This can be done either with a repeated START condition
followed by the device-read address, or simply with a new transmission RT followed by the devic-read address, when the bus is in IDLE
state. The device-read address is always followed by the 1st register byte ransmitted from the slve. In Read Mode any number of subsequent
register bytes can be read from the slave. The word address is incremented internally.
Figure 17. Random Read
S
DW
A
WA
DR
A
data
N P
read register
WA++
Random Read and Sequential Read are cmbined rmats. The repeated START condition is used to change the direction after the data transfer
from the master.
The word address transfer is initiated wh a START condition issued by the master while the bus is idle. The START condition is followed by the
device-write address and the wrd adress.
In order to change the data direcon a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address
transfer. After the recpon of he device-read address, the slave becomes the transmitter. In this state the slave transmits register data located
by the previous received ord address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on
the bus.
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AS3606 AS3607 2v2
Data Sheet - Detailed Description - SYSTEM Functions
Figure 18. Sequential Read
S
DW
A
WA
A
Sr
DR
A
data
A
reg_data 2
A
...
reg_data n
N P
read register
WA++
read register
WA++
read register
WA++
Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In differento the
Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number data
bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transission the master
has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently.
Figure 19. Current Address Read
S
DR
A
data
A
reg_da2
A
...
eg_da n
N P
read register
WA++
rearegir
WA
read register
WA++
To keep the access time as small as possibe, trmat allows a read acceswithout the word address transfer in advance to the data transfer.
The bus is idle and the master issues a STARondition followed bvice-Read address. Analogous to Random Read, a single byte
transfer is terminated with a not-acknowledge after the 1st register bnalogous to Sequential Read an unlimited number of data bytes can
be transferred, where the data bytes has to be responded wian acknowledge from the master. For termination of the transmission the master
sends a not-acknowledge following the last data byte and a susequent STOP condition.
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AS3606 AS3607 2v2
Data Sheet - Detailed Description - SYSTEM Functions
9.7.2 Parameter
Figure 20. 2-Wire Serial Timing
TS
T
SU
TH
T
HD
TL
TPD
CSDA
CSCL
1-7
8
9
1-7
8
9
1-7
Data
8
9
Start
Address R/W
ACK
Data
ACK
ACK
Stop
Condition
Conditio
DVDD =2.9V, Tamb=25ºC, unless otherwise specified.
Table 17. 2-Wire Serial Parameter
Symbol
VCSL
VCSH
HYST
VOL
Parameter
Condition
Min
Typ
Max
0.87
5.5
800
0.4
-
Unit
V
CSCL, CSDA Low Input Level
CSCL, CSDA High Input Level
CSCL, CSDA Input Hysteresis
CSDA Low Output Leve
Spike insensitivity
(max 30%DVDD
0
2.03
200
-
-
-
CSCL, CSDA (min 7%DVDD)
V
450
-
mV
V
at 3A
Tsp
50
100
ns
ns
ns
TH
Clock high time
ma. 400kHz clock speed
max. 400kHz clock speed
500
500
TL
Clock low time
CSA has to change Tsetup before rising edge
of CSCL
TSU
THD
TS
250
0
-
-
-
-
-
ns
ns
ns
ns
No hold time needed for CSDA relative to rising
edge of CSCL
CSDA H hold time relative to CSDA edge for
start/stop/rep_start
200
-
CSDA prop delay relative to lowgoing edge of
CSCL
TPD
50
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10 Register Definition
Table 18. I2C Register Overview
Addr
Name
b7
b6
b5
b4
b3
b2
b1
PMU Register
VSEL_CVDD1<6:0>
0 … OFF
0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.400V)
0x41 – 0x70: 1.4V + (VSEL-0x40) * 25mV ->(1.425V – 2.600V)
0x71 – 0x7F: 2.6V + (VSEL-0x70) * 50mV -> (2.650V – 3.350V)
VSEL_CVDD2<6:0>
CVDD1_fast
0: Cext=10µF
1: Cext=22µF
17h-1 CVDD1
17h-2 CVDD2
CVDD2_fast
0: Cext=10µF
1: Cext=22µF
0 … OFF
0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.400V)
0x41 – 0x70: 1.4V + (VSEL-0x40) * 25mV ->(1.425V – 2.60V)
0x71 – 0x7F: 2.6V + (VSEL-0x70) * 50mV -> (2.650V – 3.3V)
VSEL_CVDD3<6:0>
CVDD3_fast
0: Cext=10µF
1: Cext=22µF
0 … OFF
17h-3 CVDD3
0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.0V)
0x41 – 0x70: 1.4V + (VSEL-0x40) * 25mV ->(1.425V – 2.600V)
0x71 – 0x7F: 2.6V + (VSEL-0x70) * 50mV -> (2.50V – 3.350V)
17h-4 Hibernation
17h-5 DCDC_Cntr
-
KEEP_PVDD4
KEEP_PVDD3
KEEP_PVDD2
KEPVDD1
VM_CVDD23<1:0>
0: immediate;
: 42µs/step;
2: 166µs/step;
3: 666µs/step
KEEP_CVDD3
KEEP_CVDD2
DVM_CVDD1<1:0>
0: immediate;
1: 42µs/step;
2: 166µs/step;
3: 666µs/step
KEEP_CVDD1
CFM_CVDD23_OF
F
0: pulse skip on
1: pulse skip off
CFM_CVDD1_OFF CVDD23_REQ
0: pulse skip on
1: pulse skip off
CVDD1_FREQ
0: 2MHz
1: 1MHz
0: 2MH
1: 1M
MUX_GPIO43<1:0>
0: HiZ/HiZ; 1: xVSUP_low/xCharging;
2: xPWRUP/PWRGOOD;
DRIVE_GPIO2
0: opend drain
1: HiZ
MUX_GPIO2<1:0>
0LOW; 1: xVSUP_low;
2: HIGH; 3: xCharging
DRIVE_GPIO1
0: HiZ
1: opend drain
MUX_GPIO1<1:0>
0: xCharging; 1: xVSUP_low;
2: xPWRUP; 3: PWRGOOD
17h-7 GPIO_Cntr
3: xEOC/xCharger_active
ILIM_H_PVDD1
LP_PVD
VSEL_PVDD1<4:0>
18h-1 PVDD1
18h-2 PVDD2
18h-3 PVDD3
PVDD1_ON
PVDD2_ON
PVDD3_ON
0: 150mA
1: 250mA
0: normal de
0x00 – 0x0F: 1.2V + VSEL * 50mV → (1.2V – 1.95V)
low power mode 0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV → (2.0V – 3.5V)
LP_PVDD2
0normal mode
1: low power mode 0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV → (2.0V – 3.5V)
LP_PVDD3
0: normal mode
ILIM_H_PVDD2
0: 150mA
1: 250mA
VSEL_PVDD2<4:0>
0x00 – 0x0F: 1.2V + VSEL * 50mV → (1.2V – 1.95V)
ILIM_H_VDD
0: 1mA
VSEL_PVDD3<4:0>
0x00 – 0x0F: 1.2V + VSEL * 50mV → (1.2V – 1.95V)
1: 250mA
1: low power mode 0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV → (2.0V – 3.5V)
Table 18. I2C Register Overview
Addr Name
b7
b6
ILIM_H_PVDD4
0: 150mA
b5
b4
b3
b2
b1
b0
LP_PVDD4
0: normal mode
VSEL_PVDD4<4:0>
0x00 – 0x0F: 1.2V + VSEL * 50mV → (1.2V – 1.95V)
18h-4 PVDD4
18h-5 VDD27
PVDD4_ON
1: 250mA
1: low power mode 0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV → (2.0V – 3.5V)
PRG_VDD27
0: boot ROM
ILIM_H_VDD27
0: 100mA
VSEL_VDD27<3:0>
0x0 – 0x2: 2.3V
0x3 – 0xF: 2.0V + VSEL* 100mV → (2.3V – 3.5V)
LP_VDD27
-
1:register defined 1: 200mA
USB_CURRLIM <3:0>
0: 94mA; 1: 141mA; 2: 189mA; 3: 237mA; 4: 285mA; 5: 332A; 6: 380mA; 7:
428mA; 8: 470mA; 9: 517mA; A: 599mA; B: 760mA; C: 82mAD: 1060mA;
E-F: not defined
19h-0 CHG_Cntr
19h-1 CHG_VCntr
19h-2 CHG_ICntr
BAT_DET_OFF
AUTO_RESUME BAT_CHARGE_ON
USB_PREREG_ON
CHG_V_RESUME <2:0>
VSUP_MIN<1:0>
0: 3.9V; 1: 3.6V;
2: 4.2V; 3: 4.5V
CHG_V_EOC <:0>
0: 3.9V; 1: 395V; 2: 4.0V; 3: 4.05V;
4: 4.1V; 5: 4.15V; 6: 4.2V; 7: 4.25V
0: 3.85V; 1: 3.9V; 2: 3.95V; 3: 4.0V;
4: 4.05V; 5: 4.1V; 6:4.15V; 7: 4.2V
CHG_I_CONSTANT <3:0>
CHG_I_TRICKLE <3:0>
0: 25mA; 1: 35m2: 47mA; 3: 59mA; 4: 71mA; 5: 83mA; 6: 95mA; 7: 107mA;
8: 118mA; 9: 9mA; : 150mA; B: 190mA; C: 221mA; D: 265mA; E-F: not defined
0: 94mA; 1: 141mA; 2: 189mA; 3: 237mA; 4: 285mA; 5: 332mA; 6: 380m
428mA; 8: 470mA; 9: 517mA; A: 599mA; B: 760mA; C: 882mA; D: 1060mA
E-F: not defined
CHG_I_EOC<1:0>
0: 8%1: 15%;
2: 10%; 3: 20%
VSUP_EOC <2:0>
0: 4.3V; 1: 4.4V; 2: 4.5V; 3: 4.6V;
4: 4.7V; 5: 4.8V; 6: 4.9V; 7: 5.0V
19h-3 CHG_Conf
19h-4 CHG_NTC
19h-5 CHG_TIME
-
-
-
NTC_MODE
0: 55°C; 1: 45°C 0: 100k; 1: 10K;
CHG_TIMEOUT <3:0>
0:disabled; 1: 0.5h; 2: 1h; 3: 1,5h; 4: 2h; 5: 2.5h; 6: 3h; 7: 3.5h;
8: 4h; 9: 4.5h; A: 5h; B: 5.5h; C: 6h; D: 6.5h; E: 7h; F:7.5h
NTC_10K
NTC_ON
TMAX
CV
19h-6 CHG_STAT1
19h-7 CHG_STAT2
NO_BAT
-
BATTEMP_HIGH EOC
HBN_DELAY<0>
TRICKLE
RESUME
CC
CHG_DET
BATSW_MODE <1:0>
MUX_XIRQ<1:0>
DRIVE_XIRQ<1:0>
1Ah-1 Out_Cntr
1Ah-2 Clk_Cntr
DCDC23_1.4A
GPIO_HBN_ON
0: 0ms1: s;
2: 16ms; ms
LKINT1<1:0>
0: 2MHz; 1: 1MHz;
1kHz; 3: 125Hz
SU_SLOWDIM
0: tbd
0: 6mA OD; 1: 6mA PP;
2: 1mA PP; 3: HiZ
0: XIRQ; 1: CLKINT1;
2: CLKINT2; 3: IRQ
CLKINT2<1:0>
0: LOW; 1: CLK1Hz (charger);
2: do not use; 3: HIGH
GPIO_DIMM_HBN_SEL <1:0>
0: LOW; 1: GPIO1;
2: GPIO2; 3: GPIO3
-
SU_EXTDIM<1:0>
1Bh-1 Boost_Cntr1
1Bh-2 Boost_Cntr2
SU_ON
-
0: no dimm; 1: CURR1;
2: CURR2; 3: GPIO1/2/3
SU_OVP_OFF
SU_CURRLIM
SU_CURR_FB
SU_GAIN
SU_FASTSKIP
1: tbd
SU_IFB<4:0>
0x00 - 0x1F: 1µA * U_IB;
SU_FREQ
Table 18. I2C Register Overview
Addr Name
b7
b6
b5
b4
b3
b2
b1
b0
ICURR1<7:0>
0x00 - 0xFF: 150µA * ICURR;
ICURR2<7:0>
1Bh-3 CURR1
1Bh-4 CURR2
0x00 - 0xFF: 150µA * ICURR;
PMU_ENABLE <2:0>
DC_TEST_MUX <3:0>
SubRegister addresses for regiters:
0x17: DCDC regulators
0x18: LDOs regulaors
0x19: Charger
0x1A: IO_clock_corol
0x1B: BckLighDCDC
0: open; 1: PVDD1; 2: PVDD2;
3: PVDD3; 4: PVDD4; 5: VDD27;
6: CVDD1; 7: CVDD2; 8: CVDD3;
9-F: not defined
1Ch
PMU_Enable
PMU_GATE
System Register
20h
SYSTEM
Design_Version<3:0>
PWRUP_SD_XRES <1:0>
0: XRES; 1: -;
-
JTEMP_SP_OFF I2C_WD_ON
PWR_HOLD
SD_XRES_TIME JTEMP_<4:0>
0: 8s;
1: 4s
21h
SUPERVISOR1
Temp_Shwn = 140ºC - JTEMP_P*5ºC → (140ºC...5ºC)
Temp_IRQ 120ºC - JTEMP_SUP5ºC → 120ºC...-15ºC)
2: SD; 3: SD
VDD27low_SD_OF
F
22h
23h
24h
25h
26h
SUPERVISOR2
IRQENRD_0
IRQENRD_1
IRQENRD_2
IRQENRD_3
-
-
VSUPlow_SD_ON VSUPlow_UP<2:0>
VSUPlow_SUP_OFF
CVDD1_SD
CVDD1_IRQ
CVDD1_over
GPIO1_IRQ
CVDD2_SD
CVDD2_unde
GPIO2_IR
CVDD2_IRQ
CVDD2_over
GPIO3_IRQ
CV3_SD
VDD3_under
GPIO4_IRQ
CVDD3_IRQ
CVDD3_over
-
-
CVDD1_under
PWRUP_IRQ
CHG_TEMP_IRQ CHG_EOC_IRQ
CHGBAT_IRQ CHG_Q
-
ICURR_LV_IRQ
JTEMP_HIGH
VSUP_LOW_IRQ VDD27_LOW_IRQ
CHG_TEMP
CHG_EOC
CHG_NoBat
CHG_
-
ADC_EOC
T_DEB<1:0>
0: 3ms; 1: off;
ADC10_MUX<3:0>
0: VSUP; 1: GPIO3; 2: GPIO4; 3: VSUPSW; 4: VUSB
5: DC_TEST; 6: BATTEMP; 7: GPIO1; 8: GPIO2; 9: UP; A,B: -;
C: VBE_1µA; D: VBE_2µA; E,F: -
2Eh
2Fh
ADC10_0
ADC10_1
-
-
ADC10<9:8>
ADC10<7:0>
AS3606 AS3607 2v2
Data Sheet - Register Definition
Table 19. CVDD1 Register
Name
Base
Default
00h
CVDD1
2-wire serial
CVDD1 DC/DC Buck Regulator Control Register
Offset: 17h-1
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7
CVDD1_fast
0
R/W
Selects a faster regulation mode for CVDD1 suitable for larger load change.
0: normal mode, Cext=10µF
1: fast mode, Cext=22µF required
6:0
VSEL_CVDD1<6:0>
000000
R/W
The voltage select bits set the DC/DC output voltage level and power e
DC/DC converter down.
00h: DC/DC powered down
01h-40h: CVDD1=0.6V+VSEL_CVDD1*12.5mV
41h-70h: CVDD1=1.4V+(VSEL_CVDD1-40h25mV
71h-7Fh: CDD1=26V+(VSEL_CVDD1-70h)*5mV
Table 20. CVDD2 Register
Name
CVDD2
se
Default
00h
2-we serial
CVDD2 DC/DC Buck Regultor Control Register
Offset: 17h-2
This is an extended register and needs to be enby writing 010b to Reg. 1Ch first.
This register is rset aa VDD27-POR or XS inut.
Bit
Bit Name
Default
Acess
Bit Description
7
CVDD2_fast
0
R/W
Selects aster regulation mode for CVDD2 suitable for larger load changes.
0: al mode, Cext=10µF
1ode, Cext=22µF required
6:0
VSEL_CVDD2<6:0>
000000
R/W
The voltage select bits set the DC/DC output voltage level and power the
C/DC converter down.
00h: DC/DC powered down
01h-40h: CVDD1=0.6V+VSEL_CVDD1*12.5mV
41h-70h: CVDD1=1.4V+(VSEL_CVDD1-40h)*25mV
71h-7Fh: CVDD1=2.6V+(VSEL_CVDD1-70h)*50mV
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AS3606 AS3607 2v2
Data Sheet - Register Definition
Table 21. CVDD3 Register
Name
Base
Default
00h
CVDD3
2-wire serial
CVDD3 DC/DC Buck Regulator Control Register
Offset: 17h-3
This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7
CVDD3_fast
0
R/W
Selects a faster regulation mode for CVDD3 suitable for larger load change
0: normal mode, Cext=10uF
1: fast mode, Cext=22uF required
6:0
VSEL_CVDD3<6:0>
000000
R/W
The voltage select bits set the DC/DC output voltage level and powr the
DC/DC converter down.
00h: DC/DC powered down
01h-40h: CVDD1=0.6V+VSEL_CVDD1*12.5mV
41h-70h: CVDD1=1.4V+(VSEL_CVDD1-40h)*25mV
71h-7Fh: CVDD1=2.6V+(VSEL_CVDD1-70h)*50mV
Table 22. Hibernation Register
Name
Base
Default
00h
Hibernation
erial
U Hibernation Control Reister
Hibernation starts when writing this register, except hibnatiovia GPIO is selected.
This is an extended restr ad needs to be enabled by witing 100b to Reg. 1Ch first.
This register is reseat a VDD27-POR or XRES ut. This register MUST NOT be read back!!!
Offset: 17h-4
Bit
7
Bit Name
Default
ccess
n/a
Bit Description
-
0
0
6
KEEP_PVDD4
W
Keeps the rogrammed PVDD4 level during hibernation.
0down PVDD4
1: PVDD4
5
4
3
2
1
KEEP_PVDD3
KEEP_PVDD2
KEEP_PVDD1
KEEP_CVD3
KEP_VDD2
KEEP_CVDD1
0
0
0
0
0
0
W
W
W
W
W
W
eeps the programmed PVDD3 level during hibernation.
0: power down PVDD3
1: keep PVDD3
Keeps the programmed PVDD2 level during hibernation.
0: power down PVDD2
1: keep PVDD2
Keeps the programmed PVDD1 level during hibernation.
0: power down PVDD1
1: keep PVDD1
Keeps the programmed CVDD3 level during hibernation.
0: power down CVDD3
1: keep CVDD3
Keeps the programmed CVDD2 level during hibernation.
0: power down CVDD2
1: keep CVDD2
Keeps the programmed CVDD1 level during hibernation.
0: power down CVDD1
1: keep CVDD1
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AS3606 AS3607 2v2
Data Sheet - Register Definition
Table 23. DCDC_Cntr Register
Name
Base
Default
00h
DCDC_Cntr
2-wire serial
DC/DC Step Down Control Register
Offset: 17h-5
This is an extended register and needs to be enabled by writing 101b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7
CFM_CVDD23_OFF
CFM_CVDD1_OFF
CVDD23_FREQ
0
R/W
Disables pulse skip mode for DCDC2 and DCDC3
0: current force mode / pulse skip enabled
1: current force mode / pulse skip disable
6
5
0
0
R/W
R/W
R/W
R/W
Disables pulse skip mode for DCDC1
0: current force mode / pulse skip enabled
1: current force mode / pulse skip disable
Selects the switching frequency for DCDC2 and DCDC
0: 2MHz
1: 1MHz
4
CVDD1_FREQ
0
Selects the witchinfrequency for DCDC1
0: Hz
1: 1
3:2
DVM_CVDD23<1:0>
00
Configes the dynamic voltae manement (output voltage slope) for
CVDD2 and CVDD3
0: immediate change of te output voltage
1: 32µs/step
10: 128µs/st
11: 512µs/step
1:0
DVM_CVDD1<1:0>
00
R/W
Configurs the ynamic voltage management (output voltage slope) for
CVDD1
0ediate change of the output voltage
0/step
10: 128µs/step
: 512µs/step
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AS3606 AS3607 2v2
Data Sheet - Register Definition
Table 24. GPIO_Cntr Register
Name
Base
Default
00h
GPIO_Cntr
2-wire serial
GPIO Control Register
Offset: 17h-7
This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
Configures GPIO4 and GPIO3
7:6
MUX_GPIO43<1:0>
00
R/W
00: HiZ / HiZ (GPIOs are inputs)
01: xVSUP_low / xCharging
10: xPWRUP / PWRGOOD
11: xEOC / xCharger_active
5
DRIVE_GPIO2
0
R/W
R/W
Configures GPIO2 as input or output
0: open drain (output)
1: HiZ (input)
4:3
MUX_GPIO2<1:0>
00
Configures GPIO2 oput mode
00: LOW
01: SUP_low
10:
11: xCarging
2
DRIVE_GPIO1
0
R/W
R/W
Configures GPIO1 as inpuor ouut
: HiZ (input)
: open drain (outp
1:0
MUX_GPIO1<1:0>
00
Configures G1 output mode
00: xCharging
01: xVSP_lo
10: xPWRP
1GOOD
Table 25. PVDD1 Register
Name
PVDD1
Base
Default
00h
2-wire serial
PVDD1 Control Register
Offset: 18h-1
Thiis an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This egiser is reset at a VDD27-POR or XRES input.
Bit
Bit Name
efault
Access
Bit Description
7
PVDD1_ON
ILM_H_PVDD1
LP_PVDD1
0
R/W
Enables PVDD1 regulator
0: PVDD1 switched off
1: PVDD1 switched on
6
5
0
0
R/W
R/W
R/W
Selects the higher current limit for PVDD1
0: default mode, 150mA
1: 250mA mode
Selects the low power mode for PVDD1
0: PVDD1 is in normal operation
1: PVDD1 supply current is reduced
4:0
VSEL_PVDD1<4:0>
00000
Sets the LDO output voltage in register control mode (default voltage of the
regulator is selected by boot ROM
0x00-0x0F: 1.2V+VSEL*50mV → (1.2V - 1.95V)
0x10-0x1F: 2.0V + (VSEL-0x10)*100mV → (2.0V-3.5V)
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Data Sheet - Register Definition
Table 26. PVDD2 Register
Name
Base
Default
00h
PVDD2
2-wire serial
PVDD2 Control Register
Offset: 18h-2
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7
PVDD2_ON
0
R/W
Enables PVDD2 regulator
0: PVDD2 switched off
1: PVDD2 switched on
6
5
ILIM_H_PVDD2
LP_PVDD2
0
0
R/W
R/W
R/W
Selects the higher current limit for PVDD2
0: default mode, 150mA
1: 250mA mode
Selects the low power mode for PVDD2
0: PVDD2 is n normal operation
1: PVDD2 upply uent is reduced
4:0
VSEL_PVDD2<4:0>
00000
Sets the LDO outpuvoltage in register onol ode (default voltage of the
regr is selected by the boot ROM
0x00: 1.2V+VSEL*50mV (1.2V - 1.95V)
0x10-1F: 2.0V + (VSEL-0x10)*10mV → (2.0V-3.5V)
Table 27. PVDD3 Register
Name
PVDD3
Base
Default
00h
2-wire serial
PVDD3 Control Register
Offset: 18h-3
This is aended register and eds tbe enabled by writing 011b to Reg. 1Ch first.
This register is reset at a VDDor XRES input.
Bit
Bit Name
Default
Acces
Bit Description
7
PVDD3_ON
ILIM_H_PVDD3
LP_PVDD3
0
R/W
Enables PVDD3 regulator
0: PVDD1 switched off
1: PVDD1 switched on
6
5
0
0
R/W
R/W
R/W
Selects the higher current limit for PVDD3
0: default mode, 150mA
1: 250mA mode
Selects the low power mode for PVDD3
0: PVDD3 is in normal operation
1: PVDD3 supply current is reduced
4:0
VSEL_PD3<0>
00000
Sets the LDO output voltage in register control mode (default voltage of the
regulator is selected by the boot ROM
0x00-0x0F: 1.2V+VSEL*50mV → (1.2V - 1.95V)
0x10-0x1F: 2.0V + (VSEL-0x10)*100mV → (2.0V-3.5V)
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Data Sheet - Register Definition
Table 28. PVDD4 Register
Name
Base
Default
00h
PVDD4
2-wire serial
PVDD4 Control Register
Offset: 18h-4
This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7
PVDD4_ON
0
R/W
Enables PVDD4 regulator
0: PVDD4 switched off
1: PVDD4 switched on
6
5
ILIM_H_PVDD4
LP_PVDD4
0
0
R/W
R/W
R/W
Selects the higher current limit for PVDD4
0: default mode, 150mA
1: 250mA mode
Selects the low power mode for PVDD4
0: PVDD4 is n normal operation
1: PVDD4 upply uent is reduced
4:0
VSEL_PVDD4<4:0>
00000
Sets the LDO outpuvoltage in register onol ode (default voltage of the
regr is selected by the boot ROM
0x00: 1.2V+VSEL*50mV (1.2V - 1.95V)
0x10-1F: 2.0V + (VSEL-0x10)*10mV → (2.0V-3.5V)
Table 29. VDD27 Register
Name
VDD27
Base
Default
00h
2-wire serial
VD27 Control Register
Offset: 18h-5
This is aended register and eds tbe enabled by writing 101b to Reg. 1Ch first.
This register is reset at a VDDor XRES input.
Bit
Bit Name
Default
Acces
Bit Description
7
PRG_VDD27
ILIM_H_VDD27
LP_VDD27
0
n/a
Selects the output voltage control mode for VDD27
0:VDD27 is in default mode
1: VDD27 is register controlled (Reg. 18-5h)
6
5
0
0
R/W
R/W
Selects the higher current limit for VDD27
0: default mode, 100mA
1: 200mA mode
Selects the low power mode for VDD27
0: VDD27 is in normal operation
1: VDD27 supply current is reduced
5
-
0
n/a
3:0
VSEL_VDD2<3:0>
0000
R/W
Sets the LDO output voltage in register control mode (default voltage of the
regulator is 2.7V)
0x0-0x2: 2.3V
0x3-0xF: 2.0V + VSEL*100mV → (2.3V-3.5V)
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Data Sheet - Register Definition
Table 30. CHG_Cntr Register
Name
Base
Default
C9h
CHG_Cntr
2-wire serial
Charger Control Register
Offset: 19h-0
This is an extended register but does not need to be enabled as Reg. 1Ch is 000b per default.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7
BAT_DET_OFF
1
R/W
Disables the battery detection
0: Battery detection switched on
1: Battery detection switched off
6
5
AUTO_RESUME
1
0
R/W
R/W
R/W
Defines the behavior after end of charge (EOC)
0: auto resume is disabled
1: auto resume enabled, charger will start charginwhVBATSW
drops below the resume level
BAT_CHARGE_ON
Enables the battery charging
0: VSUP is supplevia USB pre-regulator, buthe battery switch is
open
1: normal battey charging operation from USB pre-regulator
4:1
USB_CURRLIM
<3:0>
1000
Sets SB pre-regulator curlimit
0x0: 9mA (USB low current)
0x1: 141mA
0x2: 189mA
x3: 237mA
0x4: 285mA
0x5: 332mA
0x6: 380mA
0x7: 428A
0x0mA (USB high current)
0mA
0xA: 599mA
0B: 760mA
0xC: 882mA
0xD: 1060mA
0xE, 0xF: do not use
0
USB_PREREG_ON
1
R/W
Enables the USB pre-regulator and current limiter
0: USB pre-regulator is switched off
1: USB pre-regulator supplies VSUP from VUSB input
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Data Sheet - Register Definition
Table 31. CHG_VCntr Register
Name
Base
Default
36h
CHG_VCntr
2-wire serial
Charger Voltage Control Register
Offset: 19h-1
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7:5
CHG_V_RESUME
<2:0>
001
R/W
Sets the charger auto resume voltage threshold
000: 3.85V
001: 3.90V
010: 3.95V
011: 4.00V
100: 4.05V
101: 4.10V
110: 4.15V
111: 4.20V
4:3
2:0
VSUP_MIN<1:0>
10
R/W
RW
Defines the minimum VSUP voltage durig trickle or constant current
charging. The harging current will be reduced VSUP would drop below
this old.
00: 3
01: 3.6
10: 4.2V
1: 4.5V
CHG_V_EOC
<2:0>
110
Sets the charger enf carge voltage threshold
000: 3.90V
001: 3.95V
010: 4.V
011: 4.05V
1V
1015V
110: 4.20V
11: 4.25V
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Data Sheet - Register Definition
Table 32. CHG_ICntr Register
Name
Base
Default
21h
CHG_VCntr
2-wire serial
Charger Current Control Register
Offset: 19h-2
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7:4
CHG_I_CONSTANT
<3:0>
0010
R/W
Sets the current during constant current charging
0x0: 94mA
0x1: 141mA
0x2: 189mA
0x3: 237mA
0x4: 285mA
0x5: 332mA
0x6: 380mA
0x7: 428mA
0x8: 470m
0x9: 517mA
0xAmA
0xB: A
0xC: 82mA
0xD: 1060mA
xE, 0xF: do not use
3:0
CHG_I_TRICKLE
<3:0>
0001
W
Sets the current ducostant current charging
0x0: 24mA
0x1: 35mA
0x2: 47A
0x3: 59mA
0A
0mA
0x6: 95mA
x7: 107mA
0x8: 118mA
0x9: 129mA
0xA: 150mA
0xB: 190mA
0xC: 221mA
0xD: 265mA
0xE, 0xF: do not use
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Data Sheet - Register Definition
Table 33. CHG_Config Register
Name
Base
Default
15h
CHG_Config
2-wire serial
Charger Configuration Register
Offset: 19h-3
This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
7:5
4:3
Bit Name
Default
000
Access
n/a
Bit Description
-
CHG_I_EOC<1:0>
10
R/W
Configures the end of charge current threshold. Charging will be stopped
the current drops below the threshold.
00: 8% of constant current setting
01: 15%
10: 10%
11: 20%
2:0
VSUP_EOC
<2:0>
101
R/W
Defines VSUvoltage after EOC and isolatettery.
000: 4.3V
001: 4.4V
010.5V
011:
100: V
101: 4.V
110: 4.9V
1: 5.0V
Table 34. CHG_NTC Register
Name
Bse
Default
01h
CHG_NTC
2wire srial
harger NTC Control Register
Offset: 19h-4
This is an extended regster and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
7:3
2
Bit Name
-
Default
0000
0
Access
n/a
Bit Description
NTC_MODE
R/W
Defines the temperature level for the battery temperature supervisor to stop
charging. (for beta of NTC = 4250)
0: 55ºC
1: 45ºC
1
0
NTC_10K
NTC_ON
0
1
R/W
R/W
Defines the type of NTC used for battery temperature supervisor.
0: 100kΩ
1: 10kΩ
Enables the battery temperature supervisor via NTC resistor.
0: NTC battery temp supervision disabled
1: NTC battery temp supervision enabled
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Data Sheet - Register Definition
Table 35. CHG_TIME Register
Name
Base
Default
07h
CHG_TIME
2-wire serial
Charger Time Control Register
Offset: 19h-5
This is an extended register and needs to be enabled by writing 101b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
7:5
4
Bit Name
Default
0000 0
0
Access
n/a
Bit Description
-
TMAX_TIMER
R
Returns the time-out supervision status
0: no time-out reached
1: charger time-out reached, charging stopped
W
Resets the charger time supervision
0: -
1: resets time-out counter
3:0
CHG_TIMEOUT
<3:0>
0111
R/W
Sets the curent durng constant current chargin
0x0: chargtimer dibled
0x1: 0.5h
0x2
0x3:
0x4: 2
0x5: 2.5h
x6: 3h
0x7: 3.5h
0x8: 4h
0x9: 4.5h
0xA: 5h
0xB: 5.5h
0
0h
0xE: 7h
F: 7.5h
Table 36. CHG_STAT1 Register
Name
Base
Default
xxh
CHG_STAT1
2-wire serial
Charger Status Register 1
Offset: 19h-6
Thiis an extended register and needs to be enabled by writing 110b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
BiNme
Default
Access
Bit Description
7
NO_B
x
R
Status if a battery is detected to the system, by measuring the NTC value on
BATTEMP pin.
0: battery detected
1: no battery detected
6
5
BATTEMP_HIGH
EOC
x
x
R
R
Only valid if a charger is deducted.
0: battery temperature o.k.
1: battery temperature higher 55ºC/45ºC (seed NTC_MODE)
0: end of charge not reached. Bit is cleared automatically if
USB_PREREG_ON or BAT_CHARGE_ON is cleared or resume state is
entered
1: end of charge reached
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Data Sheet - Register Definition
Table 36. CHG_STAT1 Register
Name
Base
Default
xxh
CHG_STAT1
2-wire serial
Charger Status Register 1
Offset: 19h-6
This is an extended register and needs to be enabled by writing 110b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
4
Bit Name
CV
Default
Access
Bit Description
1: if charger is in constant voltage (top-off charge) mode
1: if charger is in trickle charging mode
x
x
x
x
x
R
R
R
R
R
3
TRICKLE
RESUME
CC
2
1: if VBATSW dropped below resume threshold
1: if charger is in constant current charging mode
1: if a charger adapter is detected on VUSB pin
1
0
CHG_DET
Table 37. CHG_STAT2 Register
Name
Base
Deult
xxh
CHG_STAT2
2-wire rial
Chger Satus Register 2
Offset: 19h-7
This is an extended register and be enabled by wring 111b to Reg. 1Ch first.
This register is reset at a VDD27-PR or XRES input.
Bit
7:3
1:0
Bit Name
Default
xxxx xx
x
Access
n/a
BiDescription
-
BATSW_MODE
<1:0>
Shows the bttery sch peration mode
00: battery switcopen, no ideal diode operation (just for charger start-up)
01: battery sitch open, ideal diode operation (charger connected but EOC
reached
10: attery witch acting as a voltage limited current source (charging)
1y switch closed (charger disconnected)
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Data Sheet - Register Definition
Table 38. Out_Cntr Register
Name
Base
Default
00h
Out_Cntr
2-wire serial
DCDC mode and XIRQ Output Control Register
Offset: 1Ah-1
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7
DCDC23_1.4A
0
R/W
Combines DCDC2 and DCDC3 to one regulator for 1.4A output currents
0: DCDC2 and DCDC3 working independent
1: DCDC2 & DCDC3 combined for 1.4A (DCDC3 registers have no ffect)
6
GPIO_HBN_ON
0
R/W
R/W
0: Hibernation enable via GPIOs disabled
1: Hibernation enalbe via GPIOs enabled
GPIO selected via GPIO_DIMM_HBN_SEL <1:0>
5:4
HBN_DELAY<1:0>
00
Sets the delay time for going into hibernation after riting o register 17-4h
00: 0ms
01: 8ms
10: 16ms
11: ms
3:2
1:0
DRIVE_XIRQ<1:0>
MUX_XIRQ<1:0>
00
00
R/W
/W
Sets IRQ output pin to operain, push-pull or tri-state and sets
varioudriving strengths
00: 6mA open-drain outpt
01: 6mA push-pull output
0: 1mA push-pull t
11: HiZ, tri-ste
Multiplexes varioudgital signals to the XIRQ output pin
00: XIRQ, actie low interrupt request signal
01: CLKIN1, internal clock signal, see Clk_Cntr register
1NT2, internal clock signal, see Clk_Cntr register
1active low reset signal
Table 39. Clk_Cntr Register
Name
Clk_Cntr
Base
Default
00h
2-wire serial
Clock Control Register
Offset: 1Ah-2
Thiis an xtended register and needs to be enabled by writing 010b to Reg. 1Ch first.
Tis register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7:6
CLKINT2<10>
00
R/W
Selects the CLKINT2 input source. Note, this is an internal clock, which can
be multiplexed to the XRES output.
00: LOW, drives the signal to logic “0”
01: CLK1Hz charger
10: do not use
11: HIGH, drives the signal to logic “1”
:4
CLKINT1<1:0>
00
R/W
Selects the CLKINT1 frequency. Note, this is an internal clock, which can be
multiplexed to XIRQ output.
00: 2MHz
01: 1MHz
10: 1kHz
11: 125Hz
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Data Sheet - Register Definition
Table 39. Clk_Cntr Register
Name
Base
Default
00h
Clk_Cntr
2-wire serial
Clock Control Register
Offset: 1Ah-2
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
3:2
GPIO_DIMM_HBN_SEL
<1:0>
00
R/W
Selects input for external dimming or hibernation control
00: disable dimming or hibernation via GPIO
01: GPIO1
10: GPIO2
11: GPIO3
1:0
-
00
n/a
Table 40. BOOST_Cntr1 Register
Name
Bas
efault
00h
BOOST_Cntr1
2-wire seal
step-up Control egister 1
Offset: 1Bh-1
This is an extended register and neds to be enabled by writing 01b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Acces
Bit Description
Enables the CDC p-uregulator
7
SU_ON
0
RW
0: SU switched ff
1: SU swchd on (will be reset if VFB exceeds the maximum and the
current ops to zero)
6
5
-
0
0
n/a
SU_SLOWDIM
R/W
Sthe DCDC step-up regulator external dimming mode
0: for dimming frequencies <1kHz
: for dimming frequencies >1kHz
4:3
SU_EXTDIM<1:0>
00
R/W
Selects the DCDC step-up external PWM dimming input
00: no ext. dimming
01: CURR1 controlled
10: CURR2 controlled
11: GPIO1/2/3 controlled (selected via GPIO_DIMM_HBN_SEL <1:0>)
2
1
0
SU_OVP_OFF
SU_URR_F
SFASTSKIP
0
0
0
R/W
R/W
R/W
Disables the DCDC step-up over-voltage protection
0: SU OVP switched on
1: SU OVP switched off
Selects the DCDC step-up feedback mode
0: voltage FB via pin FBSU
1: current feedback via CURR1 or CURR2 (automatic select)
Defines the DCDC step-up regulator output voltage at low loads, when pulse
skipping is active
0: Accurate output voltage, more ripple
1: Elevated output voltage, less ripple
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Data Sheet - Register Definition
Table 41. BOOST_Cntr2 Register
Name
Base
Default
00h
BOOST_Cntr2
2-wire serial
DCDC step-up Control Register 2
Offset: 1Bh-2
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
Defines the tuning current at pin FBSU.
7:3
SU_IFB<4:0>
0 0000
R/W
0x00: 0µA
0x01: 1µA
0x02: 2µA
...
0x1F: 31µA
2
SU_CURRLIM
0
R/W
Selects the DCDC step-up converter coil current limit
0: normal current limit
1: current liit incresed by about 50%
1
0
SU_GAIN
SU_FREQ
0
R/W
R/W
DCDC stepp convter feedback gain seleted automatically depending
on rrent or voltage feedback mode. Setting tis bit to “1” will choose the
alteedback gain settin.
00
Definethe DCDC step-up switchinfrequency
0: 1MHz
1: 500kHz
Table 42. CURR1 Register
Name
CURR1
Be
Default
00h
e serial
Current Sink 1 Register
Offset: 1Bh-3
This is an extended regiter ad needs to be enabled by writing 011b to Reg. 1Ch first.
This register is eset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Acess
Bit Description
7:0
ICURR1<7:0>
0x00
R/W
Sets the current for current sink 1 in 255 steps with 140.626µA stepsize
0x00: Current sink 1 switched off
0x01: 0.15 mA
0x02: 0.30 mA
0x03: 0.45 mA
..
0xFE: 38,10 mA
0xFF: 38.25 mA
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Data Sheet - Register Definition
Table 43. CURR2 Register
Name
Base
Default
00h
CURR2
2-wire serial
Current Sink 2 Register
Offset: 1Bh-4
This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7:0
ICURR2<7:0>
0x00
R/W
Sets the current for current sink 2 in 255 steps with 140.626µA stepsize
0x00: Current sink 2 switched off
0x01: 0.141 mA
0x02: 0.281 mA
0x03: 0.422 mA
..
0xFE: 35,72 mA
0xFF: 35.86 mA
Table 44. PMU_Enable Register
Name
Base
Default
00h
PMU_Enable
2seal
PMU_Enable Reister
Selects the extended register on address 17h to 1Bh anenables writing to these PMU register. It also
sets the ADC10 multiplxer to measure various retor vltages
Offset: 1Ch
This register is reset t a VDD27-POR or XRES ut.
Bit
Bit Name
Default
ccess
Bit Description
7:4
DC_TEST_MUX
<3:0>
0000
R/W
Allows ultipleing internal and external supply voltages to one DC test
node whiccan be further multiplexed to the ADC10. The accuracy is 5mV/
Le reg. 2Eh)
0en
0x1: PVDD1
x2: PVDD2
0x3: PVDD3
0x4: PVDD4
0x5: VDD27
0x6: CVDD1
0x7: CVDD2
0x8: CVDD3
0x9-0xF: n/a
3
PMU_GATE
0
R/W
R/W
Enables all settings made in registers 17h to 1Bh at once. If this bit is set,
changes are activated as soon as they are written to the related register.
0: no change
1: change at once
2:0
PMU_ENABLE
<2:0>
000
Selects extended registers 17h to 1Bh for the next read or write. This register
has to be set before every read or write even if the selection is not changing.
0: 19h-0 selected
1: 17h-1 to 1Bh-1 selected
2: 17h-2 to 1Bh-2 selected
...
7: 17h-7 to 1Bh-7 selected
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AS3606 AS3607 2v2
Data Sheet - Register Definition
Table 45. SYSTEM Register
Name
Base
Default
51h
SYSTEM
2-wire serial
SYSTEM Register
This register is reset at a VDD27-POR or XRES input.
Offset: 20h
Bit
Bit Name
Default
Access
Bit Description
Number to identify the design version
0101: for chip version 2v2
7:4
Design_Version<3:0>
0101
R
3
2
-
0
0
n/a
JTEMP_SUP_OFF
R/W
Junction temperature supervision (level can be set in register 21h)
0: temperature supervision enabled
1: temperature supervision disabled
1
I2C_WD_ON
PWR_HOLD
0
R/W
R/W
2-wire serial interface watchdog
To reset the watchdog counter a 2-wire serial read peraton has to be
performed t least every 500ms. If the watchg couner is not reset, the
PMU will poweredown.
0: watchdois disbled
1: chdog is enabled
0
1
0: pup hold is cleared and MU will power down
1: is tomatically set to oafter ower on
Table 46. SUPERVISOR1 Register
Name
Base
Default
00h
SUPERVISOR1
2-wire serial
SUPRVISOR Register 1
This rer is reset at a VDDOR oXRES input.
Offset: 21h
Bit
Bit Name
Default
Access
Bit Description
7:6
PWRUP_SD_XRES
<1:0>
00
R/
pplying a high signal on PWRUP pin for about 8s will
00: perform a reset cycle
01: have no effect
10: initiate a shut-down
11: initiate a shut-down
5
SD_XRES_TIME
0
0
R/W
R/W
Halfs the time from pulling PWRUP high to XRES or SD
0: 8s
1: 4s
4:0
JTEMP_SUP<4:0>
Sets the threshold for junction temperature emergency shutdown and
junction temperature interrupt
Invoke shutdown at: JTemp_SD=140-JTEMP_Sup*5ºC
Invoke interrupt at: JTemp_IRQ=120-JTEMP_Sup*5ºC
JT_Sup IRQ Shutdown
00000 120°C 140°C
00001 115°C 135°C
.
.
.
.
.
.
11110 -30°C -10°C
11111 -35°C -15°C
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AS3606 AS3607 2v2
Data Sheet - Register Definition
Table 47. SUPERVISOR2 Register
Name
Base
Default
00h
SUPERVISOR2
2-wire serial
SUPERVISOR Register 2
This register is reset at a VDD27-POR or XRES input.
Offset: 22h
Bit
7:6
5
Bit Name
Default
Access
n/a
Bit Description
-
00
0
VDD27low_SD_OFF
R/W
0: VDD27low (VDD27 -10%) shut down enabled
1: VDD27low shut down disabled
4
VSUPlow_SD_ON
0
R/W
R/W
0: VSUPlow shut down enabled
1: VSUPlow shut down disabled
3:1
VSUPlow_SUP<2:0>
000
Sets the threshold for VSUP supervisor
000: 2.7V
001: 2.9V
010: 3.1V
011: 3.2V
100: 3.3V
10V
110
111: V
0
VSUPlow_SUP_OFF
0
R/W
0: VSUPlow supervisioenabld
: VSUPlow supervisn disled
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AS3606 AS3607 2v2
Data Sheet - Register Definition
Table 48. First Interrupt Register
Name
Base
Default
00h
IRQENRD_0
2-wire serial
First Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while reading gets the actual interrupt status and will clear the register at the
same time. It is not possible to read back the interrupt enable/disable settings. This register is
reset at a VDD27-POR or XRES input.
Offset: 23h
Bit
Bit Name
Default
Access
Bit Description
7
CVDD1_SD
0
W
Invokes shut-down of the PMU when a –10% under-voltage spike aCVD
occurs
0: disable
1: enable
CVDD1_under
CVDD1_IRQ
x
R
This bit is set when a –5% under-voltage at CVDD1 ours
6
5
0
W
Enables interrupt for over-voltage/under-voltge suprvision of CVDD1
0: disable
1: enable
CVDD1_over
CVDD2_SD
x
R
Thbit is set when a +8% over-voltage at CVD1 occurs
0
W
Invohut-down of the PMU en a –10% under-voltage spike at CVDD2
occur
0: disable
1: enable
CVDD2_under
CVDD2_IRQ
x
R
This bit is set whe5% under-voltage at CVDD2 occurs
4
3
0
W
Enables interrut for over-voltage/under-voltage supervision of CVDD2
0: disable
1: ena
CVDD2_over
CVDD3_SD
x
R
Tt is set when a +8% over-voltage at CVDD2 occurs
0
W
Ishut-down of the PMU when a –10% under-voltage spike at CVDD3
occurs
: disable
1: enable
CVDD3_under
CVDD3_IRQ
x
R
This bit is set when a –5% under-voltage at CVDD3 occurs
2
0
W
Enables interrupt for over-voltage/under-voltage supervision of CVDD3
0: disable
1: enable
CVDD3_over
-
x
R
This bit is set when a +8% over-voltage at CVDD3 occurs
1:0
00
n/a
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AS3606 AS3607 2v2
Data Sheet - Register Definition
Table 49. Second Interrupt Register
Name
Base
Default
00h
IRQENRD_1
2-wire serial
Second Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while reading gets the actual interrupt status and will clear the register at the
same time. It is not possible to read back the interrupt enable/disable settings. This register is
reset at a VDD27-POR or XRES input.
Offset: 24h
Bit
Bit Name
Default
Access
Bit Description
7
PWRUP_IRQ
0
W
Enables interrupt which is invoked whenever a high signal at the PRU
input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. VSUP/3 at he PRUP input pin
occurs (PWRUP pin is commonly connected to the poweup button)
6
5
GPIO1_IRQ
GPIO2_IRQ
GPIO3_IRQ
GPIO4_IRQ
-
0
W
Enables inrrupt which is invoked whenever a igh signal at the GPIO1
input pin ocurs
0: disable
1: e
x
R
This is set whenever a high lel of min. tbd at the GPIO1 input pin
occur
0
W
Enables interrupt which is voked whenever a high signal at the GPIO2
nput pin occurs
0: disable
1: enable
x
R
This bit is sewhenever a high level of min. tbd at the GPIO2 input pin
occurs
4
0
W
interrupt which is invoked whenever a high signal at the GPIO3
ioccurs
0: disable
: enable
x
R
This bit is set whenever a high level of min. tbd at the GPIO3 input pin
occurs
3
0
W
Enables interrupt which is invoked whenever a high signal at the GPIO4
input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. tbd at the GPIO4 input pin
occurs
2:0
000
n/a
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AS3606 AS3607 2v2
Data Sheet - Register Definition
Table 50. Third Interrupt Register
Name
Base
Default
00h
IRQENRD_2
2-wire serial
Third Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while reading gets the actual interrupt status and will clear the register at the
same time. It is not possible to read back the interrupt enable/disable settings. This register is
reset at a VDD27-POR or XRES input.
Offset: 25h
Bit
Bit Name
Default
Access
Bit Description
Battery over-temperature interrupt setting
0: disable
7
CHG_TEMP_IRQ
(status change)
0
W
1: enable interrupt if CHG_TEMP status bit changes
CHG_TEMP
x
R
Battery over-temperature status reading
0: battery temperature below off-threshold
1: battery temperature was too high and the chargwas urned off. The
charger will e turned on again, when the temrature gets below the on-
threshold
6
CHG_EOC_IRQ
(status change)
0
x
W
R
Charger end f chage interrupt setting.
0: e
1: einterrupt if CHG_EOtatus bit changes
CHG_EOC
Chargend of charge staus ading
0: battery charging in prgress
: charging is complcharing current is below selected level of nominal
current, charger wurnd off.
5
4
CHG_NoBAT_IRQ
(status change)
0
x
0
x
W
R
Charger no batry interrupt setting
0: disabe
1: enabinterrpt if CHG_NoBat status bit changes
CHG_NoBat
Cr no battery status reading
ry connected
1: no battery detected at VBATSW pin
CHG_DET_IRQ
(status change)
W
R
Charger detect interrupt setting.
0: disable
1: enable interrupt if CHG_DET status bit changes
CHG_DET
Charger detect status reading
0:charger disconnected
1: charger connected
3
2
-
0
0
n/a
W
ICURR_LV_IRQ
(level)
Current sink undervoltage interrupt setting.
0: disable
1: enable interrupt if the outputvoltage of one of the current sinks gets below
the target regulation voltage
x
R
Current sink undervoltage status reading
0: normal voltage on ICURR1 and ICURR2
1: voltage at ICURR1 or ICURR2 dropped below target voltage
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AS3606 AS3607 2v2
Data Sheet - Register Definition
Table 50. Third Interrupt Register
Name
Base
Default
00h
IRQENRD_2
2-wire serial
Third Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while reading gets the actual interrupt status and will clear the register at the
same time. It is not possible to read back the interrupt enable/disable settings. This register is
reset at a VDD27-POR or XRES input.
Offset: 25h
Bit
Bit Name
Default
Access
Bit Description
1
VSUP_LOW_IRQ
(level)
0
W
VSUP under-voltage supervisor interrupt setting
0: disable
1: enable
x
R
VSUP supervisor interrupt reading
0: VSUP is above brown out level
1: VSUP has reached brown out level
The threshold can be set with VSUPlow_SUP<2:0> iSUPERVISOR2
register (22h). If the shutdown is enabled the interrut will not occur.
0
VDD27_LOW_IRQ
(level)
0
x
W
R
VDD27 unervoltgsupervisor interrupt setting
0: disable
1: able
VDDupervisor interrupt reag
0: VD27 is above threshod out el
1: VDD27 has reached thrshollevel (VDD27-10%).
f the shutdown is enabled e interrupt will not occur.
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AS3606 AS3607 2v2
Data Sheet - Register Definition
Table 51. Fourth Interrupt Register
Name
Base
Default
00h
IRQENRD_3
2-wire serial
Fourth Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while reading gets the actual interrupt status and will clear the register at the
same time. It is not possible to read back the interrupt enable/disable settings. This register is
reset at a VDD27-POR or XRES input.
Offset: 26h
Bit
7:6
5
Bit Name
-
Default
Access
R/W
Bit Description
00
0
T_DEB<1:0>
R/W
Sets the de-bounce time all interrupt inputs:
0: 3ms
1: off
4:3
2
-
00
0
R/W
W
JTEMP_HIGH
(level)
Supervisor jnction over-temperature interruetting
0: disable
1: enable
x
R
Suor junction over-temperature interrupt reading
0: cmperature below threld
1: chitemperature has reaced thtreshold
The threshold can be set the UPERVISOR register (21h)
1
0
-
0
0
R/
ADC_EOC
(edge)
ADC end of onvern ierrupt setting
0: disable
1: enable
x
R
ADC end of conversion interrupt reading
conversion not finished
conversion finished. Read out ADC10_0 and ADC10_1 register to
get the result (2Eh & 2Fh)
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AS3606 AS3607 2v2
Data Sheet - Register Definition
Table 52. ADC10_0 Register
Name
Base
Default
ADC10_0
2-wire serial
0000 00xxb
First 10-bit ADC Register
Offset: 2Eh
Writing to this register will start the measurement of the selected source.
This register is reset at a VDD27-POR, exception are bit 0 and 1
Bit
Bit Name
Default
Access
Bit Description
7:4
ADC10_MUX<3:0>
0000
R/W
Selects ADC input source
0000: VSUP
0001: GPIO3
0010: GPIO4
0011: VBATSW
0100: VUSB
0101: defined by DC_TEST in register 0x1C
0110: BATTEMP
0111: GPIO1
1000: GP2
1001:PWRP
10reserved
101rvd
1100BE_1uA
1101: BE_2uA
1110: reserved
101: reserved
3:2
1:0
-
00
xx
n
R
ADC10<9:8>
ADC result it 9 to 8
Table 53. ADC10_1 Register
Name
ADC10_1
Base
Default
xxh
2-wire serial
Second 10-bit ADC Register
Offset: 2Fh
This register is reet at a VDD27-POR.
Bit
Bit Name
ADC10<7:0>
Default
Access
Bit Description
7:0
00h
R
ADC results bits 7 to 0
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AS3606 AS3607 2v2
Data Sheet - Application Information
11 Application Information
11.1 Pad Cells
Figure 21. Pad Cells Equivalant Circuit
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AS3606 AS3607 2v2
Data Sheet - Application Information
11.2 Application Schematics
Figure 22. Typical AS3606 Application Schematic
O N
D V D D
2 5
1 8
1 9
3 3
C V D D 3
L X C
2 O G P I
1 O G P I
V S S
2 8
s O L D G
I O 1 G P
C V D D 3
3
2
L X 3
L X 2
2 7
2 6
V S U P 3
P W R U P
2 2
P W R U P
Q X R I
C V D D 2
R
2 9
3 0
3 1
2 4
2 1
2 0
C V D D 2
C V D D 1
L X
S
C S D
C L
X R E S
C S D A
C S C L
U P 2
C V D D 1
g e r C h a r
S U
2
L X C
V S U P 1
C U R R
1 4
D C D C
1
C U R R
1 5
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AS3606 AS3607 2v2
Data Sheet - Application Information
Figure 23. Typical AS3607 Application Schematic
O G P I
3 O G P I
2 O G P I
1 O G P I
V S S
2 0 I O 4 G P
2 3 I O 3 G P
2 1 O G P
2 2 I O
3
C V D D 3
3 C L X
3 2
s O L
C V D D 3
L X 3
L X 2
3 1
3 0
V S U P 3
R U P
P W R U P
Q X R I
2 6
2 8
2 5
2 4
C V D D 2
3 3
3 4
3 5
R Q X I
C V D D 2
C V D D 1
2 C L X
X R E S
X R E S
C S D A
C S C L
S U
S D A
C S C L
C V 1
1 5
1 C X
V S U P 1
g e r C h a r
3 V S U
2
C U R R
1 6
D C D C
1
C U R R
1 7
C U R R 1
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AS3606 AS3607 2v2
Data Sheet - Package Drawings and Markings
12 Package Drawings and Markings
Figure 24. AS3606 QFN32, 0.5mm Pitch
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AS3606 AS3607 2v2
Data Sheet - Package Drawings and Markings
Figure 25. AS3607 QFN36, 0.5mm Pitch
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AS3606 AS3607 2v2
Data Sheet - Package Drawings and Markings
Figure 26. QFN Marking
Table 54. Package Code YYWWZZZ
YY
WW
working week assembly / packagin
X
ZZ
year
plant identifier
free choice
Table 55. Start-up Revision Code
xx
FF
00
xx
Sequene
engineering samplesno sequence progmed or sequence programmed on request
default sequee (no equence programmed)
ustomer specified suencprogrammed during production test
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AS3606 AS3607 2v2
Data Sheet - Revision History
Revision History
Revision
Date
Owner
Description
first official release
1.00
7.2010
pkm
corrected GPIO2 bit description & GPIO hibernation description
updated package drawings
1.01
9.2010
pkm
corrected charger block diagram, updated package drawings
1.02
1.03
11.2010
3.2011
pkm
pkm
added NTC supply description, added USB rising edge specification
Note: Typos may not be explicitly mentioned under revision history.
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AS3606 AS3607 2v2
Data Sheet - Ordering Information
13 Ordering Information
The devices are available as the standard products shown in Table 56.
Table 56. Ordering Information
Ordering Code
Marking
Sequence
Description
Delivery Form
Package
AS3606-BQFP-FF
R2v2-FF
sequence
programmable on
request
System PMU with HV Backlight
Tape & Reel
dry pack
QFN32 5x5 0.5mm pitch
AS3606-BQFP-00
AS3606-BQFP-xx
R2v2-00
R2v2-xx
default sequence
System PMU with HV Backlight
System PMU with HV Backlight
Tape & Reel
dry pack
QFN32 5x5 0.5mm pitch
QFN32 5x5 0.5mm ptc
customer specified
Tape & Reel
dry pack
AS3607-BQFP-FF
R2v2-FF
sequence
programmable on
request
System PMU with HV Backlight
Tape & Reel
dry pack
QFN36 6x6 0.5mm pitch
AS3607-BQFP-00
AS3607-BQFP-xx
R2v2-00
R2v2-xx
default sequence
System PMU with HV Backlight
System PMU with Hacklight
Tape & Reel
dry pack
QFN36x6 0.5mm pitch
QFN36 6x6 0.5mm pitch
customer specified
Tape & Reel
dry pack
Note: All products are RoHS compliant and austriamicrosystems gr
Buy our products or get free samples online at ICdirect: http://w.austriamicrosystems.co/ICdirect
Technical Support is found at http://www.austriamicrosystems.com/Technical-Suppt
For further information and requests, please conact us mailto:sales@austriarosstems.com
or find your local distributor at http://www.auriamicosystems.com/disutor
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Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - Copyright
Copyright
Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and pries
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG fo
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature rane,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamiosystms AG shall not
be liable to recipient or any third party for any damages, including but not limiteto personal injury, property dam, loss f profits, loss of use,
interruption of business or indirect, special, incidental or consequential damags, of any nd, in connection with or aring out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recipent or ny third party shall rise oflow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, ustri
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 313525 01
FSales ice, Distributors and Representatives, please visit:
http://ww.austriamicrosystems.com/contact
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