AS3677 [AMSCO]
Triple Channel Lighting Management Unit with DCDC step/up, ALS, 2xDLS(=DBC) and RGB Driver; 三通道的照明管理单元与DCDC步/时， ALS ， 2xDLS （ = DBC）和RGB驱动器
| 型号： | AS3677 |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | Triple Channel Lighting Management Unit with DCDC step/up, ALS, 2xDLS(=DBC) and RGB Driver |
| 文件： | 总68页 (文件大小：4711K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
austriamicrosystems AG
is now
ams AG
The technical content of this austriamicrosystems datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
e-Mail: ams_sales@ams.com
Please visit our website at www.ams.com
Datasheet
AS3677
Triple Channel Lighting Management Unit with DCDC step/up,
ALS, 2xDLS(=DBC) and RGB Driver
1 General Description
2 Key Features
ꢀ
High-Efficiency Step Up DC/DC Converter
The AS3677 is a highly-integrated CMOS Power and
Lighting Management Unit for mobile telephones, and
other Li+ battery powered devices.
- Up to 25V, up to 50mA for White LEDs
- Programmable Over voltage Protection
(10V, 16V or 25V)
The AS3677 incorporates one Step Up DC/DC Con-
verter for white backlight LEDs one Analog-to-Digital
Converter, six current sinks, LED in-circuit function test,
an I2C serial interface, and control logic all onto a single
device. It includes a charge pump to control e.g. an RGB
together with an internal pattern generator for smooth
blinking effects.
ꢀ
ꢀ
50mA Charge Pump
- 1:1 and 1:2 Mode with automatic Up Switching
- Only 2 External Capacitors Required
6 Current Sinks
- Fully Programmable (8-bit) from: 0mA to 25.5mA
- 3xHigh Voltage capable (up to 2V)
It supports ambient light sensor processing and two
Dynamic Luminance Scaling (DLS) (also called
Dynamic Backlight Control - DBC) input.
- 3xLow voltage for use wth the CP (up to 5.5V)
- Selectively Enable/Disable Current Sinks
- Dual ynamic Luminance Scaling (DLS) support to
impove backlight opratintime (can adjust any
current source)
- Light Sensor inut with internal hardware process-
ing to conrobacklight according to ambient light
using 3 goups
Internally the PWM signal for DLS can be used to
change the analog current through the current sources
(two channels can be used simultaneously). This avoids
noise in the system as the changes of backlight control
happen continuously without using the PWM modulation
scheme.
ꢀ
InternWM Generation
Output voltages and output currents are fully prgram-
mable.
8 Besution
- Autonomous Logarithmic up/down dimming
ed Pattern Generator
The AS3677 is part of the austriamicrosystms AS3675,
AS3687/87XM, AS3688 and AS368liting manage-
ment unit family. It is software compatto AS3675,
AS3676, AS3687/87XM, AS3688 and AS3689.
ꢀ
ꢀ
- Autonomous driving of Fun RGB or indicator LEDs
10-bit Successive Approximation ADC
- 27µs Conversion Time
The AS3677 is available in a space-saving WL-CSP
package measuring only 2.2x2.2x0.6mm and opertes
over the -30ºC to +85ºC temperature range
- Selectable Inputs: VANA, DLS1, DLS2, ALS/
GPIO1, GPIO2, CURR1, CURR2, CURR6, VBAT,
RGB1, RGB2 and RGB3
- Internal Temp. Measurement
- Light Sensor input with Java support (JSR-256):
read ADC processed value
Figure 1. Function Diagram
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ꢀ
ꢀ
Support for automatic LED testing (open and
shorted LEDs can be identified)
AS3677
Programmable LDO
- 1.8 to 3.35V, 10mA
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- Programmable via Serial Interface
Wide Battery Supply Range: 3.0V to 5.5V
I2C Serial Interface Control with address control pin
Over current and Thermal Protection
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Package
WL-CSP25, 2.2x2.2x0.6mm, 0.4mm pitch
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3 Applications
Lighting Management Unit for mobile phones, smart-
phones, PMP or PND
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AS3677
Datasheet - Applications
The application circuit including all external components is shown in Figure 2:
Figure 2. Application Circuit AS3677
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AS3677
Datasheet - Pinout
4 Pinout
4.1
Pin Assignments
Figure 3. Pin Assignments (Top View)
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4.2
Pin Description
Table 1. Pin Description
Pin Number
Pin Name
Description
Charge pumflyng capacitor
Charge pump output capacitor
hge pump supply voltage
A1
A2
A3
C1_P
CPOUT
VBAT_CP
DC and charge pump power ground pad - make a short connection to
apacitor C1 and C2 (and C5)
A4
VSS_DCD
Power pad - DCDC switch transistor output
Charge pump flying capacitor
Ambient Light Sensor input and General Purpose Input Output 1
Positive supply pad - Connect to battery.
ground pad
A5
B1
B2
B3
B4
C1
C2
C3
C4
C5
SW
C1_N
LS/GPIO1
VBAT
VSS
ground pad
VSS
LDO Output pad
VANA
INT
interrupt output - open drain active low
I2C address select input
Analog current sink input
Analog current sink input
ADR
RGB2
RGB1
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AS3677
Datasheet - Pinout
Table 1. Pin Description
Pin Number
Pin Name
Description
General Purpose Input Output 3
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
GPIO3
CLK
Digital input - Clock input for serial interface.
Digital Luminance Scaling PWM input2 (or General Input)
Analog current sink input
DLS2
RGB3
CURR1
GPIO2
DATA
Analog current sink input
General Purpose Input Output 2
Digital input/output - Serial interface data
Digital Luminance Scaling PWM input1 (or General Input)
Analog current sink input
DLS1
CURR6
CURR2
Analog current sink input
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AS3677
Datasheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Table 3, “General
Operating Conditions; typical values are at VBAT=3.7V and 25ºC,” on page 5 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Comments
Applicable for high-voltage
current sink pins CURR1,
CURR2, CURR6, SW
VIN_HV
26V Pins
-0.3
26
V
Applicable for 5V pins
VBAT, VBAT_CP, CK,
DATA, ADR, RGB1, RB2,
RGB3, CPOUT, C1_P, C1_N,
NT
VIN_MV
VIN_LV
5V Pins
-0.3
-0.3
7.0
5.0
V
V
Applicabfor .3V pins
ALS/GPO1, PIO2, GPIO3,
LS1DLS2, VANA
3.3V Pins
GND pins
0.0
-25
0
V
2xVS, VSS_DCDC
Input Pin Current without causing
latchup
+25
mA
At 25ºC, Norm: EIA/JESD78
Tstrg
IIN
Storage Temperature Range
55
5
125
85
ºC
V
Humidity
HBM
Non-condensing
-2000
2
Norm: JESD22-A114F
Norm: JEDEC JESD 22-
C101E
CDM
-500
-00
500
100
0.75
260
V
V
VESD
Norm: JEDEC JESD 22-
A115-B
M
TA = 70 ºC, Tjunc_max =
125ºC; RTHJU=73 K/W
Pt
Total Power Dissipation
Peak Body Temperature
Moisture sensitivity vel
W
ºC
T = 20 to 40s, in accordance
with IPC/JEDEC J-STD 020.
TBODY
MSL
Represents a max. floor life
time of unlimited
1
6 Electrical Characteristics
Table 3. General Operating Condtions; typical values are at VBAT=3.7V and 25ºC
Symbol
VHV
Paraeter
igh Voltage
Battery Voltage
Condition
Min
0.0
3.0
1.5
Typ
Max
26.0
5.5
Unit
V
Applicable for high-voltage current sink pins
CURR1, CURR2 and CURR6.
VBAT
Pin VBAT, VBAT_CP
3.7
V
Periphery Supply
Voltage
VPE
For serial interface pins.
5.5
V
Operating
AMB
-30
25
110
10
85
15
ºC
µA
µA
Temperature Range
Normal Operating current (see Operating
Modes on page 58)
IACTIVE
Battery current
Current consumption in standby mode.
Interface active
ISTANDBY Standby Mode Current
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AS3677
Datasheet - Electrical Characteristics
Table 3. General Operating Conditions; typical values are at VBAT=3.7V and 25ºC
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Shutdown Mode
Current
ISHUTDOWN
interface inactive (CLK and DATA set to 0V)
0.1
3
µA
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AS3677
Datasheet - Typical Operating Characteristics
7 Typical Operating Characteristics
Measured at VBAT=3.7V and TAMB=25ºC unless otherwise specified.
Figure 4. DCDC Efficiency vs. Load Current
Figure 5. Charge Pump: Efficiency vs. VBAT
90
90
80
70
60
50
40
30
2
85
80
75
70
65
60
Vout: 25V, L=NRH3012
Vout: 15V, L=NRH3012
ad=50mA
Iload=20mA
55
50
0
10
20
30
40
50
60
,8
3
3,2
3,4
3,
3,8
4
4,2
IOUT (mA)
VBAT [V
Figure 6. Charge Pump: Battery current vs. VBAT
ure 7. Current Sink URR1 vs. V(CURRx)
110
100
90
80
70
60
50
40
30
20
30
25
Code=255
20
Code=128
Code=32
15
10
5
Iloa50mA
10
ad=20mA
0
0
2,8
3
3,2
3,4 3,6
VBAT []
3,8
4
4,2
0
0,2 0,4 0,6 0,8
1
1,2 1,4 1,6 1,8
2
VCURR [V]
Figure 8. Current Sink RGB1 vsV(CURRx)
Figure 9. LDO Output Voltage VANA vs. Code
30
3,4
3,2
3
25
2,8
2,6
2,4
2,2
2
Code=255
20
15
10
5
Code=128
Code=32
1,8
1,6
0
0
5
10
15
20
25
30
0
0,2 0,4 0,6 0,8
1
1,2 1,4 1,6 1,8
2
VCURR [V]
binary code
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1v3-1
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AS3677
Datasheet - Typical Operating Characteristics
Figure 10. LDO Output Voltage VANA vs. Load
Figure 11. Charge Pump input and output ripple
2,81
1:2 Mode
2,8
50mA Load
2,79
0
1
2
3
4
5
6
7
8
9
10
ILOAD [mA]
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1v3-1
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AS3677
Datasheet - Detailed Description
8 Detailed Description
8.1
LDO
The LDO is a general purpose LDO and the output pin connected to VANA and intended to power an external light
sensor. Stability is guaranteed with ceramic output capacitors of 100nF ±20% (X5R).
The LDO is off by default after start-up.
Figure 12. LDO Block Diagram
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AS3677
Table 4. Electrical Characteristics
Symbol
ILOAD
Parameter
Output current
On Resistance
Dropout Voltage
Supply Current
Start-up Time
Condition
Min
Typ
10
Max
10
Unit
mA
Ω
0
RON
25
VDROPOUT
ION
250
mV
µA
µs
Without ad
VBAT > 3.0V
19
tstart
200
+3
Output Voltage
Tolerance
Vout_tol
VOUT
-3
%
1.8
1.8
2.75
3.35
V
V
Output Voltage
Full Programmable Range
8.1.1 LDO Registers
Table 5. Reg control Register
Reg control
Addr: 00
This register enables/disables the LDOs, Charge Pumps, Charge Pump LEDs,
current sinks, the Step Up DC/DC Converter, and low-power mode.
Bit
BiName
Default Access
Description
0
1
LDO is switched off
LDO is switched on
ldo_on
0
0
R/W
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AS3677
Datasheet - Detailed Description
Table 6. LDO Voltage Register
LDO Voltage
Addr: 07h
This register sets the output voltage (VANA) for the LDO.
Bit
Bit Name
Default Access
Description
Controls LDO voltage selection.
00000b
...
1.8V
LSB=50mV
3.35V
ldo_voltage
4:0
00000b
R/W
11111b
8.2
Step Up DC/DC Converter
The Step Up DC/DC Converter is a high-efficiency current mode PWM regulator, providing output voltage up to .g.
25V/50mA. A constant switching-frequency results in a low noise on the supply and output voltages.
Figure 13. Step Up DCDC Converter Internal Block Diagram
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AS3677
Table 7. Step Up DC/DC Converter Parameters
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IVDD
Quiescent Current
Pulse skipping mode.
200
µA
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AS3677
Datasheet - Detailed Description
Table 7. Step Up DC/DC Converter Parameters (Continued)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Feedback Voltage for
Current Sink
VFB
on CURR1, CURR2 or CURR6 in regulation.
0.4
0.5
0.6
V
Regulation
step_up_lowcur=0
step_up_lowcur=1
1200
750
600
330
0.42
ICOIL_MAX
Coil current limit
mA
step_up_lowcur=0
For fixed startup time of
500us
step_up_lowcur=1
RSW
ILOAD
fIN
Switch Resistance
Load Current
ON-resistance of external switching transistor.
At 25V output voltage
1.0
50
Ω
0
mA
Switching Frequency
Internally trimmed
0.9
1
1.1
Hz
Ceramic, ±20%. Use nominal 4.7µF capacitors
to obtain at least 0.7µF under all conditions
(voltage dependence of capacitors)
COUT
Output Capacitor
Inductor
0.7
7
4.
µF
µH
Use inductors with small Crsitic (<100pF) to
get high effiiency
L
10
13
tMIN_ON
Minimum on Time
Maximum Duty Cycle
Voltage ripple >20kHz
Voltage ripple <20kHz
Efficiency
90
90
140
190
ns
%
MDC
160
40
mV
mV
%
Vripple
Cout=4.7µF,Iout=0..4mA, VBAT=3.0..42V
Iout=0mAVout=17V,VBA.8V
Efficiency
85
To ensure soft startup of the dcdc converter, e over current limits ae reduced for a fixed time after enabling the dcdc
converter. The total startup time for an ouput voltage of e.g. 26V s less than 2ms.
8.2.1 Feedback Selection
Register DCDC control1 and DCDC control2 selects the of feedback for the Step Up DC/DC Converter.
The feedback for the DC/DC converter can be selcted to any of the current sinks (CURR1, CURR2, CURR6). If the
register bit step_up_fb_auto is set, the feedback ph is automatically selected between CURR1, CURR2 and CURR6
(the lowest voltage of these current sinks is sed)1. The Step Up DC/DC Converter is regulated such that the required
current at the feedback path can be supported
Note: Always choose the path with the est voltage drop as feedback to guarantee adequate supply for the other
(unregulated) paths or enble the register bit step_up_fb_auto.
8.2.2 Over voltage Protecion
The over voltage protectin is ontrolled by the register step_up_vmax (can be programmed to 10V, 16V or 25V) to
protect the external compoents (especially the output capacitor C1. If the voltage on the pin SW exceeds this voltage,
the DCDC is immdatedisabled and the register bit step_up_ov is set. To re-enable the DCDC set step_up_on=0
and afterwards stepup_on=1.
The voltage ring f the external components must be chosen to fit to the software setting of step_up_vmax2.
Noe: e vltage on CURR1, CURR2 and CURR6 must not exceed 26V (see page 20)
1. It is recommended to leave step_up_fb_auto=1 (default) all the times.
2. If the voltage is the DCDC overvoltage protection is chosen above the voltage ratings of the external com-
ponents, permanent damage might result.
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AS3677
Datasheet - Detailed Description
8.2.3 PCB Layout Hints
To ensure good EMC performance of the DCDC converter, keep its external power components C1, L1, D1 and C2
close together. Connect the ground of C1, C2 locally together and connect this with a short path to AS3677 VSS. This
ensures that local high-frequency currents will not flow to the battery.
8.2.4 Step up Registers
Table 8. Reg control Register
Reg control
Addr: 00
This register enables/disables the Charge Pump and the Step Up DC/DC
Converter.
Bit
Bit Name
Default Access
Description
Enable the step up converter
Disable the Step Up DC/DC Converter
Enable the Step Up DC/DC Coverter
step_up_on
0b
1b
3
0
R/W
Table 9. DCDC control1 Register
DDC control1
Addr: 21h
This rgister controls the Step Up DC/DC Converter.
Bit
Bit Name
Default Access
escription
Defines the clock equency of the Step Up DC/DC
Converter.
step_up_frequ
RW
R/W
0
0
0
1
1MHz
500kHz
Conols the feedback source if step_up_fb_auto = 0
0
01
no feedback selected - don’t use
CURR1 feedback enabled
(default)
step_up_fb
2:1
4:3
01
10
11
CURR2 feedback enabled
CURR6 feedback enabled
Overvoltage protection for the DCDC step up
00
01
10
11
16V
10V
step_up_vmax
00
R/W
25V
don’t use (15.5V)
Table 10. DCDC cntrolRegister
DCDC control2
Add: 22h
This register controls the Step Up DC/DC Converter and low-voltage current
sinks CURR3x.
Bit
Bit Name
Default Access
Description
Step Up DC/DC Converter output voltage at low loads,
when pulse skipping is active
skip_fast
1
0
R/W
0
1
Accurate output voltage, more ripple
Elevated output voltage, less ripple
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AS3677
Datasheet - Detailed Description
Table 10. DCDC control2 Register (Continued)
DCDC control2
Addr: 22h
This register controls the Step Up DC/DC Converter and low-voltage current
sinks CURR3x.
Bit
Bit Name
Default Access
Description
Step Up DC/DC Converter coil current limit
Normal current limit
step_up_lowcur
step_up_ov
3
1
0
R/W
R
0
1
Current limit reduced by approx. 33%
Step Up DC/DC overvoltage triggered
No overvoltage triggered
0
1
4
7
Overvoltage triggered; this bit is automatally
reset by step_up_on=0
step_up_fb select the feedack f the DCDC
converter
0
The feedback is automtcallchosen within the
current sinks CURR1, URR2 and CURR6
(ner DCDC_FB). Only thse are used for this
seection, which arenaled (currX_mode must
not be 00) and not connected to the charge
pup (currX_on_cp must be 0).
step_up_fb_auto
1
R/W
1
8.3
Charge Pump
The Charge Pump uses the external flying capacior Cto generate output volages higher than the battery voltage.
There are two different operating modes of the charge pump itself:
ꢀ
1:1 Bypass Mode
- Battery input and output are conneced by a low-impedancswitc
- battery current = output current.
ꢀ
1:2 Mode
- The output voltage is up to 2 times the battery voltithout load), but is limited to VCPOUTmax all the time
- battery current = 2 times output current
As the battery voltage decreases, the Charge Pummut be switched from 1:1 mode to 1:2 mode in order to provide
enough supply for the current sinks. Depening on the actual current the mode with best overall efficiency can be auto-
matically or manually selected:
The charge pump mode switching can e ne manually or automatically with the following possible software settings:
ꢀ
Automatic
- Start with 1:1 mode
- Switch up automatically to 1:2 mode
Manual
ꢀ
- Set modes 1:1 and 12 by software
The Charge Pumreques the external components listed in the following table:
Table 11. Charge Pmp External Components
Symbol
Parameter
Condition
Min
Typ
Max
Unit
External Flying
Capacitor
Ceramic low-ESR capacitor between pins
C1_P and C1_N
C4
470
nF
External Storage
Capacitor
Ceramic low-ESR capacitor between pins
CPOUT and VSS, pins CPOUT and VSS_CP
5
1.0
µF
Note: The connections of the external capacitors C4 and C5 should be kept as short as possible.
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AS3677
Datasheet - Detailed Description
The maximum voltage on the flying capacitor C4 is VBAT.
Table 12. Charge Pump Characteristics
Symbol
ICPOUT
VCPOUTmax
η
Parameter
Condition
Min
Typ
Max
50
Unit
mA
V
Output Current
Continuous
Depending on PCB layout
0.0
Output Voltage
Efficiency
Internally limited, Including output ripple
5.6
Including current sink loss;
ICPOUT < 50mA.
80
%
Power Consumption
without Load,
ICP1_2
1:2 Mode
2.15
mA
fclk = 1 MHz
Rcp1_1
Rcp1_2
Effective Charge
Pump Output
Resistance (Open
Loop, fclk = 1MHz)
1:1 Mode; VBAT = 3V
8.8
31
Ω
1:1.2 Mode; VBAT = 3V
Accuracy of Clock
Frequency
fclk Accuracy
currhv_switch
currlv_switch
-10
10
0.45
0.2
%
V
CURR1, 2, 6
minimum voltage
If the voltage drops belw this treshold, the
charge pump will use he nexavailable
mode
> 1:2)
RGB1-3 minimum
voltage
V
cp_stardebounce=0
240
µsec
µsec
CP automatic up-
switching debounce
time
tdeb
After switching on CP (cp_on set 1),
cpstart_debounce=1
2000
8.3.1 Charge Pump Mode Switchin
If automatic mode switching is enabled (c_moe_switching (see page 16) = 00 or cp_mode_switching = 01) the
charge pump monitors the current sinkwhih are connected ia a ed to the output CPOUT. To identify these current
sources (sinks), the registers CP moditch1 and CP mode Switch2 (register bits rgb1_on_cp … rgb3_on_cp,
curr1_on_cp, curr2_on_cp and curr6_on_cp) should be before starting the charge pump (cp_on (see page 16) =
1). If any of the voltage on these current sources drops bw the threshold (currlv_switch, currhv_switch), the next
higher mode is selected after the debounce time.
If the currX_on_cp=0 and the according curent sink is connected to the charge pump, the current sink will be func-
tional, but there is no up switching of the chae pump, if the voltage compliance is too low for the current sink to sup-
ply the specified current.
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AS3677
Datasheet - Detailed Description
Figure 14. Automatic Mode Switching
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AS3677
8.3.2 Soft Start
An implemented soft start mechnism reduces the inrush current. Battery current is smoothed when switching the
charge pump on and also at ech switching condition. This precaution reduces electromagnetic radiation significantly.
8.3.3 Unused Chare Pump
If the charge pump inot used, capacitors C4 and C5 (not C2) can be removed. The pins C1_P, C1_N and CPOUT
should be left open and keep register cp_on and cp_auto_on at 0 (default value).
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AS3677
Datasheet - Detailed Description
8.3.4 Charge Pump Registers
Table 13. Reg control Register
Reg control
This register controls the Charge Pump.
Default Access Description
Addr: 00h
Bit
Bit Name
Set Charge Pump into 1:1 mode (off state) unless
0
cp_auto_on is set
cp_on
2
0
R/W
1
Enable manual or automatic mode switching
Table 14. CP control Register
CP control
Addr: 23h
This register enables/disables the Charge Pump and the Step Up DC/DC
Converter.
Bit
Bit Name
Default Access
Description
Clock frequency sectio.
1 MHz
cp_clk
0
0
R/W
R/W
0
1
500 kz
rge Pump mode manual mode sets this mode, in
automatic mode reprts the actual mode used)
00
1:1 mode
cp_mode
2:1
4:3
00b
01
10
1:2 mode
11
Set the mode switching algorithm
Automatic Mode switching
01
cp_mode_switching
00b
R/W
10
Manual Mode switching; register cp_mode defines
the actual charge pump mode used
11
0
1
0
Mode switching debounce timer is always 240µs
Upon startup (cp_on set to 1) the mode switching
debounce time is first started with 2ms then
reduced to 240µs
cp_start_debounce
cp_auto_on
5
6
1
R/W
R/W
Charge Pump is switched on/off with cp_on
Charge Pump is automatically switched on if a
current sink, which is connected to the charge
pump (defined by registers CP Mode Switch 1 & 2)
is switched on
1
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AS3677
Datasheet - Detailed Description
Table 15. CP mode Switch1 Register
CP mode Switch1
Setup which current sinks are connected (via leds) to the charge pump; if set to
‘1’ the correspond current source (sink) is used for automatic mode selection of
the charge pump
Addr: 24h
Bit
Bit Name
Default Access
Description
current Sink RGB1 is not connected to charge
pump
0
1
0
1
0
1
rgb1_on_cp
4
1
1
1
R/W
R/W
R/W
current sink RGB1 is connected to charge pump
current Sink RGB2 is not connected to charge
pump
rgb2_on_cp
rgb3_on_cp
5
6
current sink RGB2 is connected to charge ump
current Sink RGB3 is not connected to charge
pump
current sink RGB3 is connected o chrge pump
Table 16. CP mode Switch2 Register
CP mode Switch2
Setup which currens are connected via LEDs) to the charge pump; if set
to ‘1’ the correspond rent source (sink) used for automatic mode selection
of the charge pump
Addr: 25h
Bit
Bit Name
Default Access
Description
cuSink CURR1is not connected to charge
pump
0
1
0
0
1
curr1_on_cp
0
0
0
0
R/W
R/W
RW
curent sink CURR1 is connected to charge pump
current Sink CURR2 is not connected to charge
pump
curr2_on_cp
curr6_on_cp
1
7
current sink CURR2 is connected to charge pump
current Sink CURR6 is not connected to charge
pump
current sink CURR6 is connected to charge pump
Table 17. Curr low voltage status1 Registe
Curr low voltage status1
Indicates the low voltage status of the current sinks. If the currX_low_v bit is
set, the voltage on the current sink is too low, to drive the selected output
current
Addr: 2Ah
Bit
BiName
Default Access
Description
0
1
0
1
0
1
0
1
voltage of current Sink RGB1 >currlv_switch
voltage of current Sink RGB1 <currlv_switch
voltage of current Sink RGB2 >currlv_switch
voltage of current Sink RGB2 <currlv_switch
voltage of current Sink RGB3 >currlv_switch
voltage of current Sink RGB31 <currlv_switch
voltage of current Sink CURR6 >currlv_switch
voltage of current Sink CURR6 <currlv_switch
rgb_low_v
rgb2_low_v
rgb3_low_v
curr6_low_v
4
NA
NA
NA
NA
R
R
R
R
5
6
7
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AS3677
Datasheet - Detailed Description
Table 18. Curr low voltage status2 Register
Curr low voltage status2
Indicates the low voltage status of the current sinks. If the currX_low_v bit is
set, the voltage on the current sink is too low, to drive the selected output
current
Addr: 2Bh
Bit
Bit Name
Default Access
Description
0
1
0
1
voltage of current Sink CURR1 >currhv_switch
voltage of current Sink CURR1 <currhv_switch
voltage of current Sink CURR2 >currhv_switch
voltage of current Sink CURR2 <currhv_swith
curr1_low_v
curr2_low_v
0
NA
NA
R
R
1
8.4
Current Sinks
The AS3677 contains three general purpose current sinks intended to control backlight LEDs.
CURR1, CURR2 and CURR6 are used as feedback for the Step Up DC/DC Converter (regulated to 0.5V n this config-
uration) see Feedback Selection on page 11.
Table 19. Current Sink Function Overview
Max.
Current
(mA)
Resolutin
Max.
Voltage (V)
Software Current
Control
Hardware On/Off
Control
Current Sink
(Bits
mA)
RGB1
RGB2
RGB3
Internal PWM; external
PWM at DLS1, Pattern
generator
5.5
25.5
8
8
0.1
Separate
Internal PWM; external
PWM at DLS1, Pattern
generator
CURR1
CURR2
CURR6
26.0
5.5
0.1
Separate
Internal PWM; external
PWM at DLS1 or
DLS2, Pattern
generator
The processing inside the AS3677 is shown iFigure 15 (shown for one current source only):
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AS3677
Datasheet - Detailed Description
Figure 15. Internal processing of the different signals
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8.4.1 Unused Current Sinks
Unused current sinks can be left open or used as ADC nputs (see Analog-to-Digital Converter on page 50).
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AS3677
Datasheet - Detailed Description
8.4.2 High Voltage Current Sinks CURR1, CURR2, CURR6
The high voltage current sinks have a resolution of 8 bits.
Table 20. HV Current Sinks Characteristics
Symbol
IBIT7
Parameter
Condition
Min
Typ
12.8
6.4
3.2
1.6
0.8
0.4
0.2
0.1
Max
Unit
Current sink if Bit7 = 1
Current sink if Bit6 = 1
Current sink if Bit5 = 1
Current sink if Bit4 = 1
Current sink if Bit3 = 1
Current sink if Bit2 = 1
Current sink if Bit1 = 1
Current sink if Bit0 = 1
matching Accuracy
absolute Accuracy
IBIT6
IBIT5
IBIT4
For V(CURRx) > 0.45V
mA
IBIT3
IBIT2
IBIT1
IBIT0
Δm
-7
7
+15
25
%
%
V
Δ
-15
CURR1,CURR2,CURR6
VCURR1,2,6x
IQCURR1,2,6
Voltage compliance
Quiescent current
0.45
165
µA
High Voltage Current Sinks CURR1, CURR2, CURR6 egisters
Table 21. Curr1 current Register
1 current
This register cons thHigh voltage current sink current.
Addr: 09h
Bit
Bit Name
Deault Access
Description
Defines current into current sink curr1
0h
01h
....
0 mA
0.1 mA
....
curr1_current
7:0
0
R/W
FFh
25.5 mA
Table 22. Curr2 current Register
Curr2 current
Addr: 0Ah
This register controls the High voltage current sink current.
Bit
Bit Nme
Default Access
Description
Defines current into current sink curr2
00h
01h
....
0 mA
0.1 mA
....
crr2_current
7:0
0
R/W
FFh
25.5 mA
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AS3677
Datasheet - Detailed Description
Table 23. Curr6 current Register
Curr6 current
Addr: 2Fh
This register controls the High voltage current sink current.
Bit
Bit Name
Default Access
Description
Defines current into current sink CURR6
00h
01h
....
0 mA
0.1 mA
....
curr6_current
7:0
0
R/W
FFh
25.5 mA
Table 24. curr12 control Register
curr12 control
Addr: 01h
This register select the mode of the current sinks controls Hih voage current
sink current.
Bit
Bit Name
Default Access
Descriptio
Selethe mode of the current sink curr1
00b
1b
10b
11b
off
curr1_mode
on
PWM controlled
1:0
0
0
R/W
R/W
LED pattern controlled
Selthmode of the current sink curr2
off
00b
1b
10b
11b
curr2_mode
on
3:2
PWM controlled
LED pattern controlled
Table 25. curr rgb control Register
curr rgb control
Addr: 02h
This register select the mode of the current sinks CURR6.
Bit
Bit Name
Default Access
Description
Select the mode of the current sink CURR6
00b
01b
10b
11b
off
on
curr6_mde
7:6
0
R/W
PWM controlled
LED pattern controlled
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AS3677
Datasheet - Detailed Description
8.4.3 Current Sinks RGB1, RGB2, RGB3
These current sinks have a resolution of 8 bits and can sink up to 25.5mA.
Table 26. Current Sinks RGB1, RGB2, RGB3 Parameters
Symbol
IBIT7
IBIT6
IBIT5
IBIT4
IBIT3
IBIT2
IBIT1
IBIT0
Δm
Parameter
Condition
Min
Typ
12.8
6.4
3.2
1.6
0.8
0.4
0.2
0.1
Max
Unit
Current sink if Bit7 = 1
Current sink if Bit6 = 1
Current sink if Bit5 = 1
Current sink if Bit4 = 1
Current sink if Bit3 = 1
Current sink if Bit2 = 1
Current sink if Bit1 = 1
Current sink if Bit0 = 1
matching Accuracy
For V(RGBx) > 0.2V
mA
-10
-15
+0
+15
%
%
Δ
absolute Accuracy
RGB1, RGB2, RG3
CPO
UT
VRGBX
Voltage compliance
Quiescent current
0.2
V
IQRGB1,2,3
165
µA
RGB Current Sinks Registers
Table 27. curr rgb control Register
cr rb control
Thiregister select the moe of the current sinks RGB1, RGB2, RGB3
Addr: 02h
Bit
Bit Name
efalt Access
Description
Select the mode of the current sink RGB1
00b
01b
10b
11b
off
rgb1_mode
1:0
0
0
0
/W
R/W
R/W
on
PWM controlled
LED pattern controlled
Select the mode of the current sink RGB2
00b
01b
10b
11b
off
rgb2_mode
rgb3_mode
3:2
5:4
on
PWM controlled
LED pattern controlled
Select the mode of the current sink RGB3
off
00b
01b
10b
11b
on
PWM controlled
LED pattern controlled
www.austriamicrosystems.com/AS3677
1v3-1
22 - 67
AS3677
Datasheet - Detailed Description
Table 28. Rgb1 current Register
Rgb1 current
Addr: 0Bh
This register controls the RGB current sink current.
Bit
Bit Name
Default Access
Description
Defines current into Current sink RGB1
00h
01h
....
0 mA
0.1 mA
....
rgb1_current
7:0
0
R/W
FFh
25.5 mA
Table 29. Rgb2 current Register
Rgb2 current
Addr: 0Ch
This register controls the RGB current sink curent.
Bit
Bit Name
Default Access
Description
Dfes current into Currensink RGB2
00h
....
0 A
0.1 mA
....
rgb2_current
7:0
0
R/W
FFh
25.5 mA
Table 30. Rgb3 current Register
Rgb3 current
Addr: 0Dh
This regier controls the RGB current sink current.
Bit
Bit Name
efault Access
Description
Defines current into Current sink RGB3
00h
01h
....
0 mA
0.1 mA
....
rgb3_current
7:0
0
R/W
FFh
25.5 mA
8.4.4 LED Pattern Geneato
The LED pattern generator icapble of producing a pattern with 32 bits length and 1 second duration (31.25ms for
each bit). The pattern itsecan be started every second, every 2nd, 3rd up to 7th second3.
With this pattern l urrnt sinks can be controlled. The pattern itself switches the configured current sources between
0 and their programed current.
If everything se is switched off, the current consumption in this mode is IACTIVE. (excluding current through switched
on current source) and the charge pump, if required. The charge pump can be automatically switched on/off depending
on he pern (set register cp_auto_on on page 16=1) to reduce the overall current consumption.
3. All times can be extended by a factor of 8 by setting pattern_slow=1 (this result in a delay of up to 56s)
www.austriamicrosystems.com/AS3677
1v3-1
23 - 67
AS3677
Datasheet - Detailed Description
Figure 16. LED Pattern Generator AS3677 for pattern_color = 0
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To select the different current sinks to be controlled by the LED pattern generator, see the ‘xxxx’_mode registers
(where ‘xxxx’ stands for the to be controlled current sink, e.g. curr1_mode for CURR1 current sink). See also the
description of the different current sinks.
To allow the generator of a color patterns set the bit pattern_color to ‘1’. Then the pattern can be connected to CURRx
as follows:
Figure 17. LED Pattern Generator AS3677 for pattern_color = 1
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-ꢖꢙꢒ'ꢗꢒꢕꢘꢜ+ꢖꢏꢏ&
Only those current sinks will be controd, where the ‘xode register is configured for LED pattern.
If the register bit pattern_slow is set, all pattern times are increased by a factor of eight. (bit duration: 250ms if
pattern_color=0 / 800ms if pattern_color=1, delays between pattern up to 56s).
Soft Dimming for Pattern
The internal pattern generator can be comined with the internal pwm dimming modulator to obtain as shown in the fol-
lowing figure:
Figure 18. Soft dimming Architecre fr the AS3677 (softdim_pattern=1 and pattern_color = 1)
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www.austriamicrosystems.com/AS3677
1v3-1
24 - 67
AS3677
Datasheet - Detailed Description
With the AS3677 smooth fade-in and fade-out effects can be automatically generated.
As there is only one dimming ramp generator and one pwm modulator following constraints have to be considered
when setting up the pattern (applies only if pattern_color=1):
Figure 19. Soft dimming example Waveform for CURR30-32
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ꢀꢁꢂꢂ
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ꢇꢆꢄꢍꢇꢎꢎꢇꢂꢏꢄꢐꢅ
However using the identical dimming waveform for two chs is possible as shown in the following figure:
Figure 20. Soft dimming example Waveform for CURR30-3
ꢀꢁ
ꢂꢃꢄꢅ
ꢀꢁ
ꢂꢃꢄꢆ
ꢂꢃꢄꢇ
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LED Pattern Registers
Table 31. Pattern data0...Pattern data3 Registers
Pattern data0, Pattern data1, Pattern data2, Pattern data3
Addr: 19h,1Ah,1Bh,1Ch
This registers contains the pattern data for the current sinks.
Bit
Bit Name
Default Access
Description
pattern_data_01
7:0
0
0
R/W
R/W
Pattern data0
7:0
Pattern data1
pattern_ata_
pater_daa_2
patern_data_3
7:0
7:0
0
0
R/W
R/W
Pattern data2
Pattern data3
1. Update any f the pattern register only if none of the current sources is connected to the pattern generator
('xxxxode must not be 11b). The pattern generator is automatically started at the same time when any of the
currensources is connected to the pattern generator
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1v3-1
25 - 67
AS3677
Datasheet - Detailed Description
Table 32. Pattern control Register
Pattern control
Addr: 18h
This register controls the LED pattern
Description
Bit
Bit Name
Default Access
Defines the pattern type for the current sinks
0b
1b
single 32 bit pattern (also set currX_mode = 11)
pattern_color
0
0
R/W
R/W
R/W
RGB pattern with each 10 bits (set all
currX_mode = 11)
Delay between pattern, details (see Table 35); together wit
pattern_delay2 sets the delay time between pattern
pattern_delay
2:1
3
00b
0b
Enable the ‘soft’ dimming feature for the pattern genrato
Pattern generator directly control curret
softdim_pattern
0
sources
1
‘Soft Dimming’ is performed (see page 24)
Table 33. Gpio current Register
Addr: 2Ch
pio current
Description
Bit
Bit Name
Default Access
Day between pattern (se Table 35 on page 26); together
th pattern_delay sts the delay time between patterns
pattern_delay2
4
0
R/W
attern timing control
0b
1b
normal mode
pattern_slow
6
0
R/W
slow mode (all pattern times are increased by a
factor of eight)
Table 34. Pattern End Register
Addr: 54h
Pattern End
Description
Bit
Bit Name
Default Aces
pattern_end is toggled from 0 to 1 (or from 1 to 0) at each
end of the pattern just before restarting of the internal
pattern generator at the first bit of the pattern data
(can be used to synchronize the baseband software to the
pattern_end
0
R
pattern generator)1
1. pattern_end toggles whenevthe AS3677 is in active mode (see Section 8.11 Operating Modes on page 58)
even if no pattern data has been setup.
Table 35. LED Pttrn ming
pattrn_delay2 pattern_delay[1..0]
bit duration [ms]
pattern
duration [s]
(total cycle
time:
pattern +
delay)
delay[s]
between
patterns
pattern_slow
delay between patterns
pattern_color=0 pattern_color=1
01
1
0
0
00
31
100
1
0
0
0
0
0
0
01
10
11
31
31
31
100
100
100
2
3
4
2
3
www.austriamicrosystems.com/AS3677
1v3-1
26 - 67
AS3677
Datasheet - Detailed Description
Table 35. LED Pattern timing
pattern_delay2 pattern_delay[1..0]
bit duration [ms]
pattern
duration [s]
(total cycle
time:
pattern +
delay)
delay[s]
between
patterns
pattern_slow
delay between patterns
pattern_color=0 pattern_color=1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
00
01
10
11
31
31
100
100
100
100
800
800
800
800
800
800
800
00
4
5
5
6
31
6
7
31
7
8
250
250
250
250
250
50
250
250
0
8
8
1
24
32
40
48
56
64
16
24
3
40
48
56
1. Even by setting 000 for pattern delay, there is a small delay before the new patrns starts.
8.4.5 PWM Generator
The PWM generator can be used for any cuent snk. The setting plies for all current sinks, which are controlled by
the pwm generator (e.g. CURR1 is pwm ontroed if curr1_mod= 10The pwm modulated signal can switch on/off
the current sinks and therefore dependng oits duty cycle chnge he brightness of an attached LED.
Internal PWM Generator
The internal PWM generator uses the 2MHz internal clocinput frequency and its dimming range is 6 bits digital
(2MHz / 2^6 = 31.3kHz pwm frequency) and 2 bits nalog. Depending on the actual code in the register pwm_code the
following algorithm is used:
If pwm_code bit 7 = 1
Then the upper 6 bits (Bits 7:2) of pwmcoe are used for the 6 bits PWM generation, which controls the selected cur-
rents sinks directly
If pwm_code bit 7 =0 and bit 6 = 1
Then bits 6:1 of pwm_code are sed for the 6 bits PWM generation. This signal controls the selected current sinks, but
the analog current of these sks is divided by 2
If pwm_code bit 7 and bi6 = 0
Then bits 5:0 of p_coe are used for the 6 bits PWM generation. This signal controls the selected current sinks, but
the analog current of hese sinks is divided by 4
www.austriamicrosystems.com/AS3677
1v3-1
27 - 67
AS3677
Datasheet - Detailed Description
Figure 21. PWM Control
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ꢏ
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ꢉꢉꢐꢑꢒꢉꢓꢔꢕ
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ꢉꢉꢐꢑꢒꢉꢓꢔꢕ
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ꢀꢁꢂꢃꢄꢅꢆꢇ
Automatic Up/Down Dimming
If the register pwm_dim_mode is set to 01 (up dimming) or 10 (down dimming) the value within the reister pwm_code
is increased (up dimming) or decreased (down dimming) every time and amount (either 1/4th or 1/8th) dined by the
register pwm_dim_speed. The maximum value of 255 (completely on) and the minimum value of 0 (o) is never
exceeded. It is used to smoothly and automatically dim the brightnes of the LEDs connecteo anof the current
sinks. The PWM code is readable all the time (also during up andowdimming).
The waveform for up dimming looks as follows (cycles omitted fosimplcity):
Figure 22. PWM Dimming Waveform for up dimming (pwm_ode = 01); cur_mode = PWM controlled (not
all steps shown)
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ꢂꢄꢅꢆꢂꢃꢄꢄꢇꢈꢁ
ꢀꢉꢊ
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ꢒꢓꢓꢔꢌꢕꢃꢁꢖꢌꢂꢖ
The internal pwm modulator circuit controls the currnt sinks as shown in the following figure:
Figure 23. PWM Control Circuit (currX_mode 10b (PWM controlled)); X = any current sink
ꢕꢀꢀꢋꢆꢗ(ꢅ! ꢈ
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ꢓꢌꢄꢋꢆ%ꢃꢈꢋ
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ꢒ !
!"ꢀꢁꢂꢃꢄꢅꢆ
ꢎꢘꢙꢚ
+
,
AS3677
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ꢜꢃꢒꢐ
"ꢋꢌ
ꢕ()
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ꢃꢀꢀꢋꢆꢊꢈꢁꢆꢆꢋꢌꢄꢉ
The adder logic (available for all current sinks) is intended to allow dimming not only from 0% to 100% (or 100% to 0%)
of currX_current, but also e.g. from 10% to 110% (or 110% to 10%) of currX_current. The starting current for up dim-
ming is defined by 0 + currX_adder and the end current is defined by currX_current + currX_adder.
www.austriamicrosystems.com/AS3677
1v3-1
28 - 67
AS3677
Datasheet - Detailed Description
An overflow of the internal bus (8 Bits wide to the IDAC) has to be avoided by the register settings (currX_current +
currX_adder must not exceed 255).
Note: The adder logic operates independent of the currX_mode setting, but its main purpose is to work together with
the pwm modulator (improved up/down dimming)
If the adder logic is not used anymore, set the bit currX_adder to 0. (Setting adder_currentX to 0 is not suffi-
cient)
At the end of up/down dimming, the pwm_code register keeps its final value (for up-dimming 255 and for down-
dimming 0). This can be used to identify the exact time, when up/down dimming is finished.
Table 36. PWM Dimming Table
Decrease by 1/4th
every step
Decrease by 1/8th
every step
Seconds
Seconds
Seconds
Seconds
50msec/
Step
25msec/
Step
5msec/
Step
2.5msec/
Step
Step
%Dimming
PWM
%Dimming
PWM
1
100,0
75,3
56,5
42,4
31,8
23,9
18,0
13,7
10,6
8,2
255
192
144
108
81
61
46
35
27
21
16
12
9
100,0
87,8
76,9
67,5
59,2
52,2
45,9
40,4
35,7
31,
27,5
24,3
21,6
19,2
6,9
14,9
13,3
11,8
10,6
9,4
255
224
196
172
13
117
103
91
0,00s
0,05s
010s
0,5s
0,20s
0,25s
0,30s
0,
0,s
,5s
0,50s
0,55s
0,60s
0,65s
0,70s
0,75s
0,80s
0,85s
0,90s
0,95s
1,00s
1,05s
1,10s
1,15s
1,20s
1,25s
1,30s
1,35s
1,40s
0,00s
0,03s
0,05s
0,08s
0,10s
13s
0,15s
0,18s
0,20s
0,23s
0,25s
0,28s
0,30s
0,33s
0,35s
0,38s
0,40s
0,43s
0,45s
0,48s
0,50s
0,53s
0,55s
0,58s
0,60s
0,63s
0,65s
0,68s
0,70s
0,00s
0005s
0,010s
0,015s
0,020s
0,025s
0,030s
0,035s
0,040s
0,045s
0,050s
0,055s
0,060s
0,065s
0,070s
0,075s
0,080s
0,085s
0,090s
0,095s
0,100s
0,105s
0,110s
0,115s
0,120s
0,125s
0,130s
0,135s
0,140s
0,000s
0,003s
0,005s
0,008s
0,010s
0,013s
0,015s
0,018s
0,020s
0,023s
0,025s
0,028s
0,030s
0,033s
0,035s
0,038s
0,040s
0,043s
0,045s
0,048s
0,050s
0,053s
0,055s
0,058s
0,060s
0,063s
0,065s
0,068s
0,070s
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2
27
28
29
80
6,3
70
4,7
3,5
5
2,7
7
49
2,4
6
43
2,0
5
38
1,6
4
34
1,2
3
30
0,8
27
0,4
1
24
00
0
8,2
21
7,5
19
6,7
17
5,9
15
5,5
14
5,1
13
4,7
12
4,3
11
3,9
10
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AS3677
Datasheet - Detailed Description
Table 36. PWM Dimming Table
Decrease by 1/4th
every step
Decrease by 1/8th
every step
Seconds
Seconds
Seconds
Seconds
50msec/
Step
25msec/
Step
5msec/
Step
2.5msec/
Step
Step
%Dimming
PWM
%Dimming
PWM
30
31
32
33
34
35
36
37
38
39
3,5
3,1
2,7
2,4
2,0
1,6
1,2
0,8
0,4
0,0
9
8
7
6
5
4
3
2
1
0
1,45s
1,50s
1,55s
1,60s
1,65s
1,70s
1,75s
1,80s
1,85s
1,90s
0,73s
0,75s
0,78s
0,80s
0,83s
0,85s
0,88s
0,90s
0,93s
0,95s
0,145s
0,150s
0,155s
0,160s
0,165s
0,170s
0,175s
0,80s
0185s
0,19s
0,073s
0,075s
0,078s
0,080s
0,08s
0,085s
0,088s
0,090s
0,093s
0,095s
PWM Generator Registers
Table 37. Pwm control Register
Pwm conrol
Addr: 16h
This register contros PWM generator
Description
Bit
Bit Name
Defaut Access
Selects the dimming mode
no dimming; actual content of register
pwm_code is used for pwm generator
0b
1b
logarithmic up dimming (codes are increased).
Start value is actual pwm_code
pwm_dim_mode
2:1
00b
R/W
logarithmic down dimming (codes are
decreased). Start value is actual pwm_code;
switch off the dimmed current source after
dimming is finished to avoid unnecessary
quiescent current
10b
11b
NA
Defines dimming speed by increase/decrease pwm_code
by 1/4th every 50 msec (total dim time 1.0s)
000b
by 1/8th every 50 msec (total dim time 1.9s)
001b
by 1/4th every 25 msec (total dim time 0.5s)
010b
by 1/8th every 25 msec (total dim time 0.95s)
011b
pwm_dim_speed
5:3
000b
R/W
by 1/4th every 5 msec (total dim time 100ms)
100b
by 1/8th every 5 msec (total dim time 190ms)
101b
by 1/4th every 2.5 msec (total dim time 50ms)
110b
by 1/8th every 2.5 msec (total dim time 95ms)
111b
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Datasheet - Detailed Description
Table 38. Pwm code Register
Pwm code
This register controls the Pwm code.
Description
Addr: 17h
Bit
Bit Name
Default Access
Selects the PWM code
00h
....
0% duty cycle
....
pwm_code
7:0
00b
R/W
FFh
100% duty cycle
Table 39. Adder Current 1 Register
Adder Current 1
Addr: 30h
This register defines the current which can be added to CUR1, CURR30,
CURR41, RGB1
Bit
Bit Name
Default Access
Description
Selectthe added current value – o not exceed together
wih curXcurrent the internal 8 Brange (see text)
00h
0 (reresents 0mA)
....
adder_current1
7:0
00b
R/W
FFh
255 epresents 25.5mA)
Table 40. Adder Current 2 Register
Aer Current 2
Addr: 31h
his rgister defines the currnwhich can be added to CURR2, CURR31,
CURR42, RGB2
Bit
Bit Name
fault Access
Description
ects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
00h
....
0 (represents 0mA)
....
adder_current2
7:0
00b
R/W
FFh
255 (represents 25.5mA)
Table 41. Adder Current 3 Regist
Adder Current 3
Addr: 32h
This register defines the current which can be added to CURR6, CURR32,
CURR43, RGB3
Bit
Bit Nme
Default Access
Description
Selects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
00h
....
0 (represents 0mA)
....
adder_current3
7:0
00b
R/W
FFh
255 (represents 25.5mA)
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Datasheet - Detailed Description
Table 42. Adder Enable 2 Register
Adder Enable 2
Addr: 34h
Enables the adder circuit for the selected current sources
Bit
Bit Name
Default Access
Description
Enables adder circuit for current source CURR1
Normal Operation of the current source
0
1
curr1_adder
0
0
0
0
R/W
R/W
R/W
adder_current1 gets added to the current
source current; if curr1_amb_group is not 00,
the adder current is multiplied by the ALS group
selected by curr1_amb_group
Enables adder circuit for current source CURR2
Normal Operation of the current sourc
0
1
curr2_adder
curr6_adder
1
2
adder_current2 gets added the current
source current; if curr2_am_grup is not 00,
the adder current is multiplied y the ALS group
selected by curr2_mb_roup
nableadder circuit for currensource CURR6
Normal Operaion the current source
0
1
adder_urrent3 gets added to the current
source cunt; if curr6_amb_group is not 00,
the adder curret is multiplied by the ALS group
sected by curr6_amb_group
Table 43. Adder Enable 1 Register
Adder Enable 1
Addr: 33h
Enables the addr circuit for the selected current sources
Bit
Bit Name
fault Access
Description
Enables adder circuit for current source RGB1
Normal Operation of the current source
0
1
rgb1_adder
0
0
0
R/W
R/W
R/W
adder_current1 gets added to the current
source current
Enables adder circuit for current source RGB2
Normal Operation of the current source
0
1
rgb2_adder
rgb_adder
1
2
adder_current2 gets added to the current
source current
Enables adder circuit for current source RGB3
Normal Operation of the current source
0
1
adder_current3 gets added to the current
source current
8.4.6 S - Ambient Light Sensing
Te ADC onverts every 1ms the ambient light sensor signal from pin ALS/GPIO14. This signal is pre-processed with
a ofet defined by amb_offset and a gain defined by amb_gain (1/4, 1/2, 1, 2). Then it is low-pass filtered with a pro-
grammable cut-off frequency going from 0.25Hz to 32Hz. Increasing signals and decreasing signal can have individual
cut-off frequencies adjustable from 0.25Hz to 32Hz (amb_filter_up and amb_filter_down).
This filtered signal can be readout from the register amb_result<7:0>.
4. adc_select=02h (select ALS/GPIO1 input)
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AS3677
Datasheet - Detailed Description
Each of the available three channels (N=1 or 2) has six 8-bit registers:
- groupN_y0: define current multiplier for values below groupN_X1
- groupN_y3: define current multiplier for high values (actual starting point defined by groupN_x1,groupN_k1 and
groupN_x2,groupN_k2)
- groupN_x1, groupN_k1: If ADC reading is > groupN_x1 then groupN_k1 divided by 32 defines the slope of the
first ramp
- groupN_x2, groupN_k2: If ADC reading is > groupN_x2 then groupN_k2 divided by 32 defines the slope of the
second ramp
Each current sources has a 2 bit register (currX_amb_group) to select None, Group1 or Group2 of ambient light sens-
ing.
The calculations are done every 1ms resulting in a flicker-free 1000Hz update rate of the current sources.
Note: The ADC is switched off between conversion to save power.
All groupN_k1 and groupN_k2 values are divided by 32 except group3_k1 (see page 39), which is dividby
1. This allows a step response to a small change in the input signal (e.g. for keyboard backliht).
Table 44. ALS Parameters
Symbol
Parameter
Condion
Min
Typ
Max
Unit
averaged; excluding LDsuppling external
sensor - see LDO n page 9
IALSON
ALS operating current
19
µA
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1v3-1
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AS3677
Datasheet - Detailed Description
Figure 24. Ambient Light Sensor and Interrupt Logic internal circuit
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AS3677
Ambient Light Sensor Registers
Table 45. ALS control Regiter
ALS control
Addr: 9h
control ambient light sensing
Bit
Bit Name
Default Access
Description
Enables the ambient light sensing feature
ambient light sensor disabled
amb_on
0
0
R/W
0
1
ambient light sensor enabled
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1v3-1
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AS3677
Datasheet - Detailed Description
Table 45. ALS control Register (Continued)
ALS control
Addr: 90h
control ambient light sensing
Description
Bit
Bit Name
Default Access
Control Ambient Light Sensor preprocessing gain
00
gain = 1/4
gain = 1/2
gain = 1
amb_gain
2:1
0
0
R/W
R/W
01
10
11
gain = 2
Enable S/H of group tables output - see Figure 24 on
page 34
amb_keep
3
0
1
Group output is enabled (S/= sampling)
Groups outputs on hold S/H hold)
Table 46. ALS filter Register
ALS filter
Addr: 91h
ontrol for ambient light sensor filtering
escription
Bit
Bit Name
Default Access
ontrols the filtecuoff (-3dB) frequency (increasing)
000
001
010
11
100
101
110
111
0.25Hz
0.5Hz
1Hz
amb_filter_up
2:0
00
R/W
2Hz
4Hz
8Hz
16Hz
32Hz
Controls the filter cut off (-3dB) frequency (decreasing)
000
001
010
011
100
101
110
111
0.25Hz
0.5Hz
1Hz
amb_filte_don
6:4
000
R/W
2Hz
4Hz
8Hz
16Hz
32Hz
Tabe 47. ALS offset Register
Addr: 92h
ALS offset
Description
Controls the offset of the ambient light sensor
Bit
Bit Name
Default Access
00h R/W
amb_offset
7:0
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AS3677
Datasheet - Detailed Description
Table 48. ALS result Register
Addr: 93h
ALS result
Description
Bit
Bit Name
Default Access
R
Filtered result of the ambient light sensor value
amb_result
7:0
00h
W
Pre-set the value of the ALS filter (especially useful when
doing gain switching of the ALS sensor)
Table 49. ALS curr12 group Register
ALS curr12 group
Addr: 94h
controls the group mapping for CURR1 and CURR2
Bit
Bit Name
Default Access
Description
CURR1 is mapped to ambient light sensor grou
00
None - no ambient lighsenor control
curr1_amb_group
1:0
00
00
R/W
R/W
01
10
11
Group 1
Grp 2
Group 3
CURR2 is mapped to ambient light sensor group
0
None - o ambient light sensor control
curr2_amb_group
3:2
01
10
11
Group 1
Group 2
Group 3
Table 50. ALS rgb group Register
ALS rgb group
controls thp mapping for RGB1, RGB2, RGB3 and CURR6
Addr: 95h
Bit
Bit Name
Default Acess
Description
RGB1 is mapped to ambient light sensor group
00
None - no ambient light sensor control
rgb1_amb_group
1:0
00
00
R/W
R/W
R/W
01
10
11
Group 1
Group 2
Group 3
RGB2 is mapped to ambient light sensor group
00
None - no ambient light sensor control
rg_am_group
rgb3_amb_group
3:2
5:4
01
10
11
Group 1
Group 2
Group 3
RGB3 is mapped to ambient light sensor group
00
None - no ambient light sensor control
01
10
11
Group 1
Group 2
Group 3
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AS3677
Datasheet - Detailed Description
Table 50. ALS rgb group Register (Continued)
ALS rgb group
Addr: 95h
controls the group mapping for RGB1, RGB2, RGB3 and CURR6
Bit
Bit Name
Default Access
Description
CURR6 is mapped to ambient light sensor group
00
None - no ambient light sensor control
curr6_amb_group
7:6
00
R/W
01
10
11
Group 1
Group 2
Group 3
Group1
Table 51. ALS group 1 Y0 Register
Addr: 98h
ALS group 1 Y0
Bit
Bit Name
Default Access
00h R/W
Description
group1_y0
7:0
Goup 1 y0 value - divideby 256
Table 52. ALS group 1 Y3 Register
Addr: 99h
ALS group 1 Y3
Bit
Bit Name
Default Access
00h RW
escription
group1_y3
7:0
Gup 1 y3 value - divided by 256
Table 53. ALS group 1 X1 Register
Addr: 9Ah
ALS group 1 X1
Description
Bit
Bit Name
ault Access
00h R/W
group1_x1
7:0
Group 1 x1 value
Table 54. ALS group 1 K1 Register
Addr: 9Bh
ALS group 1 K1
Description
Bit
Bit Name
Deult Access
R/W
group1_k1
7:0
Group 1 k1 value - divided by 32 defines first slope
Table 55. ALS group 1 X2 Rester
Addr: 9Ch
ALS group 1 X2
Description
Bit
Bit Name
Default Access
00h R/W
roup_x2
7:0
Group 1 x2 value
Table 56. ALgrop 1 K2 Register
Addr: 9Dh
ALS group 1 K2
Description
Bit
Bit Name
Default Access
00h
group1_k2
7:
R/W Group 1 k2 value- value divided by 32 defines second slope
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AS3677
Datasheet - Detailed Description
Group2
Table 57. ALS group 2 Y0 Register
Addr: 9Eh
ALS group 2 Y0
Description
Bit
Bit Name
Default Access
00h R/W
group2_y0
7:0
Group 2 y0 value - divided by 256
Table 58. ALS group 2 Y3 Register
Addr: 9Fh
ALS group 2 Y3
Bit
Bit Name
Default Access
00h R/W
Description
group2_y3
7:0
Group 2 y3 value - divided by 256
Table 59. ALS group 2 X1 Register
Addr: A0h
ALS group 2 X1
Description
Bit
Bit Name
Default Access
00h R/W
group2_x1
7:0
Group 2 x1 vale
Table 60. ALS group 2 K1 Register
Addr: A1h
ALS group K1
Bit
Bit Name
Default Access
00h R/W
Desription
group2_k1
7:0
Group 2 k1 vale - divided by 32 defines first slope
Table 61. ALS group 2 X2 Register
Addr: A2h
LS group 2 X2
Description
Bit
Bit Name
efault Access
00h R/W
group2_x2
7:0
Group 2 x2 value
Table 62. ALS group 2 K2 Register
Addr: A3h
ALS group 2 K2
Description
Bit
Bit Name
DefaulAccess
group2_k2
7:0
0
R/W Group 2 k2 value- value divided by 32 defines second slope
Group3
Table 63. ALS group 3 Y0 Rgistr
Addr: A4h
ALS group 3 Y0
Bit
Bit Nme
Default Access
00h R/W
Description
group3_y0
7:0
Group 3 y0 value - divided by 256
Table 64LS group 3 Y3 Register
Addr: A5h
ALS group 3 Y3
B
Bit Name
Default Access
00h R/W
Description
group3_y3
7:0
Group 3 y3 value - divided by 256
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Table 65. ALS group 3 X1 Register
Addr: A6h
ALS group 3 X1
Description
Group 3 x1 value
Bit
Bit Name
Default Access
00h R/W
group3_x1
7:0
Table 66. ALS group 3 K1 Register
Addr: A7h
ALS group 3 K1
Bit
Bit Name
Default Access
00h R/W
Description
group3_k1
7:0
Group 3 k1 value - divided by 1 defines first slope
Table 67. ALS group 3 X2 Register
Addr: A8h
ALS group 3 X2
Description
Bit
Bit Name
Default Access
00h R/W
group3_x2
7:0
Group 3 x2 value
Table 68. ALS group 3 K2 Register
Addr: A9h
AS group 3 K2
Description
Bit
Bit Name
Default Access
00h
group3_k2
7:0
R/W Gup 3 k2 value- value diided by 32 defines second slope
The output of the group selection circuit (after the S/H rcuit) can be observed with following registers:
Table 69. ALS group output 1 Register
Addr: AAh
Bit Name
amb_group1
AS group output 1
Description
Bit
efault Access
00h
7:0
R
Ambient Light Sensor Group 1 output register
Table 70. ALS group output 2 Register
Addr: ABh
ALS group output 2
Bit
Bit Name
DefaulAccess
0
Description
amb_group2
7:0
R
Ambient Light Sensor Group 2 output register
Table 71. ALS group output 3 Reister
Addr: ACh
ALS group output 3
Bit
Bit Nme
Default Access
00h
Description
amb_group3
7:0
R
Ambient Light Sensor Group 3 output register
The range seection interrupt threshold and interrupt enable is defined by following registers amb_range_int_high and
amb_range_intlow:
Tble 72ALrange high interrupt threshold Register
Addr: ADh
Bit Name
ALS range high interrupt threshold
Description
Bit
Default Access
If the filter output amb_result >= amb_range_int_high then
an amb_too_high interrupt is asserted
amb_range_int_high
7:0
00h
R/W
If amb_range_int_high=0, the interrupt is disabled
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Table 73. ALS range low interrupt threshold Register
Addr: AEh
ALS range low interrupt threshold
Description
Bit
Bit Name
Default Access
00h R/W
If the filter output amb_result <= amb_range_int_low then
an amb_too_low interrupt is asserted
amb_range_int_low
7:0
If amb_range_int_low=0, the interrupt is disabled
The range selection generates an interrupt by pulling the pin INT low (if any of the register bit of Interrupt Status are
set, INT is pulled low(. When the register Interrupt Status is readout, the interrupt is automatically cleared:
Table 74. Interrupt Status Register
Addr: AFh
Bit Name
Interrupt Status
Description
Comparator for amb_result >= amb_rage_int_high
Bit
Default Access
R/sC1
0
amb_too_high
amb_too_low
0
0
1
not triggere
triggered
Cmpaar for amb_result <= ab_range_int_low
R/sC1
0
1
0
not riggered
triggered
1. Read - self clear. The register automatically clears it contet after readout. Thiavoids any lost interrupts.
8.4.7 DLS(=DBC) - Dynamic Luminance Scaling Input
The pins DLS1 and DLS2 can be used for dyamic backlight scalinnput. Dynamic backlight scaling is used to reduce
the power of the backlight especially wheshoing dark picture contets on the display. The control unit to operate
DLS is the display processor sending a PWsignal to the AS677 nd in parallel changing the display content to com-
pensate for a reduced brightness backt.
The AS3677 can use the DLS (Dynamic Luminance Scalso called DBC = Dynamic Backlight Control) in two dif-
ferent operating modes:
1. Digital DLS Mode - selected by dls_analog=0: The input signal from pins DLS1 and DLS2 are controlling the
current source directly. A logic ‘L’ sitches off the selected current source and a logic ‘H’ enables the current
source with the configured current. Ts operating mode is compatible to the AS3676 processing of DLS.
2. Analog DLS Mode - selected bdanalog=1: In this operating mode, the input signals form DLS1 and DLS2
are digitally filtered (two parallel s are possible!) and smoothly controls the current through the selected
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current source(s). Therefore the output signal does not show any PWM signal and therefore reduces the noise
in noise sensitive systems - especially if the connection to the LED used long wires.
Note: For any current source, do not use DLS and the internal PWM generator (see PWM Generator on page 27) at
the same time.
Table 75. DLS Input Parameters
Symbol
Parameter
Condition
Min
Typ
Max
Unit
pins DLS1 and DLS2 if
used for DLS (any bit set:
curr1_on_dls,
dls_analog=0
dls_analog=1
25
1000
kHz
DLS input frequency
range
fDLS
curr2_on_dls or
3001
250001
Hz
curr6_on_dls); pin DLS1 if
used for RGB1, RGB2 and
RGB3 (only ‘digital’ DLS)
DLS internal filter 3dB
cutoff frequency
fDLS_FILTER
VIHDLS
dls_analog=1, low pass filter 4th order
2
kHz
V
High Level Input
Voltage
1.38
-5
VAT
pins DLS1 and DLS2
to VBAT oVSS
Low Level Input
Voltage
VILDLS
ILEAK
0.52
5
V
Input Leakage Current
µA
1. For duty cycles >5%
Note: If using dls_analog=1, the minimum PWM ratio is limited by the LED erformance. If the analog current is
reduced too much, it might result in uneveness of the display bight as the LEDs are usually not specified
at very low current operation).
RGB1, RGB2 and RGB3 can only use digital’ DLS - the regiser dls_analog does have no influence.
The analog processing of the DLS sigal works as follows (dl_anaog=1):
1. The input signal from pins DLnd DLS2 are fento the digital filter. A logic ‘L’ is converted into ‘0.000’ and
a logic ‘H’ is converted into ‘1.000’.
2. The digital filter processes this signal. The ilter itself is implemented as a 4th order low pass filter with fixed
coefficients. Its 3dB cut-off frequency is seto fLS_FILTER.
3. The output signal (fixed comma biary 8 bit signal) is multiplied by the individual current setting.
4. From this 8 x 8 multiplication (16bit reult), the 8 MSBs are used.
This value is converted with a current DAC to a current, which controls the LED.
8.4.8 Unused DLS Input Pin
The pins DLS1 and DLS2 shoud be connected to VSS if not used.
8.4.9 DLS Internal Pcessing
The internal processinis sown in Figure 25:
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Figure 25. DLS (Dynamic Luminance Scaling) internal circuit shown for a single current sink
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Table 76. DLS me cotrol1 Register
DLS mode control1
ddr56h
Setup which current sinks are connected to the DLS; if set to '1' the
correspond current source (sink) is combined with the DLS input
Bit
Bit Name
Default Access
Description
0
RGB1 current sink is not combined with DLS
rgb1_on_dls
4
0
R/W
RGB1 current sink is combined with DLS (only
‘digital’ DLS with input pin DLS1)
11
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Table 76. DLS mode control1 Register (Continued)
DLS mode control1
Addr: 56h
Setup which current sinks are connected to the DLS; if set to '1' the
correspond current source (sink) is combined with the DLS input
Bit
Bit Name
Default Access
Description
0
RGB2 current sink is not combined with DLS
rgb2_on_dls1
5
0
0
0
R/W
R/W
R/W
RGB2 current sink is combined with DLS (only
‘digital’ DLS with input pin DLS1)
11
0
RGB3 current sink is not combined with DLS
rgb3_on_dls
dls_analog
6
7
RGB3 current sink is combined with DLS (nly
‘digital’ DLS with input pin DLS1)
11
0
‘digital’ DLS for all current sinks
‘analog’ DLS for CURR1, CURRand CURR6 if
enabled
1
1. When this bit is set, do not use the internal PWM generator for this current source at the sme tme.
Table 77. DLS mode control2 Register
DLS mode control2
Addr: 57h
Setup which cuent sinks are connecteto the DLS; if set to '1' the
correspond cuent source (sink) is combined with the DLS input
Bit
Bit Name
Default Acces
Description
0
RR1 current sink is not combined with DLS
curr1_on_dls
0
0
0
/W
R/W
11
0
CURR1 current sink is combined with DLS
CURR2 current sink is not combined with DLS
CURR2 current sink is combined with DLS
curr2_on_dls
1
11
0
CURR2 uses DLS1 as input
CURR2 uses DLS2 as input
curr2_dls2
curr6_dls2
5
6
0
0
/W
R/W
1
0
CURR6 uses DLS1 as input
1
CURR6 uses DLS2 as input
0
CURR6 current sink is not combined with DLS
curr6_on_dls
7
0
R/W
11
CURR6 current sink is combined with DLS
1. When this bit is set, do not ue the internal PWM generator for this current source at the same time.
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8.5
General Purpose Input / Output
The pin DLS1, DLS2 are digital input, INT is an open drain output and ALS/GPIO1, GPIO2 and GPIO3 are a highly-
configurable general purpose input/output pins which can be used for the following functionality:
ꢀ
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DLS1 and DLS2 primary function is a DLS input - see DLS(=DBC) - Dynamic Luminance Scaling Input on page 40
ALS/GPIO1 primary function is ALS input - see ALS - Ambient Light Sensing on page 32
Digital Schmitt Trigger Input
Digital Output with 4mA Driving Capability at 2.8V Supply (VANA)
Tristate Output
Analog Input to the ADC
Default Mode for ALS/GPIO1 is ADC input (as required for the ALS function), GPIO2 and GPIO3 is Input with Pull-
Down
Table 78. GPIO Pin Function Summary
GPIO3 Pin
Configuration
Additional Function
ADC Input, ALS - light senor input (see
page 32)
Digital Input, Totem-Pole Output (Push/Pull),
Open Drain (PMOS or NMOS), High-Z, Pull-
Down or Pull-Up Resistor
ALS/GPIO1
GPIO2, GPIO3
DLS1, DLS2
INT
ADC Inut
ADC Input, PWM InputDLS input (see page
40)
Digital Input
Open Drain Output
ADC Input
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Figure 26. GPIOs and VANA Blockdiagram
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8.5.1 Unused GPIO and digital Input Pins
If the pins ALS/GIO1, PIO2 or GPIO3 are not used, they can be left open (an internal pulldown, which is enabled by
default, will pull them to GND, ALS/GPIO1 is configured as ADC input). The pins DLS1 and DLS2 should be connected
to VSS, INT cn be left open.
8.5.2 GO and Digital Inputs Characteristics
Tble 79. GPIO and digital inputs DC Characteristics
Smbol
Rpull
Parameter
Condition
Min
30
Typ
Max
75
Unit
kΩ
V
Pull up/Pull down
Resistance
enabled by gpio1_pulls,
gpio2_pulls and gpio3_pulls
VGPIO
Supply Voltage
=VANA
1.8
3.35
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Table 79. GPIO and digital inputs DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
High Level Input
Voltage
VIHGPIO
1.38
VANA
V
pins ALS/GPIO1, GPIO2 and
GPIO3
Low Level Input
Voltage
VILGPIO
0.52
5
V
VHYS
ILEAK
Hysteresis
0.1
V
Input Leakage Current
to VANA or VSS
at Iout
-5
µA
High Level Output
Voltage
VOHGPIO
VOLGPIO
VOLINT
0.8·VANA
V
V
V
Low Level Output
Voltage
0.2·
VANA
Low Level Output
voltage
0.2
Pin INT at 4mA
VANA = 2.8V,
gpio1_low_curr or
gpio2_low_curr or
gpio3_low_curr=
4
IOUT
Driving Capability
Capacitive Load
mA
pF
VANA = 2.8V,
gpio1_low_curr or
gpio2_lowor
gpio3_low_= 0
101
CLOAD
50
1. Limited by LDO driving capability - see LDO on page 9
8.5.3 GPIO Registers
Table 80. GPIO output 2 Register
GPIO output 2
Addr: 50h
This register controls GPIO3 outputs.
Bit
Bit Name
Default Aces
Description
Writes a logic signal to pin ALS/GPIO1; this is independent
of any other bit setting e.g., gpio1_mode Table 82.
gpio1_out
0
0
0
R/W
R/W
R/W
Writes a logic signal to pin GPIO2; this is independent of
any other bit setting e.g., gpio2_mode Table 82
gpio2_out
gpio3_out
1
2
Writes a logic signal to pin GPIO3; this is independent of
any other bit setting e.g., gpio3_mode Table 83
Table 81. GPIO signal 2 egister
GPIO signal 2
This register controls GPIO3 outputs.
Description
Addr: 1h
Bit
Bit Name
Default Access
Reads a logic signal from pin ALS/GPIO1; this is
independent of any other setting e.g.,Table 82 except
gpio1_pulls=11
gpio1_in
0
N/A
R
Reads a logic signal from pin GPIO2; this is independent of
any other setting e.g.,Table 82 except gpio2_pulls=11
gpio2_ in
gpio3_ in
1
2
N/A
N/A
R
R
Reads a logic signal from pin GPIO3; this is independent of
any other setting e.g.,Table 83 except gpio3_pulls=11
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Table 82. GPIO control Register
GPIO control
Addr: 1Eh
This register controls GPIO3 and GPIO31 pin functions.
Bit
Bit Name
Default Access
Description
Defines the direction for pin ALS/GPIO1
Input only
00
01
Output (push and pull)
gpio1_mode
1:0
00
11
00
0
R/W
R/W
R/W
R/W
Output (open drain, only push; only NMOS is
active)
10
11
Output (open drain, only pull; only PMOS is
active)
Adds the following pullup/pulldown to pin ALS/GPIO1this
is independent of setting of bits gpi1_mode
00
01
10
None
Pudown
Pullu
gpio1_pulls
gpio2_mode
gpio2_pulls
3:2
5:4
7:6
ADC input (gpio1_mod= XX); recommended
for analog signals
11
Defines the dection for pin GPIO2
Input only
00
01
Output (push and pull)
tpt (open drain, only push; only NMOS is
active)
10
1
Output (open drain, only pull; only PMOS is
active)
ds the following pullup/pulldown to pin GPIO2; this is
independent of setting of bits gpio2_mode
00
01
10
None
Pulldown
Pullup
ADC input (gpio2_mode = XX); recommended
for analog signals
11
Table 83. GPIO control 3 Registr
GPIO control 3
Addr: 1Fh
This register enables low current mode for GPIO3s.
Bit
it Name
Default Access
Description
Defines the direction for pin GPIO3
Input only
00
01
Output (push and pull)
gpio3_mode
:0
00
R/W
Output (open drain, only push; only NMOS is
active)
10
11
Output (open drain, only pull; only PMOS is
active)
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Table 83. GPIO control 3 Register (Continued)
GPIO control 3
Addr: 1Fh
This register enables low current mode for GPIO3s.
Bit
Bit Name
Default Access
Description
Adds the following pullup/pulldown to pin GPIO3; this is
independent of setting of bits gpio3_mode
00
01
10
None
Pulldown
Pullup
gpio3_pulls
3:2
01
R/W
ADC input (gpio3_mode = XX); recommende
for analog signals
11
Table 84. GPIO driving cap Register
GPIO driving cap
Addr: 20h
This register enables low current mode or GPO3s.
Bit
Bit Name
Default Access
Description
Deinethe driving capability f pin ALS/GPIO1
gpio1_low_curr
0
0
0
0
R/W
R/W
R/W
1
Iout
Iout /4
Defines thdriving capability of pin GPIO2
gpio2_low_curr
gpio3_low_curr
1
2
0
1
Iout
Iout /4
efines the driving capability of pin GPIO3
0
1
Iout
Iout /4
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8.6
LED Test
Figure 27. LED Function Testing
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AS3677
The AS3677 supports the verification of the functioalitof all the connected LEDs (open and shorted LEDs and short
to VSS can be detected). This feature is esecially useful in production test to verify the correct assembly of the LEDs,
all its connectors and cables. It can also be ued in the field to verify if any of the LEDs is damaged. A damaged LED
can then be disabled (to avoid unnecessacurrents).
The current sources, dcdc converter, chapump and the internal ADC are used to verify correct operation of each
LED string.
8.6.1 Function Testing for single LEDs connected to the Charge Pump
For any current source cnneced to the charge pump (CURR30-33) where only one LED is connected between the
charge pump and the curret sink (see Figure 27) use:
Table 85. Function esting for LEDs connected to the Charge Pump
Step
Action
Example Code
Switch on the charge pump and set it into manual
1:2 mode (to avoid automatic mode switching
during measurements)
Reg 23h ≤ 14h (cp_mode = 1:2, manual)
Reg 00h ≤ 04h (cp_on = 1)
1
e.g. for register CURR31set to 9mA use
Reg 0Dh ≤ 5Ah (rgb1_current = 9mA)
Reg 02h ≤ 01h (rgb1_mode = on)
2
3
Switch on the current sink for the LED to be tested
Measure with the ADC the voltage on CPOUT
Reg 26h ≤ 95h (adc_select=CPOUT,start ADC)
Fetch the ADC result from Reg 27h and 28h
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1v3-1
49 - 67
AS3677
Datasheet - Detailed Description
Table 85. Function Testing for LEDs connected to the Charge Pump
Step
Action
Example Code
Measure with the ADC the voltage on the switched
on current sink
Reg 26h ≤ 85h (adc_select=RGB1,start ADC)
4
5
Fetch the ADC result from Reg 27h and 28h
Switch off the current sink for the LED to be tested
Reg 02h ≤ 00h (rgb1_mode = off)
Compare the difference between the ADC
measurements (which is the actual voltage across
the tested LED) against the specification limits of
the tested LED
6
Calculation performed in baseband uProcessor
Do the same procedure for the next LED starting
from point 2
7
8
Jump to 2. If not all the LEDs have been tested
Switch off the charge pump
set charge pump automatic mode
Reg 00h ≤ 00h (cp_on = 0)
Reg 23h ≤ 00h
8.6.2 Function Testing example for LEDs connected to the DCDC
Use following procedure as an example:
Table 86. Function Testing procedure for LEDs connected to the DCDC
Step
Action
Example Coe
e.g. Test LEDs n CURR1:
Reg 1h ≤ 01h (curr1_mode=on)
Reg 09h 3ch (curr1_current = 9mA)
Switch on one current sink (only one!) for the LED
string to be tested (CURR1,2 or 6) - this exa
uses CURR1
1
Select the feedback path for the LED string to e
tested (e.g. step_up_fb = 01 for LED string on
CURR1) and disable automatic edbck
Re21h 02h (step_up_fb=CURR1)
2
3
Reg 2h <- 04h (step_up_fb_auto=off)
Set step_up_vmax to fit the externl components
used (e.g. max 1V)
eg 2h <- 00h (for 16V maximum output voltage)
4
5
Switch on the DCDconverter
Reg 00h ≤ 08h
Wait 2ms (dcdc startup e and some margin)
Reg 26h ≤ 98h (adc_select=CURR1, start ADC;
6
7
Measure the voltage on CURR1
Fetch the ADC result from Reg 27h and 28h)
If the voltage on CURR1 is below 1.0buabove
0.1V, this LED string is workig fine (typical value
will be at 0.5V
For a proper working LED result must be below
<199h (1.0V) and above >29h (0.1V)
8
9
Switch off curret sk CURR1
Reg 01h ≤ 00h (curr1_mode=off)
Repeat whole procedure for ach used LED string
(replace CURRwith CURR2 or CURR6)
Note: With the above descrbed procedures electrically open and shorted LEDs can be automatically detected
8.7
Analog-to-Digital Converter
The AS3677 has a uilt-in 10-bit successive approximation analog-to-digital converter (ADC). It is internally supplied
which is also the full-sale input range (0V defines the ADC zero-code). For input signals exceeding 2.5V a resistor
divider with a ain f 0.5 (Ratioprescaler) is used to scale the input of the ADC converter. Consequently the resolution
is:
Tble 87. ADC Input Ranges, Compliances and Resolution
Channels (Pins)
Input Range
0V-2.5V
VLSB
Note
ALS/GPIO1, GPIO2, GPIO3 and
VANA, DLS1, DLS2
2.44mV
1 / ADCTC
VLSB=2.5/1024
junction temperature
ADCTEMP_CODE
-30°C to 125°C
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AS3677
Datasheet - Detailed Description
Table 87. ADC Input Ranges, Compliances and Resolution
Channels (Pins)
Input Range
0V-5V
VLSB
Note
VLSB=(2.5/1024)/0.4; internal
resistor divider used
VBAT, CPOUT, RGB1, RGB2, RGB3
CURR1, CURR2, CURR6
4.88mV
2.44mV
0V-1.0V
VLSB=2.5/1024
Table 88. ADC Parameters
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Resolution
10
Bit
see
Table
87
VIN
Input Voltage Range
VSUPPLY = 2.5V
VSS
V
Differential Non-
Linearity
DNL
± 0.25
LSB
INL
Vos
Integral Non-Linearity
Input Offset Voltage
Input Impedance
± 0.
LSB
LSB
MΩ
pF
± 25
Rin
100
-10
Cin
Input Capacitance
9
VSUPPLY
Idd
Power Supply Range
Power Supply Current
± 2%, ily trimmed.
During cnversion only.
2.5
V
286
µA
Temperature Sensor
Accuracy
TTOL
ADCTOFFSET
ADCTC
@ 25 °C
+10
°C
°C
ADC temperature
measurement offset
value
375
Code temperature
coefficient
1.293
9
°C/
Code
Temperature chage per ADC LSB
For all low vourrent sinks, CPOUT
d VBAT
RatioPRESCALE
R
Ratio of Prescaler
0.4
Transient Parameters (2.5V, 25 ºC)
Tc
fc
ts
Conversion Time
Clock Frequency
27
1.0
16
µs
MHz
µs
All signals are internally generated and
triggered by start_conversion
Settling Time of S&H
The junction temperature (TJUNCTIN) can be calculated with the following formula (ADCTEMP_CODE is the adc conver-
sion result for channel 17h seleced by register adc_select = 010111):
TJUCTION [°C] = ADCTOFFSET - ADCTC · ADCTEMP_CODE
(EQ 1)
ADC Registers
Table 89. ADC_MSB esult Register
ADC_MSB result
Addr: 27h
Together with Register 27h, this register contains the results (MSB) of an ADC
cycle.
B
Bit Name
Default Access
N/A
Description
adc_result_msb
6:0
R
ADC results register.
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AS3677
Datasheet - Detailed Description
Table 89. ADC_MSB result Register (Continued)
ADC_MSB result
Addr: 27h
Together with Register 27h, this register contains the results (MSB) of an ADC
cycle.
Bit
Bit Name
Default Access
Description
Indicates end of ADC conversion cycle
Result is ready
result_not_ready
7
N/A
R
0
1
Conversion is running
Table 90. ADC_LSB result Register
ADC_LSB result
Addr: 28h
Together with Register 28h, this register contains the results (LSB) of an DC
cycle
Bit
Bit Name
Default Access
N/A
Description
adc_result_lsb
2:0
R
ADC result reister
Table 91. ADC_control Register
ADC_control
This registenput source selection and initialization of ADC
Addr: 26h
Bit
5:0
7
Bit Name
Default Access
escription
Scts iput source as ADC input
000000 00h)
GPIO2
000001 (01)
00010 (02h)
100 (04h)
00101 (05h)
000110 (06h)
000111 (07h)
001000 (08h)
001001 (09h)
010001 (11h)
010010(12h)
010011 (13h)
010100 (14h)
010101 (15h)
010111 (17h)
other codes
VANA
ALS/GPIO1
GPIO3
RGB1
RGB2
RGB3
adc_select1
0h
R/W
CURR1
CURR2
DLS1
DLS2
CURR6
VBAT
CPOUT
ADCTEMP_CODE (junction temperature)
reserved
start_conversion
N/A
W
Writing a 1 into this bit starts one ADC conversion cycle.
1. See Table Table 87 for ADC ranges and resolution.
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AS3677
Datasheet - Detailed Description
Figure 28. ADC Circuit
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AS3677
8.8
Power-On Reset
The internal reset is controlled by two sources:
ꢀ
ꢀ
VBAT Supply
Serial interface state (CLK, DATA)
The internal reset is forced if VBAT is low or iboth interface pins (CK, DATA) are low for more than tPOR_DEB (typ.
100ms)5. Then device enters shutdown moe. For details see sectn Operating Modes on page 58.
The reset levels control the state of all sters. As long as VBAand CLK/DATA are below their reset thresholds, the
register contents are set to default. Acess by serial ints possible once the reset thresholds are exceeded.
5. Only if shutdwn_enab=1
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AS3677
Datasheet - Detailed Description
Figure 29. Zero Power Device Wakeup block diagram
AS3677
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Table 92. Power On Reset Parameters
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Overall Power-On
Reset
Montor voltage on VBATpowon eset for
all internal funions.
VPOR_VBAT
2.0
V
Reset Level for pins
CLK, DATA
VPOR_PERI
Monitor voltage on pis CLK, DATA
1.0
V
Reset debounce tim
for pins CLK, DATA
tPOR_DEB
tstart
100
6
ms
ms
Interface Startup Time
8.8.1 Reset control register
Table 93. Overtemp control Register
Overtemp control
Addr: 29h
This register reads and resets the overtemperature flag.
Default Access Description
Bit
Bit Nam
Enable Shutdown mode and serial interface reset.
Serial Interface reset disabled. Device does not
0
enter Shutdown mode
shudwn_enab
4
1
R/W
Serial Interface reset enabled, device enters
shutdown when SCL and SDA remain low for
min. 100ms
1
8.9
Temperature Supervision
An integrated temperature sensor provides over-temperature protection for the AS3677. This sensor generates a flag
if the device temperature reaches the overtemperature threshold of 140º. The threshold has a hysteresis to prevent
oscillation effects.
If the device temperature exceeds the T140 threshold all current sources, the charge pump and the dcdc converter is
disabled and the ov_temp flag is set. After decreasing the temperature by THYST operation is resumed.
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AS3677
Datasheet - Detailed Description
The ov_temp flag can only be reset by first writing a 1 and then a 0 to the register bit rst_ov_temp.
Bit ov_temp_on = 1 activates temperature supervision Table 95. It is recommend to leave this bit set (default state).
Table 94. Overtemperature Detection
Symbol
T140
Parameter
Condition
Min
Typ
140
5
Max
Unit
ºC
ov_temp Rising
Threshold
THYST
ov_temp Hysteresis
ºC
Table 95. Overtemp control Register
Overtemp control
This register reads and resets the overtemperature flag.
Default Access Description
Addr: 29h
Bit
Bit Name
Activates/deactivates device temperatursupervision.
Default: Off - all other bits are only valid this bit is set to 1
Temperature supervision idisaled. No reset
ov_temp_on
0
1
W
0
1
will be generated if devce temperature
exceeds 40ºC
Temperature supevision is enabled
Indicates that the overtemperature threshold
has been rehed; this flag is not cleared by an
overtemperaue reset. It has to be cleared
using rst_ov_temp
ov_temp
1
2
N/A
0
R
1
The ov_temp fg is eared by first setting this bit to 1, and
then setting this bit to 0.
rst_ov_temp
R/W
8.10 Serial Interface
The AS3677 is controlled using seril ierface pins CLK and ATA:
Figure 30. Serial interface block diagram
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1v3-1
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AS3677
Datasheet - Detailed Description
The clock line CLK is never held low by the AS3677 (as the AS3677 does not use clock stretching of the bus).
Table 96. Serial Interface Voltages and Timings
Symbol
Parameter
Condition
Min
Typ
Max
Unit
High Level Input
Voltage
VIHI/F
1.38
VBAT
V
Low Level Input
Voltage
VILI/F
0.0
0.52
V
Pins DATA and CLK
VHYSTI/F
tRISE
Hysteresis
Rise Time
Fall Time
0.1
V
0
0
1000
300
ns
ns
tFALL
Low Level Output
voltage
VOL
0.2
V
Pin DATA at 4mA
tCLK_FILTER
tDATA_FILTER
Spike Filter on CLK
Spike Filter on DATA
100
30
ns
ns
The AS3677 is compatible to the NXP two wire specification http://www.nxp.com/acrobat_donloa/literature/9398/
39340011.pdf, Version 2.1, January 2000 for standard and fast mode (high speed mode).
8.10.1 Serial Interface Features
ꢀ
ꢀ
ꢀ
Fast Mode Capability (Maximum Clock Frequency is 4)
7-bit Addressing Mode
Write Formats
- Single-Byte Write
- Page-Write
ꢀ
ꢀ
Read Formats
- Current-Address Read
- Random-Read
- Sequential-Read
DATA Input Delay and CLK spike filtering by integracomponents
8.10.2 Device Address Selection
The serial interface address of the AS367has the following address:
ꢀ
ꢀ
If ADR is connected to VSS: 80h – Write Commands, 81h – Read Commands
If ADR is connected to VBAT: 82h – WCommands, 83h – Read Commands
Figure 31. Complete Serial Data ransfer
DATA
CLK
8
9
1-7
8
9
1-7
1-7
8
9
P
S
Stop
Condition
Start
Condition
Address R/W
ACK
Data
ACK
Data
ACK
Serial Data Transfer Formats
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AS3677
Datasheet - Detailed Description
Definitions used in the serial data transfer format diagrams are listed in the following table:
Table 97. Serial Data Transfer Byte Definitions
Symbol
Definition
Start Condition after Stop
Repeated Start
R/W (AS3677 Slave)
Note
1 bit
1 bit
S
R
R
Sr
10000000b (80h) ADR=VSS
10000010b (82h) ADR=VBAT
DW
DR
Device Address for Write
Device Address for Read
R
R
10000001b (81h) ADR=VSS
10000011b (83h) ADR=VBAT
WA
A
Word Address
Acknowledge
R
W
R
R
R
R
R
8 bits
1 bit
N
Not Acknowledge
1 bit
8 bs
reg_data
data (n)
P
Register Data/Write
Register Data/read
Stop Condition
1 bit
8 bits
WA++
Increment Word Address Internally
During Acknowledge
Figure 32. Serial Interface Byte Write
S
DW
A
WA
A
reg_data
A P
Write Register
WA++
(lave) receives data
(= Slave) transmits data
Figure 33. Serial Interface Page Wite
n
S
DW
A
WA
A
reg_data 1
A
reg_data 2
A
…
reg_data
A P
rite Register
WA++
Write Register
WA++
Write Register
WA++
5
5
(= Slave) receives data
(= Slave) transmits data
Byte Write and Page Write formats are uto write data to the slave.
The transmission begins with the TART condition, which is generated by the master when the bus is in IDLE state
(the bus is free). The device-wriaddress is followed by the word address. After the word address any number of data
bytes can be sent to the sav. The word address is incremented internally, in order to write subsequent data bytes on
subsequent address locaons.
For reading data rom te slave device, the master has to change the transfer direction. This can be done either with a
repeated START codition followed by the device-read address, or simply with a new transmission START followed by
the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register
byte transmittd from the slave. In Read Mode any number of subsequent register bytes can be read from the slave.
The wordress is incremented internally.
Te follong diagrams show the serial read formats supported by the AS3677.
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AS3677
Datasheet - Detailed Description
Figure 34. Serial Interface Random Read
S
DW
A
WA
A
Sr
DR
A
data
N P
Read Register
WA++
(= slave) receives data
(= slave) transmits data
Random Read and Sequential Read are combined formats. The repeated START condition is used to change the
direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START
condition is followed by the device-write address and the word address.
In order to change the data direction a repeated START condition is issued on the 1st CLKpulse after the ACKNOW
EDGE bit of the word address transfer. After the reception of the device-read address, the slave becomes the trnsmit-
ter. In this state the slave transmits register data located by the previous received word address vector. The maser
responds to the data byte with a NOT ACKNOWLEDGE, and issues a STOP condition on the bus.
Figure 35. Serial Interface Sequential Read
n
S
DW
A
WA
A
Sr
DR
A
data 1
A
data 2
...
data
N P
Red Register
++
(= slave) receives data
(= slave) transmits data
Sequential Read is the extended form of Random Read, as multiple register-ata bytes are subsequently transferred.
In contrast to the Random Read, in a sequential read the transferred reer-data bytes are responded by an acknowl-
edge from the master. The number of data byes tnsferred in one equence is unlimited (consider the behavior of the
word-address counter). To terminate the tansission the master has o send a NOT ACKNOWLEDGE following the
last data byte and subsequently generate te STOP condition.
Figure 36. Serial Interface Current Ass Read
n
S
DR
A
data 1
data 2
…
A
data
N P
Read Regis
WA++
Read Register
WA++
Read Register
WA++
(= aveceives data
(= slavsmits data
To keep the access time as small s possible, this format allows a read access without the word address transfer in
advance to the data transfer. Thbus is idle and the master issues a START condition followed by the Device-Read
address.
Analogous to Random Red, a single byte transfer is terminated with a NOT ACKNOWLEDGE after the 1st register
byte. Analogous Seqential Read an unlimited number of data bytes can be transferred, where the data bytes must
be responded to witan ACKNOWLEDGE from the master.
For termination of te transmission the master sends a NOT ACKNOWLEDGE following the last data byte and a sub-
sequent STOP ondition.
811 perating Modes
If thvoltages on CLK and DATA is less than VPOR_PERI for > tPOR_DEB (see Table 92 on page 54), the AS3677 is in
shutdown mode and its current consumption is minimized (IBAT = ISHUTDOWN) and all internal registers are reset to their
default values.
If the voltage at CLK or DATA rises above VPOR_PERI, the AS3677 serial interface is enabled and the AS3677 and the
standby mode is selected. The AS3677 is switched automatically from standby mode (IBAT = ISTANBY) into active mode
(IBAT = IACTIVE) and back, if one of the following blocks are activated:
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AS3677
Datasheet - Detailed Description
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Charge pump
Step up regulator
Any current sink
ADC conversion started
PWM active
Pattern mode active.
If any of these blocks are already switched on the internal oscillator is running and a write instruction to the registers is
directly evaluated within 1 internal CLK cycle (typ. 1µs)
If all these blocks are disabled, a write instruction to enable these blocks is delayed by 64 CLK cycles (oscillator will
startup, within max 200µs).
The mode switching is shown in Figure 37:
Figure 37. Startup and Operating Mode Selection
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www.austriamicrosystems.com/AS3677
1v3-1
59 - 67
AS3677
Datasheet - Register Map
9 Register Map
Table 98. Registermap
Register
Content
b4 b3
Definition
Name
b7
b6
b5
b2
b1
b0
step_up
_on
cp_on
ldo_on
Reg control
00h
00
curr2_mode
rgb2_mode
ldo_voltage
curr1_mode
rgb1_mode
curr12 control
curr rgb control
LDO Voltage
Curr1 current
Curr2 current
Rgb1 current
Rgb2 current
Rgb3 current
Pwm control
Pwm code
01h 00h
02h 00h
07h 00h
09h 00h
0Ah 00h
0Bh 00h
0Ch 00h
0Dh 00h
16h 00h
17h 00h
curr6_mode
rgb3_mode
curr1_current
curr2_current
rgb1_current
rgb2_current
r3_current
pw_dim_speed
pwm_cod
softdim
pwmdim_mode
pattern_delay
pattern_
color
Pattern control
18h 00h
paern
pattern_dta_0
parn_data_1
attern_data_2
pattern_data_3
Pattern data0
Pattern data1
Pattern data2
Pattern data3
GPIO control
GPIO control 3
19h 00h
1Ah 00h
1Bh 00h
1Ch 00h
1Eh 4Ch
1Fh 04h
gpio1_pulls
gpio3_pulls
gpio3_lo gpio2_lo
gpio1_mode
io2_pulls
pio2_mode
gpio3_mode
gpio1_lo
w_curr
GPIO driving cap 20h 00h
w_curr w_curr
step_up
_frequ
step_up_vmax
step_up_fb
skip_fast
DCDC control1
DCDC control2
21h 02h
22h 88h
step_
_fb_auto
step_up step_up
_ov _lowcur
cp_start
_deboun
ce
cp_auto
_on
cp_mode_switchin
g
cp_mode
cp_clk
CP control
23h 40h
rgb3_on rgb2_on rgb1_on
_cp _cp _cp
CP mode Switch1 4h 70h
CP mode Switch2 5h 00h
curr6_on
_cp
curr2_on curr1_on
_cp
_cp
start_co
nversion
adc_select
adc_result_msb
ADCntrol
26h 02h
result_n
ot_ready
AC_MSB result 27h
ADC_LSB result 28h
NA
NA
adc_result_lsb
shutdwn
_enab
rst_ov_t
emp
ov_temp
_on
ov_temp
Overtemp control 29h 11h
curr6_lo rgb3_low rgb2_low rgb1_low
w_v _v _v _v
Curr low voltage
2Ah NA
status1
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1v3-1
60 - 67
AS3677
Datasheet - Register Map
Table 98. Registermap
Register
Content
b4 b3
Definition
Name
b7
b6
b5
b2
b1
b0
curr2_lo curr1_lo
w_v w_v
Curr low voltage
2Bh NA
status2
pattern_
slow
pattern_
delay2
Gpio current
Curr6 current
2Ch 80h
2Fh 00h
curr6_current
adder_current1
(can be enabled for CURR1)
Adder Current 1 30h 00h
Adder Current 2 31h 00h
Adder Current 3 32h 00h
adder_current2
(can be enabled for CURR2)
adder_current3
(can be enabled for CURR6)
rgb3_ad rgb_ad rgb1_ad
dder der
Adder Enable 1
Adder Enable 2
33h 00h
34h 00h
curr6_acurr2_ad curr1_ad
der
der
der
ASIC ID1
ASIC ID2
3Eh A6h
3Fh 5Xh
1
0
0
1
0
1
0
1
1
0
revision
gpio3_o gpio2_o gpio1_o
GPIO output 2
GPIO signal 2
Pattern End
50h 00h
51h 00h
54h 00h
ut ut ut
gpio3_ in gpio2_ in gpio1_in
pattern_
end
DLS mode
control1
ds_nal rgb3_on rgb2_n rgb1_on
_dls dls1 _dls
56h 00h
57h 00h
90h 00h
curr1_on
_dls
DLS mode
control2
curr6_on curr6_dl _dl
curr2_on
_dls
_dls
s2
s2
amb_ke
ep
amb_gain
amb_on
ALS control
amb_filter_down
amb_filter_up
ALS filter
ALS offset
ALS result
91h 00h
92h 00h
93h 00h
amb_offset
amb_result
curr2_amb_group curr1_amb_group
rgb2_amb_group rgb1_amb_group
group1_y0
ALS curr12 group 94h 00
curr6_amb_group
rgb3_amb_group
ALS rgb group
ALS group 1 Y0
ALS group 1 Y3
95h 0h
8h 00h
99h 00h
group1_y3
group1_x1
group1_k1
group1_x2
group1_k2
group2_y0
group2_y3
group2_x1
ALS group X1 9Ah 00h
ALS g1 K1 9Bh 00h
LS grup 1 X2 9Ch 00h
ALgroup 1 K2 9Dh 00h
ALS group 2 Y0 9Eh 00h
ALS group 2 Y3 9Fh 00h
ALS group 2 X1 A0h 00h
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1v3-1
61 - 67
AS3677
Datasheet - Register Map
Table 98. Registermap
Register
Content
b4 b3
Definition
Name
b7
b6
b5
b2
b1
b0
group2_k1
group2_x2
group2_k2
group3_y0
group3_y3
group3_x1
group3_k1
group3_x2
group3_k2
ALS group 2 K1 A1h 00h
ALS group 2 X2 A2h 00h
ALS group 2 K2 A3h 00h
ALS group 3 Y0 A4h 00h
ALS group 3 Y3 A5h 00h
ALS group 3 X1 A6h 00h
ALS group 3 K1 A7h 00h
ALS group 3 X2 A8h 00h
ALS group 3 K2 A9h 00h
ALS group output
amb_group1
ab_group2
AAh 00h
1
ALS group output
ABh 00h
2
ALS group output
amb_group
ACh 00h
3
ALS range high
ADh 00h
amb_rang_int_igh
ambnge_int_low
interrupt threshold
ALS range low
AEh 00h
interrupt threshold
amb_too amb_too
Interrupt Status
AFh 00h
_low
_high
Note: If writing to register, write 0 to used bits
Write to read only bits will be ignored
yellow color = read only
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1v3-1
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AS3677
Datasheet - Application Information
10 Application Information
10.1 External Components
Table 99. External Components List
Value
Package
(min.)1
tol.
(min.)
Rating
(max)
Part Number
Min
Max
Notes
Typ
Ceramic, X5R (Vana1 output)
(e.g. Taiyo Yuden
C1
2.2µF
±20%
±20%
6.3V
25V
JMK107BJ225MA-T or
LMK107BJ225MA)
0603
only required if LDO is used
Ceramic, X5R, X7R (Step Up
DCDC output)
106
(0805)
3.2x6x0.
85mm
C2
4.7µF
(e.g. Taiyo Yuden
TMK316BJ475KD)
Ceramic, X5R (LDO outut
capacitor) (e.g. Taiyo Yude
JMK063BJ10KP-F
C3
C4
C5
100nF
470nF
1µF
±20%
±20%
±20%
6.3V
.3V
6.3V
0402
0402
0402
Ceramic, X5R (ChargPump
flying capacior) (e.g. Taiyo
Yuden JMK105BJ74KV-F)
CeramX5R (Charge Pump
output) e.g. Taiyo Yuden
JK105BJ105KV-F)
DATPullup resistor – usually
already inside master
R1
R2
0201
0201
1-10kΩ
CLK Pullup resistor – usually
already inside master
Recommended Type:
Murata LQH3NPN100NJ0 or
Panasonic ELLSFG100MA
or TDK VLF3012A or Taiyo
Yuden NRH3012T100MN
(7µH min. at 600mA)
3x3x
1.2mm (H
is max)
L1
10µH
±2
SOT666
1.6x1.6x0.
6mm
D1
PMEG4010BEA
Schottky diode
e.g. Rohm BH1620FVC or
Toshiba TPS856
1.6x1.6x
0.55mm
X1
Light Sensor
LED
D2:D10
As required by application
1. in 1/100 inch (unless oherwe specified)
10.2 Layout Recommendations
1. GND Planes: Connect the VSS pins (B4, B5) to the low noise GND-plane.
VSS_CDC (A4) should be connected to a separated GND-plane. Connect also the charge pump output
acitor (C5) and the DCDC-caps (C1, C2) to this separated GND-plane. Connect all other blocking caps to
tlow noise GND-plane. Keep the area of the separated GND plane as small as possible and connect it to
the star point of the low noise GND plane. Do not connect VSS (B4, B5) directly to VSS_DCDC (A4).
2. Supplies: The pins VBAT (B3) and VBAT_CP (A3) can be connected directly together. Put a blocking Cap
close to VBAT_CP.
3. DCDC: Put L1, D1, C1 and C2 close together and also close to the pins SW (A5) and VSS_DCDC (A4).
4. LDO: Put C3 close to pin VANA (C1)
www.austriamicrosystems.com/AS3677
1v3-1
63 - 67
AS3677
Datasheet - Package Drawings and Markings
11 Package Drawings and Markings
Figure 38. WL-CSP25 2.2x2.2x0.6mm 5x5 Balls Package Drawing
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AS3677
<Code>
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Figure 39. WL-CSP25 2.2x2.2x0.6mm 5x5 Balls Detail Dimensions
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The coplrity of the balls is 40µm.
www.austriamicrosystems.com/AS3677
1v3-1
64 - 67
AS3677
Datasheet - Package Drawings and Markings
11.1 Tape & Reel Information
Figure 40. Tape & Reel Dimensions
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1v3-1
65 - 67
AS3677
Datasheet - Ordering Information
12 Ordering Information
The devices are available as the standard products shown in Table 100.
Table 100. Ordering Information
Model
Description
Delivery Form
Package
AS3677
25pin WL-CSP
(2.2x2.2x0.6mm)
RoHS compliant / Pb-Free
Wafer Level Chip Scale Package,
size 2.2x2.2x0.6mm, 5x5 balls, 0.4mm pitch,
Green, Pb-Free
AS3677-ZWLT
Tape & Reel
Note: AS3677-ZWLT
AS3677-
Z
Temperature Range: -30ºC - 85ºC
WL Package: Wafer Level Chip Scale Package (WL-CSP) 2.2x2.2x0.6mm
Delivery Form: Tape & Reel
T
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1v3-1
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AS3677
Datasheet - Ordering Information
Copyrights
Copyright © 1997-2011, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, trans-
lated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regadin
the information set forth herein or regarding the freedom of the described devices from patent infringement. autria
crosystems AG reserves the right to change specifications and prices at any time and without notice. Therefre, prior
to designing this product into a system, it is necessary to check with austriamicrosystems AG for curent information.
This product is intended for use in normal commercial applications. Applications requiring extendetemperature
range, unusual environmental requirements, or high reliability applications, such as military, medical le-support or life-
sustaining equipment are specifically not recommended without adional processing by auramrosystems AG for
each application. For shipments of less than 100 parts the manufcturiflow might show deviaons from the standard
production flow, such as test flow or test location.
The information furnished here by austriamicrosystems Abelieved to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or ahird party for any dmages, including but not limited to
personal injury, property damage, loss of profits, loss of use, nterruption of busess indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the rnishng, performance or use of the tech-
nical data herein. No obligation or liability to recipor any third party l arie or flow out of
austriamicrosystems AG rendering of technicl r other services.
Contact Informatio
Headquarters
austriamicrosysteAG
Tobelbaderstrsse 30
Schloss Premtaeten
A-8141 ria
Te+43 (0) 3136 500 0
Fax: 43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
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1v3-1
67 - 67
相关型号：
AS3677-ZWLT
Triple Channel Lighting Management Unit with DCDC step/up, ALS, 2xDLS(=DBC) and RGB Driver
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