AS5130 [AMSCO]
8 Bit Programmable Magnetic Rotary Encoder with Motion Detection & Multiturn; 8位可编程磁旋转编码器，运动检测与多圈
| 型号： | AS5130 |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | 8 Bit Programmable Magnetic Rotary Encoder with Motion Detection & Multiturn |
| 文件： | 总41页 (文件大小：2086K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
AS5130
8 Bit Programmable Magnetic Rotary Encoder
with Motion Detection & Multiturn
1 General Description
2 Key Features
ꢀ
360º contactless angular position encoding
The AS5130 is a contactless magnetic rotary encoder
for accurate angular measurement over a full turn of
360º. It is a system-on-chip, combining integrated Hall
elements, analog front end and digital signal processing
in a single device. The angle can be measured using
only a simple two-pole magnet rotating over the center
of the chip. The magnet may be placed above or below
the IC. The absolute angle measurement provides
instant indication of the magnet’s angular position with a
resolution of 8 bit = 256 positions per revolution. This
digital data is available as a serial bit stream and as a
PWM signal. The AS5130 can be operated in pulsed
mode (Vsupply=off), which reduces the average power
consumption significantly. During Vsupply=off, the
measured angle can be stored using an internal storage
register supplied by a low power voltage line. This mode
achieves very low power consumption during polling of
the rotary position of the magnet. If the position of the
magnet changes, then the motion detection feature
wakes up an external system. The device is capable of
counting the amount of magnet revolutions. The multi
turn counter value is stored in a register and can be read
in addition to the angle information. Furthermore, any
arbitrary position can be set as zero-position. The
system is tolerant to misalignment, air gap variations,
temperature variations and external magnetic fields and
high reliability due to non-contact sensing.
ꢀ
Two digital 8-bit absolute outputs:
- Serial interface
- Pulse width modulated (PWM) output
User programmable zero position
ꢀ
ꢀ
ꢀ
High speed: up to 30000 rpm
Failure detection mode for magnet placement moni-
toring and loss of power supply
ꢀ
ꢀ
ꢀ
ꢀ
Wide temperature range: - 40ºC to + 125ºC
Multi Turn counter / Movement detection
Small Pb-free package: SSOP-16 (5,3mm x 6,2mm)
Automotive qualified to AEC-Q100, grade 1
3 Applications
The AS5130 is an ideal solution for Ignition key position
sensing, Steering wheel position sensing, Transmission
gearbox encoder, Front panel rotary switches and
replacement of Potentiometers.
Figure 1. Block Diagram
SINP / SINN / COSP / COSN
PWM
PWM
Decoder
Angle
tracking
ADC &
Angle
Sin
DIO
Zero
Pos.
Absolute
Serial
Interface
(SSI)
Cos
CS
Hall Array
&
Frontend
Amplifier
decoder
DCLK
Mag
AGC
C1
AGC
CAO
power management
PROG
OTP
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AS5130
Data Sheet - Applications
Contents
1 General Description..............................................................................................................................
2 Key Features ........................................................................................................................................
3 Applications ..........................................................................................................................................
4 Pin Assignments...................................................................................................................................
Pin Descriptions ...................................................................................................................................................
5 Absolute Maximum Ratings..................................................................................................................
6 Electrical Characteristics ......................................................................................................................
Timing Characteristics..........................................................................................................................................
Magnetic Input Range ..........................................................................................................................................
1
1
1
4
4
5
6
9
9
7 Detailed Description ........................................................................................................................... 10
Connecting the AS5130 ..................................................................................................................................... 10
Serial 3-Wire Connection (Default Setting) .................................................................................................... 10
Serial 3-Wire Connection (OTP Programming Option) .................................................................................. 12
1-Wire PWM Connection................................................................................................................................ 12
Analog Output ................................................................................................................................................ 13
Analog Sin/Cos Outputs with External Interpolator ........................................................................................ 14
Serial Synchronous Interface (SSI).................................................................................................................... 15
Commands of the SSI in Normal Mode.......................................................................................................... 15
Commands of the SSI in Extended Mode...................................................................................................... 16
Multi Turn Counter.............................................................................................................................................. 19
AS5130 Status Indicators................................................................................................................................... 20
Lock Status Bit ............................................................................................................................................... 20
Magnetic Field Strength Indicators................................................................................................................. 20
“Pushbutton” Feature ......................................................................................................................................... 21
High Speed Operation........................................................................................................................................ 21
Propagation Delay.......................................................................................................................................... 22
Sampling Rate................................................................................................................................................ 22
Chip Internal Lowpass Filtering...................................................................................................................... 22
Digital Readout Rate...................................................................................................................................... 22
Total Propagation Delay of the AS5130......................................................................................................... 22
Reduced Power Modes...................................................................................................................................... 23
Low Power Mode ........................................................................................................................................... 23
Power Cycling Mode ...................................................................................................................................... 24
Polling Mode .................................................................................................................................................. 24
8 Application Information....................................................................................................................... 28
Benefits of AS5130............................................................................................................................................ 28
Application Example 1........................................................................................................................................ 28
Application Example II 3-wire sensor with magnetic field strength indication..................................................... 28
Application Example III: Low-power encoder ..................................................................................................... 29
Application Example IV: Polling mode................................................................................................................ 30
Accuracy of the Encoder system........................................................................................................................ 30
Quantization Error.......................................................................................................................................... 30
Vertical Distance of the Magnet ..................................................................................................................... 32
Choosing the Proper Magnet ......................................................................................................................... 32
Magnet Placement ......................................................................................................................................... 33
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AS5130
Data Sheet - Applications
Lateral Displacement of the Magnet .............................................................................................................. 35
Magnet Size ................................................................................................................................................... 36
9 Package Drawings and Markings....................................................................................................... 38
Recommended PCB Footprint ........................................................................................................................... 39
10 Ordering Information......................................................................................................................... 40
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AS5130
Data Sheet - Pin Assignments
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
16
15
CAO
1
2
3
4
5
6
7
8
DVDD
PWM
WAKE
C1
PROG
VSS
14
13
SINP
AS5130
AVDD
DIO
SINN
12
11
10
9
COSP
COSN
TestCoil
CS
DCLK
Pin Descriptions
Table 1. Pin Descriptions
Pin Name
Pin Number
Description
Indicates if the magnetic field is present. If the field is too low, the signal is
HI.
CAO
1
2
OTP Programming Pad, programming voltage. For normal operation it
must be left unconnected.
PROG
Supply Ground.
VSS
SINP
SINN
COSP
COSN
Test Coil
DCLK
CS
3
4
Used for factory testing. For normal operation it must be left unconnected.
Used for factory testing. For normal operation it must be left unconnected.
Used for factory testing. For normal operation it must be left unconnected.
Used for factory testing. For normal operation it must be left unconnected.
Test pin. Must be left unconnected.
5
6
7
8
Clock Source for SSI communication. Schmitt trigger input.
Chip Select for SSI. Active high. Schmitt trigger input.
Data input / output for SSI communication.
9
10
11
12
13
DIO
Positive Supply Voltage 5V.
AVDD
C1
Test mode selector. For normal operation it must be connected to VSS.
Interrupt output. Used for polling mode. Open Drain NMOS. Use pull-up
resistor with >1.5kΩ.
WAKE
PWM
DVDD
14
15
16
Pulse Width Modulation output. 0.5us width step per LSB.
Pin to connect to low power supply for polling mode. Must be connected to
VSS in normal mode.
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AS5130
Data Sheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Electrical
Characteristics on page 6 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Min
Max
Units
Comments
Only relevant for polling operation mode,
supply voltage with capacitor of the
integrated storage register during toff phase
of AVDD
Supply Voltage
0.3
7
V
Input Pin Voltage
Input Current (latchup immunity)
Electrostatic Discharge
VSS-0.5
-100
AVDD
100
V
mA
kV
Norm: EIA/JESD78 ClassII Level A
Norm: JESD22-A114E
±2
Package Thermal Resistance SSOP-16
137.1
K/W
Still Air / Single Layer PCB
Still Air / Multi Layer PCB, JEDEC Standard
Testboard
Package Thermal Resistance SSOP-16
70
86
K/W
Storage Temperature
Ambient Temperature
Junction Temperature
-55
-40
125
125
150
ºC
ºC
ºC
Norm: IPC/JEDEC J-STD-020C.
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020C “Moisture/Reflow
Sensitivity Classification for Non-Hermetic
Solid State Surface Mount Devices”.
The lead finish for Pb-free leaded packages
is matte tin (100% Sn).
Package body temperature
Humidity non-condensing
260
85
ºC
%
5
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AS5130
Data Sheet - Electrical Characteristics
6 Electrical Characteristics
TAMB = -40 to 125ºC, unless otherwise noted.
Table 3. Electrical Characteristics
Symbol
AVDD
DVDD
IDD
Parameter
Conditions
Min
4.5
3.6
Typ
5
Max
5.5
5.5
19
Units
V
Positive Supply Voltage
Polling Mode Supply Voltage
Power Supply Current
Power Down Mode
Except OTP programming
5
V
mA
mA
bit
Ioff
1.4
8
2
Resolution
N
1.406
Startup from zero
2000
250
Startup with preset AGC
(Supplied during toff phase of AVDD
from the external buffer capacitor via
DVDD pin)
TPwrUp
Power Up Time
µs
Startup from sleep power mode
150
17
Analog signal path; over full
temperature range
Propagation Delay
Tracking rate
tda
tdd
15
µs
µs
Step rate of tracking ADC;
1 step = 1.406º
0.85
1.15
1.45
Total signal processing delay,
Analog + Digital + SSI readout
tdelay
T
Signal Processing Delay
Analog filter time constant
21.55
µs
µs
( tda + tdd + tSSI
)
Internal lowpass filter
Centered Magnet
4.1
-2
6.6
12.5
2
INLcm
Accuracy
Within horizontal displacement
radius (see parameters for magnet)
-3
3
Transition Noise
TN
rms (1 sigma)
VDD rising
0.235
4,3
PORr
PORf
Hyst
3,7
3,4
4
V
V
Power-On-Reset levels
VDD falling
3,7
500
3,9
Hysteresis | PORr - PORf |
mV
Parameters for Magnet
Frequencies above 1000 rpm
causes an additional not specified -30000
DNL Error
Rotational Speed
n
30000
8
rpm
Resolution
N
bit
Magnet diameter
Magnet thickness
MD
MT
Diametrically magnetized
6
mm
mm
2.5
Valid for use of full range of
Bi
Magnetic input range
32
75
mT
sensitivity
LSB/
mT
Magnetic Sensitivity of AGC
Magnetic Offset
s
AGC value available at SSI
0.5
5
4
BDC
Magnetic stray field without gradient
mT
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AS5130
Data Sheet - Electrical Characteristics
Table 3. Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Startup from zero
2000
Startup with preset AGC
(Supplied during toff phase of AVDD
from the external buffer capacitor via
DVDD pin)
TPwrUp
Power up time
250
us
Startup from sleep power mode
150
5
Open drain output with tri-state
behavior, see Fig 10
Vout_wake
Wake up output
V
up
Factory setting is 4 LSB, value is
accessible by SSI in buffered
register and can be changed by
customer.
Angle difference threshold for
wake up generation
WakeLSB
0
127
LSB
DC/AC Characteristics for Digital Inputs and Outputs
CMOS Input
0.7 x
VDD
VIH
High level Input voltage
V
0.3 x
VDD
Low level Input Voltage
Input Leakage Current
VIL
V
ILEAK
1
µA
CMOS Output
VDD -
0.5
VOH
VOL
High level Output voltage
Low level Output Voltage
V
V
VSS +
0.4
CL
Capacitive Load
Slew Rate
35
30
pF
ns
tslew
External capacitive load C_L = 35pF
External series resistance R = 0Ω
Junction temperature TJ = 136ºC
Rise time of the internal driver t_rise
tdelay
Time Rise Fall
15
ns
= 3ns
Fall time of the internal driver t_fall =
3ns
Programming Parameters
VPROG
Programming Voltage
IPROG
static voltage at pin PROG
8.0
8.5
V
Programming Current
100
mA
Programming ambient
temperature
TambPROG
during programming
0
2
85
ºC
µs
tPROG
VR,prog
Programming time
timing is internally generated
4
0.5
3,5
during Analog Readback mode at
pin PROG
Analog readback voltage
V
VR,unprog
2,2
8-bit PWM output
NPWM
PWM resolution
PWM pulse width
PWM pulse width
PWM period
8
bit
µs
PWMIN
angle = 0º (00H)
angle = 358.6º (FFH)
over full temperature range
=1 / PWM period
0,59
0,556 0,526
PWMAX
PWP
150,9 142,3 134,61
µs
151,5 142,8
5,44
135
µs
fPWM
PWM frequency
7
9,18
kHz
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AS5130
Data Sheet - Electrical Characteristics
Table 3. Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Digital hysteresis
Hyst
at change of rotation direction
1
bit
Serial 8-bit Output
fCLK
6
MHz
ns
Clock Frequency
Clock Frequency
Normal operation
tCLK
166.6
250
fCLK, P
During OTP programming
500
kHz
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AS5130
Data Sheet - Electrical Characteristics
Timing Characteristics
TAMB = -40 to 125 ºC, unless otherwise noted.
Table 4. Timing Characteristics
Symbol
Parameter
Conditions
Min
15
15
--
Typ
Max
--
Units
ns
Rising CLK to CS
t0
t1
t2
Chip select to positive edge of CLK
Chip select to drive bus externally
--
ns
--
ns
Setup time command bit,
Data valid to positive edge of CLK
t3
t4
30
30
ns
ns
Hold time command bit,
Data valid after positive edge of CLK
Float time,
Positive edge of CLK for last
command bit to bus float
t5
t6
30
CLK/2
ns
ns
Bus driving time,
Positive edge of CLK for last
command bit to bus drive
CLK/2
+0
CLK/2
+30
Setup time data bit,
Data valid to positive edge of CLK
CLK/2
+0
CLK/2
+30
t7
t8
ns
ns
Hold time data bit,
Data valid after positive edge of CLK
CLK/2
+0
CLK/2
+30
Hold time chip select,
Positive edge CLK to negative edge
of chip select
t9
30
ns
Bus floating time,
Negative edge of chip select to float
bus
t10
tTO
0
30
24
ns
µs
Timeout period in 2-wire mode (from
rising edge of CLK)
20
Magnetic Input Range
The magnetic input range is defined by the AGC loop. This regulating loop keeps the Hall sensor output in the optimum
range for low SNR by adjusting the Hall bias current. This loop can adjust to a magnetic field strength variation of
±38%. The AGC output voltage is an indicator for the magnetic field.
The nominal magnetic field for a balanced AGC is defined by the Hall bias and the Hall sensitivity and can be set by a
variable gain in the signal path. The gain can be set in 8 steps in the OTP or by the SSI in a mirror register. The
resulting magnetic input range is a value of Bnominal±38% inside of a range of 32mT … 75mT, if the trimming is
performed by the customer.
Table 5. Magnetic Input Range
Setting
Binary
Gain A
Blimit
0
000
1
2
3
4
5
6
7
111
001
1.05
010
1.2
011
1.4
100
1.65
101
1.9
110
2.2
0.9
2.55
Max. 75mT
Min. 32mT
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AS5130
Data Sheet - Detailed Description
7 Detailed Description
Connecting the AS5130
The AS5130 can be connected to an external controller in several ways as listed below:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Serial 3-wire connection (default setting)
Serial 3-wire connection (OTP programming option)
1-wire PWM connection
Analog output
Analog Sin/Cos outputs with external interpolator
Serial 3-Wire Connection (Default Setting)
In this mode, the AS5130 is connected to the external controller via three SSI signals: Chip Select (CS), Clock (CLK)
input and DIO (Data) in/output. This configuration not only helps to read and write data but also defines different
operation modes. The data transfer in all cases is done via the DIO port.
Figure 3. Standard SSI Serial Data Interface
+5V
AVDD
VDD
VDD
CS
micro
controller
CLK
DIO
100n
AS5130
VSS
VSS
VSS
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AS5130
Data Sheet - Detailed Description
Figure 4. Normal Operation Mode
CMD_PHASE
DATA_PHASE
DCLK
t1
t9
t0
CS
t5
DIO
CMD
CMD4
LO
CMD0
t7
t8
t3
t10
t6
t4
DIO
DIO
READ
D 15
D 14
D0
t11
t10
t12
WRITE
D 15
D 14
D0
Table 6. Serial Bit Sequence (16bit read/write)
Write Command
Read/Write Data
C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 5. Extended Operation Mode (for access of OTP only)
CMD_PHASE
DATA_PHASE_EXTENDED
DCLK
t0 t1
t9
CS
t5
CMD
DIO
CMD4
HI
CMD2
CMD0
t7
t10
t3
t8
t6
t4
DIO
DIO
READ
D45
D45
D44
D44
D0
t11
t10
t12
WRITE
D0
Table 7. Serial Bit Sequence (16bit read/write)
Write Command
Read/Write Data
C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
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AS5130
Data Sheet - Detailed Description
Serial 3-Wire Connection (OTP Programming Option)
This mode provides with an option to configure the serial interface for programming the OTP register. Using a clock
input (CLK), DIO (Data) in/output and CS pin, it is possible to write and read out data from the OTP Register. The data
transfer is done via the DIO channel. For programming, the PROG pin must be connected to +8V. Analog readout for
trimming verification is mandatory.
Figure 6. Serial Data Transmission in Continuous Readout Mode
+5V
AVDD
VDD
VDD
CS
micro
controller
DCLK
AS5130
100n
DIO
+8V
PROG
VSS
VSS
VSS
1-Wire PWM Connection
If the line (PWM) is used as angle output, the total number of connections can be reduced to three, including the
supply lines. This type of configuration is especially useful for remote sensors. Low power mode is not possible in this
configuration. If the AS5130 angular data is invalid, the PWM output will remain at low state.
Figure 7. Data Transmission with Pulse Width Modulated (PWM) Output
+5V
AVDD
VDD
VDD
micro
controller
AS5130
100n
PWM
VSS
VSS
VSS
The minimum PWM pulse width tON (PWM = high) is 1 LSB @ 0º (Angle reading = 00H). 1LSB = nom. ,0.556µs. The
PWM pulse width increases with 1LSB per step. At the maximum angle 358.6º (Angle reading = FFH), the pulse width
tON (PWM = high) is 256 LSB and the pause width tOFF (PWM = low) is 1 LSB. This leads to a total period (tON + tOFF
of 257LSB.
)
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AS5130
Data Sheet - Detailed Description
Figure 8.
PWM out
t
on
71.7µs
142.3µs
0.556µs
5V
5V
t
off
142.3µs
71.15µs
128
0.556µs
Position
0
255
Table 8.
Position
0
Angle
0º
High
1
t_high
Low
t_low
142,3
Duty-Cycle
0,556
71,15µs
71,7µs
142,3µs
256
129
128
1
0.39%
49.4%
50.2%
99.6%
127
178.59
180º
128
129
256
71,7µs
71,15µs
0,556µs
128
255
358.59º
This means that the PWM pulse width is (position + 1) LSB, where position is 0….255.
The tolerance of the absolute pulse width and frequency can be eliminated by calculating the angle with the duty cycle
rather than with the absolute pulse width:
tON
⎛
⎞
⎠
--------------------------
angle [ 8 - bit ] = 257
-1
(EQ 1)
⎝
tON + tOFF
results in an 8-bit value from 00H to FFH,
angle [ º ] =
tON
⎠
tON + tOFF
360
--------
⎛
⎝
⎞
–1
--------------------------
257
(EQ 2)
256
results in a degree value from 0º ...358.6º
Note: The absolute frequency tolerance is eliminated by dividing tON by (tON+TOFF), as the change of the absolute
timing effects both TON and TOFF in the same way.
Analog Output
The AS5130 can generate a ratiometric analog output voltage by low-pass filtering the PWM output. Figure 9 shows a
simple passive 2nd order low pass filter as an example. In order to minimize the ripple on the analog output, the cut-off
frequency of the low pass filter should be well below the PWM base frequency.
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AS5130
Data Sheet - Detailed Description
Figure 9. Ratiometric Analog Output
+5V
AVDD
VDD
VDD
micro
controller
AS5130
PWM
R≥4k7
C≥1µF
analog
out
100n
VSS
VSS
VSS
Figure 10.
5V
Analog out
0V
PWMout
Angle
0º
180º
360º
Analog Sin/Cos Outputs with External Interpolator
By connecting C1 to VDD, the AS5130 provides analog Sine and Cosine outputs (SINP, COSP) of the Hall array front-
end for test purposes. These outputs allow the user to perform the angle calculation by an external ADC + µC, e.g. to
compute the angle with a high resolution. In addition, the inverted Sinus and Cosine signals (SINN, COSN; see dotted
lines) are available for differential signal transmission.
The input resistance of the receiving amplifier or ADC should be greater than 100kΩ. The signal lines should be kept
as short as possible, longer lines should be shielded in order to achieve best noise performance.
The SINN / COSN / SINP / COSP signals are amplitude controlled to ~1.3Vp (differential) by the internal AGC
controller. The DC bias voltage is 2.25 V.
If the SINN and COSN outputs cannot be sampled simultaneously, it is recommended to disable the automatic gain
control (see Table 9) as the signal amplitudes may be changing between two readings of the external ADC. This may
lead to less accurate results.
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AS5130
Data Sheet - Detailed Description
Figure 11. Sine and Cosine Outputs for External Angle Calculation
+5V
VDD
VDD
C1
VDD
SINN
SINP
D
D
A
A
micro
controller
AS5130
100n
COSN
COSP
VSS
VSS
VSS
Serial Synchronous Interface (SSI)
Commands of the SSI in Normal Mode
Table 9. SSI in Normal Mode
#
cmd
bin
mode
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WRITE
CUST
wlsb_ wlsb_ wlsb wlsb wlsb wlsb wlsb gain gain gain
23
10111
write
nc
nc
nc
nc
nc
nc
6
5
_4
_3
_2
_1
_0
_2
_1
_0
xen_
7
xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_
22
WD2COS
10110
write
inv_7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
SET TEST
CFG1
gen_
rst
21
20
10101
10100
10011
write
write
write
reserved
rst_ot
p
rst_multi setHyst
19 HYST_RST
xen_
7
xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_
18
WD2SIN
10010
write
inv_7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
WRITE
go2sl
eep
17
16
7
10001
10000
write
write
read
CONFIG
--
wlsb_ wlsb_ wlsb wlsb wlsb wlsb wlsb gain gain gain
6
parit
y
READ CUST 00111
nc
nc
nc
nc
nc
5
_4
_3
_2
_1
_0
_2
_1
_0
xen_
7
xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_
6
RD2COS
00110
read
inv_7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
5
4
00101
00100
read
read
RD_BOTH
Multiturn <7:0>
angle <7:0>
angle_stored <7:0>
store vdd_ reg_
parit
y
3
2
1
0
STORE REF 00011
read
read
read
read
nc
nc
nc
nc
_ok
ok
set
xen_
7
xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_ xen_ inv_
RD2SIN
00010
00001
inv_7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
parit
y
RD_MULTI
lock
lock
agc <5:0>
agc <5:0>
Multiturn <7:0>
angle <7:0>
parit
y
RD_ANGLE 00000
WD2COS / WD2SIN: xen_X disables Hall element X from the sensor array in the cosine or sine channel; xinv_X
inverts the voltage output of Hall element X in the channels.
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Revision 1.00
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AS5130
Data Sheet - Detailed Description
RD2COS / RD2SIN: The Hall array configuration for cosine and sine channel can be read out by these commands,
initial values are 0.
SET TEST CFG 1: gen_rst HI triggers a digital reset.
WRITE CONFIG: go2sleep HI activates the sleep mode of the AS5130. The power consumption is significantly
reduced. go2sleep LO returns to normal operation mode. During sleep mode, the lock bit in command 0 and command
1 is LO.
WRITE CUST: With “wlsb_x” the threshold level for generation of a WAKE pulse is set (only important in polling mode).
The initial value is 4 LSB. No value lower than 4 LSB can be set. The maximum value is 127 LSB.
“gain_x” sets the gain in the signal
HYST_RST: “setHyst” enables an additional hysteresis of the digital output signal. It is enabled by default. Only after 2
consecutive equal signals the output is changed.
“rst_otp” forces the IC to read out the OTP in polling mode. This reset has to be performed after initial startup and
every WAKE signal.
“rst_multi” resets the multi turn counter to 0.
READ CUST: With this command “wlsb_x” and “gain_x” can be read out.
RD_BOTH: Angle and multi turn counter value can be read out simultaneously by this command. Due to limited data
size, the parity bit is not available in this command.
STORE REF: This command stores the actual angle as reference angle in the storage registers (only important in
polling mode). The output is the stored angle (angle_stored), a flag, if the voltage at DVDD is OK (store_ok), a flag, if
the supply voltage is OK (vdd_ok) and a check bit, if the register was written.
RD_MULTI: Command for read out of multi turn register (multiturn) and AGC value (agc). “Lock” indicates a locked
ADC and “parity” an even parity checksum.
RD_ANGLE: Command for read out of angle value and AGC value (agc). “Lock” indicates a locked ADC and “parity”
an even parity checksum.
Commands of the SSI in Extended Mode
For programming or readout of the OTP data, the chip has to be started with DVDD at a low voltage (polling mode off or
cap discharged) or the OTP reset has to be performed. If not, the OTP is not read out and the OTP data is not
available.
Table 10. SSI in Extended Mode
#
cmd
bin
mode <45:44> <43:32> <31:28> <27:26> <25> <24:23> <22:20> <19:16> <15:12> <11:9> <8>
<7:0>
WRITE_
OTP
OTP
Test
OTP
lock
Hall
Bias
Redund Sensiti Wake
ancy vity
Zero
31
11111 xt write
ID
VREF
Osc
enable Angle
30
29
28
27
26
11110 xt write
11101 xt write
11100 xt write
11011 xt write
11010 xt write
PROG_
OTP
OTP
Test
OTP
lock
Hall
Redund Sensiti Wake
Zero
25
24
15
11001 xt write
11000 xt write
01111 xt read
ID
ID
VREF
VREF
Osc
Osc
Bias
ancy vity enable Angle
OTP
Test
OTP
lock
Hall
Bias
Redund Sensiti Wake
Zero
ancy
vity
enable Angle
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Revision 1.00
16 - 41
AS5130
Data Sheet - Detailed Description
Table 10. SSI in Extended Mode
#
cmd
bin
mode <45:44> <43:32> <31:28> <27:26> <25> <24:23> <22:20> <19:16> <15:12> <11:9> <8>
<7:0>
14
13
12
11
10
01110 xt read
01101 xt read
01100 xt read
01011 xt read
01010 xt read
RD_OTP
_ANA
9
8
01001 xt read
01000 xt read
WRITE OTP: Writing of the OTP register. The written data is volatile. “Zero Angle” is the angle, which is set for zero
position. “Wake enable” enables the polling mode. “Sensitivity” is the gain setting in the signal path. “Redundancy is a
number of bits, which allows the customer to overwrite one of the customer OTP bits <0:11>.
PROG_OTP: Programming of the OTP register. Only Bits <0:15> can be programmed by the customer.
RD_OTP: Read out the content of the OTP register. Data written by WRITE_OTP and PROG_OTP is read out.
RD_OTP_ANA: Analog read out mode. The analog value of every OTP bit is available at pin 2 (PROG), which allows
for a verification of the fuse process. No data is available at the SSI.
OTP Programming
For programming of the OTP, an additional voltage has to be applied to the pin PROG. It has to be buffered by a fast
100nF capacitor (ceramic) and a 10µF capacitor. The information to be programmed is set by command 25. The OTP
bits 16 to 45 are used for AMS factory trimming and cannot be overwritten.
Figure 12. OTP Programming Connection
+5V
AVDD
VDD
Output
VDD
CS
Output
I/O
DCLK
DIO
100n
AS5130
micro
controller
8.0 - 8.5V
+
PROG
C1
100n
10µF
VSS
VSS
VSS
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AS5130
Data Sheet - Detailed Description
Figure 13. External Circuitry for OTP Programming
maximum
parasiticcable
inductance
VSUPPLY
L<50nH
VDD
Vzapp
Vprog
PROG
GND
C1
C2
PROM Cell
100nF
10µF
Table 11.
Symbol
Parameter
Supply Voltage
Ground Level
Min
5
Max
Unit
V
Notes
VDD
GND
5.5
0
0
V
V_zapp
T_zapp
f_clk
Programming Voltage
Temperature
8
8.5
85
V
At pin PROG
At pin DCLK
0
ºC
kHz
CLK Frequency
100
Programming Verification
After programming, the programmed OTP bits are verified in following two ways:
By Digital Verification: This is simply done by sending a READ OTP command (#0FH, Refer to Table 10). The
structure of this register is the same as for the OTP PROG or OTP WRITE commands.
By Analog Verification: By sending an ANALOG OTP READ command (#09H), pin PROG becomes an output,
sending an analog voltage with each clock, representing a sequence of the bits in the OTP register. A voltage of
<500mV indicates a correctly programmed bit (“1”) while a voltage level between 2.2V and 3.5V indicates a correctly
unprogrammed bit (“0”). Any voltage level in between indicates improper programming.
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AS5130
Data Sheet - Detailed Description
Figure 14. Analog OTP Verification
+5V
VDD
13
VDD
VDD
Output
11
10
12
CS
Output
I/O
CLK
DIO
AS5130
100n
micro
controller
2
PROG
VSS
C2
C1
VSS
V
15
3
14
VSS
Redundancy Decoding
If a bit is not fused properly (analog readout levels violated), the redundancy bits can be used as shown in the table
below. Only one single bit can be overwritten with a logic HI. An improper fusing cannot be made undone.
Table 12.
<15:12>
0000
0001
0010
0011
0100
0101
0110
0111
replaced bit
<15:12>
1000
1001
1010
1011
1100
1101
1110
replaced bit
none
7
8
0
1
2
3
4
5
6
9
10
11
none
none
none
1111
Multi Turn Counter
An 8-bit register is used for counting the magnet’s revolutions. With each zero transition in any direction, the output of
a special counter is incremented or decremented. The initial value after reset is 0 LSB.
The multi turn value is encoded as complement on two. Clockwise rotation gives increasing angle values and positive
turn count. Counter clockwise rotation exhibits decreasing angle values and a negative turn count respectively.
Table 13.
Bit Code
01111111
---
Decimal Value
127
---
+3
+2
+1
0
00000011
00000010
00000001
00000000
11111111
-1
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Revision 1.00
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AS5130
Data Sheet - Detailed Description
Table 13.
Bit Code
11111110
11111101
---
Decimal Value
-2
-3
---
10000000
-128
The counter output can be reset by using command 19 – HYST_RST. It is immediately reset by the rising clock edge of
this bit. Any zero crossing between the clock edge and the next counter readout changes the counter value.
AS5130 Status Indicators
Lock Status Bit
The Lock signal indicates whether the angle information is valid (ADC locked, Lock = high) or invalid (ADC unlocked,
Lock = low). To determine a valid angular signal at best performance, the following indicators should be set:
Lock = 1
AGC = >00H and < 2FH
Note: The angle signal may also be valid (Lock = 1), when the AGC is out of range (00H or 2FH), but the accuracy of
the AS5130 may be reduced due to the out of range condition of the magnetic field strength.
Magnetic Field Strength Indicators
The AS5130 is not only able to sense the angle of a rotating magnet, it can also measure the magnetic field strength
(and hence the vertical distance) of the magnet. This additional feature can be used for several purposes:
- as a safety feature by constantly monitoring the presence and proper vertical distance of the magnet
- as a state-of-health indicator, e.g. for a power-up self test
- as a pushbutton feature for rotate-and-push types of manual input devices
The magnetic field strength information is available in two forms – Magnetic field strength hardware indicator and
Magnetic field strength software indicator.
Magnetic Field Strength Hardware Indicator
Pin CAO (#1) will be low, when the magnetic field is too weak. The switching limit is determined by the value of the
AGC. If the AGC value is <3FH , the CAO output will be high (green range), If the AGC is at its upper limit (3FH), the
CAO output will be low (red range).
Magnetic Field Strength Software Indicator
D13:D7 in the serial data that is obtained by command READ ANGLE (see Table 9) contains the 6-bit AGC
information. The AGC is an automatic gain control that adjusts the internal signal amplitude obtained from the Hall
elements to a constant level. If the magnetic field is weak, e.g. with a large vertical gap between magnet and IC, with a
weak magnet or at elevated temperatures of the magnet, the AGC value will be high. Likewise, the AGC value will be
lower when the magnet is closer to the IC, when strong magnets are used and at low temperatures.
The best performance of the AS5130 will be achieved when operating within the AGC range. It will still be operational
outside the AGC range, but with reduced performance especially with a weak magnetic field due to increased noise.
Factors Influencing the AGC Value
In practical use, the AGC value will depend on several factors:
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AS5130
Data Sheet - Detailed Description
ꢀ
ꢀ
ꢀ
The initial strength of the magnet. Aging magnets may show a reducing magnetic field over time which results in
an increase of the AGC value. The effect of this phenomenon is relatively small and can easily be compensated by
the AGC.
The vertical distance of the magnet. Depending on the mechanical setup and assembly tolerances, there will
always be some variation of the vertical distance between magnet and IC over the lifetime of the application using
the AS5130. Again, vertical distance variations can be compensated by the AGC.
The temperature and material of the magnet. The recommended magnet for the AS5130 is a diametrically mag-
netized 6mm diameter magnet. Other magnets may also be used as long as they can maintain to operate the
AS5130 within the AGC range. Every magnet has a temperature dependence of the magnetic field strength. The
temperature coefficient of a magnet depends on the used material. At elevated temperatures, the magnetic field
strength of a magnet is reduced, resulting in an increase of the AGC value. At low temperatures, the magnetic field
strength is increased, resulting in a decrease of the AGC value. The variation of magnetic field strength over tem-
perature is automatically compensated by the AGC.
OTP Sensitivity Adjustment
To obtain best performance and tolerance against temperature or vertical distance fluctuations, the AGC value at
normal operating temperature should be in the middle between minimum and maximum, hence it should be around 32
(20H). To facilitate the “vertical centering” of the magnet+IC assembly, the sensitivity of the AS5130 can be adjusted in
the OTP register in 8 steps (see Table 10). The OTP sensitivity setting corresponds to the customer register setting
gain <2:0>.
“Pushbutton” Feature
Using the magnetic field strength software and hardware indicators described above, the AS5130 provides a useful
method of detecting both rotation and vertical distance simultaneously. This is especially useful in applications
implementing a rotate-and-push type of human interface (e.g. in panel knobs and switches).
The CAO output is low, when the magnetic field is below the low limit (weak or no magnet) and high when the magnetic
field is above the low limit (in-range or strong magnet).
A finer detection of a vertical distance change, for example when only short vertical strokes are made by the
pushbutton, is achieved by memorizing the AGC value in normal operation and triggering on a change from that
nominal the AGC value to detect a vertical movement.
Figure 15. Magnetic Field Strength Indicator
+5V
VDD
1k
LED1
VDD
VDD
CAO
CS
Output
AS5130
100n
Output
I/O
DCLK
DIO
VSS
C1
VSS
VSS
High Speed Operation
The AS5130 is using a fast tracking ADC (TADC) to determine the angle of the magnet. The TADC has a tracking rate
of 1.15µs (typ).
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AS5130
Data Sheet - Detailed Description
Once the TADC is synchronized with the angle, it sets the LOCK bit in the status register (see Table 9). In worst case,
usually at start-up, the TADC requires a maximum of 127 steps (127 * 1.15µS = 146,05µs) to lock. Once it is locked, it
requires only one cycle (1.15µs) to track the moving magnet.
The AS5130 can operate in locked mode at rotational speeds up to 30,000 rpm.
In Low Power Mode, the position of the TADC is frozen. It will continue from the frozen position once it is powered up
again. If the magnet has moved during the power down phase, several cycles will be required before the TADC is
locked again. The tracking time to lock in with the new magnet angle can be roughly calculated as:
tLOCK = 1.15µs* |NewPos – OldPos|
(EQ 3)
Where:
tLOCK = time required to acquire the new angle after power up from one of the reduced power modes [µs]
OldPos = Angle position when one of the reduced power modes is activated [º]
NewPos = Angle position after resuming from reduced power mode [º]
Propagation Delay
The Propagation delay is the time required from reading the magnetic field by the Hall sensors to calculating the angle
and making it available on the serial or PWM interface. While the propagation delay is usually negligible on low
speeds, it is an important parameter at high speeds. The longer the propagation delay, the larger becomes the angle
error for a rotating magnet as the magnet is moving while the angle is calculated. The position error increases linearly
with speed. The main factors that contribute to the propagation delay are discussed in detail further in this document.
Sampling Rate
For high speed applications, fast ADC’s are essential. The ADC sampling rate directly influences the propagation
delay. The fast tracking ADC used in the AS5130 with a tracking rate of only 1.15µs (typ) is a perfect fit for both high
speed and high performance.
Chip Internal Lowpass Filtering
A commonplace practice for systems using analog-to-digital converters is to filter the input signal by an anti-aliasing
filter. The filter characteristic must be chosen carefully to balance propagation delay and noise. The lowpass filter in the
AS5130 has a cutoff frequency of typ. 23.8kHz and the overall propagation delay in the analog signal path is typ.
15.6µs.
Digital Readout Rate
Aside from the chip-internal propagation delay, the time required to read and process the angle data must also be
considered. Due to its nature, a PWM signal is not very usable at high speeds, as you get only one reading per PWM
period. Increasing the PWM frequency may improve the situation but causes problems for the receiving controller to
resolve the PWM steps. The frequency on the AS5130 PWM output is typ. 1.95kHz with a resolution of 2µs/step. A
more suitable approach for high speed absolute angle measurement is using the serial interface. With a clock rate of
up to 6MHz, a complete set of data (21bits) can be read in >3.5µs.
Total Propagation Delay of the AS5130
The total propagation delay of the AS5130 is the delay in the analog signal path and the tracking rate of the ADC:
15.6µs + 1.15µs = 16.75µs
(EQ 4)
If only the SIN-/COS-outputs are used, the propagation delay is the analog signal path delay only (typ. 15.6µs).
Position Error Over Speed:
The angle error over speed caused by the propagation delay is calculated as:
Δθpd = rpm * 6 * 16.75E-6 in degrees
(EQ 5)
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AS5130
Data Sheet - Detailed Description
In addition, the anti-aliasing filter causes an angle error calculated as:
Δθlpf = ArcTan [rpm / (60*f0)]
(EQ 6)
Table 14. Examples of the Overall Position Error caused by Speed (includes both propagation delay and filter delay)
Total Position Error (Δθpd + Δθlpf)
Speed (rpm)
100
0,0175º
0,175º
1,75º
1000
10000
Reduced Power Modes
The AS5130 can be operated in three reduced power modes. All three modes have in common that they switch off or
freeze parts of the chip during intervals between measurements. In Low Power Mode or Ultra Low Power Mode, the
AS5130 is not operational, but due to the fast start-up, an angle measurement can be accomplished very quickly and
the chip can be switched to reduced power immediately after a valid measurement has been taken. Depending on the
intervals between measurements, very low average power consumption can be achieved using such a strobed
measurement mode.
ꢀ
Low Power Mode: reduced current consumption, very fast start-up. Ideal for short sampling intervals (<3ms).
ꢀ
Power Cycling mode: zero power consumption (externally switched off) during sampling intervals, but slower start-
up than Polling Mode. Ideal for sampling intervals 200ms.
ꢀ
Polling Mode: for reduction of the average power consumption; especially suited for battery powered applications.
Low Power Mode
The AS5130 can be put in Low Power Mode by simple serial commands, using the regular SSI commands. The
required serial command is WRITE CONFIG (17H, Figure 3 on page 10). The angle data is valid, as soon as the
LOCK- Flag is 1 (see Table 9).
In Reduced Power Modes, the AS5130 is inactive. The last state, e.g. the angle, AGC value, etc. is frozen and the chip
starts from this frozen state when it resumes active operation. This method provides much faster start-up than a “cold
start” from zero.
Figure 16. Low Power Mode and Ultra Low Power Mode Connection
R1
+5V
VDD
ton
toff
Ion
Ioff
VDD
VDD
on/off
C1
CS
micro
controller
100n
N
S
DCLK
DIO
AS5130
VSS
C1
VSS
VSS
Table 15.
Mode
Current Consumption (typ)
Wake-up Time to Active Operation
1.0 ms (without AGC)
3.8 ms(with locked AGC)
Active Operation
Low Power Mode
14mA
1,4mA
0.15 ms
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AS5130
Data Sheet - Detailed Description
If the AS5130 is cycled between active and reduced current mode, a substantial reduction of the average supply
current can be achieved. The minimum dwelling time in active mode is the wake-up time. The actual active time
depends on how much the magnet has moved while the AS5130 was in reduced power mode. The angle data is valid,
when the status bit LOCK has been set (see Table 9). Once a valid angle has been measured, the AS5130 can be put
back to reduced power mode. The average power consumption can be calculated as:
∗
∗
Iactive ton + Ipowerdown toff
---------------------------------------------------------------------
Iavg
=
sampling interval = ton + toff
(EQ 7)
t
on + toff
Where:
Iavg = Average current consumption
Iactive = Current consumption in active mode
Ipower_down = Current consumption in reduced power mode
ton = Time period during which the chip is operated in active mode
toff = Ttime period during which the chip is in reduced power mode
Reducing Power Supply Peak Currents
An optional RC-filter (Rx/Cx) may be added to avoid peak currents in the power supply line when the AS5130 is
toggled between active and reduced power mode. Rx must be chosen such that it can maintain a VDD voltage of 4.5 –
5.5V under all conditions, especially during long active periods when the charge on Cx has expired. Cx should be
chosen such that it can support peak currents during the active operation period. For long active periods, Cx should be
large and Rx should be small.
Power Cycling Mode
The power cycling method shown in Figure 17 cycles the AS5130 by switching it on and off, using an external PNP
transistor high side switch. The current consumption in off-mode is zero. It also has the longest start-up time of all
modes, as the chip must always perform a “cold start “ from zero, which takes about 1.9 ms (Compare with Low Power
Mode on page 23).
Figure 17. Power Cycling Mode
Rx
+5V
VDD
t
on
I
on
0
t
t
on
off
t
off
10k
VDD
VDD
on/off
Cx
>µF
CS
micro
controller
100n
N
S
DCLK
DIO
AS5130
VSS C1
VSS
VSS
The optional filter Rx/Cx may again be added to reduce peak currents in the 5V power supply line (see Reducing
Power Supply Peak Currents on page 24).
Polling Mode
Target of this mode is a reduction of the average power consumption. In this mode, the IC supply is pulsed, thereby
reducing the average power consumption to a fraction. The actual angle information and multi turn count value is not
lost; polling mode is especially suited for battery powered applications. The IC is furthermore capable of generating a
WAKE signal as soon as the magnet’s position has changed, but only if the supply of the IC is powered-on again. By
means of the WAKE signal, the system’s power consumption can be further decreased, if certain modules are
activated on demand.
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AS5130
Data Sheet - Detailed Description
Figure 18. External Circuitry for Polling Mode
+5V
DVDD
>1.5K
VSS
WAKE
VDD
t_wakeup
100n
t_off
t_on
The voltage at pin 16 (DVDD) determines whether polling mode is activated or not. Any voltage above 3.6V activates
the polling functionality. This voltage must always be present at DVDD in order to hold the information in the registers.
The procedure is as follows:
1. Initial startup: The circuit starts up with invalid trim values, which are read back from the storage registers; the
command rst_otp (command 19 – 10011) must be sent to read out valid trim values from the OTP.
2. These values are copied to the storage registers if OTP<8> (Wake enable) is set (must be set for polling
mode).
3. The values of AGC counter, actual angle, multi turn counter, hysteresis setting, wake threshold and gain set-
ting are continuously updated in the storage registers.
4. The actual angle is stored as a reference by sending command STORE REF (command 3 – 00011). without
this reference angle, a WAKE is generated at every startup.
5. The update of the storage registers is stopped if VDD drops below 4.45V and then the information is stored
(DVDD) at the next startup (VDD on), the values are read back from the storage registers and the measured
angle is compared with the stored reference angle; if the difference between both exceeds the threshold, a
WAKE pulse is generated.
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AS5130
Data Sheet - Detailed Description
Figure 19.
VDD on (fast)
POR (40us... 150us)
store_ok
HI
LO
reset & reset_storage
reset digital core only
Retrieve values from storage registers
Wait (162 clks - 86us ... 95us)
WAKE (26 clk periods)
OTP readout (46bit - 140us ... 400us)
WAKE_ON
Compare mode
HI
LO
|α measured – α stored| > α threshold
Normal mode
store_ok ?
true
false
false
Copy to Storage
WAKE (20 clk periods)
command rst_otp
Normal mode
true
OTP readout (OTP <8> = HI
Figure 21 shows the behavior of the wake up signal. The wake up signal will be low for twakeup = 10us. After that, the
wake up signal will go to tri-state condition. In case of an angle comparison with a result below the threshold, the signal
will remain in tri-state condition. After switching on AVDD, the system needs max. 250us to generate an angle with
maximum accuracy. A WAKE signal cannot be expected until the end of this period.
WAKE Interface
An open drain NMOS structure is used in the WAKE pad. In order to generate a clear output signal level, a pull up
resistor is required. The pad can drive 4mA.
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AS5130
Data Sheet - Detailed Description
Figure 20. WAKE Output Pin
AVDD
pull up
resistor
PAD
WAKE
AS5130
Table 16.
Symbol
Parameter
Min
Max
Unit
Notes
The used pad can drive 4mA.
Rpull_up
Pull up resistor
Wake up pulse
1.5
10
100
kΩ
Interrupt signal to external devices, tri-state
output, low active.
twake up
17
µs
ton
toff
On-time
Off-time
250
---
---
---
µs
Time for power up in polling mode. (1)
No limit unless DVDD is always supplied.
ms
Figure 21. Wake Up Signal During Polling Mode of AVDD
t_on
t_off
t_on
AVDD
tri-state
tri-state
WAKE
t_wakeup
delta (actual - reference angle)
</= threshold
delta (actual - reference angle)
> threshold
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AS5130
Data Sheet - Application Information
8 Application Information
Benefits of AS5130
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Complete system-on-chip
Flexible system solution providing absolute angle position, with serial data and PWM output
Ideal for applications in harsh environments due to magnetic sensing principle
High reliability due to non-contact sensing
Robust system, tolerant to misalignment, airgap variations, temperature variations and external magnetic fields
Application Example 1
The AS5130 requires the serial interface via SSI for the programming of the OTP register. This configuration is
recommended for applications, where the supply voltage for the AS5130 is shared among other parallel IC’s during
programming, such as a microcontroller.
Figure 22. Programming via SSI Serial Interface
+5V
AVDD
VDD
VDD
7.7V
+
PROG
DIO
100n
AS5130
Programming
tool
DCLK
CS
VSS
VSS
VSS
Application Example II 3-wire sensor with magnetic field strength indication
In Figure 23, a simple 360º sensor with PWM output is shown. The complete application requires only three wires,
VDD, VSS and the PWM output. The circle over the center of the chip represents the diametrically polarized magnet.
Additionally, the CAO pin will deliver an analog voltage indicating a missing magnetic field. This signal could be used to
drive an external LED or to detect an alert signal.
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AS5130
Data Sheet - Application Information
Figure 23. 3-Wire Angle Sensor
+5V
1k
LED1
VDD PROG
CAO
S
100n
N
PWM out
PWM
AS5130
VSS
VSS
Application Example III: Low-power encoder
Via SSI, the AS5130 will be able to toggle between active mode and low power mode. In active mode, the current
consumption is ~15mA and in sleep mode 2mA. The fastest possible startup time from low power mode is 150µs. The
AS5130 can be periodically switched between active and low power mode, the average power consumption depends
on the duty cycle. In order to read out the correct data, the active mode time must be larger than 150µs.
Figure 24. Low Power Encoder
+5V
AVDD
VDD
VDD
on/off
CS
micro
controller
100n
N
S
CLK
DIO
AS5130
VSS
VSS
VSS
∗
∗
Iactive ton + Ipowerdown toff
---------------------------------------------------------------------
ton + toff
Iavg
=
(EQ 8)
Example: sampling period = one measurement every 10ms.
System constants = Iactive = 15mA, Ipower_down = 2 mA, toff = 9,85ms, ton(min) = 150µs (start-up from low power mode):
∗
∗
15mA 150μs + 2mA 9, 85ms
-------------------------------------------------------------------------
Iavg
=
= 2.195mA
(EQ 9)
150μs + 9, 85ms
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AS5130
Data Sheet - Application Information
Application Example IV: Polling mode
Figure 25. Polling Mode
+5V
AVDD
t
t
off
on
AVDD
VDD
on/off
10k
Cx
>1µF
CS
micro
controller
100n
+5V
N
S
CLK
DIO
AS5130
VSS
VSS
VSS
Once powered up for at least 2.5ms, the AS5130 can be operated in a pulsed mode, where it is periodically turned on/
off by a high side FET (PMOS) switching transistor with a low Ron (<10Ω). The on-time is at least 250µs in order to
perform one measurement. A valid measurement result can be verified by checking the lock bit (ADC is locked) in the
serial data stream.
After startup an OTP reset has to be performed in order to read out valid trimming information. Then a special SSI
command (STORE REF) copies the actual angle into a buffered reference angle register. Now the AS5130 can be
turned off. Special registers will be buffered by the low power supply and will keep the actual settings. After a ton of min.
250 us, the actual angle is compared with the stored reference angle. If the angle difference is larger than a threshold
value (wlsb, SSI command WRITE CUST), the AS5130 will send an interrupt request to an external device via the
WAKE pin.
Due to the internal POR level of the IC, ton starts after VDD has reached 4.3V (worst case POR level).The average
power consumption in this pulsed mode depends on the supply current in active mode and the duty cycle of the on/off
pulse:
∗
Iactive ton
------------------------
Iavg
=
(EQ 10)
ton + toff
Example: Sampling period = one measurement every 100ms. System constants = Iactive = 19mA, ton(min) = 250µs:
∗
19mA 250μs
------------------------------------------
Iavg
=
= 47.5µA
(EQ 11)
250μs + 99.75ms
Accuracy of the Encoder system
This section enlightens on the individual factors that influence the accuracy of the encoder system, and provides
techniques to improve them. Accuracy is defined as the difference between measured angle and actual angle. This is
not to be confused with resolution, which is the smallest step that the system can resolve. The two parameters are not
necessarily linked together. A high resolution encoder may not necessarily be highly accurate as well.
Quantization Error
There is however a direct link between resolution and accuracy, which is the quantization error:
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AS5130
Data Sheet - Application Information
Figure 26. Quantization Error of a Low Resolution and a High Resolution System
Quantization
ideal function
Error
ideal function
digitized
function
digitized
function
low
resolution
high
resolution
+1/2 LSB
+1/2 LSB
error
-1/2 LSB
-1/2 LSB
The resolution of the encoder determines the smallest step size. The angle error caused by quantization cannot get
better than ± ½ LSB. As shown in Figure 26, a higher resolution system (right picture) has a smaller quantization error,
as the step size is smaller. For the AS5130, the quantization error is ± ½ LSB = ± 0.7º
Figure 27. Typical INL Error over 360º
INL including quantization error
1,5
1
0,5
0
-0,5
-1
-1,5
0
45
90
135
180
225
270
315
360
Angle steps
INL
Average (16x)
Figure 27 shows a typical example of an error curve over a full turn of 360º at a given X-Y- displacement. The curve
includes the quantization error, transition noise and the system error. The total error is ~2.2º peak/peak (+/-1.1º).
The sawtooth-like quantization error (see Figure 26) can be reduced by averaging, provided that the magnet is in
constant motion and there are an adequate number of samples available. The solid bold line in Figure 27 shows the
moving average of 16 samples. The INL (intrinsic non-linearity) is reduced to from ~+/- 1.1º down to ~ +/-0.3º. The
averaging however, also increases the total propagation delay, therefore it may be considered for low speeds only or
adaptive; depending on speed (see Position Error Over Speed: on page 22).
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AS5130
Data Sheet - Application Information
Vertical Distance of the Magnet
The chip-internal automatic gain control (AGC) regulates the input signal amplitude for the tracking-ADC to a constant
value. This improves the accuracy of the encoder and enhances the tolerance for the vertical distance of the magnet.
Figure 28. Typical Curves for Vertical Distance versus ACG Value on Several Untrimmed Samples
Linearity and AGC vs Airgap
64
56
48
40
32
24
16
8
2,2
2,0
1,8
1,6
1,4
1,2
1,0
0
0
500
1000
1500
2000
2500
Airgap [mm]
sample#1
sample#2
sample#3
sample#4
Linearity [°]
As shown in Figure 28, the AGC value (left Y-axis) increases with vertical distance of the magnet. Consequently, it is a
good indicator for determining the vertical position of the magnet, for example as a pushbutton feature, as an indicator
for a defective magnet or as a preventive warning (e.g. for wear on a ball bearing etc.) when the nominal AGC value
drifts away. If the magnet is too close or the magnetic field is too strong, the AGC will be reading 0. If the magnet is too
far away (or missing) or if the magnetic field is too weak, the AGC will be reading 63 (3FH).
The AS5130 will still operate outside the AGC range, but the accuracy may be reduced as the signal amplitude can no
longer be kept at a constant level. The linearity curve in Figure 28 (right Y-axis) shows that the accuracy of the AS5130
is best within the AGC range, even slightly better at small airgaps (0.4 – 0.8mm). At very short distances (0 – 0.1) the
accuracy is reduced, mainly due to nonlinearities in the magnetic field. At larger distances, outside the AGC range
(~2.0 – 2.5mm and more) the accuracy is still very good, only slightly decreased from the nominal accuracy. Since the
field strength of a magnet changes with temperature, the AGC will also change when the temperature of the magnet
changes. At low temperatures, the magnetic field will be stronger and the AGC value will decrease. At elevated
temperatures, the magnetic field will be weaker and the AGC value will increase.
Choosing the Proper Magnet
There is no strict requirement on the type or shape of the magnet to be used with the AS5130. It can be cylindrical as
well as square in shape. The key parameter is that the vertical magnetic field Bz measured at a radius of 1mm from the
rotation axis is sinusoidal with a peak amplitude of 20..80mT (see Figure 29).
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AS5130
Data Sheet - Application Information
Figure 29. Vertical Magnetic Fields of a Rotating Magnet
typ. 6mm diameter
N
S
Magnet axis
R1
Vertical field
component
R1 concentric circle;
radius 1.0 mm
Vertical field
component
Bz
(20…80mT)
360
0
360
Magnet Placement
Ideally, the center of the magnet, the diagonal center of the IC and the rotation axis of the magnet should be in one
vertical line. The lateral displacement of the magnet should be within +/-0.25mm from the IC package center or +/-
0.5mm from the IC center, including the placement of the chip within the IC package. The vertical distance should be
chosen such that the magnetic field on the die surface is within the specified limits. The typical distance “z” between
the magnet and the package surface is 0.5mm to 1.8mm with the recommended magnet (6mm x 2.5mm). Larger gaps
are possible, as long as the required magnetic field strength stays within the defined limits. A magnetic field outside the
specified range may still produce acceptable results, but with reduced accuracy. The out-of-range condition will be
indicated, when the AGC is at the limits (AGC= 0 : field too strong; AGC=63=(3FH): field too weak or missing magnet).
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AS5130
Data Sheet - Application Information
Figure 30. Bz Field Distribution Along the X-axis of a 6mmØ Diametric Magnetized Magnet
Bz; 6mm magnet @y=0; z=1mm
N
S
0.001
0.0005
0
-0.0005
-0.001
-0.0015
3.5
2.5
1.5
0.5
-0.5
-1.5
-2.5
-3.5
X-displacement [mm]
Figure 30 shows a cross sectional view of the vertical magnetic field component Bz between the north and south pole
of a 6mm diameter magnet, measured at a vertical distance of 1mm. The poles of the magnet (maximum level) are
about 2.8mm from the magnet center, which is almost at the outer magnet edges. The magnetic field reaches a peak
amplitude of ~+/-106mT at the poles. The Hall elements are located at a radius of 1mm (indicated as squares at the
bottom of the graph). Due to the side view, the two Hall elements at the Y-axis are overlapping at X=0mm, therefore
only 3 Hall elements are shown. At 1mm radius, the peak amplitude is ~+/-46mT, respectively a differential amplitude
of 92mT. The vertical magnetic field Bz follows a fairly linear pattern up to about 1.5mm radius. Consequently, even if
the magnet is not perfectly centered, the differential amplitude will be the same as for a centered magnet.
For example, if the magnet is misaligned in X-axis by -0.5mm, the two X-Hall sensors will measure 70mT (@x= -
1.5mm) and -22mt (@x= -0.5mm). Again, the differential amplitude is 92mT. At larger displacements however, the Bz
amplitude becomes nonlinear, which results in larger errors that mainly affect the accuracy of the system (see Figure
32).
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AS5130
Data Sheet - Application Information
Figure 31. Vertical Magnetic Field Distribution of a Cylindrical 6mmØ Diametric Magnetized Magnet at 1mm Gap
BZ; 6mm magnet @ Z=1mm
area of X-Y-misalignment from
center: +/- 0.5mm
N
circle of Hall elements on
chip: 1mm radius
125
100
75
50
25
0
Bz [mT]
-25
-50
-75
4
-100
-125
3
2
1
4
S
3
0
2
-1
2
-2
1
Y-displacement [mm]
0
-3
-1
X-displacement [mm]
-4
-2
-3
Figure 31 shows the same vertical field component as Figure 30, but in a 3-dimensional view over an area of +/-4mm
from the rotational axis.
Lateral Displacement of the Magnet
As shown in the magnet specifications (see Parameters for Magnet under Electrical Characteristics on page 6), the
recommended horizontal position of the magnet axis with respect to the IC package center is within a circle of 0.25mm
radius. This includes the placement tolerance of the IC within the package.
Figure 32 shows a typical error curve at a medium vertical distance of the magnet around 1.2mm (AGC = 24). The X-
and Y- axis of the graph indicate the lateral displacement of the magnet center with respect to the IC center. At X=Y=0,
the magnet is perfectly centered over the IC. The total displacement plotted on the graph is for ±1mm in both
directions. The Z-axis displays the worst case INL error over a full turn at each given X-and Y- displacement. The error
includes the quantization error of ±0.7º (refer to Quantization Error on page 30). For example, the accuracy for a
centered magnet is between 1.0 – 1.5º (spec = 2º over full temperature range). Within a radius of 0.5mm, the accuracy
is better than 2.0º (spec = 3º over temperature).
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AS5130
Data Sheet - Application Information
Figure 32. Typical Error Curve of INL Error Over Lateral Displacement (including quantization error)
INL vs. Displacement: AS5030 for AGC24
4,500-5,000
4,000-4,500
3,500-4,000
3,000-3,500
2,500-3,000
2,000-2,500
1,500-2,000
1,000-1,500
0,500-1,000
0,000-0,500
5,000
4,500
4,000
3,500
3,000
2,500
1000
750
500
250
INL [°]
2,000
1,500
1,000
0,500
0,000
0
-1000
-750
-250
-500
-500
-750
-1000
Y Displacement [µm]
-250
0
250
500
X Displacement [µm]
750
1000
Magnet Size
Figure 30 to Figure 32 illustrate a cylindrical magnet with a diameter of 6mm. Smaller magnets may also be used, but
since the poles are closer together, the linear range will also be smaller and consequently the tolerance for lateral
misalignment will also be smaller.
If the ±0.25mm lateral misalignment radius (rotation axis to IC package center) is too tight, a larger magnet can be
used. Larger magnets have a larger linear range and allow more misalignment. However at the same time the slope of
the magnet is more flat, which results in a lower differential amplitude. This requires either a stronger magnet or a
smaller gap between IC and magnet in order to operate in the amplitude-controlled area (AGC >0 and AGC < 63).
In any case, if a magnet other than the recommended 6mm diameter magnet is used, two paramters should be
verified:
ꢀ
Verify, that the magnetic field produces a sinusoidal wave, when the magnet is rotated. Note that this can be done
with the SIN-/COS- outputs of the AS5130; e.g. rotate the magnet at constant speed and analyze the SIN- (or
COS-) output with an FFT-analyzer. It is recommended to disable the AGC for this test (see Analog Sin/Cos Out-
puts with External Interpolator on page 14).
ꢀ
Verify that the Bz-Curve between the poles is as linear as possible (see Figure 30). This curve may be available
from the magnet supplier(s). Alternatively, the SIN- or COS- output of the AS5130 may also be used together with
an X-Y- table to get a Bz-scan of the magnet (as in Figure 30 or Figure 31). Furthermore, the sinewave tests
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AS5130
Data Sheet - Application Information
described above may be re-run at defined X-and Y- misplacements of the magnet to determine the maximum
acceptable lateral displacement range. It is recommended to disable the AGC for both these tests (see Analog Sin/
Cos Outputs with External Interpolator on page 14).
Note: For preferred magnet suppliers, please refer to the austriamicrosystems website (Rotary Encoder section).
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AS5130
Data Sheet - Package Drawings and Markings
9 Package Drawings and Markings
The device is available in a 16-Lead Shrink Small Outline Package.
Figure 33. SSOP-16 Package Drawings
AYWWIZZ
AS5130
Table 17. SSOP-16 package dimensions
mm
inch
Typ
Symbol
Min
1.73
0.05
1.68
0.25
0.09
6.07
7.65
5.2
Typ
1.86
0.13
1.73
0.315
-
Max
1.99
0.21
1.78
0.38
0.20
6.33
7.9
Min
Max
A
A1
A2
b
0.068
0.002
0.066
0.010
0.004
0.239
0.301
0.205
0.073
0.005
0.068
0.012
-
0.078
0.008
0.070
0.015
0.008
0.249
0.311
0.212
c
D
6.20
7.8
0.244
0.307
0.209
0.0256
-
E
E1
e
5.3
5.38
0.65
-
K
0º
8º
0º
8º
L
0.63
0.75
0.95
0.025
0.030
0.037
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AS5130
Data Sheet - Package Drawings and Markings
Recommended PCB Footprint
Figure 34. PCB Footprint
Table 18. Recommended Footprint Data
Symbol
mm
9.02
6.16
0.46
0.65
5.01
inch
0.355
0.242
0.018
0.025
0.197
A
B
C
D
E
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AS5130
Data Sheet - Ordering Information
10 Ordering Information
The devices are available as the standard products shown in Table 19.
Table 19. Ordering Information
Model
Description
Delivery Form
Tape & Reel
Tubes
Package
AS5130ATST
AS5130ATSU
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AS5130
Data Sheet - Ordering Information
Copyrights
Copyright © 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement.
austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice.
Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring
extended temperature range, unusual environmental requirements, or high reliability applications, such as military,
medical life-support or life-sustaining equipment are specifically not recommended without additional processing by
austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show
deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
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