AS5263 [AMSCO]
12-Bit Redundant Automotive Angle Position Sensor; 12位冗余汽车角度位置传感器
| 型号： | AS5263 |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | 12-Bit Redundant Automotive Angle Position Sensor |
| 文件： | 总38页 (文件大小：2755K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Datasheet
AS5263
12-Bit Redundant Automotive Angle Position Sensor
1 General Description
The AS5263 is a contactless magnetic angle position sensor for
accurate angular measurement over a full turn of 360º. A sub range
can be programmed to achieve the best resolution for the
2 Key Features
ꢀ
ꢀ
ꢀ
360º contactless high resolution angular position encoding
User programmable start and end point of the application region
User programmable clamping levels and programming of the
transition point
application. The AS5263 includes two AS5163 in one QFN package.
It is a system-on-chip, combining integrated Hall elements, analog
front-end, digital signal processing and best in class automotive
protection features in a single device.
ꢀ
Powerful analog output
- Short circuit monitor
- High driving capability for resistive and capacitive load
Wide temperature range: -40ºC to +150ºC
To measure the angle, only a simple two-pole magnet, rotating over
the center of the chip, is required. The magnet may be placed above
or below the IC.
ꢀ
ꢀ
ꢀ
Small Pb-free package: 32-pin QFN (7x7m)
The absolute angle measurement provides instant indication of the
magnet’s angular position with a resolution of 0.087º = 4096
positions per revolution. The start and end point of the sub segment
will be programmed with a resolution of 14-bit (0.022º= 16384 steps
per revolution). According to this resolution the adjustment of the
application specific mechanical positions are possible. The angular
output data is available over a 12-bit PWM signal or 12-bit ratiometric
analog output.
Broken GND and VDD detectioover a wide ange of different
load cnditions
ꢀ
ꢀ
ꢀ
Simplifid programming duto provided programming hardware
and software
Failure detection me for magnet placement monitoring and
loss of power suply
Indication of gh voltage condition
An internal voltage regulator with over voltage protection and evrs
polarity protection allows the AS5263 to operate in automtive
application up to a voltage to 27V. Programmability ovr the utput
pin reduces the number of pins on the application onneor. The
AS5263 is the ideal solution for safety critical applicaons due to the
redundant approach.
3 Appcations
The AS5263 is ideal for automotive applications like transmission
earboposition sensor, headlight position control, torque sensing,
vae position sensing, pedal position sensing, throttle position
ensing, and non-contact potentiometers.
Figure 1. AS5263 Block Diagram
VDD5_B
VDD3_B
VDD5_T VDD3_T
VDD_T
VDD_B
High voltage/
Reverse polar
protection
AS5263
OTP
Register
Single pin
Interface
Zero
Position
HArray
Full Turn Output
Sin
12-bit
PWM
OUT
Driver
M
U
X
Frontend
Amplifier
CORDIC
14-bit
OUT_T
OUT_B
Angle
Cos
Output
DSP
12
12-bit
DAC
ADC
Programmable
Angle
KDOWN_T
KDOWN_B
Top Silicon Die
Bottom Silicon Die
_T …… Pin of the Top Device
_B …… Pin of the Bottom Device
GND_T GND_B
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AS5263
Datasheet - Contents
Contents
1 General Description ..................................................................................................................................................................
2 Key Features.............................................................................................................................................................................
3 Applications...............................................................................................................................................................................
4 Pin Assignments .......................................................................................................................................................................
4.1 Pin Descriptions....................................................................................................................................................................................
5 Absolute Maximum Ratings ......................................................................................................................................................
6 Electrical Characteristics...........................................................................................................................................................
1
1
1
3
3
5
6
6.1 Operating Conditions...........................................................................................................................................................................
6.2 Magnetic Input Specification...............................................................................................................................................................
6.3 Electrical System Specifications........................................................................................................................................................
6.4 Timing Characteristics........................................................................................................................................................................
7 Detailed Description...............................................................................................................................................................
7
7
8
7.1 Operation..........................................................................................................................................................................................
9
7.1.1 VDD Voltage Monitor............................................................................................................................................................. 9
7.2 Analog Output.............................................................................................................................................................................. 10
7.2.1 Programming Parameters.................................................................................................................................................... 10
7.2.2 Application Specific Angular Range Programming.................................................................................................... 10
7.2.3 Application Specific Programming of the Break Point ........................................................................................................ 11
7.2.4 Full Scale Mode.................................................................................................................................................................... 11
7.2.5 Inverted Dual Channel Output ...................................................................................................................................... 12
7.2.6 Resolution of the Parameters ......................................................................................................................................... 12
7.2.7 Analog Output Diagnostic Mode.......................................................................................................................................... 14
7.2.8 Analog Output Driver Parameters........................................................................................................................................ 14
7.3 Pulse Width Modulation (PWM) Outp......................................................................................................................................... 15
7.4 Kick Down Function............................................................................................................................................................ 16
8 Application Information ........................................................................................................................................................... 18
8.1 Programming the AS5263 .............................................................................................................................................................. 18
8.1.1 Hardware Setup....................................................................................................................................................................... 18
8.1.2 Protocol Timing and Commands SingPin Interface ........................................................................................................... 19
8.1.3 UNBLOCK .......................................................................................................................................................................... 21
8.1.4 WRITE128 ............................................................................................................................................................................... 22
8.1.5 READ128............................................................................................................................................................................... 23
8.1.6 DOWNLOAD............................................................................................................................................................................ 24
8.1.7 UPLOAD.............................................................................................................................................................................. 24
8.1.8 FUSE .................................................................................................................................................................................... 24
8.1.9 PASSFUNC ............................................................................................................................................................................ 25
8.1.10 READ...................................................................................................................................................................................... 25
8.1.11 WRE ..................................................................................................................................................................................... 26
8.2 Programming Data..................................................................................................................................................................... 27
82.1 Read / Write User Data.............................................................................................................................................................. 32
8.2.2 Programming Procedure............................................................................................................................................................ 32
8.2.3 Physical Placement of the Magnet ............................................................................................................................................ 33
8.2.4 Magnet Placement..................................................................................................................................................................... 33
9 Package Drawings and Markings ........................................................................................................................................... 34
10 Ordering Information............................................................................................................................................................. 36
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AS5263
Datasheet - Pin Assignments
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
30 29
28 27
26
25
32
31
24
23
GNDP_B
GNDP_T
NC
NC
1
2
22
21
20
19
KDOWN_B
KDOWN_T
NC_B
NC_T
NC_B
3
4
AS5263
5
6
VDD3_T
VDD3_B
NC_
NC
NC
18
17
7
8
GNDA_T
GNDA_B
9
10
11
12
13
14 15
16
4.1 Pin Descriptions
Table 1 provides the description of each pin of the stanard 32-pin QFN (7x7mm) package. It is recommended to keep the electrical separation
as well on the printed circuit board (PCB) in the appcation (see Table 1).
Table 1. Pin Descriptions
Pin Number
Pin Name
NC
Pin Type
Description
Not bonded
Not bonded
1
2
3
4
-
-
C
Test pin for fabrication. Connected to top ground in the application.
Test pin for fabrication. Connected to bottom ground in the application.
C_T
NC_B
DIO/AIO
multi purpose pin
3.45V- Regulator output, internally regulated from VDD5. This pin
needs an external ceramic capacitor of 2.2μF. Connect second terminal of
capacitor to GND intended for the top die.
5
6
VDD3_T
VDD3_B
3.45V- Regulator output, internally regulated from VDD5. This pin
needs an external ceramic capacitor of 2.2μF. Connect second terminal of
capacitor to GND intended for the bottom die.
Supply pin
Analog ground pin. Connected to GND for the top die in the application.
7
8
GNDA_T
GNDA_B
Analog ground pin. Connected to GND intended for the bottom die in the
application.
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AS5263
Datasheet - Pin Assignments
Table 1. Pin Descriptions
Pin Number
Pin Name
Pin Type
Description
Test pin for fabrication. Connected to GND intended for the top die in
the application.
9
NC_T
NC_B
Test pin for fabrication. Connected to GND intended for the bottom die
in the application.
DIO/AIO
multi purpose pin
10
Test pin for fabrication. Open in the application.
Test pin for fabrication. Open in the application.
11
12
NC
NC
Digital ground pin. Connected to GND intended for the top die in the
application.
13
14
15
16
GNDD_T
GNDD_B
NC_T
Supply pin
Digital ground pin. Connected to GND intended for the bottom de in
application.
Test pin for fabrication. Connected to GND intended for the top die in
the application.
DIO/AIO
multi purpose pin
Test pin for fabrication. Connected to GND intendefor the bottom die
in the application.
NC_B
Not boned
Not bonde
17
18
NC
NC
-
-
Tor fabrication. Concted to GND intended for the top die in
the pplication.
19
20
21
NC_T
NC_B
DIO/AIO
multi purpose pin
Test pin for fabricationConected to GND intended for the bottom die
in the application.
Kick down funcnaliy. Open drain user pull-up resistor connected to
the intendeDD top supply.
KDOWN_T
Digital otput open
drai
Kick dowfunctionality. Open drain user pull-up resistor connected to
the innded VDD bottom supply.
22
23
24
KDOWN_B
GNDP_T
GNDP_B
og ground pin. Connected to GND for the top die in the application.
Supply pin
log ground pin. Connected to GND intended for the bottom die in the
application.
Test pin for fabrication. Connected to GND intended for the top die in
the application.
25
26
27
28
NC_T
NC_B
Test pin for fabrication. Connected to GND intended for the bottom die
in the application.
O/AIO
multi purpose pin
Output pin. Can be programmed as analog output or PWM output. Over
this pin the programming of the top die is possible.
OUT_T
OT_B
Output pin. Can be programmed as analog output or PWM output. Over
this pin the programming of the bottom die is possible.
Positive supply pin. This pin is over voltage protected.
Positive supply pin. This pin is over voltage protected.
29
30
VD_T
VDD_B
4.5V- Regulator output, internally regulated from VDD. This pin needs
an external ceramic capacitor of 2.2μF. Connect second terminal of
capacitor to GND intended for the top die.
3
32
VDD5_T
VDD5_B
Supply pin
4.5V- Regulator output, internally regulated from VDD. This pin needs
an external ceramic capacitor of 2.2μF. Connect second terminal of
capacitor to GND intended for the bottom die.
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AS5263
Datasheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 6 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Comments
Electrical Parameters
DC supply voltage at pin VDD
Overvoltage
VDD
-18
27
V
No operation
permanent
Output voltage OUT
VOUT
VKDOWN
VDD3
VDD5
Iscr
-0.3
-0.3
-0.3
-0.3
-100
27
27
5
V
V
Output voltage KDOWN
DC supply voltage at pin VDD3
DC supply voltage at pin VDD5
Input current (latchup immunity)
V
7
V
100
mA
Norm: JEDC 78
Electrostatic Discharge
Norm: MIL 88E method 3015
This value is pplcble to pins VDD, GND, OUT,
ad KDOWN.
Electrostatic discharge
ESD
±4
V
ºC
All other pins ±2 kV.
Temperature Ranges and Storage Conditions
Tstrg
Storage temperature
-55
+150
Min -67ºF; Max +257ºF
t=20 to 40s,
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020 “Moisture/Reflow
Sensitivity Classification for Non-Hermetic Solid
State Surface Mount Devices”.
TBody
Body temperature (Lead-free pacge)
260
85
ºC
%
The lead finish for Pb-free leaded packages is
matte tin (100% Sn).
Humidity non-condensing
Moisture Sensitive Level
H
5
MSL
3
Represents a maximum floor life time of 168h
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AS5263
Datasheet - Electrical Characteristics
6 Electrical Characteristics
6.1 Operating Conditions
In this specification, all the defined tolerances for external components need to be assured over the whole operation conditions range and also
over lifetime.
TAMB = -40 to +150ºC, VDD = +4.5V to +5.5V, CLREG5 = 2.2µF, CLREG3 = 2.2µF, RPU = 1KΩ, RPD = 1KΩ to 5.6KΩ (Analog only),
CLOAD = 0 to 42nF, RPUKDWN = 1KΩ to 5.6KΩ, CLOAD_KDWN = 0 to 42nF, unless otherwise specified. A positive current is intended to flow into
the pin.
Table 3. Operating Conditions
Symbol
TAMB
Isupp
Parameter
Ambient temperature
Supply current
Conditions
-40ºF…+302ºF
Min
Typ
Max
+150
20
Unit
ºC
-40
Lowest magnetic input field
mA
6.2 Magnetic Input Specification
TAMB = -40 to +150ºC, VDD5 = 4.5 - 5.5V (5V operation), unless otherwise noted.
Two-pole cylindrical diametrically magnetized source:
Table 4. Magnetic Input Specification
Symbol
Bpk
Parameter
itions
Min
Typ
Max
Units
Required vical component of the
magnetic field stngth on the die’s srfac,
measured along a concentric circle with a
radius of 1.1mm
Magnetic input field amplitude
30
70
mT
Boff
Magnetic offset
Constant magntic strfiel
Including offset gdient
±10
5
mT
%
Field non-linearity
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AS5263
Datasheet - Electrical Characteristics
6.3 Electrical System Specifications
TAMB = -40ºC to +150ºC, VDD = 4.5V - 5.5V (5V operation), Magnetic Input Specification; unless otherwise noted.
Table 5. Electrical System Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RES
Resolution Analog and PWM Output
Angular operating range ≥ 90ºC
12
bit
Maximum error with respect to the best line fit.
Centered magnet without calibration,
TAMB=25ºC
Integral non-linearity (optimum)
360 degree full turn
INLopt
±0.5
±0.9
deg
deg
Maximum error with respect to the best line fit.
Centered magnet without calibration,
TAMB = -40 to +150ºC
Integral non-linearity (optimum)
360 degree full turn
INLtemp
Best line fit = (Errmax – Errmin) / 2
Over displacement tolerance with 6mm
diameter magnet, without calibration,
TAMB = -40 to +150ºC
Integral non-linearity
360 degree full turn
INL
±14
0.06
deg
Note: This parameter is a system parameter
and is dependent on the selected magnet.
1 sigma;
Note: The noise perforance is dependent
on the programof the output
characteristic.
Deg
RMS
TN
Transition noise
VDD5LowTH
VDD5HighTH
tPwrUp
Undervoltage lower threshold
Undervoltage higher threshold
Power-up time
3.1
3.6
3.4
3.9
3.7
4.2
10
VDD5 = 5V
V
ms
System propagation delay
absolute output: delay of ADC,
DSP and absolute inteac
Fast mode, times 2 in ow mode
tdelay
100
µs
Note: The INL performance is specified over the full turn of 360 d. An operation in an angle segment increases the accuracy. A two
point linearization is recommended to achieve the bst INL performance for the chosen angle segment.
6.4 Timing Characteristics
Table 6. Timing Conditions
Symbol
FRCOT
TCLK
Parameter
Conditions
Min
4.05
202
Typ
4.5
Max
4.95
247
12
Units
MHz
ns
Internal Master lock
Interface ClocTime
TCLK = 1/ FRCOT
222.2
TDETWD
WatchDog error etection time
ms
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AS5263
Datasheet - Detailed Description
7 Detailed Description
The AS5263 is manufactured in a CMOS process and uses a spinning current Hall technology for sensing the magnetic field distribution across
the surface of the chip.
The integrated Hall elements are placed around the center of the device and deliver a voltage representation of the magnetic field at the surface
of the IC.
Through Sigma-Delta Analog / Digital Conversion and Digital Signal-Processing (DSP) algorithms, the AS5263 provides accurate high-resolution
absolute angular position information. For this purpose a Coordinate Rotation Digital Computer (CORDIC) calculates the angle and the
magnitude of the Hall array signals.
The DSP is also used to provide digital information at the outputs that indicate movements of the used magnet towards or away from the device’s
surface.
A small low cost diametrically magnetized (two-pole) standard magnet provides the angular position information (see Figure 26).
The AS5263 senses the orientation of the magnetic field and calculates a 14-bit binary code. This code is mapped to a programmable oput
characteristic. The type of output is programmable and can be selected as PWM or analog output. This signal is available at the pins 27, 8
(OUT_T, OUT_B).
The analog output and PWM output can be configured in many ways. The application angular region can be programmed a usr friendly way.
The starting angle T1 and the end point angle T2 can be set and programmed according the mechanical range of the aplicaon with a
resolution of 14 bits. In addition the T1Y and T2Y parameter can be set and prorammed according the applicationThe transition point 0 to 360
degree can be shifted using the break point parameter BP. This point is progrmmable h a high resolution of 14 bits of 360 degrees. The
voltage for clamping level low CLL and clamping level high CLH can be programmed wth a resolution of 7 itBh levels are individually
adjustable.
These parameters are also used to adjust the PWM duty cycle.
The AS5263 provides also a compare function. The internal angular code is compared to a programmable level using hysteresis. The function is
available over the output pins 21, 22 (KDOWN_T, KDOWN_).
The output parameters can be programmed in an OTP reister. No additional voltage quired to program the AS5263. The setting may be
overwritten at any time and will be reset to default whepowr is cycled. To make setng permanent, the OTP register must be programmed
by using a lock bit the content could be frozen for ver.
The AS5263 is tolerant to magnet misalignmenand uwanted external manetic flds due to differential measurement technique and Hall
sensor conditioning circuitry.
It is also tolerant to air gap and temperature variations due to Sin-/Cal evaluation.
The AS5263 is tolerant to magnet misalignment and magnetistray fields due to differential measurement technique and Hall sensor
conditioning circuitry.
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AS5263
Datasheet - Detailed Description
7.1 Operation
The AS5263 operates at 5V ±10%, using two internal Low-Dropout (LDO) voltage regulators. For operation, the 5V supply is connected to pin
VDD. While VDD3 and VDD5 (LDO outputs) must be buffered by 2.2µF capacitors, the VDD requires a 1µF capacitor. All capacitors (low ESR
ceramic) are supposed to be placed close to the supply pins (see Figure 3).
The VDD3 and VDD5 outputs are intended for internal use only. It must not be loaded with an external load.
Figure 3. External Circuitry for the AS5263 (figure shows only one sensor die)
5V Operation
2.2µF
2.2µF
VDD5_T
VDD3_T
LDO
1µF
VDD_T
LDO
Inteal
VDD4.5V
Internal
VD3.45V
4.5 - 5.5V
GNDD_T
GNDA_T
GNDP_T
Notes:
1. The pins VDD3 and VDD5 must lways be buffered by a capacitor. These pins must not be left floating, as this may
cause unstable internal supply voltges, which may lead to larger output jitter of the measured angle.
2. Only VDD is overvoltage protectup to 27V. In addition, the VDD has a reverse polarity protection.
7.1.1 VDD Voltae Montor
VDD Overvoltage Management. If the voltage applied to the VDD pin exceeds the overvoltage upper threshold for longer than the detection
time, then the deice eters a low power mode reducing the power consumption. When the overvoltage event has passed and the voltage
applied to DD pin falls below the overvoltage lower threshold for longer than the recovery time, then the device enters the normal mode.
VD5 Undervoltage Management. When the voltage applied to the VDD5 pin falls below the undervoltage lower threshold for longer than
the V5_detection time, then the device stops the clock of the digital part and the output drivers are turned off to reduce the power
consumption. When the voltage applied to the VDD5 pin exceeds the VDD5 undervoltage upper threshold for longer than the VDD5_recovery
time, then the clock is restarted and the output drivers are turned on.
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AS5263
Datasheet - Detailed Description
7.2 Analog Output
The reference voltage for the Digital-to-Analog converter (DAC) is taken internally from VDD. In this mode, the output voltage is ratiometric to the
supply voltage.
7.2.1 Programming Parameters
The Analog output voltage modes are programmable by OTP. Depending on the application, the analog output can be adjusted. The user can
program the following application specific parameters:
Mechanical angle start point
Mechanical angle end point
Voltage level at the T1 position
Voltage level at the T2 position
Clamping Level Low
T1
T2
T1Y
T2Y
CLL
CLH
BP
Clamping Level High
Break point (transition point 0 to 360 degree)
The above listed parameters are input parameters. Over the provided programming software and programmer, tese paameters are converted
and finally written into the AS5263 128-bit OTP memory. More details about thconverion can be found in the ANAS5163+AS5263_V1.0
application note.
7.2.2 Application Specific Angular Range Programming
The application range can be selected by programming T1 with a related Y and T2 with a related T2into the AS5263. The internal gain factor
is calculated automatically. The clamping levels CLL and CLH can be progammed independent frm the T1 and T2 position and both levels can
be separately adjusted.
Figure 4. Programming of an Individual Application Rang
90 degree
plication range
electrical range
T2
mechanical range
clamping range
high
T1
100%VDD
CLH
T2Y
0 degree
CLL
180 degree
T1Y
CLH
BP
CLL
0
clamping range
low
T1
T2
70 degree
Figure 4 sha simple example of the selection of the range. The mechanical starting point T1 and the mechanical end point T2 define the
mehanicang. A sub range of the internal Cordic output range is used and mapped to the needed output characteristic. The analog output
igal has 12 bit, hence the level T1Y and T2Y can be adjusted with this resolution. As a result of this level and the calculated slope the clamping
region ow is defined. The break point BP defines the transition between CLL and CLH. In this example, the BP is set to 0 degree. The BP is also
the end point of the clamping level high CLH. This range is defined by the level CLH and the calculated slope. Both clamping levels can be set
independently form each other. The minimum application range is 12 degrees.
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AS5263
Datasheet - Detailed Description
7.2.3 Application Specific Programming of the Break Point
The break point BP can be programmed as well with a resolution of 14 bits. This is important when the default transition point is inside the
application range. In such a case, the default transition point must be shifted out of the application range. The parameter BP defines the new
position. The function can be used also for an on-off indication.
Figure 5. Individual Programming of the Break Point BP
90 degree
Application range
electrical range
T2
clamping range
high
mechanical range
T1
100%VDD
CLH
CLH
T2Y
0 degree
180 degree
T1Y
CLL
CLL
BP
ping range
low
T1
T2
clamping range
low
270 degree
7.2.4 Full Scale Mode
The AS5263 can be programmed as well in he ll scale mode. The BP parmeter defines the position of the transition.
Figure 6. Full Scale Mode
100 % VDD
0
360
For simplification, Figure 6 describes a linear output voltage from rail to rail (0V to VDD) over the complete rotation range. In practice, this is not
feasible due to saturation effects of the output stage transistors. The actual curve will be rounded towards the supply rails (as indicated Figure 6).
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AS5263
Datasheet - Detailed Description
7.2.5 Inverted Dual Channel Output
The AS5263 can be programmed as described in Figure 7.
Figure 7. Inverted Slope Output
electrical range
mechanical range
100%VDD
CLH
CLH
T2Y
T1Y
CLL
CLL
0
100%VDD
CLH
CLH
T1Y
T2Y
C
0
CLL
T1
T2
7.2.6 Resolution of the Parametes
The programming parameters have a wide esolution of up to 14 bits.
Table 7. Resolution of the Progaming Parameters
Symbol
T1
Parameter
Resolution
Note
Mechanical angle start point
Mechanical angle stop point
Mechanical start voltage level
Mechanical stop voltage level
Clamping level low
14 bits
14 bits
12 bits
12 bits
7 bits
T2
T1Y
T2
CLL
CLH
BP
4096 LSBs is the maximum level
31 LSBs is the minimum level
Clamping level high
7 bits
Break point
14 bits
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AS5263
Datasheet - Detailed Description
Figure 8. Overview of the Angular Output Voltage
100
96
Failure Band High
Clamping Region High
CLH
T2Y
ApplicaRegion
T1Y
CLL
Clampegion Low
Failure Band Low
4
0
Figure 8 gives an overview of the different ranges. The failure bands are used to indicate a wrong operation of the AS5263. This can be caused
due to a broken suppllne. Busing the specified load resistors, the output level will remain in these bands during a fail. It is recommended to
set the clamping level CLabove the lower failure band and the clamping level CLH below the higher failure band.
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7.2.7 Analog Output Diagnostic Mode
Due to the low pin count in the application, a wrong operation must be indicated by the output pin OUT_T, OUT_B. This could be realized using
the failure bands. The failure band is defined with a fixed level. The failure band low is specified from 0% to 4% of the supply range. The failure
band high is defined from 100% to 96%. Several failures can happen during operation. The output signal remains in these bands over the
specified operating and load conditions. All the different failures can be grouped into the internal alarms (failures) and the application related
failures.
CLOAD ≤ 42 nF, RPU= 2k…5.6kΩ
R
PD= 2k…5.6kΩ load pull-up
Table 8. Different Failure Cases of AS5263
Type
Failure Mode
Symbol
Failure Band
Note
Out of magnetic range
(too less or too high magnetic
input)
Could be switched off by one OTP bit
EXT_RANGE.
Programmable by OTP bit DIAGIGH
MAGRng
High/Low
Cordic overflow
Programmable by OTbit DIAG_HIGH
Programmable by TP bit DIAG_HIGH
Programle by OTP bit DIAG_HIGH
Programmable by OTP bit DIAG_HIGH
COF
OCF
WDF
OF
High/Low
High/Low
High/Low
Hgh/Low
Internal alarms (failures)
Offset compensation finished
Watchdog fail
Oscillator fail
Overvoltage condition
Broken VDD
O
Dependent on the load resistor
Pull up → failure band high
Pull down → failure band low
BVD
BVSS
SCO
High/Lw
gh/Low
Application related
failures
Broken VSS
Short circuit output
Switch off → short circuit dependent
For efficient use of diagnostics it is recommended tprogram to clamping leels CLL and CLH.
7.2.8 Analog Output Driver Paramete
The output stage is configured in a push-pull output. Therefore it is to sink and source currents.
CLOAD ≤ 42 nF, RPU= 2k…5.6kΩ
R
PD= 2k…5.6kΩ load pull-up
Table 9. General Parameters for the Output Driver
Symbol
IOUTSCL
IOUTSCH
TSCDET
TSCREC
ILEAKOUT
BGNDPU
BGND
BVDDU
BDDPD
Parameter
Min
8
Typ
Max
32
Unit
Note
Short circuit output crrent (low side driver)
Short circuit outpucurrent (high side driver)
Short cicuit detection time
mA
mA
VOUT=27V
-8
20
2
-32
600
20
VOUT=0V
µs
output stage turned off
output stage turned on
VOUT=VDD=5V
RPU = 2k…5.6k
RPD = 2k…5.6k
RPU = 2k…5.6k
RPD = 2k…5.6k
Shocircuit recovery time
ms
Output Leakage current
-20
96
0
20
µA
Output voltage broken GND with pull-up
Output voltage broken GND with pull-down
Output voltage broken VDD with pull-up
Output voltage broken VDD with pull-down
100
4
%VDD
%VDD
%VDD
%VDD
96
0
100
4
Note: A Pull-Up/Down load is up to 1kΩ with increased diagnostic bands from 0%-6% and 94%-100%.
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Table 10. Electrical Parameters for the Analog Output Stage
Symbol
Parameter
Min
4
Typ
Max
96
Unit
Note
Output Voltage Range
VOUT
% VDD
6
94
Valid when 1k ≤ RLOAD < 2k
Output Integral nonlinearity
Output Differential nonlinearity
Output Offset
VOUTINL
VOUTDNL
VOUTOFF
VOUTUD
10
LSB
LSB
mV
µs
-10
-50
10
50
At 2048 LSB level
Info parameter
Update rate of the Output
100
Between 10% and 90%RPD
=1kΩ, CLOAD=1nF; VD=5V
Output Step Response
VOUTSTEP
550
µs
%
Output Voltage Temperature drift
Output ratiometricity error
VOUTDRIFT
VOUTRATE
2
2
Of valat mid code
-1.5
1.5
%VDD 0.04*VDD VOT ≤ 0.96*VDD
1Hz…30kHz;
mVpp
Noise1
VOUTNOISE
10
at 2048 LSB level
1. Not tested in production; characterization only.
7.3 Pulse Width Modulation (PWM) Output
The AS5263 provides a pulse width modulated output (PWM), whose duty cycle is proportionl to thmeasured angle. This output format is
selectable over the OTP memory. If output pins OUT_T, OU_B rconfigured as open drain cnfiguration, then an external load resistor (pull
up) is required. The PWM frequency is internally trimmed to an accuracy of ±10% ovetemperature range. This tolerance can be cancelled
by measuring the ratio between the on and off state. In additin, the programmed ampig levels CLL and CLH will also adjust the PWM signal
characteristic.
Figure 9. PWM Output Signal
PWmax
P
Position 0
Position 1
Posn 4094
Positn 4095
TPWM = 1/fPWM
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The PWM frequency can be programmed by the OTP bits PWM_frequency (1:0). Therefore, four different frequencies are possible.
Table 11. PWM Signal Parameters
Symbol
fPWM1
fPWM2
fPWM3
fPWM4
Parameter
Min
Typ
Max
Unit
Hz
Note
PWM_frequency (1:0) = “00”
PWM_frequency (1:0) = “01”
PWM_frequency (1:0) = “10”
PWM_frequency (1:0) = “11”
PWM frequency1
PWM frequency2
PWM frequency3
PWM frequency4
123.60
247.19
494.39
988.77
137.33
274.66
549.32
1098.63
151.06
302.13
604.25
1208.50
Hz
Hz
Hz
(1+1)*1/
fPWM
PWMIN
PWMAX
MIN pulse width
MAX pulse width
µs
(1+4094)*1/
fPWM
ms
Taking into consideration the AC characteristic of the PWM output including load, it is recommended to use the clamping funion. The
recommended range is 0% to 4% and 96% to 100%.
Table 12. Electrical Parameters for the PWM Output Mode
Symbol
PWMVOL
ILEAK
Parameter
Output voltage low
Output leakage
Min
0
Typ
Max
0.4
20
Unit
V
Note
IOUT=8mA
VOUT=VDD=5V
-20
4
µA
%
PWMDC
PWM duty cycle range
96
Between 75% and 25%
PU/RPD = 1kΩ,
CLOAD = 1nF, VDD = 5V
R
PWMSRF
PWM slew rate
1
2
4
V/µs
7.4 Kick Down Function
The AS5263 provides a special compare functThis function is implenteusing a programmable angle value with a programmable
hysteresis. It will be indicated over the open drain output pin KDOWOWN_B. If the actual angle is above the programmable value plus
the hysteresis, the output is switched to low. The output will remain at level until the value KD is reached in the reverse direction.
Figure 10. Kick Down Hysteresis Implementation
KDHYS
DOWN
KD(5:0)+KDHYS
KD(5:0)
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Table 13. Programming Parameters for the Kick Down Function
Symbol
Parameter
Resolution
Note
KD
Kick Down angle
6 bits
KDHYS (1:0) = “00” → 8 LSB hysteresis
KDHYS (1:0) = “01” → 16 LSB hysteresis
KDHYS (1:0) = “10” → 32 LSB hysteresis
KDHYS (1:0) = “11” → 64 LSB hysteresis
KDHYS
Kick Down Hysteresis
2 bits
Pull-up resistance 1k to 5.6K to VDD
CLOAD max 42nF
Table 14. Electrical Parameters of the KDOWN Output
Symbol
Parameter
Min
Typ
Max
Unit
Note
VKDOWN = 2V
Short circuit output current
(Low Side Driver)
IKDSC
6
24
mA
Short circuit detection time
Short circuit recovery time
Output voltage low
outpt stage turned off
outut stage turned on
TSCDET
TSCREC
KDVOL
20
2
600
20
µs
ms
V
IKDOWN = 6mA
0
1.1
20
VKDOWN = 5V
Output leakage
KDILEAK
-20
µA
Between 75% and 25%,
KDOWN slew rate (falling edge)
RPUKDWN = 1kΩ, CLOAD_KDWN
KDSRF
1
2
4
V/µs
= 1nF, VDD = 5V
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8 Application Information
The benefits of AS5263 are as follows:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Unique fully differential patented solution
Best protection for automotive applications
Easy to program
Flexible interface selection PWM, analog output
Ideal for applications in harsh environments due to contactless position sensing
Robust system, tolerant to magnet misalignment, airgap variations, temperature variations and external magnetic fields
No calibration required because of inherent accuracy
High driving capability of analog output (including diagnostics)
8.1 Programming the AS5263
The AS5263 programming is a one-time-programming (OTP) method, based on polysilicon fuses. The advantage of this ethois that no
additional programming voltage is needed. The internal LDO provides the current for programming.
The OTP consists of 128 bits, wherein several bits are available for user programming. In addition, factory settingare stoed in the OTP
memory. Both regions are independently lockable by built-in lock bits.
A single OTP cell can be programmed only once. By default, each cell is “0”; a prorammed cell will contain a “1”. While it is not possible to reset
a programmed bit from “1” to “0”, multiple OTP writes are possible, as lonly unprogrammed “0”-bits are programmed to “1”.
Independent of the OTP programming, it is possible to overwrite the OTP gister temporarily with an OTP write command. This is possible only
if the user lock bit is not programmed.
Due to the programming over the output pin, the device will itially art in the communication mde. In this mode, the digital angle value can be
read with a specific protocol format. It is a bidirectional communication possible. Paramcan be written into the device. A programming of the
device is triggered by a specific command. With anothr command (pass2funciothe dvice can be switched into operation mode (analog or
PWM output). In case of a programmed user lock b, the AS5263 automatically startup in the functional operation mode. No communication of
the specific protocol is possible after this.
8.1.1 Hardware Setup
The pin OUT and the supply connection are required for OTP memorss. Without the programmed Mem_Lock_USER OTP bit, the device
will start up in the communication mode and will remain into aIDLE operation mode. The pull up resistor RCommunication is required during
startup. Figure 1 shows the configuration of an AS5263.
Figure 11. Programming Schematic of the AS5263
SENSOR PCB
VDD_X
VDD_X
1uF
Programmer
AS5263
VDD
DIO
RCommunication
VDD5_X
VDD3_X
OUT_X
KDOWN_X
2.2uF
(low ESR)
0.3 ohm
2.2uF
(low ESR)
GNDA_X GNDD_X GNDP_X
GND
GND
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8.1.2 Protocol Timing and Commands of Single Pin Interface
During the communication mode, the output level is defined by the external pull up resistor RCommunication. The output driver of the device is in tri-
state. The bit coding (see Figure 18) has been chosen in order to allow the continuous synchronization during the communication, which can be
required due to the tolerance of the internal clock frequency. Figure 18 shows how the different logic states '0' and '1' are defined. The period of
the clock TCLK is defined with 222.2 ns.
The voltage levels VH and VL are CMOS typical.
Each frame is composed by 20 bits. The 4 MSB (CMD) of the frame specifies the type of command that is passed to the AS5263. The 16 data
bits contain the communication data. There will be no operation when the ‘not specified’ CMD is used. The sequence is oriented in such a way
that the LSB of the data is followed by the command. The number of frames vary depending on the command. The single pin programming
interface block of the AS5263 can operate in slave communication or master communication mode. In the slave communication mode, the
AS5263 receives the data organized in frames. The programming tool is the driver of the single communication line and can pull down the levl.
In case of the master communication mode, the AS5263 transmits data in the frame format. The single communication line can be pulled ow
by the AS5263.
Figure 12. Bit Coding of the Single Pin Programming Interface
Bit “0”
Bit “1”
V
H
V
H
V
L
T
T
2
T
1
T
1
T = 1* T
1
T
BIT
= T + T = 512 * T
1 2 CLK
T = 384
2
Figure 13. Protocol Definition
IE STAT
PACKET
IDLE START
DATA
COMMAND
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Table 15. OTP Commands and Communication Interface Modes
AS5263
Communication Mode
Possible Interface
Description
Command Number of
Commands
CMD
Frames
UNBLOCK
WRITE128
Resets the interface
SLAVE
SLAVE
0x0
1
0x9
(0x1)
Writes 128 bits (user + factory settings) into the device
8
READ128
UPLOAD
DOWNLOAD
FUSE
Reads 128 bits (user + factory settings) from the device
Transfers the register content into the OTP memory
Transfers the OTP content to the register content
Command for permanent programming
SLAVE and MASTER
SLAVE
0xA
0x6
0x5
0x4
0x7
xB
0xC
9
1
1
1
1
2
1
SLAVE
SLAVE
PASS2FUNC
READ
Change operation mode from communication to operation
Read related to address the user data
SLAVE
SLAVE and MASTER
SLAVE
WRITE
Write related to address the user data
Note: Other commands are reserved and shall not be used.
When single pin programming interface bus is in high impedance statee logical level of the bus is held by the pull up resistor RCommunication
.
Each communication begins by a condition of the bus level which is calART. This is done by cing the bus in logical low level (done by
the programmer or AS5263 depending on the communication mode). Aftwards the bit information of e command is transmitted as shown in
Figure 14.
Figure 14. Bus Timing for the WRITE128 Command
START
IDLE
DATA1
DATA0
DATA2
DATA14
1
0 0 1
1
0 0 0
1
0 0 0
20*TBIT
Figure 15. Bus Timing for the READ12Command
START
IDLE
DO NOT CARE
20*TBIT
DO NOT ARE
DATA1
DATA0
DATA3
DATA14
0
1
0
1
IDLE
0
0 0 P
0
0 0 P
Slave Communication Mode
Master Communication Mode
TSW
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In case of READ or READ128 command (see Figure 15) the idle phase between the command and the answer is 10 TBIT (TSW).
Figure 16. Bus Timing for the READ Commands
START
IDLE
ADDR2
ADDR1
DATA1
DATA0
0
1
0
1
IDLE
0
0 0 P
20*TBIT
Slave Communication Mode
TSW
Master Communication Mode
In case of a WRITE command, the device stays in slave communication mode nd will ot switch to master commuication mode.
When using other commands like DOWNLOAD, UPLOAD, etc. instead of REAor WRE, it does not mater wht is written in the address
fields (ADDR1, ADDR2).
8.1.3 UNBLOCK
The Unblock command can be used to reset only the one-wire interface of the AS5263 in order to rcover the possibility to communicate again
without the need of a POR after a stacking event due to noison the bus line or misalignment ith the AS5263 protocol.
The command is composed by a not idle phase of at leas6 TBIT followed by a packeh all 20 bits at zero (see Figure 17).
Figure 17. Unblock Sequence
VH
PACKET[19:0] = 0x00000
NOT IDLE
START
IDLE
IDLE
VL
= 6 * TBIT => 3072* TCLK
512*TK = 512*TCLK
20*TBIT => 10240*TCLK
= 512*TCLK
COMMAND FROM EXT MASTER
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8.1.4 WRITE128
Figure 18 illustrates the format of the frame and the command.
Figure 18. Frame Organization of the WRITE128 Command
DATA1
DATA0
DATA2
DATA4
DATA6
DATA8
ATA10
DATA12
DATA14
CMD
MSB LSB
MSB LSB
MSB LSB
MSB LSB
MSLSB
MSB LSB
SB LSB
MSB LSB
MSB LSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
1
0
0
1
DATA3
DATA5
DATA7
DATA9
DATA11
DATA13
DATA15
CMD
MSB LSB
MSB
1
0
0
0
CMD
MSB LSB
MSB
0
0
0
CMD
MSB LSB
MSB
1
0
0
0
CMD
MSB LSB
MSB
1
0
0
0
CMD
MSB LSB
MSB
1
0
0
0
CMD
MSB LSB
MSB
1
0
0
0
CMD
MSB LSB
MSB
1
0
0
0
The command cntain8 frames. With this command, the AS5263 receives only frames. This command will transfer the data in the special
function rers (SFRs) of the device. The data is not permanent programmed using this command.
Tle 16 dcribe the organization of the OTP data bits.
The acess is performed with CMD field set to 0x9. The next 7 frames with CMD field set to 0x1. The 2 bytes of the first command will be written
at address 0 and 1 of the SFRs; the 2 bytes of the second command will be written at address 2 and 3; and so on, in order to cover all the 16
bytes of the 128 SFRs.
Note: It is important to always complete the command. All 8 frames are needed. In case of a wrong command or a communication error, a
power on reset must be performed. The device will be delivered with the programmed Mem_Lock_AMS OTP bit. This bit locks the
content of the factory settings. It is impossible to overwrite this particular region. The written information will be ignored.
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8.1.5 READ128
Figure 19 illustrates the format of the frame and the command.
Figure 19. Frame Organization of the READ128 Command
DO NOT CARE
DO NOT CARE
DATA0
CMD
MSB LSB
MSB LSB
MSB LSB
MSB LSB
MSLSB
MSB LSB
B LSB
MSB LSB
MSB LSB
MSB LSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
0
1
0
1
DATA1
DATA3
DATA5
DATA7
DATA9
DATA11
DATA13
DATA15
CMD DUMMY
MSB
0
0
0
P
P
P
P
P
P
P
P
DATA2
CMD DUMY
MSB
0
0
DATA4
CMD DUMMY
MSB
0
0
0
DATA6
CMD DUMMY
MSB
0
0
0
DATA8
CMD DUMMY
MSB
0
0
0
DATA10
DATA12
DATA14
CMD DUMMY
MSB
0
0
0
CMD DUMMY
MSB
0
0
0
CMD DUMMY
MSB
0
0
0
The command is composed by a first frame transmitted to the AS5263. The device is in slave communication mode. The device remains for the
time TSWITCH in IDLE mode before changing into the master communication mode. The AS5263 starts to send 8 frames. This command will read
the SFRs. The numbering of the data bytes correlates with the address of the related SFR.
An even parity bit is used to guarantee a correct data transmission. Each parity (P) is related to the frame data content of the 16 bit word. The
MSB of the CMD dummy (P) is reserved for the parity information.
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8.1.6 DOWNLOAD
Figure 20 shows the format of the frame.
Figure 20. Frame Organization of the DOWNLOAD Command
DO NOT CARE
DO NOT CARE
CMD
MSB LSB
MSB LSB
MSB
LSB
1
0
1
0
The command consists of one frame received by the AS5263 (slave communication mode). The OTP cell fuse content will be downloadinto
the SFRs.
The access is performed with CMD field set to 0x5.
8.1.7 UPLOAD
Figure 21 shows the format of the frame.
Figure 21. Frame Organization of the UPLOAD Command
DO NOT CARE
DO NOT CARE
CMD
MSLSB
MSB LSB
MSB
LSB
0
1
1
0
The command consists of one frame received by the AS5263 (slave unication mode) and transfers the data from the SFRs into the OTP
fuse cells. The OTP fuses are not permanent programmed ung this command.
The access is performed with CMD field set to 0x6.
8.1.8 FUSE
Figure 22 shows the format of the frame.
Figure 22. Frame Organization of the FUE Command
O NOT CARE
DO NOT CARE
CMD
MSB LSB
MSB LSB
MSB
LSB
0
0
1
0
The command consists of one frame received by the AS5263 (slave communication mode) and it is giving the trigger to permanent program the
non volatile fuse elements.
The access is performed with CMD field set to 0x4.
Note: After this command, the device automatically starts to program the built-in programming procedure. It is not allowed to send other com-
mands during this programming time. This time is specified to 4ms after the last CMD bit.
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8.1.9 PASS2FUNC
Figure 23 shows the format of the frame.
Figure 23. Frame Organization of the PASS2FUNCTION Command
DO NOT CARE
DO NOT CARE
CMD
MSB LSB
MSB LSB
MSB
LSB
1
1
1
0
The command consists of one frame received by the AS5263 (slave communication mode). This command stopthe communication receiving
mode, releases the reset of the DSP of the AS5263 device and starts to work ifunctial mode with the values of e SFR currently written.
The access is performed with CMD field set to 0x7.
8.1.10 READ
Figure 24 shows the format of the frame.
Figure 24. Frame Organization of the READ Command
ADDR2
DATA2
ADDR1
DATA1
CMD
MSB LSB
MSLSB
MSB LSB
MSB
LSB
LSB
1
1
0
1
CMD DUMMY
MSB
0
0
0
P
The command is compoed by a first frame sent to the AS5263. The device is in slave communication mode. The device remains for the time
TSWITCH in IDLE mode before changing into the master communication mode. The AS5263 starts to send the second frame transmitted by the
AS5263.
The acceperformed with CMD field set to 0xB.
Whn the AS5263 receives the first frame, it sends a frame with data value of the address specified in the field of the first frame.
Table 1shows the possible readable data information for the AS5263 device.
An even parity bit is used to guarantee a correct data transmission. The parity bit (P) is generated by the 16 data bits. The MSB of the CMD
dummy (P) is reserved for the parity information.
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8.1.11 WRITE
Figure 25 shows the format of the frame.
Figure 25. Frame Organization of the WRITE Command
DATA
ADDR
CMD
MSB LSB
MSB LSB
MSB
LSB
0
0
1
1
The command consists of one frame received by the AS5263 (slave communition moe). The data byte will be written to the address. The
access is performed with CMD field set to 0xC.
Table 17 shows the possible write data information for the AS5263 devi
Note: It is not recommended to access OTP memory addresses using his command.
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8.2 OTP Programming Data
Table 16. OTP Data Organization
Data Byte
Bit Number
Symbol
AMS_Test
AMS_Test
AMS_Test
AMS_Test
AMS_Test
AMS_Test
AMS_Test
AMS_Test
AMS_Test
AMS_Test
AMS_Test
AMS_Test
ChipID<0>
ChipID<1>
ChipID<2>
ChipID<>
CipID4>
ChipD<5>
ChipID<6>
ChipID<7>
ChipID<8>
ChipID<
CipID<10>
hipID<11>
ipID<12>
ChipID<13>
ChipID<14>
ChipID<15>
ChipID<16>
ChipID<17>
ChipID<18>
ChipID<19>
Default
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
S
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
Description
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
DATA15
(0x0F)
AMS Test Area
DATA14
(0x0E)
DATA13
(0x0D)
Chip ID
DATA12
(0x0C)
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Table 16. OTP Data Organization
Data Byte
Bit Number
Symbol
ChipID<20>
MemLock_AMS
KD<0>
Default
Description
Chip ID
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
FS
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Lock of the Factory Setting Area
KD<1>
DATA11
(0x0B)
KD<2>
Kick Down Threshold
KD<3>
KD<4>
KD<5>
ClampLow<0>
ClampLow<1>
ClampLow<2>
ClampLow<3>
ClampLow<4>
ClampLow<5>
ClampLow<6>
DAC_MODE
ClampHi0>
Clampi<1>
ClapHi<2>
CampHi<3>
ClampHi<4>
ClampHi<5>
ClampHi>
Clamping vel Lo
DAC12/DAC10 Mode
Clamping Level High
DATA10
(0x0A)
DATA9
(0x09)
Diagnostic Mode, default=0 for
Failure Band Low
7
DG_HIGH
0
0
1
2
3
4
5
6
7
setIn<0>
OffsetIn<1>
OffsetIn<2>
OffsetIn<3>
OffsetIn<4>
OffsetIn<5>
OffsetIn<6>
OffsetIn<7>
0
0
0
0
0
0
0
0
DATA8
(0x08)
Offset
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AS5263
Datasheet - Application Information
Table 16. OTP Data Organization
Data Byte
Bit Number
Symbol
OffsetIn<8>
OffsetIn<9>
OffsetIn<10>
OffsetIn<11>
OffsetIn<12>
OffsetIn<13>
OP_Mode<0>
OP_Mode<1>
OffsetOut<0>
OffsetOut<1>
OffsetOut<2>
OffsetOut<3>
OffsetOut<4>
OffsetOut<5>
OffsetOut<6>
OffsetOut<7>
OffsetOu8>
Offsetut<9>
ffseOut<10>
OfetOut<11>
KDHYS<0>
KDHYS<1>
PWM Frequecy<0>
PWM Frequency<1>
BP0>
Default
Description
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Offset
DATA7
(0x07)
Selection of Analog=‘00’ or PWM
Mode=‘01’
DATA6
(0x06)
Output Offset
DATA5
(0x05)
Kick Down Hysteresis
Select the PWM frequency (4
frequencies)
BP<1>
BP<2>
BP<3>
DATA4
(0x04)
Break Point
BP<4>
BP<5>
BP<6>
BP<7>
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AS5263
Datasheet - Application Information
Table 16. OTP Data Organization
Data Byte
Bit Number
Symbol
BP<8>
Default
Description
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BP<9>
BP<10>
Break Point
BP<11>
DATA3
(0x03)
BP<12>
BP<13>
FAST_SLOW
EXT_RANGE
Gain<0>
Gain<1>
Gain<2>
Gain<3>
Gain<4>
Gain<5>
Gain<6>
Gain<7>
Gain<8
Gain9>
Gan<10>
ain<11>
Gain<12>
Gain<13>
Output Data Rate
Enables a wider z-Range
DATA2
(0x02)
Gain
Gain
DATA1
(0x01)
Clockwise /Counterclockwise
rotation
6
Invert_Sloe
0
7
0
1
2
3
4
5
6
7
Lock_OTPCUST
rndancy<0>
rdundancy<1>
redundancy<2>
redundancy<3>
redundancy<4>
redundancy<5>
redundancy<6>
redundancy<7>
0
0
0
0
0
0
0
0
0
Customer Memory Lock
DATA0
(0x00)
Redundancy Bits
te: Fatory settings (FS) are used for testing and programming at AMS. These settings are locked (only read access possbile).
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AS5263
Datasheet - Application Information
Data Content.
ꢀ
Redundancy (7:0): For a better programming yield, a redundancy is implemented. In case the programming of one bit fails, then this
function can be used. With an address (7:0) one bit can be selected and programmed.
ꢀ
Lock_OTPCUST = 1, locks the customer area in the OTP and the device, from hereon, starts in operating mode.
Redundancy Code
OTP Bit Selection
Redundancy <7:0>
in decimal
0
1
none
OP_Mode<1>
2
DIAG_HIGH
3
PWM Frequency<0>
ClampHi<6> - ClampHi<0>
ClampLow<6> - ClampLow<0>
OP_Mode<0>
4 - 10
11 - 17
18
19 - 32
33 - 46
47 - 60
61 - 72
73
OffsetIn<13> - OffsetIn<0>
Gain<13> - Gain<0>
BP<13> - BP<0>
OffsetOut<11> - OffsetOut<0>
Invert_Slope
74
FAST_SLOW
75
EXT_RANGE
76
DAC_MODE
77
Lock_OTPCUST
78 - 83
84 - 85
86
KD<5> - KD<0>
KDHYS<1> - KDHS<0>
PWM Frequenc>
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Invert_Slope = 1, inverts the output characteristic in analog output mode
Gain (7:0): With this value, the steepness of the output slpe an be adjusted
EXT_RANGE = 1, provides a wider z-Range of thmagnet by turning off the alarm function
FAST_SLOW = 1, improves the noise perfrmce due to internal filtering
BP (13:0): The breakpoint can be set with retion of 14-bit
PWM Frequency (1:0): Four differenfreqency settings are possible. Please refer to Table 11.
KDHYS (1:0): Avoids flickering at thKDOWN output (pin 11). For settings, refer to Table 12.
OffsetOut (11:0): Output haracteristic parameter
ANALOG_PWM = 1, sects the PWM output mode
OffsetIn (13:0): Outut characteristic parameter
DIAG_HIGH = 1: case of an error, the signal goes into high failure-band.
Clam(6:0): Sets the clamping level high with respect to VDD.
DAC_MODE disables filter at DAC
ClmpLow (6:0): Sets the clamping level low with respect to VDD
KD (5:0): Sets the kick-down level with respect to VDD
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AS5263
Datasheet - Application Information
8.2.1 Read / Write User Data
Table 17. Read / Write Data
Area
Address
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Region
0x10
0x11
0x12
0x17
16
17
18
23
CORDIC_OUT[7:0]
CORDIC_OUT[13:8]
0
0
OCF
COF
0
0
0
0
DSP_RES R1K_10K
AGC_VALUE[7:0]
Read only
Read and Write
Data Content:
Data only for read:
ꢀ
CORDIC_OUT(13:0): 14-bit absolute angular position data
ꢀ
OCF (Offset Compensation Finished): logic high indicates the finished Offset Compensation Algorithm. As n as his bit is set, the
AS5263 has completed the startup and the data is valid.
ꢀ
ꢀ
COF (Cordic Overflow): Logic high indicates an out of range error in the CRDIC part. When this bit is et, hCORDIC_OUT(13:0) data is
invalid. The absolute output maintains the last valid angular values alarm may be resolved by bringing the magnet within the X-Y-Z
tolerance limits.
AGC_VALUE (7:0): Magnetic field indication
Data for write and read:
ꢀ
DSP_RES resets the DSP part of the AS5263 the default value is 0. This is activ. The interface is not affected by this reset.
ꢀ
R1K_10K defines the threshold level for the OTP ses. This bit can be changd for verification purpose. A verification of the programming
of the fuses is possible. The verification is madatory after programming.
8.2.2 Programming Procedure
Note: After programming the OTP fuses, a verification is mandate procedure described below must be strictly followed to ensure
properly programmed OTP fuses.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Pull-up on OUT pin
VDD=5V
Wait startup time, device enters communicatiode.
Write128 command: The trimming bs are written in the SFR memory.
Read128 command: The trimminbits are read back.
Compare read data to previos writtn data. If the data matches, then proceed further.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Upload command: The SFmemory is transferred into the OTP RAM.
Fuse command: The OTRAM is written in the Poly Fuse cells.
Wait fuse time (6ms)
Write commnd (R1K_10K=1): Poly Fuse cells are transferred into the RAM cells compared with 10KΩ resistor.
Dowd command: The OTP RAM is transferred into the SFR memory.
Read128 command: The fused bits are read back.
Cmpare read data to previous written and read data. If the data matches, then proceed further.
ꢀ
ꢀ
ꢀ
Write command (R1K_10K=0): Poly Fuse cells are transferred into the RAM cells compared with 1KΩ resistor.
Download command: The OTP RAM is transferred into the SFR memory.
Read128 command: The fused bits are read back.
Compare read data to previous written and two times read data. If the data matches, then proceed further.
ꢀ
Pass2Func command or POR: Go to Functional mode.
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AS5263
Datasheet - Application Information
An equal output of all read out data is sufficient to verify the OTP programming. If the data output is a mismatch, then the programming of the
OTP was not successful and can cause a change of the OTP register content during operation over temperature and life time.
8.2.3 Physical Placement of the Magnet
The best linearity can be achieved by placing the center of the magnet exactly over the defined center of the chip as shown in Figure 26.
Figure 26. Defined Chip Center and Magnet Displacement Radius
Defined
center
Rd
Area of recommended maium
magnet misalignment
8.2.4 Magnet Placement
The magnet’s center axis should be aligned within a diplacement radius Rd of 0mm arger magnets allow more displacement) from the
defined center of the IC.
The magnet may be placed below or above the evicThe distance shoube chsen such that the magnetic field on the die surface is within
the specified limits (see Figure 26). The typicaance “z” between the magnt and the package surface is 0.5mm to 1.5mm, provided the
recommended magnet material and dimension(6mm x 3mm) are rger distances are possible, as long as, the required magnetic field
strength stays within the defined limits.
However, a magnetic field outside the specified range may stprodce usable results, but the out-of-range condition will be indicated by an
alarm forcing the output into the failure band.
Figure 27. Vertical Placement of the Magnet
N
S
Package surface
Die surface
z
Die 1
Die 2
0.561mm
±0.075mm
0.850mm
nom.
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AS5263
Datasheet - Package Drawings and Markings
9 Package Drawings and Markings
The device is available in a 32-pin QFN (7x7mm) package.
Figure 28. Package Drawings and Dimensions
YYWWIZZ
AS5263
Symbol
A
Min
0.80
0
Typ
0.90
Max
1.00
0.05
1.00
-
A1
A2
A3
L
0.02
-
0.65
-
0.20 REF
0.60
0.50
0º
0.75
14º
Θ
b
0.23
0.28
7.00 BSC
7.00 BSC
0.65 BSC
6.75 BSC
6.75 BSC
4.80
0.35
D
E
e
D1
E1
D2
E2
aaa
bbb
ccc
ddd
eee
fff
4.70
4.0
4.70
4.80
.90
Notes:
1. Dimensions and tolerancing conform to ASME Y14.5M-
-
-
-
-
-
0.15
-
-
-
-
-
-
0.10
1994.
0.0
2. All dimensions are in miilimeters. Angles are in degrees.
0.05
3. Coplanarity applies to the exposed heat slug as well as the
terminal.
0.08
0.10
4. Radius on terminal is optional.
N
32
5. N is the total number of terminals.
Marking: YYWWIZZ.
YY
WW
I
ZZ
Last two digits of the Manufacturing Year
Manufacturing Week
Plant Identifier
Traceability Code
Note: IC’s marked with a white dot or the letters “ES” denote Engineering samples.
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AS5263
Datasheet - Revision History
Revision History
Revision
Date
Owner
Description
1.0
1.1
May 31, 2010
apg/rfu
Initial version
Updated Absolute Maximum Ratings, Operating Conditions, Magnetic Input
Specification, Electrical System Specifications, Figure 3, Table 5, Table 6,
Table 9, Table 10, Table 14, Table 15, page 31, Programming Procedure,
Figure 26, Figure 27, Package Drawings and Markings.
Oct 14, 2010
rfu
Deleted chapter on “Choosing the Proper Magnet”.
Updated Absolute Maximum Ratings, Package Drawings and Markings.
Dec 14, 2010
Jan 12, 2011
1.2
Updated Figure 26 and Figure 28. Removed “AS5263 Stacked Die
Technology” diagram.
mub
Updated Electrical System Specifications, Application Specific Angular ange
Programming.
1.3
1.4
Apr 08, 2011
May 11, 2011
Updated Programming Procedure.
Note: Typos may not be explicitly mentioned under revision history.
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AS5263
Datasheet - Ordering Information
10 Ordering Information
The devices are available as the standard products shown in Table 18.
Table 18. Ordering Information
Ordering Code
Description
Delivery Form
Package
AS5263-HQFT
Redundant 12-bit Magnetic Rotary Encoder
Tape & Reel
32-pin QFN (7x7mm)
Note: All products are RoHS compliant and austriamicrosystems green.
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For further information and requests, please contact us mailto: sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
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AS5263
Datasheet - Copyrights
Copyrights
Copyright © 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and pries
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG fo
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature rae,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment ar
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamirosysms AG shall not
be liable to recipient or any third party for any damages, including but not limiteto personal injury, property dam, loss f profits, loss of use,
interruption of business or indirect, special, incidental or consequential damags, of any ind, in connection with or arig out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recient or ny third party shall risoflow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
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austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales OfficeDistributors and Representatives, please visit:
http://www.austriaicrosystems.com/contact
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