AS5510中文资料_数据手册_规格书

AS5510

Linear Hall Sensor with I²C Output

1 General Description

2 Key Features

10bit resolution

The AS5510 is a linear Hall sensor with 10 bit resolution and I²C

interface. It can measure absolute position of lateral movement of a

simple 2-pole magnet. Depending on the magnet size, a lateral

stroke of 0.5~2mm can be measured with air gaps around 1.0mm. To

conserve power, the AS5510 may be switched to a power down state

when it is not used.It is available in a WLCSP package and qualified

for an ambient temperature range from -30°C to +85°C.

I²C Interface

Power down mode

Programmable sensitivity

3 Applications

The AS5510 is ideal for:

Figure 1. Linear Position Sensor with AS5510 + Magnet

Position sensing

Magnet

Servo drive feedback

Camera lens control

N

S

Closed loop position control.

AS5510

PCB

Figure 2. Block Diagram

Front

End

Offset

Compensation

ADC 10 bit

Buffer & Filter

Biasing &

Reference

DSP

I²C

Factory Gain Trim

Test

SDA

ADR

SCL

VDD VSS

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AS5510

Datasheet - Contents

Contents

1 General Description ..................................................................................................................................................................

2 Key Features.............................................................................................................................................................................

3 Applications...............................................................................................................................................................................

4 Pin Assignments .......................................................................................................................................................................

4.1 Pin Descriptions....................................................................................................................................................................................

5 Absolute Maximum Ratings ......................................................................................................................................................

6 Electrical Characteristics...........................................................................................................................................................

6.1 DC Characteristics for Digital Inputs and Outputs................................................................................................................................

1

3

4

5

6.1.1 CMOS Input: ADR ....................................................................................................................................................................... 5

6.1.2 CMOS I²C: SDA, SCL.................................................................................................................................................................. 5

6.2 Electrical and Magnetic Specifications .................................................................................................................................................

7 Detailed Description..................................................................................................................................................................

7.1 Typical Application................................................................................................................................................................................

7.2 I²C Interface..........................................................................................................................................................................................

6

7

7.2.1 I²C Interface Data ........................................................................................................................................................................ 8

7.3 I²C Modes.............................................................................................................................................................................................

9

7.4 SDA, SCL Input Filters ....................................................................................................................................................................... 12

7.5 Register Map and Description ............................................................................................................................................................ 12

8 Package Drawings and Markings ........................................................................................................................................... 14

8.1 Chip Scale Package 1.4 x 1.1mm ...................................................................................................................................................... 14

8.2 Package Dimensions.......................................................................................................................................................................... 14

8.3 Recommended Footprint.................................................................................................................................................................... 15

9 Ordering Information............................................................................................................................................................... 17

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AS5510

Datasheet - Pin Assignments

4 Pin Assignments

Figure 3. Pin Configuration of AS5510 (Top view)

Pin A1 indicator

1

2

3

A

VSS

ADR

VDD

SDA

SCL

Test

B

Note: The AS5510 is available in a 6-pin Chip Scale Package with a ball pitch of 400μm.

4.1 Pin Descriptions

Table 1. Pin Description

Pin Name

Pin Number

Pin Type

Description

Negative supply pin, analog and digital ground

VSS

A1

Supply pin

I²C address selection pin

Connect to either VSS (56h) or VDD (57h)

ADR

VDD

SDA

A2

A3

B1

Digital input

Supply pin

Positive supply pin. A capacitor of 100nF should be connected to

this pin and VSS

Digital input / Digital output

open drain

I²C data I/O, 20mA driving capability

I²C clock

SCL

Test

B2

B3

Digital input

Test pin, must be connected to VSS during operation

Digital input/output

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AS5510

Datasheet - Absolute Maximum Ratings

5 Absolute Maximum Ratings

Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of

the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Table 2. Absolute Maximum Ratings

Parameter

Min

-0.3

-100

Max

5

Units

V

Comments

DC supply voltage at pin VDD

Input pin voltage

VDD +0.3

100

V

Norm: JEDEC 78

Input current (latchup immunity)

Electrostatic discharge

Storage temperature

mA

kV

°C

Norm: MIL 883 E method 3015

±2

-55

T_Body

5

+125

The reflow peak soldering temperature (body

temperature) specified is in accordance with IPC/

JEDEC J-STD-020“Moisture/Reflow Sensitivity

Classification for Non-Hermetic Solid State

Surface Mount Devices”.

Body temperature (Lead-free package)

+260

85

°C

%

Humidity non-condensing

Moisture Sensitive Level

Represents a max. floor life time of unlimited

1

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AS5510

Datasheet - Electrical Characteristics

6 Electrical Characteristics

Table 3. Operating Conditions

Symbol

VDD

I_supp

I_pd

Parameter

Supply voltage at pin VDD

Supply current

Conditions

Min

Typ

3

Max

Units

V

2.5

3.6

3.5

25

mA

μA

°C

@ 25°C ambient temperature

Power down current

Ambient temperature

T_amb

-30

85

6.1 DC Characteristics for Digital Inputs and Outputs

6.1.1 CMOS Input: ADR

Table 4. Electrical Characteristics ADR Input

Symbol

V_IH

Parameter

Conditions

Min

Typ

Max

Units

V

High level input voltage

Low level input voltage

Input leakage current

0.7 * VDD

VDD

0.3 * VDD

1

V_IL

0

V

I_LEAK

-1

μA

Note: Operating conditions: T_amb= -30°C to +85°C, VDD = 2.5V to 3.6V (3V operation) unless otherwise noted.

6.1.2 CMOS I²C: SDA, SCL

Table 5. Electrical Characteristics I²C

Symbol

V_IL

Parameter

Conditions

Min

-0.5

Typ

Max

Units

LOW-level input voltage

0.3 * VDD

VDD +0.5V

V

V_IH

HIGH-level input voltage

Hysteresis of Schmitt Trigger inputs

0.7 * VDD

0.05 * VDD

V_hys

VDD > 2.5V

VOL = 0.4V

LOW-level output voltage (open-drain

or open-collector) at 3mA sink current

V_OL

0.4V

V

I_OL

t_of

LOW-level output current

20

mA

ns

120¹

50²

Output fall time from V_IHmaxto V_ILmax

Pulse width of spikes that must be

suppressed by the input filter

t_SP

ns

+10³

550

I_i

Input current at each I/O pin

-10

μA

pF

C_B

Total capacitive load for each bus line

I/O capacitance (SDA, SCL)⁴

C_I/O

10

1. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used this has to be consid-

ered for bus timing.

2. Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.

3. I/O pins of Fast-mode and Fast-mode plus devices must not obstruct the SDA and SCL lines if VDD is switched off.

4. Special purpose devices such as multiplexers and switches may exceed this capacitance due to the fact that they connect multiple

paths together.

Note: Operating conditions: T_amb= -30°C to +85°C, VDD = 2.5V to 3.6V (3V operation) unless otherwise noted.

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AS5510

Datasheet - Electrical Characteristics

6.2 Electrical and Magnetic Specifications

Table 6. Electrical and Magnetic Specifications

Symbol

Parameter

Conditions

Min

Typ

10

Max

Units

bit

RES

Resolution

Default Setting

±50

mT

±25

Bin

Magnetic Input Range

Configurable via I²C or factory

trimming option

±12.5

±18.75

Input related offset¹

Linearity error²

Offset_inp

0.45

3

mT

%

This time is needed for the first

power-up of the device until the

offset compensation is finished;

Includes readout of the PPROM

fuses

Initial Power up time from cold start³

Power-on time⁴

t_PwrUp

1.5

ms

Time after switching from power-

down mode into active mode until

the offset compensation is finished

t_PwrOn

250

μs

Fast Mode (default setting)

f_S

ADC sampling frequency

System propagation delay

50

20

KHz

After offset compensation finished

t_delay

μs

Input related noise⁵

Noise_inp

Equivalent to 8 * rms

0.8

mTpp

Slow mode (I²C command option)

f_S

ADC sampling frequency

System propagation delay

12.5

50

KHz

After offset compensation finished

Equivalent to 8 * rms

t_delay

μs

Input related noise⁵

Noise_inp

0.5

mTpp

1. Offset_inp= 0.35mT residual offset + 0.1mT earth magnetic field.

2. Linearity error=













out(maxB) adc out(zeroB)

adc

–

lin error

-------------------------------------------------------------------------------------------------------------

= 1 –

× 100

–

maxB









adc out

adc out(zeroB)

–

2 ×

–

--------------

–









2

3. This time is needed for the first power-up of the device until the offset compensation is finished; Includes readout of the PPROM fuses;

It depends on the sensitivity setting.

4. Time after switching from power-down mode into active mode until the offset compensation is finished.

5. Input related Noise (Noise_Inp) is the repeatability of the measurement.

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AS5510

Datasheet - Detailed Description

7 Detailed Description

7.1 Typical Application

Figure 4. Typical Application

VDD =

2.5 ~ 3.6V

VDD

VSS

Microcontroller

VDD

100nF

AS5510

#1

SCL

SDA

SCL

SDA

I²C

interface

I²C ADDR = 56h

ADR

Test

VDD

VSS

100nF

AS5510

#2

SCL

SDA

I²C ADDR = 57h

VDD

ADR

Test

7.2 I²C Interface

The AS5510 includes an I²C slave according to the NXP specification UM10204.

7-bit slave address 101011x, the last address bit x is set by the ADR pin (0 or 1)

Random/Sequential Read

Byte/Page Write

Fast-mode plus with 20mA SDA drive strength

Internal hold time of 120ns for SDA signal is included (Start/Stop detection)

Not implemented:

10-bit Slave Address

Clock Stretching

General Call Address

General Call – Software Reset

Read of Device ID

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AS5510

Datasheet - Detailed Description

The communication from the AS5510 includes:

Reading the magnetic field strength in 10-bit data

Reading the status bits

Note: The I²C address of the chip is selected by hardware (pin ADR). Depending on the state of this pin, the I²C address is either

Pin ADR = LOW

 I²C address = 1010110b(56h)

Pin ADR = HIGH  I²C address = 1010111b(57h)

7.2.1 I²C Interface Data

Table 7. I²C Timings

Symbol

Parameter

Conditions

Min

Typ

Max

Units

f_SCLK

SCL clock frequency

1

MHz

Bus free time; time between STOP and

START condition

t_BUF

0.5

μs

Hold time; (repeated) START

condition¹

t_HD.STA

0.26

μs

t_LOW

t_HIGH

t_SU.STA

t_HD.DAT

LOW period of SCL clock

HIGH period of SCL clock

0.5

0.26

Setup time for a repeated START

condition

Data hold time²

0.45

Data setup time³

t_SU.DAT

50

ns

μs

t_R

t_F

Rise time of SDA and SCL signals

120

Fall time of SDA and SCL signals⁴

t_SU.STO

Setup time for STOP condition

0.26

1. After this time the first clock is generated

2. A device must internally provide a hold time of at least 120ns (Fast-mode Plus) for the SDA signal (referred to the V_IHminof the SCL) to

bridge the undefined region of the falling edge of SCL.

3. A fast-mode device can be used in standard-mode system, but the requirement t_SU.DAT= 250ns must then be met. This is automatically

the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL sig-

nal, it must output the next data bit to the SDA line t_Rmax+ T_SU.DAT= 1000 + 250 = 1250ns before the SCL line is released.

4. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used this has to be consid-

ered for bus timing.

Note: Operating conditions T_amb= -30 to +85°C, VDD=2.5 to 3.6V (3V operation) unless otherwise noted.

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AS5510

Datasheet - Detailed Description

Figure 5. I²C Timing Diagram

SDA

t_buf

t_HD.STA

t_LOW

t_R

t_F

SCL

t_SU.DAT

t_SU.STA

t_SU.STO

t_HD.STA

t_HD.DAT

t_HIGH

Stop

Start

Repeated

Start

7.3 I²C Modes

The AS5510 supports the I²C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a

receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A

master device that generates the serial clock (SCL), controls the bus access and generates the START and STOP conditions must control the

bus. The AS5510 operates as a slave on the I²C bus. Within the bus specifications a standard mode (100 kHz maximum clock rate) a fast mode

(400 kHz maximum clock rate) and fast mode plus (1MHz maximum clock rate) are defined. The AS5510 works in all three modes. Connections

to the bus are made through the open-drain I/O lines SDA and the input SCL. Clock stretching is not included.

The following bus protocol has been defined:

Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH

are interpreted as start or stop signals.

Accordingly, the following bus conditions have been defined:

Bus Not Busy. Both data and clock lines remain HIGH.

Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.

Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.

Data Valid. The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH

period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of

data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred

between START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and

each receiver acknowledges with a ninth bit.

Acknowledge. Each receiving device, when addressed, is obliged to generate an acknowledge bit after the reception of each byte. The

master device must generate an extra clock pulse that is associated with this acknowledge bit.A device that acknowledges must pull down the

SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related

clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of READ access to the slave by not

generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to

enable the master to generate the STOP condition.

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AS5510

Datasheet - Detailed Description

Figure 6. Data Read (Write Pointer, Then Read) - Slave Receive and Transmit

Slave Address

Repeated if more Bytes are transferred

ACK

MSB

1

LSB R/W ACK

SDA

SCL

2

...

6

7

8

9

1

...

7

8

9

Start

Stop Condition or

Condition

Repeated Start Condition

Depending upon the state of the R/W bit, two types of data transfer are possible:

Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address, followed by

R/W = 0. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. If the slave does not understand

the command or data it sends a “not acknowledge”. Data is transferred with the most significant bit (MSB) first.

Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then

returns an acknowledge bit, followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received

bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial

clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a

repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit

(MSB) first.

The AS5510 can operate in the following two modes:

Slave Receiver Mode (Write Mode). Serial data and clock are received through SDA and SCL. Each byte is followed by an acknowledge

bit (or by a not acknowledge depending on the address-pointer pointing to a valid position). START and STOP conditions are recognized as the

beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (see

Figure 7). The slave address byte is the first byte received after the START condition. The slave address byte contains the 7-bit AS5510 address.

The 7-bit slave address is followed by the direction bit (R/W), which, for a write, is 0. After receiving and decoding the slave address byte the

device outputs an acknowledge on the SDA. After the AS5510 acknowledges the slave address + write bit, the master transmits a register

address to the AS5510. This sets the address pointer on the AS5510. If the address is a valid readable address the AS5510 answers by sending

an acknowledge. If the address-pointer points to an invalid position a “not acknowledge” is sent. The master may then transmit zero or more

bytes of data. In case of the address pointer pointing to an invalid address the received data are not stored. The address pointer will increment

after each byte transferred independent from the address being valid. If the address-pointer reaches a valid position again, the AS5510 answers

with an acknowledge and stores the data. The master generates a STOP condition to terminate the data write.

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AS5510

Datasheet - Detailed Description

Figure 7. Data Write - Slave Receiver Mode

1010110

XXXXXXXX

<Data(n)>

<Data(n+1)>

XXXXXXXX

<Data(n+X)>

S

0

A

XXXXXXXX

A

XXXXXXXX NA P

S – Start

A – Acknowledge (ACK)

P – Stop

Data transferred: X+1 Bytes + Acknowledge

Slave Transmitter Mode (Read Mode). The first byte is received and handled as in the slave receiver mode. However, in this mode, the

direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the AS5510 while the serial clock is input on

SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (Figure 8 and Figure 9). The slave address byte

is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit AS5510 address. The 7-bit

slave address is followed by the direction bit (R/W), which, for a read, is 1. After receiving and decoding the slave address byte the device

outputs an acknowledge on the SDA line. The AS5510 then begins to transmit data starting with the register address pointed to by the register

pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register

pointer. The AS5510 must receive a “not acknowledge” to end a read.

Figure 8. Data Read (from Current Pointer Location) - Slave Transmitter Mode

1010110

<Data(n)>

<Data(n+1)>

XXXXXXXX

<Data(n+2)>

XXXXXXXX

<Data(n+X)>

XXXXXXXX

S

1

A

XXXXXXXX

A

NA P

S – Start

A – Acknowledge (ACK)

NA – Not Acknowledge (NACK)

P – Stop

Data transferred: X+1 Bytes + Acknowledge

Note: Last data byte is followed by NACK

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AS5510

Datasheet - Detailed Description

Figure 9. Data Read (Write Pointer, Then Read) - Slave Receive and Transmit

1010110

XXXXXXXX

1010110

<Data(n)>

<Data(n+1)>

XXXXXXXX

<Data(n+X)>

S

0

A

Sr

1

A

XXXXXXXX

A

XXXXXXXX NA P

S – Start

SA – Repeated Start

A – Acknowledge (ACK)

NA – Not Acknowledge (NACK)

P – Stop

Data transferred: X+1 Bytes + Acknowledge

Note: Last data byte is followed by NACK

Automatic increment of address pointer. The AS5510 slave automatically increments the address pointer after each byte transferred.

The increase of the address pointer is independent from the address being valid or not.

Invalid Addresses. If the user sets the address pointer to an invalid address, the address byte is not acknowledged. Nevertheless a read or

write cycle is possible. The address pointer is increased after each byte.

Reading. When reading from a wrong address, the AS5510 slave returns all zero. The address pointer is increased after each byte. Sequential

read over the whole address range is possible including address overflow.

Write. A write to a wrong address is not acknowledged by the AS5510 slave, although the address pointer is increased. When the address

pointer points to a valid address again, a successful write accessed is acknowledged. Page write over the whole address range is possible

including address overflow.

7.4 SDA, SCL Input Filters

Input filters for SDA and SCL inputs are included to suppress noise spikes of less than 50ns. Furthermore the SDA line is delayed by 120ns to

provide an internal hold time for Start/Stop detection to bridge the undefined region of the falling edge of SCL. The delay needs to be smaller

than t_HD.STA260ns. For Standard-mode and Fast-mode an internal hold time of 300ns is required, which is not covered by the AS5510 slave.

7.5 Register Map and Description

Table 8. Register Map

Bit

Access

Register Address

Type

7

6

5

4

3

2

D2

1

0

00h

01h

D7

D6

D5

D4

D3

D1

D9

D0

D8

R

OCF

Parity (even)

Fast(0)

Slow mode (1)

02h

Polarity(0)

PD(0)

R/W

03h

04h

05h

06h

07h

0Bh

Offs7

Offs6

Offs5

Offs4

Offs3

Offs2

Offs1

Offs9

Offs0

Offs8

R/W

Reserved for factory testing

R/W

Sens 1

Sens 0

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AS5510

Datasheet - Detailed Description

Table 9. Register Description

Register Address

00h, 01h

Description

10 Bit ADC output value that corresponds to the magnetic field input

Even parity bit calculated from D9 to D0

Name

D9 to D0

Parity

01h

Offset compensation loop status

0 = Offset compensation loop in use

1 = Offset compensation loop has finished

01h

02h

OCF

PD

Power down mode

0 = Normal operation (Default)

1 = Power Down mode.

Output signal polarity

0 = Normal polarity (Default)

1 = Reversed polarity (reversed magnet)

Polarity

0 = Fast mode (Default)

1 = Slow mode. Enables averaging of the output values (reduced noise, better

repeatability slower sampling frequency. See Section 6.2

Fast / Slow mode

10 Bit value of the offset compensation.

This register is factory trimmed

03h, 04h

Offs9 to Offs0

Test

These registers are reserved for factory testing

05h, 06h, 07h

Sensitivity setting

0h = Input range ±50mT Sensitivity = 97.66µT/LSB (Default)

1h = Input range ±25mT Sensitivity = 48.83µT/LSB

2h = Input range ±12.5mT Sensitivity = 24.41µT/LSB

3h = Input range ±18.75mT Sensitivity = 36.62µT/LSB

0Bh

Sensitivity

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AS5510

Datasheet - Package Drawings and Markings

8 Package Drawings and Markings

8.1 Chip Scale Package 1.4 x 1.1mm

Figure 10. 6-Pin WL-CSP 1.4 x 1.1mm

XXXX

8.2 Package Dimensions

Figure 11. Package Dimensions

Top View

Side View

Device number

Bottom View

Notes:

1. ccc Coplanarity

2. All dimensions in μm

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AS5510

Datasheet - Package Drawings and Markings

8.3 Recommended Footprint

Figure 12. Recommended Footprint

X

Package Dimensions

Symbol

Typ

1460

330

400

1100

350

400

270

Unit

x0

x1

x0

X

x0

x1

Y

y0

y1

y0

μm

y0

y1

D

Y

D

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AS5510

Datasheet - Revision History

Revision History

Revision

Date

27 Jan, 2012

Owner

Description

0.1

rph

Initial revision

Note: Typos may not be explicitly mentioned under revision history.

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AS5510

Datasheet - Ordering Information

9 Ordering Information

The devices are available as the standard products shown in Table 10.

Table 10. Ordering Information

Model

Description

Delivery Form

Package

AS5510 DWLT

Linear Hall Sensor

Tape & Reel

6pin WL-CSP 1.4 x 1.1mm

D......Temperature Range: -30°C to +85°C

WL...Package: WL-CSP Wafer Level - Chip Scale Package

T......Delivery Form: Tape & Reel

Note: All products are RoHS compliant and ams green.

Buy our products or get free samples online at www.ams.com/ICdirect

Technical Support is available at www.ams.com/Technical-Support

For further information and requests, email us at sales@ams.com

(or) find your local distributor at www.ams.com/distributor

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AS5510

Datasheet - Copyrights

Copyrights

reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the

copyright owner.

All products and companies mentioned are trademarks or registered trademarks of their respective companies.

Disclaimer

Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no

warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described

devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior

to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal

commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability

applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing

by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard

production flow, such as test flow or test location.

The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third

party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or

indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the

technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other

services.

Contact Information

Headquarters

ams AG

Tobelbaderstrasse 30

A-8141 Unterpremstaetten, Austria

Tel : +43 (0) 3136 500 0

Fax : +43 (0) 3136 525 01

For Sales Offices, Distributors and Representatives, please visit:

http://www.ams.com/contact

www.ams.com/AS5510

Revision 0.1

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型号	制造商	描述	价格	文档
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AS55P05S	ANBON	SOP-8	获取价格
AS55P10S	ANBON	DFN5*6-8L	获取价格
AS5601	AMSCO	12-bit Programmable Contactless Encoder	获取价格
AS5601-ASOM	AMSCO	12-bit Programmable Contactless Encoder	获取价格
AS5601-ASOT	AMSCO	12-bit Programmable Contactless Encoder	获取价格
AS5601BS	CALOGIC	SCSI Terminator, 18-Line, 110ohm, PDSO28, SOIC-28	获取价格
AS568	ETC	SEMI-PRECISION POWER WIREWOUND RESISTOR	获取价格

AS5510

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