AS8515-ZMFM [AMSCO]
Data Acquisition System with Power Management and LIN Transceiver for 12V Battery Sensor Applications; 数据采集系统的电源管理和LIN收发器，用于12V电池传感器的应用
| 型号： | AS8515-ZMFM |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | Data Acquisition System with Power Management and LIN Transceiver for 12V Battery Sensor Applications |
| 文件： | 总65页 (文件大小：557K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS8515
Data Acquisition System with Power Management and LIN Transceiver
for 12V Battery Sensor Applications
Internal temperature sensor
1 General Description
Synchronous acquisition for both ADC channels
The AS8515 is designed for simultaneous measurement of shunt
Reference-voltage source (high precision and high stability)
current sensor signal and battery voltage by two independent ADC
Offset auto zero architecture on both channels
channels. Both channels can measure small signals up to ±219 mV
versus ground through programmable gain amplifier or larger signals
in the 1V range without amplifier. After analog to digital conversion
and digital filtering, the resulting digital values are accessible through
4-wire serial interface. The device is powered directly from the
battery through LDO and provides a 3.3V supply for an external
microcontroller. For communication with the next level ECU, the
device offers a LIN 2.1 transceiver. Measurement of battery voltage
is supported through resistive attenuator with disable for power
saving in standby.
Current monitoring comparator with interrupt signal generation
and µC clock enable. Timer with 2 related outputs for single
shot sampling of current and voltage channel in low power
mode.
Precision on chip RC oscillator or external clock. Low slew, low
EMC clock output which can be used by external
microcontroller which is enabled respectively disabled by mode
control through SPI and interrupt from current monitor in low
power mode.
The device is a stacked die system providing a high voltage CMOS
IC for power management and transceiver functions as a Top die
and low voltage sensor interface functions as a Bottom die inside
a 32-pin MLF (5x5 mm) package.
The integrated circuit can execute measurements with internal and
external sensors and sources for the voltage channel and with
external sensor for the current channel.
External Sensors:
Current measurement via Shunt resistor (4 ranges)
2 Key Features
A precision voltage attenuator with power down facility
Battery voltage (internal voltage divider to battery)
ETR and ETS for external temperature sensor (with switchable
LIN 2.1 transceiver
current source)
Power-On Reset with programmable reset timeout and brown-
Internal Sensors:
out detection through factory setting
On chip temperature sensor
A window Watchdog function in the normal mode and a timeout
Watchdog in the device standby mode as a factory option
Internal current sources for functional test of measurement path
and the connection of shunt resistor
Load dump protection (42V) for all battery supplied pins and
Enable pin
3 Applications
The AS8515 is suitable for battery sensors, having shunt current
sensor at minus pole. For lead acid, Li-Ion batteries up to 18V
nominal, 42V over voltage capability.
The device is also ideal as a general purpose sensor interface for
automotive LIN slaves.
Internal reverse polarity protection (up to -27V) for all battery-
sensing pins, and LIN bus pin
Over temperature warning & shutdown functions
Two independent high resolution A/D converters with
programmable over sampling ratio
Programmable sampling rate up to 4kHz throughput
Programmable gain, low noise amplifier for current channel with
gain stages 5, 25, 40, 100
www.ams.com
Revision 0.7
1 - 65
AS8515
Datasheet - Applications
Figure 1. AS8515 Block Diagram
AVDD
VCC
MEN
DVDD
To voltage
Channel ADC
Voltage Channel
Multiplexer,
VSUP
LDO
Current Source
CHOP_CLK
CLK
AS8515
Low
Precision
Clock
LPM
High
Precision
Clock
Control
Logic
POR_VSUP
POR_VCC
Current Channel ADC
DEC
RSHH
RSHL
PGA
Temperature
Limiter
VSENSE
Voltage Channel ADC
DEC
VSENSE_IN
PGA
VSENSE_GND
SPI,
Diagnosis,
WWD
SPI,
Comparator,
Filter Option
Reference
Generator
LIN
LIN
www.ams.com
Revision 0.7
2 - 65
AS8515
Datasheet - Contents
Contents
1 General Description ..................................................................................................................................................................
2 Key Features.............................................................................................................................................................................
3 Applications...............................................................................................................................................................................
4 Pin Assignments .......................................................................................................................................................................
4.1 Pin Descriptions....................................................................................................................................................................................
5 Absolute Maximum Ratings ......................................................................................................................................................
6 Electrical Characteristics...........................................................................................................................................................
1
1
1
5
5
7
8
6.1 Operating Conditions............................................................................................................................................................................
6.2 DC/AC Characteristics for Digital Inputs and Outputs..........................................................................................................................
8
8
6.3 System Specifications ........................................................................................................................................................................ 10
7 AS8515 Top Die Overview...................................................................................................................................................... 11
7.1 Voltage Attenuator.............................................................................................................................................................................. 11
7.2 Voltage Regulators (LDO) .................................................................................................................................................................. 11
7.3 LIN Transceiver .................................................................................................................................................................................. 11
7.4 Temperature Monitor/Limiter............................................................................................................................................................... 11
7.5 VSUP Under-voltage Reset................................................................................................................................................................ 12
7.6 Reset .................................................................................................................................................................................................. 12
7.7 VCC Under-voltage Reset.................................................................................................................................................................. 12
7.8 Window Watchdog (WWD)................................................................................................................................................................. 13
7.9 Timeout Watchdog (TWD).................................................................................................................................................................. 13
7.10 Modes of Operation.......................................................................................................................................................................... 14
7.10.1 Normal Mode ........................................................................................................................................................................... 15
7.10.2 Standby Mode.......................................................................................................................................................................... 15
7.10.3 Temporary Shutdown Mode .................................................................................................................................................... 15
7.10.4 Thermal Shutdown Mode......................................................................................................................................................... 15
7.11 Initialization....................................................................................................................................................................................... 16
7.12 Wake-up ........................................................................................................................................................................................... 17
7.12.1 Remote Wake-up Event........................................................................................................................................................... 17
7.13 LIN BUS Transceiver........................................................................................................................................................................ 18
7.13.1 Transmit Mode......................................................................................................................................................................... 18
7.13.2 Receive Mode.......................................................................................................................................................................... 18
7.14 Rx and Tx Interface .......................................................................................................................................................................... 19
7.14.1 Input Tx.................................................................................................................................................................................... 19
7.14.2 Output Rx................................................................................................................................................................................. 19
7.15 MODE Input EN................................................................................................................................................................................ 20
7.16 Top Die Block Specifications ............................................................................................................................................................ 21
7.16.1 Voltage Attenuator................................................................................................................................................................... 21
7.16.2 Voltage Regulator (LDO) ......................................................................................................................................................... 22
7.16.3 VCC Power-on-Reset .............................................................................................................................................................. 22
7.16.4 VSUP Power-on-Reset............................................................................................................................................................ 22
7.16.5 Window Watchdog Timer......................................................................................................................................................... 23
7.16.6 LIN Transceiver ....................................................................................................................................................................... 23
7.17 Timing Diagrams .............................................................................................................................................................................. 24
www.ams.com
Revision 0.7
3 - 65
AS8515
Datasheet - Contents
7.17.1 Tx Timeout Watchdog.............................................................................................................................................................. 26
7.17.2 Temperature Limiter ................................................................................................................................................................ 26
7.18 Top Die Registers ............................................................................................................................................................................. 26
8 AS8515 Bottom Die Overview ................................................................................................................................................ 28
8.1 Current Measurement Channel .......................................................................................................................................................... 28
8.2 Voltage/Temperature Measurement Channel..................................................................................................................................... 28
8.3 Digital Implementation of Measurement Path..................................................................................................................................... 29
8.4 Reference-Voltage.............................................................................................................................................................................. 29
8.5 Oscillators........................................................................................................................................................................................... 29
8.6 Power-On Reset................................................................................................................................................................................. 29
8.7 Modes of Operation............................................................................................................................................................................ 30
8.7.1 Normal Mode 1 (NOM1) ............................................................................................................................................................ 31
8.7.2 Normal Mode 2 (NOM2) ............................................................................................................................................................ 31
8.7.3 Standby Mode1 (SBM1) ............................................................................................................................................................ 32
8.7.4 Standby Mode2 (SBM2) ............................................................................................................................................................ 33
8.8 Initialization Sequence at Power ON.................................................................................................................................................. 33
8.8.1 Soft-reset of Device Using Bit D[7] of Reset Register 0x09....................................................................................................... 34
8.8.2 Soft-reset of the Measurement Path Using Bit D[7] of Reset Register 0x09 ............................................................................. 35
8.8.3 Reconfiguring Gain Setting of PGA .......................................................................................................................................... 35
8.8.4 Configuring the Device During Normal Mode ............................................................................................................................ 35
8.8.5 Standby Mode - Power Consumption........................................................................................................................................ 36
8.9 Bottom Die Block Specifications......................................................................................................................................................... 36
8.9.1 Current Measurement Ranges (across 100µΩ (±5%) shunt resistor)...................................................................................... 36
8.9.2 System Specifications................................................................................................................................................................ 43
9 4-Wire SPI Interface................................................................................................................................................................ 44
9.1 SPI Timing Parameters ...................................................................................................................................................................... 44
9.1.1 SPI Frame.................................................................................................................................................................................. 45
9.1.2 Write Command......................................................................................................................................................................... 45
9.1.3 Read Command......................................................................................................................................................................... 46
9.1.4 Timing........................................................................................................................................................................................ 47
9.2 Bottom Die Registers.......................................................................................................................................................................... 48
10 Application Information ......................................................................................................................................................... 60
11 Package Drawings and Markings.......................................................................................................................................... 61
12 Ordering Information............................................................................................................................................................. 64
www.ams.com
Revision 0.7
4 - 65
AS8515
Datasheet - Pin Assignments
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
RSHH
32
EN
31
RESET Rx
Tx
28
CST
27
INT
26
30
29
25
1
2
3
4
24
23
22
CLK
RSHL
VREF
VCM
SDI
MEN
21
20
19
CHOP_CLK
AVDD
AS8515
DVDD
DVSS
5
6
7
8
AVSS
ETR
18
17
SDO
ETS
SCLK
VSENSE_IN
9
10
11
12
13
14
15
16
VSS
VSENSE_GND LIN
VSENSE VSUP
VCC
CSB
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Name
Pin Number
Pin Type
Description
Negative differential input for current channel
RSHL
1
2
Analog input
Internal reference voltage to Sigma Delta ADC;
Connect 100nF to AVSS from this pin.
VREF
VCM
Analog output
Analog output
Common mode voltage to the internal measurement path;
Connect 100nF to AVSS from this pin.
3
+3.3V Power-supply; Supplied by LDO output (VCC) in Top die;
Should be shorted to pin 21 (VCC) externally.
AVDD 1
AVSS 2
4
5
Analog input
Power supply
0V Power-supply Ground analog
www.ams.com
Revision 0.7
5 - 65
AS8515
Datasheet - Pin Assignments
Table 1. Pin Descriptions
Pin Name
ETR
Pin Number
Pin Type
Description
Voltage channel single ended input
6
7
Analog input
ETS
Battery voltage attenuator output and voltage channel input
Input signal for voltage channel (low)
LIN BUS
VSENSE_IN
VSENSE_GND
LIN
8
Analog I/O
Analog input
Analog I/O
9
10
VSS 2
0V Power-supply Ground analog
11
12
Power supply
Analog input
Battery voltage input
Connect 100nF to VSS from this pin.
VSENSE
Supply input from battery (through external reverse polarity
protection device)
VSUP
-
13
Power supply
-
14
15
-
VCC 1
CSB
Regulated 3.3V output supply for loads up to 50mA
Analog output
Chip select for Bottom die
Clock signal SPI
16
17
18
Digital input
Digital input
Digital output
SCLK
SDO
Data signal SDO
DVSS2
0V Power-supply digital
19
Power supply
+3.3V Power-supply; Supplied by LDO output (VCC) in Top die;
Should be shorted to pin 21(VCC) externally.
DVDD 1
20
21
Analog input
Digital output
Chopper clock
CHOP_CLK
Digital output for Bottom die in SBM mode3 and input for Top
die
MEN
22
Digital I/O
Data signal SDI
SDI
CLK
-
23
24
25
26
27
28
29
30
31
32
Digital input
Digital I/O
Internal/External digital clock signal
-
-
Interrupt not: Wake-up, digital interrupt, ready flag 2
Chip select for Top die
INT
Digital output
Digital input
Digital input
Digital output
Digital output
Digital input
Analog input
CST
Tx
LIN transceiver transmit pin
LIN transceiver receive pin
Reset output (open drain)
Enable input
Rx
RESET
EN
Positive differential input for current channel
RSHH
1. Pin #4, pin #20 and pin #15 needs to be shorted externally on the board. Pin #21 is the LDO output that supplies pin #4 and pin #20.
2. Pin #5, pin #11 and pin #19 needs to be shorted externally on the board as they are the grounds.
3. Use as output port only.
www.ams.com
Revision 0.7
6 - 65
AS8515
Datasheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 8 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Min
Typ
Max
Units
Comments
Electrical Parameters
VSUP
Supply voltages
-0.3
-27
42
42
V
V
VSENSE
Battery voltage inputs
DC supply voltage
Enable input
AVDD,
DVDD
-0.3
-0.3
5
V
V
EN
VCC
LIN
42
VCC generated by Top die must not be larger
than 5V on board level as it has to be
connected with Bottom die AVDD and AVCC
Regulated output supplies
-0.3
5
V
LIN bus
-27
-0.3
-100
40
5
V
V
Analog & digital inputs and outputs
Input current (latch-up immunity)
100
mA
Norm: AEC-Q100-004
Electrostatic Discharge
±6
±4
±2
kV
kV
kV
LIN, VSS
VSUP, VSENSE
All other pins
Electrostatic discharge
Norm: AEC-Q100-002
ESD
Continuous Power Dissipation
Total operating power dissipation
MLF-32 in still air, soldered on JEDEC
standard board @125º ambient,
static operation = no time limit
1
0.375
W
Ptot
(all supplies and outputs)
Temperature Ranges and Storage Conditions
RΘ
Tstg
TJ
Package thermal resistance
Storage temperature
34
40
ºC/W
ºC
-55
150
130
Junction temperature
ºC
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020 “Moisture/Reflow
Sensitivity Classification for Non-Hermetic
Solid State Surface Mount Devices”.
The lead finish for Pb-free leaded packages is
matte tin (100% Sn).
TBODY
Package body temperature
260
85
ºC
%
Humidity non-condensing
Moisture Sensitive Level
5
Represents a maximum floor time of 168h
MSL
3
1. Total power dissipation cannot exceed 0.375W to avoid increase in junction temperature, i.e. greater than 130ºC. VCC LDO can supply
current externally, which is not greater than 17mA at 18V VSUP and 20mA at 16V VSUP.
www.ams.com
Revision 0.7
7 - 65
AS8515
Datasheet - Electrical Characteristics
6 Electrical Characteristics
Unless otherwise noted in this specification, all defined tolerances of parameters are assured over the whole operation conditions range and also
over lifetime.
6.1 Operating Conditions
Table 3. Operating Conditions
Symbol
VSUP
VSENSE
AVDD
AVSS
DVDD
DVSS
LIN
Parameter
Supply voltages
Min
4.3
4.5
3.15
0
Typ
Max
18
Unit
V
Note
Battery voltage input
Positive supply voltage
Negative supply voltage
Positive digital supply voltage
Negative digital supply voltage
LIN bus
18
V
3.45
V
V
3.15
0
3.45
V
V
Referring to DVSS, Typical 10%
0
18
18
V
EN
Enable input
0
V
VCC
Regulated output supply
Ambient temperature
3.15
-40
3.45
115
V
TAMB
ºC
Maximum junction temperature (TJ) is 130ºC
1
Supply current
27
mA
ISUP
When external clock is selected, internal clock
will be 4.096 MHz
fCLK
System clock frequency
8.192
MHz
1. Total power dissipation cannot exceed 0.375W to avoid increase in junction temperature, i.e. greater than 130ºC. VCC LDO can supply
current externally, which is not greater than 17mA at 18V VSUP and 20mA at 16V VSUP.
6.2 DC/AC Characteristics for Digital Inputs and Outputs
All pull-up, pull-downs have been implemented with active devices. SDO have been measured with 10pF load.
INT Output.
Table 4. INT
Symbol
VOH
VOL
Parameter
Condition
Min
Typ
Max
Unit
V
High level output voltage
Low level output voltage
Output current
2.5
0.4
4
V
IO
mA
CST, CSB, TxD.
Table 5. CST, CSB
Symbol
VIH
Parameter
Condition
Min
Typ
Max
Unit
V
High level input voltage
Low level input voltage
Input leakage current
Pull-up current
0.8*VCC
VIL
0.2*VCC
+1
V
ILEAK
IPU
-1
µA
µA
Pulled to GND
-150
-10
www.ams.com
Revision 0.7
8 - 65
AS8515
Datasheet - Electrical Characteristics
SDI, SCLK.
Table 6. SDI, SCLK
Symbol
VIH
Parameter
Condition
Min
Typ
Max
Unit
V
High level input voltage
Low level input voltage
Input leakage current
0.8*VCC
VIL
0.2*VCC
+1
V
ILEAK
-1
µA
SDO Output.
Table 7. SDO
Symbol
VOH
VOL
Parameter
Condition
Min
Typ
Max
Unit
V
High level output voltage
Low level output voltage
Output current
2.5
0.4
4
V
IO
mA
CHOP_CLK Output.
Table 8. CHOP_CLK
Symbol
VOH
VOL
Parameter
Conditions
Min
Typ
Max
Units
V
High level output voltage
Low level output voltage
Output current
2.5
0.4
4
V
IO
mA
EN Input.
Table 9. EN
Symbol
VIH
Parameter
Conditions
Min
Typ
Max
Units
V
High level input voltage
Low level input voltage
Input leakage current
Pull-down current
0.8*VCC
VIL
0.2*VCC
+1
V
ILEAK
Ipd_en
EN = VSS
-1
µA
µA
Pulled up to VCC
30
100
CLK I/O.
Table 10. CLK I/O
Symbol
Parameter
Condition
Min
Typ
Max
Unit
V
VIH
VIL
High level input voltage
Low level input voltage
Input leakage current
Pull-down current
2.4
1
+1
100
4
V
ILEAK
IPD_EN
IO
-1
µA
µA
mA
V
10
Output current
VOH
VOL
High level output voltage
Low level output voltage
2.5
0.4
V
www.ams.com
Revision 0.7
9 - 65
AS8515
Datasheet - Electrical Characteristics
MEN Output.
Table 11. MEN
Symbol
VOH
VOL
Parameter
Conditions
Min
Typ
Max
Units
V
High level output voltage
Low level output voltage
Output current
2.5
0.4
2
V
IO
mA
Rx Output.
Table 12. Rx
Symbol
VOH
Parameter
High level output voltage
Low level output voltage
Output Current
Conditions
Min
Typ
Max
Units
V
VCC-0.5
VOL
VSS+0.4
1
V
IO
mA
µA
Ipu_reset
Pull-up current
Pulled down to VSS
-30
-100
RESET Output.
Table 13. RESET
Symbol
VOH
VOL
Parameter
Conditions
Min
Typ
Max
Units
V
High level output voltage
Low level output voltage
Output current
2.5
0.4
8
V
IO
Open Drain Pull-down
mA
6.3 System Specifications
Table 14. System Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Unit
No load on VCC, LIN bus in dominant
state
Ivsupnom
Current consumption in normal mode
Current consumption standby
7
mA
No load on VCC,
LIN bus in recessive state
Ivsupstdby
80
µA
Note: Stand by mode power consumption is sum of stop mode power consumption and average of normal mode power consumption over a
period of 2s (NOM1 time of device is low in Standby mode).
www.ams.com
Revision 0.7
10 - 65
AS8515
Datasheet - AS8515 Top Die Overview
7 AS8515 Top Die Overview
The AS8515 Top die consists of a resistive divider, a low dropout regulator, and a LIN bus transceiver. Additionally integrated are a RESET unit
with a power-on-reset delay, programmable window watchdog and timeout watchdog timers as a factory programming option. It also includes a
watchdog timeout on LIN Tx node to indicate if the Microcontroller is stuck in a loop and the LIN bus remains in dominant time for more than the
necessary time.
7.1 Voltage Attenuator
A resistive divider is used as a battery voltage attenuator. Like the amplifier, the attenuator can be enabled or disabled through SPI, and in the
device standby mode, we additionally need logic high on MEN pin for enabling. Internal reverse polarity protection is provided for VSENSE pin.
Figure 3. Attenuator Implementation
VSENSE
PD
VSENSE_IN
VSENSE_GND
7.2 Voltage Regulators (LDO)
The device has a low-dropout voltage regulator named LDO, 3.3V voltage outputs. The output of the LDO is VCC. The regulator is always ON
except when the device enters the over-temperature shutdown.
The regulator has in-built short-circuit current limitation feature. The regulator can be temporarily shut down for hard reset of the external circuitry
by configuring the device to temporary shutdown mode through SPI.
The LDO power-up happens when the POR-VSUP event occurs (RESET_VSUP_N switching from low to high). The LDO will be switched off if
there is an under voltage on VCC, that is, when RESET_VCC_N switches back to low.
7.3 LIN Transceiver
The device has a LIN transceiver with slew-controlled bus driver for controlling the electromagnetic emissions from the LIN bus. Further, the slew
rate is independent of the bus load. The transmitter relays the data from the LIN controller (Tx pin) to the bus (LIN pin), and the receiver provides
the data on the bus to the controller (Rx pin). The transceiver conforms to the LIN 2.1 standard.
The LIN transceiver has a timeout watchdog for Tx. After the timeout, the LIN bus will be released to the recessive state from the dominant state.
The bus driver has an in-built short-circuit current limitation facility to protect the device from damage when there is a short between the bus and
the supply. In addition to the data receiver, there is a low-power receiver active in the device standby mode which received a wake-up event from
the LIN bus to bring the device to normal mode.
7.4 Temperature Monitor/Limiter
The temperature limiter circuit powers down the device when the junction temperature exceeds 170°C (nominal). It also issues an over-
temperature warning at 160°C (nominal). The device is powered up again when the junction temperature falls below 140°C (nominal). The over-
temperature warning flag is also cleared at this temperature.
The temperature limiter circuit can be optionally disabled through SPI.
www.ams.com
Revision 0.7
11 - 65
AS8515
Datasheet - AS8515 Top Die Overview
7.5 VSUP Under-voltage Reset
When VSUP drops below VSUVR_ON, the RESET_VSUP_N switches back to low level. This is treated as a master reset and will have the
highest priority over all other signals. In this case, the regulators, LIN transceiver, and all other blocks are shut off, and the device comes to a
complete stop. The device returns to the normal mode when VSUP rises over VSUVR_OFF again irrespective of the mode it was in prior to this
under-voltage condition.
7.6 Reset
RESET module generates an active-low reset signal for the external circuitry supplied by VCC. The behavior of the reset output is depicted in
Figure 4 in different cases. As shown, RESET signal is affected by an under-voltage condition on VCC and Watchdogs which are described in
detail in the subsequent sections.
The reset period can be one-time programmed to 4, 16 and 32 ms with a default value of 8 ms.
Figure 4. Reset Functionality
VSUP
T>Tj
T<Tj
t<trr
VCC
VUVR_OFF
VUVR_ON
tRes
tRes
tRes
tRes
trr
tRes
RESET
Over-temp
Shutdown
Glitch in
VSUP
Reset by
Watchdog
SC Current
Limitation Active
Start-up
VSUP UV
7.7 VCC Under-voltage Reset
When VCC drops below VUVR_ON, the RESET_VCC_N switches back to low level. This event generates a reset output. The reset output is
released again only a reset period (tRes) later after VCC rises above VUVR_OFF. If the time difference between the VCC falling below VUVR_ON
and rising above VUVR_OFF is less than trr, there will be no reset output. The reset output is affected in the conditions like over-temperature
shutdown and temporary shutdown only through VCC under voltage.
www.ams.com
Revision 0.7
12 - 65
AS8515
Datasheet - AS8515 Top Die Overview
7.8 Window Watchdog (WWD)
The Window Watchdog ensures that the Microcontroller is properly functioning in the normal mode of the device. The Watchdog is started after a
reset and the Microcontroller needs to send a trigger in the window of WD_TSV (service time). If the trigger occurs early, in the period WD_TCL,
or after WD_TSV, a reset output is generated.
The Microcontroller can access the trigger bit for the watchdog through SPI. The WWD can be enabled and the window times can be
programmed through factory setting and enabled as a factory option.
Figure 5. Window Watchdog Functionality
Period
Non-Service time (WD_TCL)
Service time (WD_TSV)
50 %
100 %
Trigger
restart
period
Trigger
via SPI
Last trigger
Earliest point for
correct trigger
(No RESET)
Latest point for
correct trigger
(No RESET)
Correct trigger
(No RESET)
Wrong trigger
(RESET generation)
Wrong trigger
(RESET generation)
7.9 Timeout Watchdog (TWD)
The Timeout Watchdog ensures that the Microcontroller is in proper functional state in the device standby mode. The Watchdog timer will be
started upon a rising edge on INT and will generate a reset output if the Microcontroller doesn’t send a trigger before the timeout.
The Microcontroller can access the trigger bit for the watchdog through SPI. The TWD can be enabled by factory setting and the timeout interval
can be programmed through SPI.
www.ams.com
Revision 0.7
13 - 65
AS8515
Datasheet - AS8515 Top Die Overview
7.10 Modes of Operation
The AS8515 Top die provides the following four main operating modes:
Normal Mode
Standby Mode
Temporary Shutdown Mode
Thermal Shutdown Mode
The LIN transceiver can be programmed to operate with lower slew in the normal mode. See Figure 6 for a detailed state transition diagram. Soft
states like “TxWD Wait”, “Standby Wait”, and other wait states have also been included in the state diagram for completeness.
Figure 6. Finite State Machine Model of AS8515 Top Die
INIT0
por_vsup
! temp170
OVTEMP
OTP LOAD
otp_load
temp170
temp170
128msec
RESET TIMEOUT
Temp Shut
reset
timeout
! por_vcc ||
wwdtimeout
test_en
RX=0
WAIT_TEST
NORMAL
Standby &
otp_mode
temp170
temp170
STANDBY
! por_vcc ||
stdby_timeout
WAIT_OTP
Rwake / local wake
! por_vcc ||
wwdtimeout
TXWD WAIT
temp170
temp170
STANDBY WAIT
! por_vcc ||
stdby_timeout
www.ams.com
Revision 0.7
14 - 65
AS8515
Datasheet - AS8515 Top Die Overview
Table 15. Transition Table
Transition
Interface
Reg.
0x05
D0
Flags
UVSENSE
OT
Comments
UVCC
inactive inactive
From Mode
To Mode
LIN
Rx
Tx
EN
Rwake
Tx is high for
TSTNDY_trigger
X-H1 H2
H-L2
Stand-By
X-RS
L
H2
L
X
X
X
The Control Bit is set
through the 4-Wire SPI
interface
Temporary
Shutdown
X-H1
X
X-RS
X-RS
H
X
X
X
inactive
set
set
set
Normal Mode
Temperature monitor
output asserted
(covered by scan)
Over-
X-H1
X
X
Temperature
H-X1
X
L-H2
X
Normal (LW)
Normal (RW)
X
X
L
L
X
X
X
inactive inactive
inactive inactive
Remote Wake up Event
occurred on LIN
H-X1
H
set
The Control bit is set
through the 4-Wire SPI
interface
Standby Mode
Temporary
Shutdown
H1
H2
L
RS
RS
L
L
X
X
X
X
X
X
inactive
set
set
set
H
Temperature monitor
output asserted
(covered by scan)
Over-
Temperature
H1
H
Temporary
Shutdown
Mode
Internal 128ms timer
expired
H-X1
X
Normal
RS-X
X
L
inactive
clear
Over-
temperature
Mode
Temperature monitor
output de-asserted
(covered by scan)
H-X1
X
Normal
RS-X
X
X
X
L
X
X
X
clear
X
clear
X
L-H2
All States
Power Off
X
X
X
1. Effect of transition
2. Cause for transition
Note: L = Low state, H = High state, OT = Over temperature Reset, UVCC = Under-voltage VCC, UVSENSE = Under-voltage VSENSE,
Rwake = Remote wake, X = don’t care.
7.10.1 Normal Mode
This is the mode after the power-up. In this mode, voltage regulator, LIN transceiver, window Watchdog is all active. The resistive divider can be
enabled through SPI. LIN transceiver is capable of sending the Tx data from microcontroller to the LIN bus at a maximum rate of 20Kbps.
7.10.2 Standby Mode
Standby Mode is a functional low power mode and is entered by pulling EN to ground. The LIN transceiver, resistive divider, window watchdog,
and Tx timeout watchdog circuits are disabled. But, it is possible to selectively enable the voltage and current measurement paths in this mode
using an externally generated measurement enable (MEN) signal on the MEN pin. The timeout Watchdog can be enabled in this mode to make
sure that the Microcontroller is active.
7.10.3 Temporary Shutdown Mode
In this mode, the regulator is powered down and the VCC is pulled down. This provides an alternative way to reset those components powered
by AS8515. The feature has to be enabled by the factory programming option and can be invoked through SPI. The LIN transceiver along with
the LIN wake-up circuits are powered down. No remote wake functionality possible. LIN bus enters into recessive state. The system goes out of
this mode to normal mode after the timeout of an internal timer.
7.10.4 Thermal Shutdown Mode
If the junction temperature TJ is higher than Tsd, the device will be switched into the thermal shutdown mode. The regulator and the transceiver
are completely disabled. Only the over-temperature monitor is active. As soon as the temperature returns back to TRET, the system enters
normal mode.
www.ams.com
Revision 0.7
15 - 65
AS8515
Datasheet - AS8515 Top Die Overview
7.11 Initialization
When the power supply is switched on, when VSUP > VSUVR_OFF, RESET_VSUP_N becomes high. This starts the regulator LDO with 3.3V
and Vuvr_off option of 2.75V. When VCC > Vuvr_off (2.75V), active-low PORN_2_OTP is generated. The rising edge of PORN_2_OTP loads
contents of fuse onto the factory setting latch after load access time TLoad. LOAD_OTP_IN_PREREG signal loads contents of factory setting
latch onto a register. This register provides the actual settings of LDO, Vuvr_off and Reset Timeout period TRes. This is done as the factory
setting block is powered by the VCC. If VCC > Vuvr_off (phase 2), Reset timeout is restarted. RESET signal is de-asserted after Reset Timeout
period TRes (phase 2) and then device enters into normal mode. The circuit also needs to initialize correctly for very slow ramp rates on VSUP (of
the order of 0.5V/min).
Figure 7. Initialization Sequence
VSUP_POR_Threshold
VSUP
RESET_VSUP_N
PHASE 2
PHASE 1
LDO On
LDO On
VCC Por Threshold = 2.75V
LDO setting = 3.3V
Reset Timeout = 4msec
VCC Por Threshold = from OTP Block
LDO setting = from OTP Block
Reset Timeout = from OTP Block
LDO Off
Device Settings
LDO settings to 5 V
LDO settings to 3.3 V
VCC_POR_Threshold
VCC
RESET_VCC_N
PORN_2_OT
P
6 Cycles of
RC-Oscillator
LOAD_OTP_IN_PREREG
RESET
If Phase 1 POR threshold != Phase 2 POR threshold
Tres = Reset Timeout from OTP Block
If Phase 1 POR threshold == Phase 2 POR threshold
Tres = Reset Timeout from OTP Block
Table 16. VSUP>Vsuvr_on and VCC<Vuvr_on
Block
Output Signal
LIN=high-z, Rx=follows VCC…
VCC=low…
TRANSCEIVER=Enabled (disabled only during initial VSUP ramp-up)
LDO=Enabled (disabled only during initial ramp-up)
RESET BLOCK=Enabled
RESET=high-z…
RESISTIVE DIVIDER=Enabled
VSENSE=high…, VSENSE_DIV=enabled
www.ams.com
Revision 0.7
16 - 65
AS8515
Datasheet - AS8515 Top Die Overview
Table 17. VSUP<Vsuvr_on
Block
Output Signal
LIN=high-z, Rx=high-z…
VCC=low
TRANSCEIVER=Disabled
LDO=Disabled
RESET BLOCK=Disabled
RESISTIVE DIVIDER=Disabled
RESET=high-z
VSENSE=high, VSENSE_DIV=low
7.12 Wake-up
When the device enters standby mode, it can be brought back to the normal mode. A dominant state on the BUS for duration of tWAKE (see Table
25) will result in the device wake-up which is termed as remote wake.
7.12.1 Remote Wake-up Event
In all low power modes of Top die, low power BUS receiver is ON. If BUS is in dominant state for longer than tWAKE then, remote wake is
sensed on the BUS and REMOTE_WAKE_flag is set. Indication of wake-up is given to µC by setting a bit in interrupt register and giving interrupt
on INTN pin.
Figure 8. Remote Wake-up Event
BUS
>Twake
REMOTE_WAKE_flag
Remote wake detected
www.ams.com
Revision 0.7
17 - 65
AS8515
Datasheet - AS8515 Top Die Overview
7.13 LIN BUS Transceiver
The AS8515 has an integrated bi-directional bus interface device for data transfer between LIN bus and the LIN protocol controller. The
transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver with high voltage comparator followed
by a de-bouncing unit.
7.13.1 Transmit Mode
During transmission the data at the pin Tx will be transferred to the BUS driver to generate a bus signal. To minimize the electromagnetic
emission of the bus line, the BUS driver has an integrated slew rate control and wave shaping unit.
Transmitting will be interrupted in the following cases:
Thermal Shutdown active
Master Reset (VSUP < Vsuvr_on)
The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode This diode prevents the reverse
current of VBUS during differential voltage between VSUP and BUS (VBUS>VSUP). No additional termination resistor is necessary to use the
AS8515 in LIN slave nodes. If this IC is used for LIN master nodes it is necessary that the BUS pin is terminated via an external 1kΩ resistor in
series with a diode to VSENSE.
7.13.2 Receive Mode
The data signals from the BUS pin will be transferred continuously to the pin Rx. Short spikes on the bus signal are suppressed by the
implemented debouncing circuit. Including all tolerances the LIN specific receive threshold values of 0.4*VSUP and 0.6*VSUP will be securely
observed.
Figure 9. Receive Mode Impulse Diagram
Vthr_max
60%
Vthr_cnt
Vthr_hys
50%
40%
BUS
Vthr_min
t < tdeb_BUS
t < tdeb_BUS
Rx
www.ams.com
Revision 0.7
18 - 65
AS8515
Datasheet - AS8515 Top Die Overview
7.14 Rx and Tx Interface
7.14.1 Input Tx
The 3.3V input Tx controls directly the BUS level. LIN Transmitter acts like a slew-controlled level shifter. A dominant state (low) on Tx leads to
the LIN bus being pulled low (dominant state) too. The Tx pin has an internal active pull up connected to VCC. This guarantees that an open Tx
pin generates a recessive BUS level.
Figure 10. Tx Interface
VCC
MCU
AS8515
VCC
RC-Filter
(10ns)
Tx
IPU_TxD
7.14.2 Output Rx
The received BUS signal will be output to the Rx pin:
BUS < Vthr_cnt – 0.5 * Vthr_hys → Rx = low
BUS > Vthr_cnt + 0.5 * Vthr_hys → Rx = high
This output is a push-pull driver between VCC and GND with an output current of 1mA
Figure 11. Rx Interface
MCU
AS8515
VCC
Rx
www.ams.com
Revision 0.7
19 - 65
AS8515
Datasheet - AS8515 Top Die Overview
7.15 MODE Input EN
The AS8515 Top die is switched from normal mode to the standby mode with a falling edge on EN and keeping Tx high for TSTNDY_trigger time.
Device is switched from standby mode to normal mode with a rising edge at the EN pin. The mode change for Top die with a falling edge on EN
can be done independently from the state of the transceiver bus. This ensures the direct control of device to enter into standby mode by
microcontroller using EN pin.
Figure 12. EN Pin Functionality
EN
Tx
TSTNDY_trigger
Ttx_hd
Ttx_su
Standby/Sleep
Mode
Normal
Mode
Normal Mode
The EN input has an internal active pull down to secure that if this pin is not connected, a low level will be generated.
Figure 13. Enable Interface
CLOAD
+
+3.3V
EN
VCC
RESET
Tx
VBAT
VSUP
LIN
+
CIN
MCU
VSS
Rx
VSENSE
If the application doesn’t need the low-power modes of the device, a direct connection of EN to VCC is possible. In this case the Top die
operates in permanent normal mode. Also possible is the external (outside of the module) control of the EN line via VSUP signal as shown
below.
www.ams.com
Revision 0.7
20 - 65
AS8515
Datasheet - AS8515 Top Die Overview
Figure 14. EN Connection for Permanent Normal Mode
CLOAD
+
+3.3V
EN
VCC
RESET
Tx
VBAT
VSUP
LIN
+
CIN
MCU
VSS
Rx
7.16 Top Die Block Specifications
This section provides specification of design related key parameters.
7.16.1 Voltage Attenuator
Table 18. Voltage Attenuator
Symbol
Parameter
Condition
Min
Typ
Max
Unit
RDIV
Division ratio
21
V/V
Input voltage range/
Battery voltage range
VSENSE
4.5
12
18
V
εp,RDIV
Ratio error
At room temperature, VSENSE=12V
±1
%
Temperature: -25 to +65º @VSENSE=12V
Maximum values will be added after device
evaluation (to be guaranteed by evaluation)
εdt1,RDIV
εdt2,RDIV
εdv1,RDIV
εdv2,RDIV
±0.05
±0.2
Ratio drift
(with reference to Temperature)
%
%
Temperature: -40 to +125º @VSENSE=12V
Maximum values will be added after device
evaluation (to be guaranteed by evaluation)
VSENSE: 11V to 13V @Temperature=27º
Maximum values will be added after device
evaluation (to be guaranteed by evaluation)
±0.05
±0.2
Ratio drift
(with reference to VSENSE)
VSENSE: 6V to 18V @Temperature=27º
Maximum values will be added after device
evaluation (to be guaranteed by evaluation)
www.ams.com
Revision 0.7
21 - 65
AS8515
Datasheet - AS8515 Top Die Overview
7.16.2 Voltage Regulator (LDO)
Table 19. Voltage Regulator
Symbol
VSUP
Parameter
Condition
Min
4.3
Typ
12
Max
18
Unit
V
Input Supply Voltage
Output Voltage Range
LDO Load Current
VCC
3.15
3.3
3.45
45
V
ILOAD
ICC_SH
dVCC1
mA
mA
mV/V
Output Short Circuit Current
Line Regulation
Normal mode
250
8
ΔVCC / ΔVSUP for VSUP range
ΔVCC / ΔICCn
(0.5mA < ILOAD < 50mA)
LOREG
Load Regulation
1
mV/mA
CL1
ESR1
2.2
1
10
10
220
1
μF
Ω
Output Capacitor 1 LDO
Electrolytic
Ceramic
CL2
100
0.02
22
nF
W
Output Capacitor 2 LDO
Input capacitor (Electrolytic)
Input capacitor (Ceramic)
ESR2
CSUP1E
ESR1_CSUP
CSUP2C
ESR2_CSUP
100
10
220
1
μF
Ω
1
For EMC suppression
100
0.02
nF
Ω
7.16.3 VCC Power-on-Reset
Table 20. VCC
Symbol
Vuvr_off
Vuvr_on
Parameter
Condition
Min
2.55
2.3
Typ
Max
2.95
2.7
Unit
V
VCC under-voltage threshold OFF
VCC under voltage threshold ON
Rising edge of VCC
Falling edge of VCC
V
Hysteresis of under-voltage threshold
on/off VCC
Vhyst_vcc
0.1
0.25
0.4
V
7.16.4 VSUP Power-on-Reset
Table 21. VSUP
Symbol
Vsuvr_off
Parameter
Condition
Min
4.8
3.5
1.1
Typ
5.1
3.8
Max
5.4
4.1
1.5
Unit
V
VSUP under-voltage threshold OFF
VSUP under-voltage threshold ON
Hysteresis of VSUP under-voltage
Rising edge of VSUP
Falling edge of VSUP
Vsuvr_on
V
Vhyst_VSUP
V
www.ams.com
Revision 0.7
22 - 65
AS8515
Datasheet - AS8515 Top Die Overview
7.16.5 Window Watchdog Timer
Table 22. WWD
Symbol
WD_TCL
Parameter
Condition
Min
Typ
0-100
Max
Unit
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
WWD non-service time
WWD Service time
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
Factory
setting 1
WD_TSV
WD_TCL1
WD_TSV1
WD_TCL2
WD_TSV2
WD_TCL3
WD_TSV3
WD_TCL4
WD_TSV4
WD_TCL5
WD_TSV5
100-200
0-80
WWD non-service time
WWD Service time
Factory
setting 2
80-160
0-60
WWD non-service time
WWD Service time
Factory
setting 3
60-120
0-200
WWD non-service time
WWD Service time
Factory
setting 4
200-400
0-160
WWD non-service time
WWD Service time
Factory
setting 5
160-320
0-120
WWD non-service time
WWD Service time
Factory
setting 6
120-240
7.16.6 LIN Transceiver
DC Electrical Characteristics.
Table 23. Driver
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Current limitation in dominant state
LIN = VSUP_max
Ibus_lim
40
120
200
mA
Output Voltage BUS (dominant state),
ILIN = 40mA
(short-circuit condition tested at VOL=2.5V)
LIN_VOL
2
V
Normal mode
(recessive BUS level on Tx pin)
Pull-up resistor
20
40
60
KΩ
Driver OFF; 7.3V < VSUP < 18;
8V < VBAT < 18,
VSUP < VBUS < 1.08 * VSUP
(to be tested at VBUS = 18V)
Ibus_leak_rec
20
µA
Table 24. Receiver
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Input Leakage current at receiver
Driver OFF;
Ibus_leak_dom
Ibus_no_GND
Ibus_no_bat
-1
mA
VBUS = 0V; VSUP = 12V; VCC = 3.3V
VSS = VSUP; VSUP = 12V;
0V < VBUS < 18V, VCC = 3.3V
(to be tested at VBUS = 18V)
-1
1
mA
µA
VSUP = VSS; 0V < VBUS < 18V,
VCC = VSS
(to be tested at VBUS = 18V)
100
0.4
Vbus_dom
Vbus_rec
Vbus_cnt
VSUP
VSUP
0.6
1
0.475
0.525
0.175
VSUP
VSUP
Vbus_cnt = (Vth_dom + Vth_rec)/2
1
Vhys
0.05
Vhys = (Vth_dom – Vth_rec
)
1. Vth_dom : Receiver threshold of the recessive to dominant LIN bus edge
Vth_rec : Receiver threshold of the dominant to recessive LIN bus edge
www.ams.com
Revision 0.7
23 - 65
AS8515
Datasheet - AS8515 Top Die Overview
AC Electrical Characteristics.
LIN Driver, Bus load conditions (CBUS ; RBUS): 1nF; 1kΩ / 6, 8nF; 660Ω / 10nF; 500Ω
Table 25. LIN Driver
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Vth_rec(max) = 0.744 x VSUP;
Vth_dom(max) = 0.581 x VSUP;
VSUP = 6.0V...18V; tbit = 50µs;
D1 = tbus_rec(min) / (2 x tbit)
D1
(worst case 20Kbps transmission)
0.396
Vth_rec (min) = 0.422 x VSUP;
Vth_dom (min) = 0.284 x VSUP;
VSUP = 6V...18V; tbit = 50µs;
D2 = tbus_rec(max) / (2 x tbit)
D2
D3
D4
(worst case 20kbps transmission)
(worst case 10.4kbps transmission)
(worst case 10.4kbps transmission)
0.581
Vth_rec (max) = 0.778 x VSUP;
Vth_dom (max) = 0.616 x VSUP;
VSUP = 6.0V...18V; tbit = 96µs;
D3 = tbus_rec(min) / (2 x tbit)
0.417
Vth_rec (min) = 0.389 x VSUP;
Vth_dom (min) = 0.251 x VSUP;
VSUP = 6V...18V; tbit = 96µs;
D4 = tbus_rec(max) / (2 x tbit)
0.59
VCC = 3.3V;
tdLR
tdHR
6
6
µs
µs
Propagation delay bus dominant to Rx LOW
VCC = 3.3V;
Propagation delay bus dominant to Rx HIGH
tRS
Receiver delay symmetry
-2
2
µs
µs
tWAKE
Dominant time for wake-up via LIN bus
30
150
Transition from standby mode to normal
mode (clock frequency is 128KHz ±25%)
Clock
tsln
4
6
cycles
Transition from normal mode to standby
mode (clock frequency is 128KHz ±25%)
Clock
cycles
tnsl
trec_deb
Receiver de-bounce time
0.6
3
µs
Internal capacitance of the LIN node
configured as a slave with a 180pF cap on
the LIN bus
Cint
220
250
pF
7.17 Timing Diagrams
Figure 15. Timing Diagram for Propagation Delays
50%
TxD
tdf_TXD
tdr_TXD
VBUS
100
%
95%
BUS
50%
50%
5%
0%
tdf_RXD
tdr_RXD
RxD
50%
www.ams.com
Revision 0.7
24 - 65
AS8515
Datasheet - AS8515 Top Die Overview
Figure 16. Timing Diagram for Duty Cycle According to LIN 2.1 and J2602
tBit
tBit
TxD
tx_dom_max
tx_rec_max
tx_dom_min
tx_rec_min
trec(min)
100
%
VSUP
tdom(max)
74.4%
77.8%
tdom(min)
58.1%
61.6%
58.1%
61.6%
BUS
42.2%
38.9%
28.4%
25.1%
28.4%
25.1%
trec(max)
0%
VSS
tbit
tbit
TxD
LIN
tbus_dom(max)
tbus_rec(min)
Vth_rec(max)
Vth_dom(max)
Vth_rec(min)
Vth_dom(min)
tbus_rec(max)
tbus_dom(min)
www.ams.com
Revision 0.7
25 - 65
AS8515
Datasheet - AS8515 Top Die Overview
7.17.1 Tx Timeout Watchdog
Table 26. Tx Timeout Watchdog
Symbol
Parameter
Timeout period for the dominant state
Conditions
Min
Typ
Max
Units
tlin_wdog
0.5
1
2
s
7.17.2 Temperature Limiter
Table 27. Temperature Limiter
Symbol
Tsd
Parameter
Conditions
Min
155
142
125
Typ
170
157
140
Max
185
172
155
Units
ºC
Shut down temperature
Over-temperature warning
Return temperature
Totset
Tret
Junction temperature
ºC
ºC
7.18 Top Die Registers
The serial interface can be used for communication between AS8515 and an external microcontroller. The device is only a slave and the
microcontroller has to initiate the communication. The device can be configured by writing into the control registers and the diagnostic
information can be read out from the diagnostic registers. Pin CST is used as chip select for SPI communication.
A total of 32 registers, each of 8-bits which include configuration, diagnostic, and backup are available. The registers can be accessed using the
4-wire serial interface. Table 28 provides a description of all AS8515 Top die registers.
Table 28. AS8515 Top Die Registers
Address Register Name Default Value
Configuration and Control Registers
R/W
Description
0x00
0x01
0x02
Reserved
Reserved
Reserved
D0 Reserved
D1 Voltage Attenuator Enable Bit.
0 Disabled, 1 Enabled
D2 Enable/Disable Over Temperature Monitor
0 Disabled, 1 Enabled
D3 Enable/Disable LIN Transceiver
0 Disabled, 1 Enabled
Device
Configuration
Register
On POR_VCC
0000_1100
0x03
R/W
D4 Reserved
D5-D7 Reserved
D0 High-slew / Low-slew control
1 High-slew, 0 Low-slew
D1-D7 Reserved
Device Control On POR_VSUP
0x04
0x05
R/W
R/W
Register
0000_0001
D0 Temporary shutdown control bit
1 Enter temporary shutdown
D1-D7 Reserved
Temporary
Shutdown
Register
On POR_VCC
0000_0000
D0 Window Watchdog trigger bit
D1 Timeout Watchdog trigger bit
Upon a trigger, the bit will be cleared within 2 internal clock cycles.
D2-D7 Reserved
Window Watch
Dog Trigger
Register
On POR_VCC
0000_0000
0x06
W
0x07
0x0A
0x0B
Reserved
Reserved
Reserved
www.ams.com
Revision 0.7
26 - 65
AS8515
Datasheet - AS8515 Top Die Overview
Table 28. AS8515 Top Die Registers
Address Register Name Default Value
R/W
Description
0x0C
0x0D
Reserved
Reserved
D0 Timer resolution
0 1 second, 1 32 seconds
Watchdog Timer On POR_VCC
0x0E
0x0F
R/W D1-D7 Timeout period.
If D0=1, then timeout period = D[7:1]*64*0.512 seconds, else timeout period
= D[7:1]*0.512 seconds
Control Register
0000_0000
Reserved
Diagnostic Registers
D7-D0 = DR[7:0], 8-LSB bits of the 24-bit Diagnostic Register.
D0 POR-VSUP
Set when VSUP < Vsuvr_on, cleared after µC read
D1 Under voltage VCC (UVVCC)
Set when VCC < Vuvr_on, cleared after µC read
D2 Over-temperature Reset (OTEMP170)
Set when temp > Tsd, cleared after µC read
D3 Over-temperature warning (OTEMP160)
Set when temp > Totset, cleared after µC read
D4 Overvoltage VSENSE (OVVSENSE)
Set when VSUP > Vovthh, cleared after µC read
D5 Reserved
Diagnostic
Register-1
On POR_VSUP
0000_0011
0x08
R
D6 Remote wakeup (RWAKE)
Set on remote wakeup event on LIN Bus, cleared after µC read
D7 Set on failure of window Watchdog trigger, cleared after µC read
D7-D0 = DR[15:8], Next 8-LSB bits of the 24-bit Diagnostic Register.
D0 Tx timeout of 1sec (TXTIMEOUT)
Set on Tx low > 1sec, cleared after µC read
D1 TEMPSHUT
This bit is set on entering temporary shutdown state and cleared after µC read.
D2 Set on failure of timeout Watchdog trigger, cleared after µC read
D3 Load Dump Flag
Diagnostic
Register-2
On POR_VSUP
0000_0000
0x09
R
D7-D4 Reserved
www.ams.com
Revision 0.7
27 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
8 AS8515 Bottom Die Overview
The AS8515 Bottom die consists of two independent high resolution 16-bit SD analog to digital conversion channels. The measurement path
of these two channels integrates a programmable gain amplifier, chopper and de-chopper, sigma-delta modulator, decimator and a digital filter
for simultaneous measurement of Current and Voltage/Temperature.
The two measurement channels, namely the Current and Voltage/Temperature measurement channels have identical data path.
The input signal is amplified in the Programmable Gain Amplifier (PGA) with any of the selected gains of 1, 5, 25, 40 and 100 facilitating
measurement of a wide range of Current, voltage and temperature levels. Gain Settings for different input ranges and any associated restrictions
are explained in the Table 30.
Offset in the measurement path is minimized with the use of a chopper and a de-chopper at appropriate stages in the data path. By default the
chopper/de-chopper is ON in the measurement path. It may be disabled by programming the appropriate register.
The amplified input signal is converted into a single-bit pulse-density modulated stream by the Σ-Δ Modulator. A decimator acting as a low-pass
filter filters out the quantization noise and generates 16-bit data corresponding to the input signal. The decimation ratios of 64, 128 may be
selected in the first filter stage. For reducing data rate further, the second stage decimation can be used.
An optional FIR Filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems.
8.1 Current Measurement Channel
The voltage across a Shunt Resistor, connected in series with the Battery negative terminal, forms the input signal to the Current Measurement
channel. RSHH and RSHL are the Current measurement input pins. Offset in the input signal is nullified with the use of a chopper and a de-
chopper at appropriate stages in the data path. The programmable gain amplifier in the data path with programmable settings of 1, 5, 25, 40 and
100 enables measurement of current ranges from ±1A to ±1500A on a 100µΩ shunt. The sampled input signal is converted into a single-bit
pulse-density modulated stream by the Σ-Δ Modulator. A decimator acting as a low-pass filter filters out the quantization noise and generates 16-
bit data equivalent to the input current signal. The programmable input sampling rate and the decimation ratio determine the output data rates.
The data path can be programmed to provide sub 1Hz to 4kHz rates in the various modes available. An optional FIR filter specifically designed
for 1KHz sample rate is provided to offer matched low pass filter response typically required in lead acid battery sensor systems.
After enabling the current measurement channel, the delay for the availability of the first sample is two conversion cycles.
8.2 Voltage/Temperature Measurement Channel
The other two parameters of the Battery for measurement are Voltage and its Temperature. The second channel accepts signals from four
independent sources through a Multiplexer as listed below:
An attenuator battery voltage obtained through internal resistor divider from Top die, (or)
A signal from the external temperature sensor, (or)
A signal from external reference, (or)
A signal from the internal temperature sensor.
Apart from this difference in the multiplexing of four input signals, the rest of the data path is identical to the Current measurement channel.
RSHH and RSHL are the Current measurement input pins.
The Battery Voltage which can go up to 18V is attenuated through a Resistor Divider externally and is applied to the Voltage Channel. For
Automotive Battery measurement, the PGA is to be bypassed to connect battery voltage attenuated by a factor of 21 directly to the ADC input.
The latency for the first result from the voltage measurement channel is two conversion cycles.
A second option on this measurement channel is to measure Temperature. Internally generated constant current is pumped through the
Temperature Sensor with positive temperature coefficient, and, a high- precision resistor. The voltages across the sensor and the resistor form
the inputs to the measurement channel one at a time. The difference between the two voltages which is independent of the magnitude of the
current is used to determine the temperature accurately. The voltage across the sensor is applied between the ETS and VSS pins and, the
voltage across the high-precision resistor is applied between ETR and VSS. External temperature measurement involves the acquisition of two
signals one after the other using the same constant current source. The latency for the first result from the temperature measurement channel is
two conversion cycles.
A third option on the measurement channel is to measure the internal temperature. Hence, one of the three options for measurement of Battery
Voltage, External Temperature and, internal temperature may be carried out by selection of appropriate inputs through the internal multiplexer
selection.
ETR and ETS inputs can optionally be used to measure other signal sources like external resistive attenuators for battery voltages different to
12V nominal.
ETR and ETS are single ended inputs and referenced to AVSS. Voltage drop on internal bond wire causes ~100 digits of offset with systematic
temperature dependency of another 50 LSB’s over temperature.
www.ams.com
Revision 0.7
28 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
8.3 Digital Implementation of Measurement Path
Figure 17. Block Diagram of Digital Implementation
R2
FIR_MA_SEL
FIR / MA
R1
fchop * 2 / R2
fchop * 2 / R2
DATAOUT
fchop * 2
MOD_I
N
fmod / R1
CIC1
64 / 128
Dechopper
CIC2
fmod
R1
MOD_CLK
fchop
R1 = First decimation ratio (64 or 128)
R2 = Second decimation ratio (1 to 32768)
CHP_CLK
CLK DIVISION
BLOCK
MOD_CLK
Figure 17 shows the digital implementation of the decimator and filter to process the 1-bit output of the Modulator. This block receives a 1-bit
pulse density modulated output (MOD_IN) from the second order sigma delta modulator along with the oversampling frequency clock
(MOD_CLK). The MOD_CLK directly goes to a clock division block, which generates chopper clock (CHOP_CLK). The CHOP_CLK can be one
of 2kHz or 4kHz selected by Register CLK_REG in Table 49. The MOD_CLK can be either 1MHz or 2MHz. The Decimation is a two phase
process. In the first phase, the R1 down sampling rate can be obtained by selecting either 64 or 128 in Registers DECREG_R1_I,
DECREG_R1_V in Table 49. The 16-bit CIC1 output is dechopped with respect to CHOP_CLK. The output of Dechopper is passed through the
CIC2 filter with a decimation ratio of 1to 32768 in steps of power of 2. This output is then processed through a FIR or Moving Average (MA) filter.
FIR Filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems. MA filter is used to provide
averaged output and the number of samples for averaging can be any integer value from 1 to 15.
8.4 Reference-Voltage
Band gap-reference voltage is used for the ADC as a reference and for the generation of the current for external temperature measurement.
8.5 Oscillators
A High-speed oscillator (HS) generates the oversampling clock. For internal state machine and Interrupt generation, a low-speed Oscillator (LS)
is also available.
8.6 Power-On Reset
The AS8515 has PORs, APOR and DPOR on analog and digital power supplies respectively. On PORs of both supplies, initialization sequence
happens and the system status is shown in state diagram (see Figure 18).
As shown in the state diagram, the system is in RESET state until DPOR output goes to logic HIGH and subsequently until APOR output goes to
logic HIGH. Once analog power supply is available, the system goes into OTP_INT state and loads the default values into the control and data
registers and goes into STOP state. If analog POR, APOR goes low at any time, the system goes into RESET state. In the STOP state, the
AS8515 can be programmed and by giving start command it starts working following the state machine.
www.ams.com
Revision 0.7
29 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
8.7 Modes of Operation
The device operates in four different modes, namely,
Normal Mode 1 (NOM1)
Normal Mode 2 (NOM2)
Standby Mode 1 (SBM1)
Standby Mode 2 (SBM2)
The Normal Modes are full-power modes with the exception that in Normal Mode 2, sampling is normally at a programmed lower frequency and
is increased to a higher rate only when a measured input signal level crosses the programmed threshold in the current measurement channel.
The Standby Modes are lower power modes. Sampling is normally at a very low frequency interval. In Standby Mode 2, data sampling can be
carried out only when the internal comparator detects the input current to be greater than the programmed threshold and it generates interrupt on
the INT pin.
The device enters into the “Stop” state on Power On. This is a state where in the data path is inactive and can be entered into from any of the
four Modes. The State transition Diagram involving the state of Stop and the four Modes is illustrated in the Figure 18.
Figure 18. Finite State Machine Model of AS8515 Bottom Die
RESET
Wait for otp_load
Completes in 32 cycles
OTP_INT
of lp_clk
STOP
1.5msec &
Analog Stablization
NORM
A_STB
NORM
period
Wait for 1.5msec
NORM
or
stop
Wait for x
number of
conversions
Wait for TT1
timeout
SBM
SBM_ON
SBM_OFF
www.ams.com
Revision 0.7
30 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
Figure Notes:
1. Device soft reset can be written in any of the following states STOP, A_STB, SBM_ON, SBM_OFF by writing “0” into D[7] of the RESET
_REG (Address 0X09).
2. Measurement path of soft reset should be written in any the states, STOP, SBM_OFF by writing “0” into D[6] of the RESET _REG (Address
0X09).
3. When soft reset is used for the measurement path or for the device, external clock needs to be disabled if the system clock is external
clock in the application.
8.7.1 Normal Mode 1 (NOM1)
On Power-on-reset of the device, AS8515 goes into STOP State.
Transition to Normal mode1 (NOM1) occurs when the “START BIT” D0 of Mode Control Register MOD_CTL_REG in Table 49 is set to “1”
through the serial port SPI. Data Rate of voltage and current channels can be independently programmed and both the channels generate
interrupts for every output available from ADC. The interrupt signal is generated on the INT pin. The width of the interrupt pulse is eight cycles of
lp_clk. The data is stable up to the next interrupt. If the data rate is different for the two channels, the interrupt rate would follow the higher rate
among the two channels. Data update can be known by reading the status register. The functionality is explained in the waveform shown in
Figure 19. When the device is configured to NORMAL Mode1 from any mode the configuration should be through the STOP state only.
Figure 19. Normal Mode 1
I
IDATA
Sampling with f1
t
V,T
V,TDATA
Sampling with f2
STOP
t
START
Current Channel
DATA Register
Voltage Channel
DATA Register
INT at f1 rate from
current channel
T
INT
Interrupt from the current channel is at f1 rate which is integer multiple of f2 rate from voltage channel
8.7.2 Normal Mode 2 (NOM2)
NOM2 differs from NOM1 in such a way that it allows for a relaxed data rate at a period of TMC by programming the corresponding register as
long as the amplitude of current is less than a programmed threshold ITHC. However, when, the measured input signal exceeds the programmed
threshold, the data rate is changed to the rate of NOM1 mode.
Transition to NOM2 occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in Table 49 is set to 1 and mode control bits to
01 through SPI. In this mode the data rate should be programmed with the time of TMC. An interrupt signal is generated on INT at the rate of TMC
secs with a pulse width of eight cycles of lp_clk. The data is stable up to the next interrupt. The data sample is compared against the programmed
threshold and when it is exceeded, the data sampling rate is changed to provide data at the data rate of NOM1 mode. However, as soon as the
data sample amplitude falls below the programmed threshold, the sampling rate is restored to provide data at the rate of TMC. The functionality is
illustrated in the waveform Figure 20.
www.ams.com
Revision 0.7
31 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
Figure 20. Normal Mode 2
I
I < I THS
V,I,T
V,I,T
V,I,T
V,I,T
V,I,T
IDD
TMC
TMC
ITHS
t
Sampling with f
I > ITHS
INT
T
INT
8.7.3 Standby Mode1 (SBM1)
The low-power Standby Mode can be entered only through the STOP state. Transition to SBM1 mode occurs when the “START BIT” D0 of Mode
Control register MOD_CTL_REG in Table 49 is set to “1” and Mode Control Bits to “10” through SPI. In this mode the date rate is programmable
with the time of Ta. An interrupt signal is generated on INT at the rate of Ta seconds, and with a pulse width of eight cycles of lp_clk. The data is
stable up to the next interrupt. The functionality is illustrated in Figure. During the period of Ta, only one data sample is made available and,
during the rest of the period, the device is maintained in STOP state to reduce power consumption. The microcontroller which receives the data
on the Interrupt, is also expected to be processing the data for a short time as shown clearly in the Figure 21 to ensure the overall low-power
consumption of the data acquisition and processing system.
Figure 21. Standby Mode 1
I DD
MCU
MCU
MCU
V, I, T
V, I, T
ADC
t
Ta sec.
Ta sec.
Ta sec.
T
conv
T
conv
T
conv
Start SBM1
Channel
DATA Register
DATA – A0
DATA – A1
DATA – A2
DATA – A3
INT
T
INT
www.ams.com
Revision 0.7
32 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
8.7.4 Standby Mode2 (SBM2)
Standby Mode 2 is an extension of the Standby Mode1 to achieve even a lower power in the data acquisition system by providing interrupt to the
microcontroller only when the data sample exceeds the set current threshold. The Standby Mode can be entered only through the STOP state.
Transition to SBM2 mode occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in Table 49 is set to “1” and Mode Control
Bits D7,D6 to “1,1” through SPI. In this mode the date rate is programmable with the time of Ta in the Ta control registers B, C. The data sample
is made available and an interrupt signal is generated on INT pin only when the input signal exceeds the threshold set in Current Threshold
Registers D,E. It should be noted here that the data is stable for Ta seconds. The functionality is illustrated in Figure 22.
Figure 22. Standby Mode 2
IDD
MCU
|I| > I Threshold I
I
ADC
t
T
a
sec.
Ta sec.
Ta sec.
T
conv
T
conv
Tconv
Start SBM2
Channel
DATA Register
DATA – A3
DATA – A0
DATA – A1
DATA – A2
INT
T
INT
8.8 Initialization Sequence at Power ON
Figure 23. Bottom Die Device Initialization Sequence at Power ON
VPORHID/VPORHIA
DVDD/AVDD
POR_N
INT
Start
ADC
1.5mS
TADC
D2
500µS
D3
D4
D3
D4
D3
D4
D1
D1
D2
D1
D2
Configure
Device
CHOP_CLK
Channel Data
Register
0x0000
DATA1
DATA2
TDATA_INVALID
TDATA_STATUS_RD
TDATA_VALID
Device initialization starts if the DVDD and AVDD supplies are switched ON and DVDD > VPORHID. The duration period of Initialization is 500μsec
and during this period, INT pin toggles at the rate of internal low power oscillator. Toggling on INT during the period of initialization should be
ignored in the system. Device configuration and activation should be carried out only after the initialization period.
On ADC start, device enters into analog stabilization state and takes 1.5msec for oscillator and Reference to settle. After this 1.5msec period, the
first interrupt will occur after a time period of TADC
.
www.ams.com
Revision 0.7
33 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
TDATA_STATUS_RD is the time period during which the micro-controller should complete reading of data and status from the device. If reading is
carried out beyond this time period, then, ADC performance will degrade for next sample generation. Status register gets cleared automatically
only when micro-controller reads this register. Data in the channel registers is changed after TDATA_VALID duration. Ensure that data channel
registers and status registers are not read during the TDATA_INVALID duration.
Example:
Configuration registers are set as follows:
CLK_REG = 8’b0010_0000
DEC_REG_R1_I = 0100_0101
DEC_REG_R2_I = 1100_0101
FIR_CTL_REG_I = 0000_0100
ADC is configured to a data rate of 1KHz, CHOP_CLK to 2KHz, and Modulator clock to 1MHz, Decimation ratio of CIC1 = 64, and Decimation
ratio of CIC2 = 4. With these settings the various time periods as shown in the Figure 23 are as follows:
TDATA_STATUS_RD = 100 μsec
(TDATA_STATUS_RD = (1/mod_clk) * R1 * [((mod_clk/(2*chop_clk))*(1/R1)) - 2.5)
TDATA_INVALID = 8 μsec
TADC = 1msec
TDATA_VALID = TADC - TDATA_INVALID = 1msec - 8 μsec
CHOP_CLK and POR_N are internal signals of the device.
Table 29 provides valid combinations of Modulator clock, Chopper clock and Decimation R1 and the corresponding values of TDATA_STATUS_RD and
TADC
.
Table 29. Valid Combinations of Modulator Clock, Chopper Clock and Decimation Ratio R1
TADC
Chopper Frequency
TDATA_STATUS_RD
Modulator Clock
Decimation Ratio R1
R2/(2*CHOP_CLK)
for R2=4
CHOP_CLK
1.024MHz
2.048MHz
2KHz
64
64
1usec * 64 * [4 - 2.5] = 96usec
1mSec
1mSec
0.5usec * 64 * [8 - 2.5] = 176usec
2KHz
0.5usec * 128 * [4 - 2.5] = 96usec
0.5usec * 64 * [4 - 2.5] = 48usec
2.048MHz
2.048MHz
2KHz
4KHz
128
64
1mSec
0.5mSec
8.8.1 Soft-reset of Device Using Bit D[7] of Reset Register 0x09
It is possible to soft-reset the device by writing “0” into D[7] bit of Reset Register at 0x09. On applying soft-reset, the device enters into
initialization state and D[6] bit changes back to “1”. The duration period of Initialization is 500μsec, and, during this period, INT pin toggles at the
rate of internal low power oscillator. Toggling on INT during the period of initialization should be ignored in the system. Device configuration and
activation should be carried out only after the initialization period. See Figure 24 for the timing details of the sequence of device initialization on
soft-reset.
www.ams.com
Revision 0.7
34 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
Figure 24. Bottom Die Device Initialization Sequence at Soft-reset
Start
ADC
1.5mS
INT
500µS
D4
D3
D4
D
3
D4
D3
D4
D3
D4
D1
D2
D1 Soft Reset
D1
D2
D1
D2
D1
D2
Re-Configure
Device
Using D7
CHOP_CLK
Channel Data
Register
0x0000
DATA-N
DATA-N+1
TDATA_INVALID
DATA1
DATA2
TDATA_STATUS_RD
TDATA_STATUS_RD
TDATA_VALID
TDATA_INVALID
TDATA_VALID
8.8.2 Soft-reset of the Measurement Path Using Bit D[7] of Reset Register 0x09
Measurement path also can be reset by using D[6] bit of Reset Register at 0x09. On applying soft-reset only signal measurement path registers
will be reset. For applying this reset, device should be in STOP state. If the device is working with external clock, at the time of soft-reset the
clock needs to be disabled.
8.8.3 Reconfiguring Gain Setting of PGA
Only PGA gain settings can be changed dynamically while ADC conversions are in progress. When PGA gain settings are changed, the first
sample from the ADC is invalid. Ignore the first interrupt after the gain re-configuration. Valid data starts from the second interrupt onwards.
Figure 25. Bottom Die - Re-configuration of Gain Setting of PGA
Gain Re-Configuration can be
carried out in this slot, skip next
interrupt and Channel Data.
Read Channel
data in this slot
VALID
DATA
TDATA_STATUS_RD
INT
D3
D4
D4
D3
D4
D3
D4
D3
D4
D1
D2
D1
D2
D1
D2
D1
D2
CHOP_CLK
Channel Data
Register
DATA-N
DATA-N+1
DATA1
TDATA_STATUS_RD
DATA2
TDATA_STATUS_RD
TDATA_INVALID
TDATA_INVALID
TDATA_VALID
TDATA_VALID
8.8.4 Configuring the Device During Normal Mode
Following registers can be programmed dynamically when the device is in operational mode (Normal mode).
ACH_CTL_REG address is 0x17 for channel selection on the voltage measurement path
PGA_CTL_REG address is 0x13 for gain setting
PD_CTL_REG2 address is 0x15 for PGA Bypass
ISC_CTL_REG address is 0x18 for current source programmability
During the operation (Normal mode) of the device, if any of the registers need to be programmed or changed other than the above mentioned
registers, then it is required to STOP the device by writing into MOD_CTL_REG “STOP” bit and configure the device as per the requirements and
start the device.
www.ams.com
Revision 0.7
35 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
8.8.5 Standby Mode - Power Consumption
In Standby Mode 1 there is a timer based accurate measurement every Ta seconds. The device itself stays in idle-mode as long as it does not
get a different command from the SPI interface. Internal oscillator frequency is typically foscint=262 kHz to reduce power consumption as long as
the timer runs. After every time out of Ta seconds, it performs accurate measurement of current, voltage/ temperature. Data ready is signaled to
microcontroller through an interrupt signal on INT and goes into STOP state.
In the SBM the following equations hold:
T
sbm1
= Ta= 10s (default value is 10secs); the power consumption is valid for this setting. This is the period of the repetition rate in SBM 1
and SBM2.
Tsett ≈ 2ms (depending on external capacitors). This is the time required by the analog part to settle when the new measuring period is
started. Any measurements performed during Tsett produce invalid results.
T1 = 3ms (by default setting, every third measurement is sent to microcontroller in the SBM mode 1) is the time needed to perform the first
measurement.
Tmeas =Tsett +T1 is the total active time needed to get a valid result.
DRSBM = Tmeas/Tsbm ≈ 5ms/10s. This is the ratio of repetition time versus the active time (Device in NOM mode).
Power consumption = (DRSBM*NOM mode power consumption) + ((10s-5ms)/10s)*Stop mode power consumption)
8.9 Bottom Die Block Specifications
This section provides specification of design related key parameters.
8.9.1 Current Measurement Ranges (across 100µΩ (±5%) shunt resistor)
Table 30. Current Measurement Ranges
PGA
Gain
Nominal
1
PSR2
[dB]
Imax
[A]
Vsh
[mV]
Data Rate
(fOUT
VINADC
[mV]
Symbol
Parameter
)
I70
I200
I400
I1500
Input current range of 70A in NOM
Input current range of 200A in NOM
Input current range of 400A in NOM
±77
±235
±400
±8.1
±24.7
±42
100
40
25
5
@ 1 kHz
@ 1 kHz
@ 1 kHz
@ 1 kHz
890
1088
1137
1204
60
60
60
60
Input current range of 1500A in NOM +2076/-1523 +218/-160
1. V
= V * Gain, gain deviations to be considered according to Table 32 and Table 33.
sh
INADC
2. AVDD, DVDD of 3.3V with ±5% variation.
Note: The Data Rate at the output can be calculated according to the formula:
fsout=2*fchop /R2 (R2 is down sampling ratio taking values 1, 2, 4 up to 32768 as powers of 2)
Table 31. Valid Combinations of the Chopper Clock, Oversampling Clock and Decimation Ratios
Over Sampling Frequency
1.024MHz
Chopper Frequency
Decimation Ratio
2kHz
2kHz
2kHz
4kHz
64
64
2.048MHz
2.048MHz
128
64
2.048MHz
www.ams.com
Revision 0.7
36 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
Differential Input Amplifier for Current Channel.
Table 32. Differential Input Amplifier for Current Channel
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIN_AMP
Input voltage range
RSHH and RSHL
-160
+160
mV
RSHH and RSHL@ +160mV input
voltage at 125ºC with PGA
Input current 1, 11
I _AMP
IN
-50
2
50
nA
-160
+300
Absolute input voltage range 2
ICM
mV
Gain1 3, 4, 9
Gain2 3, 4, 9
Gain3 3, 4, 9
G = G1
G = G2
G = G3
I10
100
40
25
5
I200
I400
Gain4 3, 4, 9
G = G4
e
I1500
Gain deviation
i = 1, 2, 3, 4
0.9 * Gi
15
1.1 * Gi
±0.5
Pole frequency 4, 5
Gain drift with temperature 6
Offset drift with temperature 7, 10
Input referred offset 7, 10
f _AMP
P
kHz
%
-20ºC to +65ºC
Gain 5, 25, referenced to room
temperature
εT1
VOSDRIFT
350
µV
µV
V
os
After trim at -20deg
Chopping enabled
350
V
os_ch
0
LSB
nV/√Hz
dB
Noise density 4, 8
V
25
70
Ndin
THD
Total harmonic distortion
For 150 Hz input signal
Notes:
1. Leakage test accuracy is limited by tester resource accuracy and tester hardware.
2. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
3. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are pro-
grammed independently.
4. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaran-
teed by design.
5. Pole frequency of input amplifier changes with GAIN. The number is valid for the gain at G1, while the bandwidth will be higher for other
ranges. This parameter is not measured in production.
6. Based on device evaluation. Not tested.
7. These offsets are cancelled if chopping enabled (default).
8. Noise density calculated by taking system bandwidth as 150Hz.
9. Refer to Measurement Ranges shown in Table 30.
10. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
11. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of
protection diode.
www.ams.com
Revision 0.7
37 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
Differential Input Amplifier for Voltage Channel.
Table 33. Differential Input Amplifier for Voltage Channel
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Input voltage range 1, 10
V
IN_AMP
-160
+160
mV
VBAT_IN, ETR, ETS @ +160mV input
voltage at 125ºC with PGA
Input resistance 2, 10
I
12.5
kΩ
IN_RES
-160
+300
Absolute input voltage range 3
ICM
mV
Gain1 4, 5
Gain2 4, 5
Gain3 4, 5
G = G1
G = G2
G = G3
100
40
25
5
Gain4 4, 5
G = G4
e
Gain deviation
i = 1, 2, 3, 4
0.9 * Gi
15
1.1 * Gi
Pole frequency 5, 6
fP_AMP
kHz
Noise density 5, 7
VNDIN
THD
25
70
nV/√Hz
Total harmonic distortion
For 150Hz input signal
dB
-20ºC to +65ºC
Gain 5, 25, referenced to room
temperature
Gain drift with temperature 8
εT1
±0.5
350
%
VOS
After trim at -20ºC
Chopping enabled
µV
LSB
µV
Input referred offset 9
V
0
os_ch
Offset drift with temperature 9
VOSDRIFT
350
Notes:
1. Input for the voltage channel can be as high as 1220mV, in this high input case PGA will be bypassed.
2. Leakage test accuracy is limited by tester resource accuracy and tester hardware, especially at low temperatures due to condensing
moisture.
3. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
4. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are pro-
grammed independently.
5. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaran-
teed by design.
6. Pole frequency of input amplifier changes with changing the GAIN. The number is valid for the gain at G1, while the bandwidth will be
higher for other ranges. This parameter is not measured in production.
7. Noise density calculated by taking system bandwidth as 150Hz.
8. Based on device evaluation. Not tested.
9. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
10. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of
protection diode.
www.ams.com
Revision 0.7
38 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
Sigma Delta Analog to Digital Converter.
Table 34. Sigma Delta Analog to Digital Converter
Symbol
Parameter
Reference voltage 6
Conditions
Min
Typ
Max
Units
V
REF
1.225
V
Input range 1
V
At V
= 1.22V
REF
0
±1.22
128
V
INADC
Oversampling ratio/Decimation Ratio 2
R1
64
128
1024/
2048
Oversampling frequency 3
f
kHz
OVS
RES
BW
16
bits
Hz
dB
Number of bits
Bandwidth 4
1
500
Signal to noise ratio 5
S/N
90
Notes:
1. Production test at ±800mV. Maximum VIN can be 1.22V with VREF=1.225V.
2. Programmable. It is defined with respect to the first decimator in the ΣΔ ADC.
3. Programmable: Internal clock is 1024/2048 kHz; external clock max is 8192 kHz.
4. Dependent on fovs, R1 and R2. The bandwidth is calculated according to the formula:
BW=fovs/(2*R1*R2); the sampling frequency at the output of the A/D converter is 2*BW.
5. Defined at maximum input signal, BW=500 Hz (1Hz to 500 Hz), fovs=1024 kHz, R1=64, fchop=2 kHz and R2=2.
6. Reference voltage might be forced from external.
Bandgap Reference Voltage.
Table 35. Bandgap Reference Voltage
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Reference Voltage after trim 1, 2, 3
Reference Voltage Initial Accuracy 1, 2, 3
V
Trim at 65ºC
1.225
V
REFTRIM
V
At 65ºC (0 Hour data)
±3.5
±0.4
mV
%
REFACC
Temperature range
-20ºC to 65ºC
V
Reference Voltage Temperature drift
REFDRIFT
Temperature range
-40ºC to 125ºC
+0.4/
-0.6
%
PSRRREF
SUTAVDD
PSR @ dc
80
5
dB
ms
Start Up Time with supply ramp 4
Start Up Time from power down 4
Output resistance of band gap
SUTPD
RNDVREF
VNDVREF
CLVREF
1
ms
Ω
500
100
1000
300
Bandgap reference thermal noise density 4
nV/√Hz
nF
Output Capacitor (Ceramic)
ESRVREF
0.02
1
Ω
Notes:
1. Accuracy at 65ºC. No DC current is allowed from this pin.
2. Specification does not include solder shift and life time drift.
3. Please refer Figure 26 for typical life time drift based on system level measurements.
4. This is a design parameter and not production tested.
www.ams.com
Revision 0.7
39 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
Figure 26. Typical System-level VREF Drift
AS8515
1.2265
1.2260
1.2255
1.2250
1.2245
1.2240
1.2235
1.2230
DUT1
DUT2
DUT3
DUT4
0.10%
-0.10%
0
50
100
150
200
250
300
System Level Operating Time in Normal mode at 115ºC ambient [h]
www.ams.com
Revision 0.7
40 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
Internal (Programmable) Current Source for External Temperature Measurement.
Table 36. External Temperature Measurement
Symbol
ICURON
Parameter
Conditions
Min
Typ
270
10
Max
Units
µA
5-bit current source enabled 1
5-bit current source disabled
5-bit programmable current source
Limited by leakage
0
320
ICUROFF
nA
ppm
/ ºK
Temperature coefficient of current source 2
Voltage on pin ETR 3
TK_CS
1000
VMAXETR
1000/G
1.22
mV
V
Max voltage on pin ETR when PGA is
bypassed 4
VMAXETRMOD
VMAXETS
Voltage on pin ETS for resistor sensor 3
1000/G
1.22
V
Max. Voltage on pin ETS when PGA is
bypassed 5
VMAXETSMOD
V
Notes:
1. Current value can be programmed through stop mode in steps of 8μA from 0 to 256μA with a process error of 30%.
2. Temperature coefficient is not important since external temperature measurement is a 2 step measurement. The value specified is
guaranteed by design and will not be tested in production.
3. Maximum voltage on pin ETR (reference) can be calculated by given formula, where G is the gain of PGA (G=100).
4. Maximum voltage on pin ETR, if PGA is bypassed.
5. Maximum voltage on pin ETS, if PGA is bypassed.
CMREF Circuit (VCM).
Table 37. CMREF Circuit
Symbol
VVCM
CL
Parameter
Output voltage
Load capacitance
Min
Typ
1.7
Max
Units
V
1.6
1.8
100
nF
Internal AVDD Power-on Reset.
Table 38. Internal AVDD Power-on Reset
Symbol
Parameter
Min
Typ
Max
Units
Power On Reset Threshold
VPORHIA
2.2
2.4
2.6
V
POR time - The duration from Power ON till
the time, internal Power On Reset signal
tPORA
1
µs
1
goes HIGH
2
IPORA
1.5
µA
Current consumption in POR block
1. POR pulse is always longer than tPORA whatever the slope of the supply.
2. IPORA can not be switched off.
www.ams.com
Revision 0.7
41 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
Internal DVDD Power-on Reset.
Table 39. Internal DVDD Power-on Reset
Symbol
Parameter
Min
Typ
Max
Units
Power On Reset Threshold
VPORHID
VHYST
2.2
2.4
2.7
V
1
0.2
1
0.25
0.4
V
Hysteresis
POR time - The duration from Power ON till the
time, internal Power On Reset signal goes
tPORD
µs
µA
2
HIGH
3
IPORD
1.5
Current
1. VPORLO = VPORHI - VHYST where VPORLO is the lower threshold of POR.
2. VPORLO = VPORHI - VHYST where VPORLO is the lower threshold of POR.
3. IPORD can not be switched off.
Low Speed Oscillator.
Table 40. Low Speed Oscillator
Symbol
fLS
Parameter
Frequency
Min
Typ
Max
Units
kHz
%
262.144
fLS_ACC
ILS
Accuracy
± 7
5
Supply current
µA
High Speed Oscillator.
Table 41. High Speed Oscillator
Symbol
Parameter
Min
Typ
Max
Units
fHS
Frequency
4.096
MHz
Accuracy 1
fHSACC
IHS
±4
%
Supply current
300
µA
Notes:
1. Accuracy after trimming.
External Clock.
Table 42. External Clock
Symbol
Parameter
Clock frequency
Conditions
Min
Typ
Max
Units
2048/
4096/
8192
fCLKEXT
kHz
to be programmed in Register 08
CLK_REG through the serial bus SPI.
DIVCLKEXT
DCCLKEXT
Clock division factor
2/4/8
Duty Cycle of external clock
40
60
%
www.ams.com
Revision 0.7
42 - 65
AS8515
Datasheet - AS8515 Bottom Die Overview
Internal Temperature Sensor.
Table 43. Internal Temperature Sensor
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ºC
TINTRNG
Temperature sensor range
Temperature measurement accuracy
-40
125
Δ
TIN
3
ºC
Guaranteed by design; at PGA gain 5
which is the recommended Gain for
internal temperature measurement.
TINTSLP
Temperature sensor slope
27
Digits/C
Digits
TINT65G5
Temperature sensor output at gain 5
40660
41807
43012
8.9.2 System Specifications
Table 44. System Specifications
Symbol
Parameter
Min
Typ
Max
Units
Channel to channel isolation 1
IS
-90
dB
dB
Difference in channel to channel attenuation
@600Hz 1, 2
At
3
5
Difference in phase shift between the two
channels @600Hz 1, 2
Ph
Deg
System Measurement Error Budget for Voltage and Current Channel.
Temperature Range: -20ºC to +65ºC; Output data rate is 1kHz, VCC = 3.3V, chopping enabled.
Table 45. System Measurement Error Budget for Gains 5 and 25
Symbol
Parameter
Conditions
Min
Typ
Max
Units
System measurement error 3, 4
Err
±0.6
1
%
%
From device evaluation
±0.5
Measurement error due to PGA gain drift
Measurement error due to VREF drift
±0.4
%
%
Measurement error due to non-linearity of PG Tested by distortion measurements
±0.025
Notes:
1. These specifications are defined by taking one channel as reference and measured on the other channel.
2. Guaranteed by design.
3. System measurement error due to noise, individual block parameter drifts and non linearity. Based on evaluation, not tested.
4. System error due to offset is neglected because of chopper architecture.
www.ams.com
Revision 0.7
43 - 65
AS8515
Datasheet - 4-Wire SPI Interface
9 4-Wire SPI Interface
The SPI interface can also be used as interface between the AS8515 and an external micro-controller to configure the device and access the
status information. Micro-controller begins communication with the SPI configured as a slave. The SPI protocol is very simple and the length of
each frame is an integer multiple of byte except when a transmission is started. Basically each frame has 1 command bits, 5 address/
configuration bits, 1 or more data bytes. SPI clock polarity settings depend on the value of the SCLK on the CS falling edge. This setting is done
on each start of the SPI transaction. During the transaction SPI clock polarity will be fixed to the settings done. On the CS falling edge the values
on SCLK signal decide setting of the active SPI clock edge for data transfer (see Table 46).
Table 46. CS and SCLK
CS1
SCLK
Description
Serial data transferred on rising edge of SPI clock.
Sampled at falling edge of SPI clock.
FALL
LOW
Serial data transferred on falling edge of SPI clock.
Sampled at rising edge of SPI clock.
FALL
ANY
HIGH
ANY
Serial data transfer edge is unchanged.
1. Pin CST is used to program top device and pin CSB is used to program bottom device.
9.1 SPI Timing Parameters
Table 47. 4-Wire Serial Port Interface
Symbol
General
BR
Parameter
Conditions
Min
Typ
Max
Units
Bit rate
250
Kbps
µs
SPI
T
Clock high time
Clock low time
2
2
SCLKH
T
µs
SCLKL
Write Timing
t
Data in setup time
Data in hold time
CS hold time
20
10
20
ns
ns
ns
DIS
t
DIH
T
CSH
Read Timing
t
Data out delay
80
80
ns
ns
DOD
t
Data out to high impedance delay
Time for the SPI to release the SDO bus
DOHZ
Timing parameters when entering 4-Wire SPI mode (for determination of CLK polarity)
Clock setup time
(CLK polarity)
Setup time of SCLK with respect to
CS falling edge
t
20
20
ns
ns
CPS
Clock hold time
(CLK polarity)
Hold time of SCLK with respect to
CS falling edge
t
CPHD
www.ams.com
Revision 0.7
44 - 65
AS8515
Datasheet - 4-Wire SPI Interface
9.1.1 SPI Frame
A frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an integer number of
bytes. Command is coded on the 1 first bit, while address is given on LSB 5 bits (see Table 48).
Table 48. Command Bits
Command Bits
Register Address or Transmission Configuration
C0
Reserved
Reserved
<A4:A0>
A4
A3
A2
A1
A0
C0
0
Command
WRITE
Description
ADDRESS
ADDRESS
Writes data byte on the given starting address
Reads data byte from the given starting address
1
READ
If the command is read or write, one or more bytes follow. When the micro-controller sends more bytes (keeping CS LOW and SCLK toggling),
the SPI interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses.
9.1.2 Write Command
For Write command C0 = 0.
After the command code C0 and two reserved bits, the address of register to be written has to be provided from the MSB to the LSB. Then one
or more data bytes can be transferred, always from the MSB to the LSB. For each data byte following the first one, used address is the
incremented value of the previously written address. Each bit of the frame has to be driven by the SPI master on the SPI clock transfer edge and
the SPI slave on the next SPI clock edge samples it. These edges are selected as per clock polarity settings. In the following figures two
examples of write command (without and with address self-increment.
Figure 27. Protocol for Serial Data Write with Length = 1
CS
SCLK
0
RES0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
RES1
SDI
SDO
Data D7 – D0 is moved to
Address A4..A0 here
Transfer edge
Sampling edge
www.ams.com
Revision 0.7
45 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Figure 28. Protocol for Serial Data Write with Length = 4
CS
SCLK
D D
7 6
D
5
D D D
D
1
D
0
A
4
D D
7 6
D
5
D D D D D
A
3
A
2
A
1
A
0
D D
7 6
D
5
D D D
D
1
D D D
7 6
D
5
D D D
D
1
D
0
D D
7 6
D
5
D D D
4 3 2
D
1
D
0
RERE
S1 S0
0
SDI
4
3 2
4
3 2 1 0
4
3
2
0
4
3
2
SDO
Data D7-D0 is
Data D7-D0 is
Data D7-D0 is
Data D7-D0 is
Data D7-D0 is
moved to Address
A4-A0 +1 here
moved to Address
A4-A0 +2 here
moved to Address
A4-A0 +3 here
moved to Address
A4-A0 here
moved to Address
A4-A0 +4 here
9.1.3 Read Command
For Read command C0=1.
After the command code C0 and two reserved bits, the address of register to be read has to be provided from the MSB to the LSB. Then one or
more data bytes can be transferred from the SPI slave to the master, always from the MSB to the LSB. To transfer more bytes from consecutive
addresses, SPI master has to keep active the SPI CS signal and the SPI clock as long as it desires to read data from the slave. Each bit of the
command and address sections of the frame have to be driven by the SPI master on the SPI clock transfer edge and the SPI slave on the next
SPI clock edge samples it. Each bit of the data section of the frame has to be driven by the SPI slave on the SPI clock transfer edge and the SPI
master on the next SPI clock edge samples it. These edges are selected as per clock polarity settings. In the following figures, two examples of
read command (without and with address self-increment) have been shown.
Figure 29. Protocol for Serial Data Read with Length = 1
CS
SCLK
RES1
1
RES0
A4
A3
A2
A1
A0
SDI
SDO
D7
D6
D5
D4
D3
D2
D1
D0
Data D7 – D0 at Address A4..A0
is read here
Transfer edge
Sampling edge
Transfer edge
Sampling edge
www.ams.com
Revision 0.7
46 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Figure 30. Protocol for Serial Data Read with Length = 4
CS
SCLK
A A A
A
1
A
0
RE
S1
RE
S0
1
SDI
4
3 2
D
7
D
6
D D D D D D D D
D
5
D D D D D D D D D D D D D D D
D
5
D D D D
4 3
D
0
D D D D D D D
7 6 5 4 3 2 1
D
0
SDO
5
4
3
2
1
0
7
6
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
2
1
Data D7-D0 at
Data D7-D0 at
Data D7-D0 at
Data D7-D0 at
Data D7-D0 at
Address A4-A0
is read here
Address A4-A0 +1
is read here
Address A4-A0 +2
is read here
Address A4-A0 +3
is read here
Address A4-A0 +4
is read here
9.1.4 Timing
In the following figures timing waveforms and parameters are exposed.
Figure 31. Timing for Writing
CS
...
t
t
t
t
SCLKL
CPS
CPHD
SCLKH
t
CSH
SCLK
CLK
polarity
...
...
...
t
t
DIH
DIS
SDI
DATAI
DATAI
DATAI
SDO
www.ams.com
Revision 0.7
47 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Figure 32. Timing for Reading
CS
t
t
SCLKL
SCLKH
SCLK
SDI
DATAI
DATAI
t
t
DOHZ
DOD
SDO
DATAO (D7)
DATAO (D0)
9.2 Bottom Die Registers
This section describes the control registers used in AS8515 Bottom die. Registers can be broadly classified into the following categories.
Data access registers
Status Registers
Digital signal path control registers
Digital Control registers
Analog Control Registers
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Data Access Registers
DREG_I1
(ADC Data Register for Current)
00
0000_0000
0000_0000
0000_0000
0000_0000
R
R
R
R
D[7:0]
D[7:0]
D[7:0]
D[7:0]
Denotes the Current ADC MSB Byte (ADC_I[15:8])
Denotes the Current ADC LSB Byte (ADC_I[7:0])
Denotes the Voltage ADC MSB Byte (ADC_V[15:8])
Denotes the Voltage ADC LSB Byte (ADC_V[7:0])
DREG_I2
(ADC Data Register for Current)
01
02
03
DREG_V1
(ADC Data Register for Voltage)
DREG_V2
(ADC Data Register for Voltage)
www.ams.com
Revision 0.7
48 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Status Registers
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
NOM1/NOM2 Data Ready
NOM2 Threshold Crossover
SBM1 Data Ready
SBM2 Threshold Crossover
APOR status
04
STATUS_REG
0000_0000
R
Data from current channel updated
Data from voltage channel updated
Reserved
www.ams.com
Revision 0.7
49 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Digital Signal Path Control Registers for Current Channel
This bit selects decimation rate is used for current
channel. Default is 0 (Down Sampling Rate is 64)
D[7]
0
1
Down Sampling Rate is 64
Down Sampling Rate is 128
These two bits select division ratio of oversampling
frequency clock MOD_CLK to be used as chopper
clock, CHOP_CLK.
Default is “10” (divide by 512)
00
01
10
11
Chopper Clock Always High
Divide by 256
D[6:5]
Divide by 512
Divide by 1024
These four bits select the decimation ratio of second
CIC stage. Default is “0010” (equal to 4)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
4
8
05
DEC_REG_R1_I
0100_ 0101 R/W
16
32
64
D[4:1]
128
256
512
1024
2048
4096
8192
16384
32768
CIC1 Saturation Interrupt Mask Control.
Default is 1
D[0]
0
1
Unmask
Mask
www.ams.com
Revision 0.7
50 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
D[7]
D[6]
I-Channel Enable, Default 1=enable
V-Channel Enable, Default 1=enable
Interrupt polarity
D[5]
D[4]
0
1
Active high
Active low
. Interrupt Mask Control for Current Channel Data
Ready Interrupt on INT pin (Default is 0)
0
1
Unmasked
Masked
These two bits select the source of output 16-bit data in
Normal mode from Current channel. Default is 01
06
DEC_REG_R2_I
1100_0101
R/W
00
01
10
11
FIR / MA Output
CIC2 Output
D[3:2]
D[1:0]
Dechop/Demod Output
CIC1 Output
These two bits select the source of output 16-bit data in
SBM mode from Current channel. Default is 01
00
01
10
11
FIR / MA Output
CIC2 Output
Dechop/Demod Output
CIC1 Output
www.ams.com
Revision 0.7
51 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
This bit selects FIR / MA Filter in Current channel.
Default is 0 (FIR)
D[7]
0
1
FIR
MA Filter
These bits select the number of data samples for
averaging in MA filter in Current channel.
Default is 0000 (bypass)
0000
0001
0011
0111
1111
bypass
D[6:3]
1
3
7
07
FIR CTL_REG_I
0000_0100
R/W
15
These two bits select the Measurement Path
architecture in both Current and Voltage channels.
Default is 10 (Dechopper after CIC)
00
01
Demodulator after CIC1
Demodulator before CIC1
D[2:1]
D[0]
Dechopper after CIC1
(preferred and suggested)
10
11
Demodulator before CIC1 with settled
sample
Reserved. Default 0. Do not change
www.ams.com
Revision 0.7
52 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Digital Control Registers
Oversampling frequency clock selection. Default is 00
(high speed (HS) internal Clock)
00
01
10
Internal HS Clock with No Clock Output
Internal HS Clock with Clock Output
External Clock
D[7:6]
D[5:4]
These two bits select the division ratio for HS clock/
external clock. Default is 10 (division by 4)
00
01
10
11
No division
Divide by 2
Divide by 4
Divide by 8
CLK_REG
(Clock Control Register)
08
0010_0000
R/W
These two bits select the division ratio of HS clock, by
which it should be divided before providing it on CLK
pin. Default is 00 (No Division)
00
01
10
11
No Division
Divide by 2
Divide by 4
Divide by 8
D[3:2]
D[1]
This bit selects the division ratio of LS clock
LS _CLK undivided (Low Speed clock)
LS _CLK divide by 2
0
1
D[0]
D[7]
Reserved
Entire device can be soft reset by writing “0” into this
register bit. This bit will take a default 1 value on coming
out of Reset
RESET_REG
(Reset Control Register)
09
1100_0000
R/W
Measurement Path can be soft reset by writing “0” into
this register bit. This bit will take a default 1 value after
Measurement Path is reset.
D[6]
D[5:0]
Reserved
www.ams.com
Revision 0.7
53 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
These two bits select the operating mode of the Device.
Default is 00 (Normal Mode 1)
00
01
10
11
Normal Mode 1
Normal Mode 2
Standby Mode 1
Standby Mode 2
D[7:6]
These three bits select the number of cycles to be
ignored before comparison with the set threshold in
Standy Mode. Default is 000 (3 cycles of data)
000
001
010
011
100
101
110
111
3 cycles of data
4 cycles of data
5 cycles of data
6cycles of data
7 cycles of data
8 cycles of data
9 cycles of data
10 cycles of data
D[5:3]
MOD_CTL_REG
(Mode Control Registers)
0A
0000_0000
R/W
This bit controls the CHOP_CLK availability on
CHOP_CLK pin.
Default is 0
D[2]
D[1]
0
1
Disabled
Enabled
Enabling the MEN pin to indicate transition from
Standby to Normal Mode.
0
1
Disabled
Enabled
This bit is used to take the device from STOP state to
any of the Modes based on D[7:6] selection of this
register.
D[0]
D[7]
0
1
Retain in STOP state
Enables transition to Normal or Standby
Modes.
Unit of Ta in SBM1/SBM2. Default is 1
Unit is in milliseconds
Unit is in seconds
0
1
MOD_Ta_REG1
(Ta Control Register)
0B
1000_0000
D[6:0]
D[7:0]
MSB value of Ta
MOD_Ta_REG2
(Ta Control Register)
Unit of Ta in SBM1/SBM2
LSB value of Ta
0C
0D
0E
0000_0000
0000_0000
0000_0000
R/W
R/W
R/W
MOD_ITH_REG1
(Current Threshold Register)
D[7:0]
D[7:0]
MSB bits of 16 bits SBM2 threshold register
LSB bits of 16 bits SBM2 threshold register
MOD_ITH_REG2
(Current Threshold Register)
www.ams.com
Revision 0.7
54 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Table 49. Control Registers
Addr in
Register Name
POR Value
0000_0000
0000_0000
R/W
R/W
R/W
8-bit Control / Status Data
HEX
MOD_TMC_REG1
(TMC Control Registers)
MSB value of number of data samples to be dropped
from ADC before sending Interrupt in NOM2
0F
D[7:0]
D[7:0]
MOD_TMC_REG2
(TMC Control Register)
LSB value of number of data samples to be dropped
from ADC before sending Interrupt in NOM2
10
11
12
NOM_ITH_REG1
NOM_ITH_REG2
0000_0000
0000_0000
R/W
R/W
D[7:0]
D[7:0]
Eight MSB bits of NOM2 current threshold register
Eight LSB bits of NOM2 current threshold register
Analog Control Registers
Setting of Gain G of Current Channel PGA. Default is
01 (G = 25)
00
01
10
11
5
D[7:6]
25
40
100
PGA_CTL_REG
(PGA Control Registers)
13
0101_0000
R/W
Setting of Gain G in Voltage channel. Default is 01 (G =
25)
00
01
10
11
5
D[5:4]
D[3:0]
25
40
100
Reserved
0
1
0
1
Disable Chopper clock to Current channel
Enable Chopper clock to Current channel
Disable Chopper clock to Voltage channel
Enable Chopper clock to Voltage channel
Reserved
D[7]
D[6]
D[5]
D[4]
Reserved
PD_CTL_REG_1
(Power Down Control Register)
14
1100_1111
R/W
0
1
0
1
0
1
0
1
Disable Current channel PGA
D[3]
D[2]
D[1]
D[0]
Enable Current channel PGA
Disable Current channel ΣΔ Modulator
Enable Current channel ΣΔ Modulator
Disable Voltage channel PGA
Enable Voltage channel PGA
Disable Voltage channel ΣΔ Modulator
Enable Voltage channel ΣΔ Modulator
www.ams.com
Revision 0.7
55 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Disable CIC1 of both channels
0
1
0
1
0
1
0
1
D[7]
D[6]
D[5]
D[4]
Enable CIC1 of both channels
Disable CIC2 of both channels
Enable CIC2 of both channels
Disable Dechopper in both channels
Enable Dechopper in both channels
Disable FIR in both channels
Enable FIR in both channels
Do not bypass PGA in Current Channel
Default 0
0
1
0
D[3]
PD_CTL_REG_2
(Power Down Control Register)
Bypass PGA in Current Channel
15
1111_0011
R/W
Do not bypass PGA in Voltage Channel
Default 0
Bypass PGA in Voltage Channel
Note: For Automotive Battery
measurement, ensure that the PGA is
bypassed to connect battery voltage
(attenuated by factor of 21) directly to the
ADC input.
D[2]
1
0
1
0
1
0
1
0
1
0
1
Disable Current Channel Chopper
Enable Current Channel Chopper
Disable Voltage Channel Chopper
Enable Voltage Channel Chopper
Disable Common Mode Reference
Enable Common Mode Reference
Disable Internal Current Source
D[1]
D[0]
D[7]
D[6]
D[5]
Enable Internal Current Source
Disable Internal temperature sensor
Enable Internal temperature sensor
Reserved. (Default 1) Do not change
Reserved. (Default 1) Do not change
Data Output in binary numbering system
PD_CTL_REG_3
(Power Down Control Register)
16
1111_1000
D[4]
D[3]
0
1
D[2]
Data Output in 2’s complement numbering
system
D[1]
D[0]
Reserved. (Default 0) Do not change
Reserved
www.ams.com
Revision 0.7
56 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
These bits specify the selection of voltage/temperature
in Voltage Channel
Default is 00 (Voltage Channel)
00
01
10
11
Voltage Channel
External Temperature Channel ETR
External Temperature Channel ETS
Internal Temperature Channel
D[7:6]
D[5]
D[4]
Reserved. (Default 0) Do not change
Internal current source switch enable. Default is 0
Note: D4 bit is used for Enabling current source to
the channel selected by bits D[7,6] of this
register.
ACH_CTL_REG
(Analog Channel Selection
Register)
17
0000_0000
R/W
0
1
Disabled
Enabled
Enable/disable Internal current source to RSHH pin of
Current channel
D[3]
0
1
Disabled
Enabled
Enable/disable current source switch to RSHL pin of
Current channel
D[2]
0
1
Disabled
Enabled
D[1:0]
Reserved
These three bits specify the selection of magnitude of
current from the Internal current source. Default is
00000 (0µA).
00000
00001
00010
00100
01000
10000
11111
0µA
8.5µA
17µA
D[7:3]
ISC_CTL_REG
(Current Source Setting Register)
18
0000_0000
R/W
34.5µA
68µA
135µA
270µA
D[2:0]
D[7]
Reserved
1
Reserved (default = 1) Do not change
Reserved
19
44
OTP_EN_REG
0000_0000
0000_0000
R/W
R
D[6:0]
D[7]
Status indicating data saturation in Current channel
Status indicating data saturation in Voltage channel
Reserved
STATUS_REG_2
D[6]
D[5:0]
www.ams.com
Revision 0.7
57 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Digital Signal path control registers for Voltage Channel
Selection of Decimation ratio for Voltage/Temperature
channel.
Default is 0 (Down Sampling Rate is 64)
D[7]
0
1
Down Sampling Rate is 64
Down Sampling Rate is 128
Division of oversampling clock, which is used as
Chopper Clock. Default is 10 (divide by 512)
00
01
10
11
Chopper Clock Always High
Divide by 256
D[6:5]
Divide by 512
Divide by 1024
Decimation ratio of CIC2. Default is 0010 (4)
0000
1
2
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
8
45
DEC_REG_R1_V
0100_ 0101 R/W
16
32
64
D[4:1]
128
256
512
1024
2048
4096
8192
16384
32768
CIC1 Saturation Interrupt Mask Control.
Default is 1
D[0]
0
1
Unmasked
Masked
www.ams.com
Revision 0.7
58 - 65
AS8515
Datasheet - 4-Wire SPI Interface
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
D[7:5]
D[4]
Reserved
Interrupt Mask Control for Voltage channel data Ready
Interrupt on INT pin (Default is 0)
0
1
Unmasked
Masked
These two bits select the source of output 16-bit data in
Normal mode from Voltage channel. Default is 01
46
DEC_REG_R2_V
R/W
0000_0100
00
01
10
11
FIR / MA Output
CIC2 Output
D[3:2]
Dechop/Demod Output
CIC Output
D[1:0]
D[7]
Reserved
This bit selects FIR / MA Filter in Voltage channel.
Default is 0 (FIR)
0
1
FIR
MA Filter
These bits select the number of data samples for
averaging in MA filter in Voltage channel.
Default is 0000 (bypass)
47
FIR CTL_REG_V
0000_0000
R/W
0000
0001
0011
0111
1111
bypass
D[6:3]
D[2:0]
1
3
7
15
Reserved
Note: All the registers from address 0x19 to 0x2C are read-only.
www.ams.com
Revision 0.7
59 - 65
AS8515
Datasheet - Application Information
10 Application Information
Figure 33. Application Diagram
32
30
29
28
27
26
25
31
1
24
23
22
21
20
Optional
RSHH
2
VREF
SDI
100nF
3
VCM
MEN
4
100nF
AVDD
CHOP_CLK
DVDD
3.3V
AS8515
5
AVSS
3.3V
19
18
17
6
ETR
DVSS
SDO
7
ETS
8
VSENSE_IN
CSB
16
14
10
11
12
13
15
9
200nF
22µF
VBAT
SUP
Diode
µC
Load
+
-
100µohm
12V
Battery
Note: VSENSE_IN, VSENSE_GND, MEN, and CHOP_CLK should be left unconnected.
Note: Keep the differential input signal lines short, symmetric, and as close as possible. Use of PCB shielding layers is recommended, but
consider Eddy currents for fast changes in shunt current and related parasitic signal / ground shift generation.
www.ams.com
Revision 0.7
60 - 65
AS8515
Datasheet - Package Drawings and Markings
11 Package Drawings and Markings
The devices are available in a 32-pin MLF (5x5 mm) package.
Figure 34. Package Drawings and Dimensions
AS8515
YYWWVZZ
@
www.ams.com
Revision 0.7
61 - 65
AS8515
Datasheet - Package Drawings and Markings
Symbol
Min
0.80
0
Nom
0.90
Max
1.00
0.05
1.00
Symbol
D2
Min
Nom
3.50
3.50
0.15
0.10
0.10
0.05
0.08
0.10
32
Max
A
A1
A2
A3
L
3.40
3.60
0.02
E2
3.40
3.60
-
0.65
aaa
bbb
ccc
ddd
eee
fff
-
-
-
-
-
-
-
-
-
-
-
-
0.20 REF
0.40
0.30
0º
0.50
14º
θ
b
-
0.18
0.25
0.30
D
5.00 BSC
5.00 BSC
0.50 BSC
4.75 BSC
4.75 BSC
E
N
e
D1
E1
Notes:
1. Dimensions and tolerancing conform to ASME Y14.5M -1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Bilateral coplanarity zone applies to the exposed pad as well as the terminal.
4. Radius on terminal is optional.
5. N is the total number of terminals.
Marking: YYWWVZZ.
YY
WW
V
ZZ
Traceability Code
@
Last two digits of the
manufacturing year
Manufacturing Week
Plant Identifier
Sublot identifier
www.ams.com
Revision 0.7
62 - 65
AS8515
Datasheet - Revision History
Revision History
Revision
Date
Owner
Description
0.1
Dec 16, 2011
zmo/mbr
Initial draft
Updated table information on LIN Driver (page 24)
Pins 10, 11 updated in the file (Pin Assignments, Figure 33)
0.2
Jan 25, 2012
zmo
Updated power dissipation info in Absolute Maximum Ratings (page 7)
Updated Table 14, Figure 33.
0.3
0.4
Mar 07, 2012
Aug 14, 2012
Updated Operating Conditions, Electrical Characteristics, Ordering
Information, Figure 12. Table 30, Table 32, Table 33, Table 45.
0.5
0.6
Nov 22, 2012
Mar 22, 2013
Jul 26, 2013
Jul 31, 2013
zmo/mbr
Table 1 and Table 6 updated.
zmo
mbr
Updated Table 30, added Figure 26 and notes to Table 35, modified
Table 30, updated information in Figure 26.
0.7
Updated AS8515 Block Diagram Figure 1.
Note: Typos may not be explicitly mentioned under revision history.
www.ams.com
Revision 0.7
63 - 65
AS8515
Datasheet - Ordering Information
12 Ordering Information
The devices are available as the standard products shown in Table 50.
Table 50. Ordering Information
Ordering Code
AS8515-ZMFP
AS8515-ZMFM
Description
Delivery Form
Package
Tape & Reel (5000 pcs)
Tape & Reel (500 pcs)
Data acquisition system with power management
and LIN transceiver
32-pin MLF (5x5 mm)
Note: All products are RoHS compliant and ams green.
Buy our products or get free samples online at ICdirect: http://www.ams.com/ICdirect
Technical Support is available at http://www.ams.com/Technical-Support
For further information and requests, please contact us mailto: sales@ams.com
or find your local distributor at http://www.ams.com/distributor
www.ams.com
Revision 0.7
64 - 65
AS8515
Datasheet - Copyrights
Copyrights
Copyright © 1997-2013, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights
reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the
copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal
commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability
applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing
by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard
production flow, such as test flow or test location.
The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third
party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other
services.
Contact Information
Headquarters
ams AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.ams.com/contact
www.ams.com
Revision 0.7
65 - 65
相关型号：
AS8515-ZMFP
Data Acquisition System with Power Management and LIN Transceiver for 12V Battery Sensor Applications
AMSCO
AS8520
LIN Transceiver with Voltage Regulator, Attenuator, Relay Drivers, MCU Interface for Automotive Applications
AMSCO
AS8520-AQFT
LIN Transceiver with Voltage Regulator, Attenuator, Relay Drivers, MCU Interface for Automotive Applications
AMSCO
AS8525
LIN Transceiver with Voltage Regulators, Programmable Gain High Side Amplifier, and Voltage Attenuator
AMSCO
AS8525-AQFM
LIN Transceiver with Voltage Regulators, Programmable Gain High Side Amplifier, and Voltage Attenuator
AMSCO
AS8525-AQFP
LIN Transceiver with Voltage Regulators, Programmable Gain High Side Amplifier, and Voltage Attenuator
AMSCO
AS8530
LIN Transceiver with Integrated Voltage Regulator and MCU Interface for Automotive Applications
AMSCO
AS8530-ASOM
LIN Transceiver with Integrated Voltage Regulator and MCU Interface for Automotive Applications
AMSCO
AS8530-ASOP
LIN Transceiver with Integrated Voltage Regulator and MCU Interface for Automotive Applications
AMSCO
AS8530-ASOT
LIN Transceiver with Integrated Voltage Regulator and MCU Interface for Automotive Applications
AMSCO
AS8530-ASOT-001
LIN Transceiver with Integrated Voltage Regulator and MCU Interface for Automotive Applications
AMSCO
AS8530-ASOT-002
LIN Transceiver with Integrated Voltage Regulator and MCU Interface for Automotive Applications
AMSCO
©2020 ICPDF网 联系我们和版权申明