TCS3415FN [AMSCO]
DIGITAL COLOR SENSORS;
| 型号： | TCS3415FN |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | DIGITAL COLOR SENSORS 光电二极管 |
| 文件： | 总41页 (文件大小：1816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAOS Inc.
is now
ams AG
The technical content of this TAOS datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
e-Mail: ams_sales@ams.com
Please visit our website at www.ams.com
TCS3404, TCS3414
DIGITAL COLOR SENSORS
r
r
TAOS137A − APRIL 2011
PACKAGE CS
6-LEAD CHIPSCALE
(TOP VIEW)
Features
D Programmable Interrupt Function with
User-Defined Upper and Lower Threshold
Settings
SCL SYNC GND
A1
A2
A3
D Internal Filter Eliminates Signal Fluctuation
Due to AC Lighting Flicker — No External
Capacitor Required
B1
SDA
B2
VDD
B3
INT
D In-Package Trim Provides an Easy and
Accurate Means to Achieve
System-to-System Repeatability
2
D 16-Bit Digital Output with I C at 400 kHz
PACKAGE FN
DUAL FLAT NO-LEAD
(TOP VIEW)
D Programmable Analog Gain and Integration
Time Supporting 1,000,000-to-1 Dynamic
Range
6 GND
5 VDD
4 INT
SCL 1
SYNC 2
SDA 3
D SYNC Input Synchronizes Integration Cycle
to Modulated Light Sources (e.g. PWM)
D Operating Temperature Range
−40ꢀC to 85ꢀC (CS Package)
−30ꢀC to 70ꢀC (FN Package)
ckage Drawings are Not to Scale
D Operating voltage of 2.7 V to 3.6 V
D Available in Both an FN and a CS Package.
The CS Package is the Industry’s Smalles
Digital RGB Color Sensor
Applications
End Products and Market Segments
D Provides Method to Derive hromaticity
D HDTVs
Coordinates to Manage Display
Backlighting (i.e. RGB LED, CCFL, et.)
D Tablets, Laptops, Monitors
D Medical Instrumentation
D Consumer Toys
D Provides Means to Derive Colo
Temperature to White-Color Balance
Displays Under Various Lightin
Conditions
D Industrial/Commercial Lighting
D Industrial Process Control
Description
The TCS3404 and TCS3414 digital color light sensors are designed to accurately derive the color chromaticity
and illuminance (intensity) of ambient light and provide a digital output with 16-bits of resolution. The devices
include an 8 × 2 rray of filtered photodiodes, analog-to-digital converters, and control functions on a single
monolithic CMOS integrated circuit. Of the 16 photodiodes, 4 have red filters, 4 have green filters, 4 have blue
filters, nd 4 have no filter (clear). With the advanced patent pending in-package trim capability,
device-to-device and system-to-system tolerance can be minimized allowing very precise repeatability to be
atted.
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
Texas Advarnced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972) 673-0759
www.taosinc.com
1
TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
A synchronization input (SYNC) provides precise external control of sensor integration allowing the internal
conversion cycles to be synchronized to a pulsed light source. Furthermore, the synchronization feature
supports the following advanced modes of operation to maximize flexibility across a broad range of hardware
systems: (1) sync for one internal-time cycle, and (2) accumulate for specified number of pulses. The device
also supports free-running and serial-bus-controlled integration modes if precise coupling between the sensor
and light source is not required.
Four parallel analog-to-digital converters (ADC) transform the photodiode currents to an SMBus (TCS3404) or
2
I C (TCS3414) digital output that, in turn, can be input to a microprocessor. The RGB values can be read in a
single read cycle to minimize the number of read command protocols defined in the communication interface.
The slave address for this device is 39h (0111001b). A single SMB-Alert style interrupt (TCS3404) as well as
a single traditional level-style interrupt (TCS3414) can be dynamically configured for any one of the fou
channels including a corresponding high/low threshold setting. The interrupt will remain asserted until he
firmware clears the interrupt.
The TCS3404/14 devices can help (1) automatically adjust the display brightness of a backlight to extend
battery, increase lamp life, and provide optimum viewing in diverse lighting conditions, (2) white-color balance
display panel and/or captured images in diverse lighting conditions, and (3) manage RGB LED backlighting to
maintain color consistency over a long period of time.
These devices are also ideal in controlling keyboard illumination in low ambient light onditons. Chromaticity
coordinates (x,y) can be used to derive color temperature r the prpose of white-color balancing of displays
and/or captured images. Illuminance, in lux, can be used to pproximate the human ee response of ambient
light and to manage exposure control in digital camerThe TCS3404/14 devices are ideal in notebook/tablet
PCs, LCD monitors, flat-panel televisions, cell phonend digital camer. Additional applications include
street light control, security lighting, sunlight harvestingand automotive instrumentation clusters.
Functional Block Diagram
IR-Blocking Filter
(CS Package Only)
Integating
Converter
Red Channel
Integrating
A/D Converter
Green Chann
Integrating
A/D Converter
lue Cannel
Integrating
A/D Converter
Clear Channel
Command
Register
4-Parallel ADC
Registers
V
DD
Interrupt
INT
SCL
SDA
Synchronization
Two-Wire Serial Interface
SYNC
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
r
r
2
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TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
CS PKG FN PKG
NAME
GND
NO.
A3
B3
A1
B1
A2
B2
NO.
6
Power supply ground. All voltages are referenced to GND.
Level interrupt — open drain.
INT
4
O
I
2
SCL
SDA
SYNC
1
Serial clock input terminal — clock signal for I C serial data.
2
3
I/O
I
Serial data I/O terminal — serial data I/O for I C.
2
Synchronous input.
Supply voltage.
V
5
DD
Available Options
2
DEVICE
TCS3404
TCS3404
TCS3413
TCS3413
INTERFACE
SMBus
I C ADDRESS
PACKAGE − LEADS
Chipscale−6
PACKAGE DESIGNATOR
ORDERING NUMBER
TCS3404CS
TCS3404FN
TCS3413CS
TCS3413FN
TCS3414CS
TCS3414FN
TCS3415CS
TCS3415FN
TCS3416CS
TCS3416FN
−
CS
FN
CS
FN
CS
FN
CS
FN
CS
FN
SMBus
−
Dual Flat No-Lead−6
Chipscale6
2
I C
0x29
0x29
0x39
0x39
0x49
0x49
0x59
0x59
2
I C
Dual Flat Noead−6
Chipscale−
†
2
TCS3414
TCS3414
I C
†
2
I C
Dual Fead−6
Chicale−6
2
TCS3415
TCS3415
TCS3416
TCS3416
I C
2
I C
Dual Flat No-Lead−6
Chipscale−6
2
I C
2
I C
Dual Flat No-Lead−
†
Recommended device for single-device systems..
Absolute Maximum Ratings ovoperating free-air temperature range (unless otherwise noted)†
Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 V
DD
Digital output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.8 V
O
Digital output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1 mA to 20 mA
O
Storage temperature range, T
ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
stg
†
Stresses beyond those listed under “absolute mmum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at tese or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximu-ratd conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with repect to GND.
Recommended Operating Conditions
MIN NOM
MAX
3.6
UNIT
V
Supply voltage, V
2.7
3
Opeating e-ar temperature, T (CS PAckage)
−40
85
°C
A
Opeating free-air temperature, T (FN PAckage)
−30
−0.5
2.1
70
0.8
3.6
°C
V
A
SCL, SA input low voltage, V
IL
SCL, SDA input high voltage, V
V
IH
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
r
r
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3
TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
Electrical Characteristics, TA = 25ꢀ C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Power on (ADC inactive)
MIN
TYP
7.7
MAX
10
UNIT
mA
mA
μA
Power on (ADC active)
Power down
8.7
11
I
Supply current @ V = 3.6 V
DD
DD
700
1000
0.4
5
V
I
INT, SDA output low voltage
3 mA sink current
0
V
OL
Input leakage current (SDA, SCL, SYNC)
V
= V V = GND
DD, IL
−5
μA
LEAK
IH
AC Electrical Characteristics, VDD = 3.3 V, TA = 25ꢀ C (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
400
UN
Hz
kHz
μs
2
Clock frequency 400 kHz (I C)
f
t
t
(SCL)
Clock frequency 100 kHz (SMBus)
Bus free time between start and stop condition
10
1.3
100
(BUF)
Hold time after (repeated) start condition. After
this period, the first clock is generated.
0
μs
(HDSTA)
t
t
t
t
t
t
t
t
t
Repeated start condition setup time
Stop condition setup time
Data hold time
0.6
0.6
0
μs
μs
μs
ns
μs
μs
ms
ns
ns
pF
μs
μs
ns
ns
(SUSTA)
(SUSTO)
(HDDAT)
(SUDAT)
(LOW)
(HIGH)
(TIMEOUT)
F
0.9
Data setup time
100
1.3
0.6
25
SCL clock low period
SCL clock high period
Detect clock/data low timeout (SMBus nly)
Clock/data fall time
35
300
300
10
Clock/data rise time
R
C
Input pin capacitance
i
t
SYNC low period (see Figure 1)
SYNC high period (see Figure 1)
SYNC fall time (see Figure 1)
SYNC rise time (see Figure 1)
50
50
50
50
LOW (SYNC)
HIGH (SYNC)
F (SYNC)
t
t
t
R (SYNC)
†
Specified by design and characterization; not productested.
t
t
W SYNC)
R (SYNC)
F (SYNC)
t
HIGH (SYNC)
Figure 1. Timing Diagram for Sync
Copyright E 2011, TAOS Inc.
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TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
Optical Characteristics, VDD = 3 V, TA = 25ꢀ C, GAIN = 64ꢁ, Tint = 12ms (unless otherwise noted) (see
Notes 1 and 2)
Red Channel
Green Channel
Blue Channel
Clear Channel
MIN TYP MAX
TEST
CONDITIONS
PARAMETER
UNIT
MIN TYP MAX
MIN TYP MAX
MIN TYP MAX
λ = 470 nm,
p
0%
0%
15% 15%
15% 60%
110% 0%
50% 65%
90% 59.0
65.6
76.9
90.1
62.5
78.4
72.5
82.7
99.5
69.1
4.3
Irradiance
responsivity
(CS
package)
See Note 3
(counts/
λ = 524 nm,
p
90%
15%
0%
0%
35% 71.2
15% 80.6
90% 56.3
35% 72.5
R
e
μW/
See Note 4
2
cm )
λ = 640 nm,
p
80%
0%
See Note 5
λ = 470 nm,
p
15% 10%
15% 60%
50% 65%
Irradiance
responsivity
(FN
package)
See Note 3
unts/
λ = 524 nm,
p
0%
90%
15%
0%
0%
R
e
μW/
See Note 4
2
cm )
λ = 640 nm,
p
80%
110%
0%
15% 94.2 105.3 1163
See Note 5
NOTES: 1. The percentage shown represents the ratio of the respective red, green, or blue channel value to he clar channel value.
2. Optical measurements are made using small-angle incident radiation from a light-emitting diode (LE) opcal source.
3. The 470 nm input irradiance is supplied by an InGaN light-emitting diode with the following charcterisics:
peak wavelength λ = 470 nm, spectral halfwidth Δλ½ = 35 m, and luminous efficacy = 75 l/W.
p
4. The 524 nm input irradiance is supplied by an InGaN light-mitting de with the following chaateristics:
peak wavelength λ = 524 nm, spectral halfwidth Δλ½ = 47 m, and uminous efficacy = 52m/W.
p
5. The 640 nm input irradiance is supplied by a AlInGalight-emitting diode with the following characteristics:
peak wavelength λ = 640 nm, spectral halfwidth Δλm, and luminous ficacy = 155 lm/W.
p
6. Illuminance responsivity R is calculated from the irradce responsivity R by ung the LED luminous efficacy values stated in
v
e
2
notes 3, 4, and 5 and using 1 lx = 1 lm/m .
Operating Characteristics, VDD = 3 V, TA = 25ꢀ C, (unss otherwise noted) (see Notes 2, 3, and 4)
PARAMETER
TST CONDITIONS
MIN
3.8
TYP
4
MAX
4.2
UNIT
4×
16×
64×
15.2
60.8
0
16
64
3
16.8
67.2
Gain scaling, relative to 1× gain set
Dark ADC count value
= 0, 64× gain setting, T = 400 ms
15 counts
e
int
Maximum digital count value
Oscillator frequency
Prescale = 1, T = 400 ms (Note 1)
65535 counts
int
f
4.2
−5
4.4
4.6
5
MHz
%
osc
Internal integration time tolerance
Temperature coefficient of responsivity NC mode) λ ꢀ 700 nm, −40°C ꢀ T ꢀ 85°C
200
ppm/°C
A
NOTES: 1. At shorter integration times andr higher Prescale settings, the device will reach saturation of the analog section before the digital
count reaches the maxium 16-bit value. The worst-case (lowest) analog saturation value can be obtained using the formula: Analog
saturation = (foscmi) ×Tint) ÷Prescale, where Fosc(min) is the minimum oscillator frequency in Hz, and tint is the actual integration
time (internal, mnually-timed, or sync-generated) in seconds.
2. Gain is conolled y the gain register (07h) described in the Register section.
3. Measurents aken when the Photodiode field value in the Photodiode Register (06h) is 00b and when the Prescaler field value
in the Gain Register (07h) is 000b.
4. Thfull scale ADC count value is slew-rate limited for short integration times and is limited by the 16-bit counter for long integration
tim. Te nominal transition between the two regions is t = 65535/5000 = 13.1 ms.
int
Copyright E 2011, TAOS Inc.
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r
r
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5
TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
PARAMETER MEASUREMENT INFORMATION
t
t
(R)
t
(F)
(LOW)
V
IH
SCL
SDA
V
IL
t
t
t
(HDSTA)
(HIGH)
(SUSTA)
t
t
t
(SUSTO)
t
(BUF)
(HDDAT)
(SUDAT)
V
V
IH
IL
P
S
S
P
Stop
Condition
Start
Condition
Start
Stop
t
(LOWSEXT)
SCL
SCL
ACK
ACK
t
t
t
(LOWMEXT)
(LOWMEXT)
(LOWMEXT)
SCL
SDA
Figure 2. TiminDiagrams
1
9
1
9
SCL
SDA
A6 A5
A4
A3
A2 A0 R/W
DD6
D5 D4 D3 D2
D1 D0
Start by
Master
ACK
TCS3404
ACK by Stop by
TCS3404/14 Master
Frame 1 Slave Address Byte
Frame 2 Command Byte
Figure 3. Example Tming Diagram for Send Byte Format
1
9
1
9
SCL
SDA
A6 A
A4
A3
A2 A1 A0 R/W
D7 D6
D5 D4 D3 D2
D1 D0
Start by
Master
ACK by
TCS3404/14
NACK by Stop by
Master Master
Frame 1 Slave Address Byte
Frame 2 Data Byte From TCS3404/14
Figure 4. Example Timing Diagram for Receive Byte Format
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TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
TYPICAL CHARACTERISTICS
SPECTRAL RESPONSIVITY
CS PACKAGE
SPECTRAL RESPONSIVITY
FN PACKAGE
120
100
80
60
40
20
0
Clear
Red
Clear
100
80
Red
Green
Blue
Green
60
Blue
40
20
0
300 400 500 600 700 800 900 1000 1100
300 400 500 600 00 800 900 1000 1100
λ − Wavelength − nm
λ − Wavelength − nm
Figure 5
Figure 6
Note: Spectral responsivity is normalized at 655 nm.
Note: Spctral responsivity is normalized at 850 nm.
IDD ON
vs.
IDD OFF
vs.
FREE-AIR TEMPERATURE
(Power On — ADC Inactive)
FREE-AIR TEMPERATRE
(Power Down
9.5
950
3.6 V
3.6 V
900
9.0
8.5
8.0
850
800
750
3.3 V
3.3 V
3.0 V
3.0 V
700
650
600
2.7 V
2.7 V
7.5
7.0
0
25
50
75
100
0
25
50
75
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 8
Figure 7
Note: When the device is powered on and the ADC is active,
is approximately 1 mA higher.
I
DD
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TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
TYPICAL CHARACTERISTICS
NORMALIZED RESPONSIVITY
NORMALIZED INTEGRATION TIME
vs.
vs.
ANGULAR DISPLACEMENT — FN PACKAGE
FREE-AIR TEMPERATURE
106
105
104
103
102
1.0
0.8
0.6
0.4
Internally Timed
Integration
101
100
99
0.2
0
Externally Timed Integration
98
97
90
0
−60
−0
0
30
60
0
25
50
75
100
ꢁ
−
A
n
g
l
a
r
D
i
s
p
l
a
c
e
m
e
n
t
−
°
T
A
− Free-Air Temperature − °C
Figure 9
Figure 10
NORMALIZED RESPONSIVIY
vs.
NORMALIZED RESPONSIVITY
vs.
ANGULAR DISPLACEMENT—CACKAGE
ANGULAR DISPLACEMENT—CS PACKAGE
1
1
0.8
0.6
0.8
0.6
0.4
0.2
0
0.4
0.2
0
ꢂꢁ
−30
ꢃꢁ
30
ꢂꢁ
−30
ꢃꢁ
30
90
90
90
−60
0
60
−90
−60
0
60
ꢁ
−
A
n
g
u
l
a
r
D
i
s
p
l
a
c
e
m
e
n
t
−
°
ꢁ
−
A
n
g
u
l
a
r
D
i
s
p
l
a
c
e
m
e
n
t
−
°
Figure 11
Figure 12
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TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
PRINCIPLES OF OPERATION
Analog-to-Digital Converter
The TCS3404/14 contains four integrating analog-to-digital converters (ADC) that integrate the currents from
the four photodiodes (channel 1 through channel 4). Integration of all four channels occurs simultaneously, and
upon completion of the conversion cycle the conversion results are transferred to the channel data registers,
respectively. The transfers are double-buffered to ensure that invalid data is not read during the transfer. After
the transfer, the device automatically begins the next integration cycle.
There are two ways to control the integration cycles: internally timed and externally timed. Internall-timed
integration cycles can either be continuous back-to-back conversions or can be externally triggered as a sngle
event using the SYNC pin. Externally-timed integrations can be controlled by setting and clearing a eter bit
(i.e. ADC_EN in Control Register) using the serial interface, or by 1 or more pulses input to the SC pin.
Integration options are configured through the Timing Register (see the Timing Register sectin for more
information).
Digital Interface
Interface and control of the TCS3404/14 is accomplished through a two-wire serinterace to a set of registers
that provide access to device control functions and ouut dat. The serial interface s compatible with System
Management Bus (SMBus) versions 1.1 and 2.0, and I C buFast-Mode.
The TCS3404/14 device supports a single slave ss outlined in able 1. Additional devices shown in the
2
Available Options table on page 3 support additionI C slave addressefor systems requiring more than one
device.
Table . Slave Addr
SLAVE ADRES
B ALERT ADDRESS
01001
0001100
2
NOTE: The slave and SMB Alert addresss 7 bits. Please note the SBus and I C protocols on the following pages. A read/write bit should
be appended to the slave address e master device mmunicate properly with the device.
Interrupt
Although the ADC channel data regisers can be read at any time to obtain the most recent conversion value,
in some applications, periodic pollg of the device may not be desirable. For these types of applications, the
device supports a variety of interroptions allowing the user to configure the device to signal when a change
in light intensity has occurred. High and low threshold registers allow a range of light levels to be defined, outside
of which the device generats an interrupt. A persistence setting allows the user to specify a time duration that
the measured value musremain outside of the defined range before generating an interrupt. The interrupt
function can be asigned to any one of the four ADC color channels. See Interrupt Control Register for more
information on configuring the interrupt functions.
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TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
SMBus and I2C Protocols
Each Send and Write protocol is, essentially, a series of bytes. A byte sent to the TCS3404/14 with the most
significant bit (MSB) equal to 1 will be interpreted as a COMMAND byte. The lower four bits of the COMMAND
byte form the register select address (see Table 1), which is used to select the destination for the subsequent
byte(s) received. The TCS3404/14 responds to any Receive Byte requests with the contents of the register
specified by the stored register select address.
The TCS3404/14 implements the following protocols of the SMB 2.0 specification:
D
D
D
D
D
D
D
Send Byte Protocol
Receive Byte Protocol
Write Byte Protocol
Write Word Protocol
Read Word Protocol
Block Write Protocol
Block Read Protocol
2
The TCS3404/14 implements the following protocols of the C spcification:
2
D
D
I C Write Protocol
2
I C Read (Combined Format) Protocol
When an SMBus Block Write or Block Read is initiated (see descripon of COMMAND Register), the byte
following the COMMAND byte is ignored but is a rquirement of tSMBus specification. This field contains
the byte count (i.e. the number of bytes to be transferred). The TC344 (SMBus) device ignores this field and
extracts this information by counting he actual number of bytes transferred before the Stop condition is
detected.
2
2
When an I C Write or I C Read (Coined Format) is initated, the byte count is also ignored but follows the
2
SMBus protocol specification. Data ytes continue ransferred from the TCS3414 (I C) device to Master
until a NACK is sent by the Master.
The data formats supported by the TCS3404 and TCS3414 devices are:
2
D
D
Master transmitter transmits to slave eceiver (SMBus and I C):
−
The transfer direction in this cais not changed.
Master reads slave immeditely after the first byte (SMBus only):
−
At the moment of thfirst acknowledgment (provided by the slave receiver) the master transmitter
becomes a master receiver and the slave receiver becomes a slave transmitter.
2
D
Combined format (SMBus and I C):
−
During a cange of direction within a transfer, the master repeats both a START condition and the slave
address but with the R/W bit reversed. In this case, the master receiver terminates the transfer by
geneatina NACK on the last byte of the transfer and a STOP condition.
Fa omplete description of SMBus protocols, please review the SMBus Specification at
2
2
http:www.smbus.org/specs. For a complete description of the I C protocol, please review the NXP I C design
specification at http://www.i2c−bus.org/references/.
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1
7
1
1
A
X
8
1
1
S
Slave Address
Wr
Data Byte
A
X
P
A
Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK)
P
Stop Condition
Rd
S
Read (bit value of 1)
Start Condition
Sr
Wr
X
Repeated Start Condition
Write (bit value of 0)
Shown under a field indicates that that field is required to have a value of X
... Continuation of protocol
Master-to-Slave
Slave-to-Master
2
Figure 13. SMBus and I C Packet Procol Element Key
1
7
1
8
1
1
S
Slave Addres
Wr
A
Data Byt
A
P
Figue 1. SMBus SenBytProtocol
1
7
1
1
8
1
A
1
1
S
Se Address
R
Data Byte
P
Figure 15. SMBus Receive Byte Protocol
1
7
1
8
1
8
1
1
S
Slave Addess
Wr
A
Command Code
A
Data Byte
A
P
Figure 16. SMBus Write Byte Protocol
1
7
1
1
8
1
1
7
1
1
8
1
A
1
1
S
Slave Address
Wr
A
Command Code
A
S
Slave Address
Rd
A
Data Byte Low
P
Figure 17. SMBus Read Byte Protocol
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1
7
1
1
8
1
8
1
8
1
1
S
Slave Address
Wr
A
Command Code
A
Data Byte Low
A
Data Byte High
A
P
Figure 18. SMBus Write Word Protocol
1
7
1
1
8
1
1
7
1
1
8
1
...
S
Slave Address
Wr
A
Command Code
A
S
Slave Address
Rd
A
Data Byte Low
A
8
1
1
Data Byte High
A
P
1
Figure 19. SMBus Read Word Protocol
1
7
1
1
8
1
8
1
8
1
...
S
Slave Address
Wr
A
Command Code
A
Byte Count = N
A
Data Byte 1
A
8
1
8
1
1
...
Data Bte
A
Data Byte N
A
P
2
Figure 20. SMBus Block Writor I C Write Protools
2
NOTE: The I C write protocol does not use the Byte Count packet, and the Master will continue seding Data Bytes until the Master initiates a
Stop condition. See the Command Register on page 13 for additional information regrding the Block Read/Write protocol.
1
7
1
1
8
1
7
1
1
8
1
...
S
Slave Address
Wr
A
Command Coe
A
Sr Slave Adress Rd
A
Byte Count = N
A
1
8
1
8
1
1
...
Data Byte 1
A
ata Byte 2
A
Data Byte N
A
1
P
2
Figure 21. SMBus Block Read or I C Read (Combined Format) Protocols
2
NOTE: The I C read protocol does not use the Byte Cunt pcket, and the Master will continue receiving Data Bytes until the Master initiates
a Stop Condition. See the Command Registepage 13 for additional information regarding the Block Read/Write protocol.
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Register Set
The TCS3404/14 is controlled and monitored by 18 user registers and a command register accessed through
the serial interface. These registers provide for a variety of control functions and can be read to determine results
of the ADC conversions. The register set is summarized in Table 2.
Table 2. Register Set
ADDRESS
−−
REGISTER NAME
COMMAND
REGISTER FUNCTION
Specifies register address
00h
01h
02h
03h
04h
07h
08h
09h
0Ah
0Bh
0Fh
10h
11h
CONTROL
Control of basic functions
TIMING
Integration time/gain control
Interrupt control
INTERRUPT
INT SOURCE
ID
Interrupt source
Part number/ Rev ID
GAIN
ADC gain control
LOW_THRESH_LOW_BYTE
LOW_THRESH_HIGH_BYTE
HIGH_THRESH_LOW_BYTE
HIGH_THRESH_HIGH_BYTE
−−
Low byte of low interrupt threshold
High byte of low interrupt threshold
Low byte of igh interrupt threshold
High byte high intrupt threshold
SMBus block ra(10h through 17h)
Low f DC green chan
High be of ADC green channel
Low byte of ADC red chnel
Hgh byte of ADC rehanl
Low byte of DC bchannel
High byte of ADblue channel
Low byte of AC clear channel
High byte f ADC clear channel
DATA1LOW
DATA1HIGH
12h
13h
14h
15h
16h
17h
DATA2LOW
DATA2HIGH
DATA3LOW
DATA3HIGH
DATA4LOW
DATA4H
The mechanics of accessing a specific register ds on the specific SMB protocol used. Refer to the section
on SMBus protocols on the previous pags. In general, the COMMAND register is written first to specify the
specific control/status register for followinread/write operations.
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Command Register
The command register specifies the address of the target register for subsequent read and write operations.
This register contains eight bits as described in Table 3 and defaults to 00h at power on.
Table 3. Command Register
7
CMD
0
6
5
4
3
2
ADDRESS
0
1
0
0
0
COMMAND
TRANSACTION
Reset Value:
0
0
0
0
FIELD
BITS
DESCRIPTION
CMD
7
Select command register. Must write as 1.
Transaction. Selects type of transaction to follow in subsequent data transfer.
FIELD VALUE
TRANSACTION
Byte protocol
Word protocol
Block protocol
DESCRIPTION
SMB read/write byte protol
SMB read/write word proocol
SMB read/write block otocl
00
01
10
TRANSACTION
6:5
Clear any pending terrupt and is a write-
once-to-clear field
11
Interrupt cler
Register Address. This field selects the specific ntrl or status register folwing write and read com-
mands according to Table 2.
ADDRESS
4:0
2
2
NOTES: 1. An I C block transaction will continue until the Master sends a op condition. See Fiure 1nd Figure 19. Unlike the I C protocol,
the TCS3404/14 SMBus read/write protocol requires a Byte Count. All eight ADChnel Data Registers (10h through 17h) can
be read simultaneously in a single SMBus transactin. This is the only 64-bit data bock supported by the TCS3404 SMBus protocol.
The TRANSACTION field must be set to 10, and a read ondition should tiated with a COMMAND CODE of CFh. By using
a COMMAND CODE of CFh during an SMBs ock Read Protocolthe T344 device will automatically insert the appropriate
Byte Count (Byte Count = 8) as illustrated in Figur18. A write conditn should not be used in conjunction with the 0Fh register.
2. Only the Send Byte Protocol should e usd when clearing inrrupt
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Control Register (00h)
The CONTROL register contains two bits and is primarily used to power the TCS3404/14 device up and down
as shown in Table 4.
Table 4. Control Register
7
Resv
0
6
Resv
0
5
Resv
0
4
3
Resv
0
2
Resv
0
1
ADC_EN
0
0
CONTROL
00h
ADC_VALID
0
POWER
0
Reset Value:
FIELD
Resv
BIT
7:6
5
DESCRIPTION
Reserved. Write as 0.
Reserved. Write as 0.
Resv
ADC_VALID
Resv
4
ADC valid. This read-only field indicates that the ADC channel has completed an integration le.
Reserved. Write as 0.
3:2
ADC enable. This field enables the four ADC channels to begin integration. Writig a activates the ADC
channels, and writing a 0 disables the ADCs.
ADC_EN
POWER
1
0
Power on. Writing a 1 powers on the devic, and writing a 0 turns it off.
NOTES: 1. Both ADC_EN and POWER must be asserted before the ADC chanels will operate crre.
2. INTEG_MODE and TIME/COUNTER fields in the Ting Register (01h) should be written bfore ADC_EN is asserted.
3. If a value of 03h is written, the value returned during a cle will be 03h. s feature can be used to verify that the device is
communicating properly.
4. During writes and reads, the POWER bit is overridden nd the oscillator is enbled, independent of the state of POWER.
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Timing Register (01h)
The TIMING register controls the synchronization and integration time of the ADC channels. The Timing
Register settings apply to all four ADC channels. The Timing Register defaults to 00h at power on.
Table 5. Timing Register
7
6
5
4
3
0
2
1
0
0
0
TIMING
01h
Resv SYNC_EDGE
INTEG_MODE
PARAM
Reset Value:
0
0
0
0
0
FIELD
BITS
DESCRIPTION
Resv
7
Reserved. Write as 0.
Sync pin edge. If SYNC_EDGE is low, the falling edge of the sync pin is used to stop an inegraon
cycle when INTEG_MODE is 11. If SYNC_EDGE is high, the rising edge of the sync pin is used o
stop an integration cycle when INTEG_MODE is 11.
SYNC_EDGE
6
Selects preset integration time, manual integration (via serial bus), or external synhronation (SYNC
IN) modes.
FIELD VALUE
MODE
In this mode, the ingrator iree-running and one of te hree
internally-generated Nominantegration Times is selected for each conversion
(see Integration Time ble below).
00
Manually stategration through serial bus using ADC_EN field in Con-
trol Register.
INTEG_MODE
5:4
01
10
Synchronize exctly one internallytimd integration cycle as specified in the
NOMINAL INTEGRATION TIME eginng 2.4 μs after being initiated by the
SYC IN pin.
tegrate over specified nur of pulses on SYNC IN pin (See SYNC IN
PUSE COUNT table lowMnimum width of sync pulse is 50 μs. SYNC
IN must be low at least 6 μs.
11
Uses single, multiprpose bitmapped field to elect one of three predefined integration times or set the
number of SYNIN ulses to count whthe ITEG_MODE accumulate mode (11) is selected.
NOTE: INTEODE and TIME/TER fields should be written before ADC_EN is asserted.
FIELD VALUE
0000
NOMINAL INTEGRATION TIME
12 m
0001
100 ms
40 ms
0010
FIELD VALUE
000
SYNC IN PULSE COUNT
PARAM
3:0
1
001
2
0010
4
0011
8
0100
16
32
64
128
256
0101
0110
0111
1000
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Interrupt Control Register (02h)
The INTERRUPT register controls the extensive interrupt capabilities of the device. The open-drain interrupt
pin is active low and requires a pullup resistor to V in order to pull high in the inactive state. Using the Interrupt
DD
Source Register (03h), the interrupt can be configured to trigger on any one of the four ADC channels. The
TCS3404/14 permits both SMB-Alert style interrupts as well as traditional level style interrupts. The Interrupt
Register provides control over when a meaningful interrupt will occur. The concept of a meaningful change can
be defined by the user both in terms of light intensity and time, or persistence of that change in intensity. The
value must cross the threshold (as configured in the Threshold Registers 08h through 0Bh) and persist for some
period of time as outlined in the table below.
When a level Interrupt is selected, an interrupt is generated whenever the last conversion results in a value
outside of the programmed threshold window. The interrupt is active-low and remains asserted until cleareby
writing an 11 in the TRANSACTION field in the COMMAND register.
In SMB-Alert mode, the interrupt is similar to the traditional level style and the interrupt line is assrted low. To
clear the interrupt, the host responds to the SMB-Alert by performing a modified Receive Byte operation, in
which the Alert Response Address (ARA) is placed in the slave address field, and te TCS3404/14 that
generated the interrupt responds by returning its own address in the seven most signifcant bits of the receive
data byte. If more than one device connected on the bus has pulled the SMBAlert line low, the highest priority
(lowest address) device will win control of the bus durng the slave address trafer. f the device loses this
arbitration, the interrupt will not be cleared. The Alert espone Address is 0Ch.
When INTR = 11, the interrupt is generated immdiately following the SMBus wrte operation. Operation then
behaves in an SMB-Alert mode, and the softwarinterrupt may bcleared by an SMB-Alert cycle.
Table 6. Interrupt Control Regster
7
Resv
0
6
5
0
0
3
Re
0
2
1
0
0
INTERRUPT
02h
INTR_STOP
0
INTR
PERSIST
0
Reset Value:
0
FIELD
BITS
DESCRIPTION
Resv
7
Reserved. Write as 0.
Stop ADC integration ointeupt. When high, ADC integration will stop once an interrupt is asserted.
To resume operation (1) eassert ADC_EN using CONTROL register, (2) clear interrupt using
COMMAND rester, and (3) re-assert ADC_EN using CONTROL register. Note: Use this bit to isolate
a particular condion when the sensor is continuously integrating.
INTR_STOP
6
INTR Conol lect. This field determines mode of interrupt logic according to the table below:
FIELD VE
INTERRUPT CONTROL
0
01
10
11
Interrupt output disabled.
Level Interrupt.
INTR
5:4
SMB-Alert compliant.
Sets an interrupt and functions as mode 10.
NOTE: Value 11 may be used to test interrupt connectivity in a system or to assist in debugging interrupt
service routine software. See Application Software section for further information.
Resv
3
Reserved. Write as 0.
Interrupt persistence. Controls rate of interrupts to the host processor:
FIELD VALUE
TIMER
Every
DESCRIPTION
000
001
010
011
Every ADC cycle generates interrupt
Any value outside of threshold range.
Consecutively out of range for 0.1 second
Consecutively out of range for 1 second
PRSIST
2:0
Single
0.1 sec
1 sec
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Interrupt Source Register (03h)
The Interrupt Source register selects which ADC channel value to use to generate an interrupt. Only one of the
four ADC channels can be selected.
Table 7. Interrupt Source Register
7
Resv
0
6
Resv
0
5
Resv
0
4
Resv
0
3
Resv
0
2
1
0
0
INT SOURCE
03h
Resv
INT SOURCE
Reset Value:
0
0
FIELD
BITS
DESCRIPTION
Resv
7:2
Reserved. Write as 0.
Interrupt Source. Selects which ADC channel to use to generate an interrupt:
FIELD VALUE
INTERRUPT SOURCE
00
01
10
11
Green channel
Red channel
Blue channel
Clear channel
INT SOURCE
1:0
NOTE: The INTERRUPT THRESHOLD Register (08h−0Bh) should be igured appropriately to correspond o the ADC channel value that
generates an interrupt.
ID Register (04h)
The ID register provides the value for boh the part number ad silicon revision number for that part number.
It is a read-only register, whose value ever changes.
Table 8. ID egister
7
6
5
4
−
3
−
2
−
1
−
0
−
ID
04h
PARTNO
REVNO
Reset Value:
FIELD
−
BITS
7:4
−
−
DESCRIPTION
Part Number entifiation: field value 0000 = TCS3404
PARTNO
REVNO
field value 0001 = TCS3413, TCS3414, TCS3415, and TCS3416
3:0
Revision numer identification
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Gain Register (07h)
The Gain register provides a common gain control adjustment for all four parallel ADC output channels. Two
gain bits [5:4] in the Gain Register allow the relative gain to be adjusted from 1× to 64× in 4× increments. The
advantage of the gain adjust is to extend the dynamic range of the light input up to a factor of 64× before analog
or digital saturation occurs. If analog saturation has occurred, lowering the gain sensitivity will likely prevent
analog saturation especially when the integration time is relatively short. For longer integration times, the 16-bit
output could be in digital saturation (64K). If lowering the gain to 1× does not prevent digital saturation from
occurring, the use of PRESCALER can be useful.
The PRESCALER is 3 bits [2:0] in the gain register that divides down the output count (i.e. shifts the LSB of the
count value to the right). The PRESCALER adjustment range is divide by 1 to 64 in multiples of 2.
The most sensitive gain setting of the device would be when GAIN is set to 11b (64×), and PRESCALEis set
to 000b (divide by 1). The least sensitive part setting would be GAIN 00 (1×) and PRESCALER 110 (de by
64). If the part continues to be in digital saturation at the least sensitive setting, the integration ime can be
lowered (see Timing Register section).
Table 9. Gain Register
7
Resv
0
6
Resv
0
5
0
4
0
3
esv
0
2
1
0
0
GAIN
07h
GAIN
PESCLER
0
Reset Value:
0
FIELD
BITS
DESCRIPTIN
Resv
7:6
5:4
3
Reserved. Write as 0.
Analog Gain Control. This feld switches the mon analog gain of the four ADC channels. Four gain
modes are provided:
FIELD VALUE
GAIN
00
1×
4×
16×
4×
GAIN
Resv
10
11
Reserved. Write as 0.
Prescaler. Thifield controls a 6-bit digital prescaler and divider. The prescaler reduces the sensitivity
of each ADC interator as shown in the table below:
FIELD VAE
PRESCALER MODE
000
01
010
011
100
101
110
111
Divide by 1.
Divide by 2.
Divide by 4.
Divide by 8.
Divide by 16.
Divide by 32.
Divide by 64.
Not used.
PRESCALER
2:0
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Interrupt Threshold Register (08h − 0Bh)
The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison
function for interrupt generation. The high and low bytes from each set of registers are combined to form a 16-bit
threshold value. If the value generated by the Interrupt Source Register (03h) converges below or equal to the
low threshold specified, an interrupt is asserted on the interrupt pin. If the value generated by Interrupt Source
Register (03h) converges above the high threshold specified, an interrupt is asserted on the interrupt pin.
Registers LOW_THRESH_LOW_BYTE and LOW_THRESH_HIGH_BYTE provide the low byte and high byte,
respectively, of the lower interrupt threshold. Registers HIGH_THRESH_LOW_BYTE and
HIGH_THRESH_HIGH_BYTE provide the low and high bytes, respectively, of the upper interrupt threshold.
The interrupt threshold registers default to 00h on power up.
Table 10. Interrupt Threshold Register
REGISTER
ADDRESS
08h
BITS
7:0
DESCRIPTION
LOW_THRESH_LOW_BYTE
LOW_THRESH_HIGH_BYTE
HIGH_THRESH_LOW_BYTE
HIGH_THRESH_HIGH_BYTE
ADC interrupt source lower byte of the low threshld
ADC interrupt source upper byte of the lw threshold.
ADC interrupt source lower byte of the high reshold.
ADC interrupt source upper byte of e higthreshold.
09h
7:0
0Ah
7:0
0Bh
7:0
NOTES: 1. The Interrupt Source Register (03h) selects which ADC channel tgeneraan interrupt and should crespond to the threshold
setting. Both registers should be configured appropriately when stting uan interrupt serve roine.
2. Since two 8-bit values are combined for a single 16-bit value or each of the high and low interrupt thrsholds, the SMBus Send Byte
protocol should not be used to write to these registers. Any ransferred by the Send Byte protocol with the MSB set would
be interpreted as the COMMAND field and stored as an adss for subsequent readwrite operations and not as the interrupt
threshold information as desired. The Write Word protocol hould be used to wte byte-paired registers. For example, the
LOW_THRESH_LOW_BYTE and LOW_THRESH_HIGH_BYTE registers (awell s the HIGH_THRESH_LOW_BYTE and
HIGH_THRESH_HIGH_BYTE registers) can be rittn ogether to set the 16-bit DC value in a single transaction.
ADC Channel Data Registers (10h − 17)
The ADC channel data are expressed a16-bit values spead across four registers. The channel low and high
provide the lower and upper byts pectively for each ADC channel data registers. Each DATALOW and
DATAHIGH register is identified bew as 1, 2, 3, ol channel data registers are read-only and default to
00h on power up.
Table 11. ADC Channel Data Registers
REGISTER
GREEN_LOW
GREEN_HIGH
RED_LOW
ADDRESS
10h
BITS
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
DESCRIPTION
ADC channel 1 lower byte
11
ADC channel 1 upper byte
ADC channel 2 lower byte
ADC channel 2 upper byte
ADC channel 3 lower byte
ADC channel 3 upper byte
ADC channel 4 lower byte
ADC channel 4 upper byte
1h
RED_HIGH
13h
BLUE_LOW
BLUE_HIH
CEAR_OW
CLER_HIGH
14h
15h
16h
17h
The uppyte data registers can only be read following a read to the corresponding lower byte register. When
thlowebye register is read the upper eight bits are strobed into a shadow register, which is read by a
subequent read to the upper byte. The upper register will therefore read the correct value even if additional
ADC integration cycles complete between the reading of the lower and upper registers.
NOTE: The SMBus Read Word protocol can be used to read byte-paired registers. For example, the DATA1LOW and DATA1HIGH registers (as
well as the other three individual register pairs) may be read together to obtain the 16-bit ADC value in a single transaction.
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APPLICATION INFORMATION: SOFTWARE
Basic Operation
After applying V , the device will initially be in the power−down state. To operate the device, issue a command
DD
to access the control register followed by the data value 03h to the control register to set ADC_EN and POWER
to power up the device. At this point, all four ADC channels will begin a conversion at the default integration time
of 12 ms. After 12 ms, the conversion results will be available in ADC Channel Data Registers (10h through 17h).
The following pseudo code illustrates a procedure for reading the TCS3404/14 device using Word and Byte
transactions:
// Read ADC Channels Using Read Word Protocol − RECOMMENDED
Address = 0x39
Command = 0x80
PowerUp = 0x03
//Power Up and Enable ADC
//Wait for integration conversion
//Address the Ch1 lower data register and configure for Read Word
Command = 0xB0
//Set Command bit and Word tansaction
//Reads two bytes from sequential register10h and 11h
//Results are returned in DataLow and DatHigariables
ReadWord (Address, Command, DataLow, DataHgh)
Channel1 = 256 * DataHigh + DataLow
//Address the Ch2 lower data register d configure for Read Word
Command = 0xB2
//Set Commnd bit and Word transaction
//Reads two bytes from sequentil rgisters 12h and 3h
//Results are returned in DataLow and DataHigh riables
ReadWord (Address, Command, DatLow, DataHi)
Channel2 = 256 * DataHigh + ataLow //Shift DtaHigh to upper byte
//Address the Ch3 lower data register anconfigure for Read Word
Command = 0xB4
//Set Command bit and Word transaction
//Reads two bytes from sequential reters 14h and 15h
//Results are returned in DataLw and DataHigh variables
ReadWord (Address, Command, DataowDataHigh)
Channel3 = 256 * DataHigh DataLow
//Address the Ch4 lower da register and configure for Read Word
Command = 0xB8
//Set Command bit and Word transaction
//Reads two bytes fom equential registers 16h and 17h
//Results are retrned in DataLow and DataHigh variables
ReadWord (Addres, ommand, DataLow, DataHigh)
Channel4 = 25* ataHigh + DataLow //Shift DataHigh to upper byte
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// Read ADC Channels Using Read Byte Protocol
Address = 0x39
//Slave addr − also 0x29 or 0x49
//Address the Ch1 lower data register
//Result returned in DataLow
//Address the Ch1 upper data register
//Result returned in DataHigh
//Shift DataHigh to upper byte
//Address the Ch2 lower data register
//Result returned in DataLow
//Address the Ch2 upper data register
//Result returned in DataHigh
//Shift DataHigh to upper byte
//Address the Ch3 lower data register
//Result returned in DataLow
//Address the Ch3 upper data register
//Result returned in DataHigh
//Shift DataHigh to upper byte
//Address the Ch4 lower data regster
//Result returned in DataLw
//Adress the Ch4 upper ata register
//esureturned in Dataigh
Command = 0x90
ReadByte (Address, Command, DataLow)
Command = 0x91
ReadByte (Address, Command, DataHigh)
Channel1 = 256 * DataHigh + DataLow
Command = 0x92
ReadByte (Address, Command, DataLow)
Command = 0x93
ReadByte (Address, Command, DataHigh)
Channel2 = 256 * DataHigh + DataLow
Command = 0x94
ReadByte (Address, Command, DataLow)
Command = 0x95
ReadByte (Address, Command, DataHigh)
Channel3 = 256 * DataHigh + DataLow
Command = 0x96
ReadByte (Address, Command, DataLow)
Command = 0x97
ReadByte (Address, Command, DataHigh)
Channel4 = 256 * DataHigh + DataLow
//hift ataHigh to upper byte
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DIGITAL COLOR SENSORS
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APPLICATION INFORMATION: SOFTWARE
Configuring the Timing Register
The command, timing, and control registers are initialized to default values on power up. Setting these registers
to the desired values would be part of a normal initialization or setup procedure. In addition, to maximize the
performance of the device under various conditions, the integration time and gain may be changed often during
operation. The following pseudo code illustrates a procedure for setting up the timing register for various
options.
// Set up Timing Register
//Low Gain (1x), integration time of 12ms (default value)
Address = 0x39
Command = 0x81
//Timing Register
Data = 0x02
WriteByte(Address, Command, Data)
//Low Gain (1x), integration time of 101ms
Command = 0x81
//Timing Register
Data = 0x01
WriteByte(Address, Command, Data)
//Low Gain (1x), integration time of 12ms
Data = 0x00
WriteByte(Address, Command, Data)
//High Gain (16x), integration time of 01ms
Command = 0x81
//TiminReister
Data = 0x01
WriteByte(Address, Command, Data)
Command = 0x87
/Gan Control Register
Data = 0x20
WriteByte(Address, Command, Data)
//Read data registers (see BaOperation ampe)
//Perform Manual Integration of 50 us
//Set up for manual integration
Command = 0x80
Data = 0x01
//Disable ADC_EN
WriteByte(Address, Command, ata)
Command = 0x81
Data = 0x10
WriteByte(Address, ommnd, Data)
//Set manual integration
//Enable ADC_EN and begin integration
//Wait for 50ms
Command = 0x80
Data = 0x03
WriteByte(Addrss, Command, Data)
//Integrae for 50ms
Sleep (50)
/top integrating
mand 0x80
Data = 0x01
//Disable ADC_EN and stop integration
WriteByte(Address, Command, Data)
//Read data registers (see Basic Operation example)
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TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
APPLICATION INFORMATION: SOFTWARE
Synchronization
There are two basic modes of operation for controlling synchronization: (1) internally timed, and (2) externally
timed. Internally-timed integration cycles can either be continuous back-to-back conversions or can be
externally triggered as a single event using the SYNC pin. Externally-timed integrations can be controlled by
setting and clearing the ADC Enable in the Control Register using the serial interface, or by one or more pulses
input to the SYNC pin. Internally-timed integration cycle times are dependent on the PARAM field value and the
internal clock frequency. Nominal integration times and respective scaling between integration times scale
proportionally as shown in the PARAM field in Table 5. See Operating Characteristics Table notes for detailed
information regarding how the scale values were obtained.
If a particular integration time period is required that is not listed in the PARAM Integration Time field value, n
the manual timing control feature can be used to manually start and stop the integration time period by setting
INTEG_MODE=01b. Manual integration is performed as follows:
Integration Period
Time duration determined by
length of time that ADC_E= 1
ADC_EN
INTERRUPT
A
B
Figure 22. MnuaIntegration (INTEG_MODE 01b)
1. Disable ADC_EN (= 0) before iting a manual integation cycle
2. Clear and enable INTR before each cycle
3. Write 01b to INTEG_MODE field
4. Set ADC_EN (= 1) to start integration
5. Clear ADC_EN ( = 0) to stop integtion
6. Read channel data
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TAOS137A − APRIL 2011
APPLICATION INFORMATION: SOFTWARE
When the INTEG_MODE field value is set to 10b, an externally-controlled synchronization input (SYNC) is used
to trigger the start of an integration period. The integration period starts on the rising edge of the SYNC pulse,
triggers a single, internally-timed integration cycle, and continues until the Nominal Integration Time, as defined
in the PARAM field, is completed.
Integration Period
Time duration determined by
PARAM field (nominal
integration time)
SYNC IN
INTERRUPT
A
B
NOTE: ADC_EN must be toggled (i.e. from high to low and back to high again) before next integration ccle
Figure 23. One-Shot Integration (INTEG_ODE 10b) Falling Edge
1. Enable ADC_EN (= 1)
2. Set PARAM for desired integration cycle (12m100ms, or 400ms)
3. Set INTEG_MODE to 10b
4. Disable SYNC and clear INTR
5. Read channel data
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TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
APPLICATION INFORMATION: SOFTWARE
When the INTEG_MODE field value is set to 11b, the device integrates from the rising edge of the first pulse
until the rising or falling edge of a subsequent pulse as specified by the SYNC_EDGE and PARAM field values.
See example timing diagrams below. ADC_EN must be toggled (i.e. from high to low and back to high again)
before the next integration cycle. With this device feature, the SYNC IN input pin can be used to synchronize
the device with an external light source (e.g. LED).
Integration
Period
SYNC IN
INTERRUPT
A
B
NOTES: 1. Rising edge of second SYNC IN pulse required to terminate integation cye
2. ADC_EN must be toggled (i.e. from high to low and back to high gain) bore next integratn cycle
Figure 24. Integrate Over One Pulse (SYNC_EDGE INTEG_MODE 11b, PARAM 0b) Rising Edge
1. Enable ADC_EN (= 1)
2. Set SYNC EDGE to 1
3. Set PARAM for SYNC PULSE COUNT f 1
4. Set INTEG_MODE to 11b
5. Input two external SYNC pulses
6. Disable SYNC and read chann
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APPLICATION INFORMATION: SOFTWARE
Integration Period
SYNC IN
INTERRUPT
A
B
NOTE: ADC_EN must be toggled (i.e. from high to low and back to high again) before next integration cycle
Figure 25. Integrate Over One Pulse (SYNC_EDGE 0b, INTEG_MODE 11b, PARAM 0b) FallinEdge
1. Enable ADC_EN (= 1)
2. Set SYNC EDGE to 0
3. Set PARAM for SYNC PULSE COUNT of 1
4. Set INTEG_MODE to 11b
5. Input external SYNC pulse
6. Disable SYNC and read channels
Itegration Period
N
N+1
SYNC IN
INTERRUPT
A
B
NOTES: 1. Rising edge of third SYNC IN pulsequired to terminate integration cycle
2. ADC_EN must be toggle(i.e. om high to low and back to high again) before next integration cycle
Figure 26. Integrate Over Two Pulses (SYNC_EDGE 1b, INTEG_MODE 11b, PARAM Xb) Rising Edge
1. Enable ADC_EN (= 1)
2. Set SYNEDGE to 1
3. Set ARAM for desired SYNC PULSE COUNT
4. t INTEG_MODE to 11b
5. Iput N+1 external SYNC pulses
6Disable SYNC and read channels
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TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
APPLICATION INFORMATION: SOFTWARE
Integration
Period
1
N
SYNC IN
INTERRUPT
A
B
NOTE: ADC_EN must be toggled (i.e. from high to low and back to high again) before next integration cycle
Figure 27. Integrate Over Two Pulses (SYNC_EDGE 0b, INTEG_MODE 11b, PARAM Xb) Falling Ege
1. Enable ADC_EN (= 1)
2. Set SYNC EDGE to 0
3. Set PARAM for desired SYNC PULSE COUNT
4. Set INTEG_MODE to 11b
5. Input N external SYNC pulse(s)
6. Disable SYNC and read channels
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APPLICATION INFORMATION: SOFTWARE
A synchronization input (SYNC IN) is supported to precisely start/stop sensor integration and synchronize with
the light source. The TIMING Register (01h) provides two synchronization modes of operation. The first mode
of operation synchronizes the SYNC IN pin for one integration cycle as specified in the Timing Register (01h).
When the rising edge of the signal is detected, the TCS3404/14 begins integration. The second mode
accumulates a specified number of SYNC IN pulses (see Timing Register) in which the minimum pulse width
is 50 μs. A pulse counter is used to count the rising and falling edges of the pulse(s) and precisely integrate the
light level when the SYNC IN pulse is high.
The following pseudo code illustrates a procedure for reading the TCS3404/14 device using the synchronizaton
feature:
// Synchronize one integration cycle
// See ”Basic Operation” to power−on and start device
// See ”Configuring the Timing Register” to setup environment
Address = 0x39
Command = 0x81
Data = 0x21
//Slave addr − also 0x29 or 0x4
//Set Command bit and address Timng Register
//Sync one 100ms integration peiod
//External SYNC IN pulse initiates 100ms integation
Sleep (100)
// See ”Basic Operation” to read Data gisters using Byte or Word Protocol
// Synchronize N number of SYNC IN pulses
// See ”Basic Operation” to power−on and start devie
// See ”Configuring the Timing giter” to setenvironment
Address = 0x39
Command = 0x81
Data = 0x30
//Slaaddr − also 0x29 or 0x49
//Set Comand bit and address Timing Register
//Interate one SYNC IN pulse
//External SYNC IN pulsynchronizetegration
// See ”Basic Operation” to read Dagisters using Byte or Word Protocol
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TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
APPLICATION INFORMATION: SOFTWARE
Interrupts
The interrupt feature of the TCS3404/14 device simplifies and improves system efficiency by eliminating the
need to poll the sensor for a light intensity value. Interrupt mode is determined by the INTR field in the Interrupt
Control Register. The interrupt feature may be disabled by writing a field value of 00h to the Interrupt Control
Register (02h) so that polling can be performed.
The versatility of the interrupt feature provides many options for interrupt configuration and usage. The primary
purpose of the interrupt function is to signal a meaningful change in light intensity. However, it also be used as
an end-of-conversion signal. The concept of a meaningful change can be defined by the user both in terms of
light intensity and time, or persistence, of that change in intensity. The TCS3404/14 device implements to
16-bit-wide interrupt threshold registers that allow the user to define thresholds above and below a desred t
level. An interrupt will then be generated when the value of a conversion exceeds either of these limts. For
simplicity of programming, the threshold comparison uses the Interrupt Source Register (03h) to selecwhich
ADC channel (1 through 4) to generate the interrupt. This simplifies calculation of thresholds tat are based on
a percent of the current light level. For example, it is adequate to use only one channel (e.g. gren channel) when
calculating light intensity differences since, for a given light source, channel values are liearly proportional to
each other and thus each value scales linearly with light intensity.
To further control when an interrupt occurs, the TCS3404/1devicprovides an nterrupt persistence feature.
This feature allows the user to specify the length in tie of the number of consecutive ADC channel values for
which a light intensity exceeding either interrupt threshmust persist befe actually generating an interrupt.
This can be used to prevent transient changes in light tensity from generatng an unwanted interrupt. See
Table 6 regarding the number of timer values provided.
Two different interrupt styles are available: Level and SMBus Alerte difference between these two interrupt
styles is how they are cleared. Both result ithe interrupt lne gng active low and remaining low until the
interrupt is cleared. A level style interrupt s cleared by setting he Interrupt Clear field in the the COMMAND
register to 11b. The SMBus Alert style nterrupt is cleared by an Alert Response as described in the Interrupt
Control Register section and SMuspecification.
To configure the interrupt as an end−of−conversioal so that every ADC integration cycle generates an
interrupt, the interrupt PERSIST field in the Interrupt Ctrol Register (02h) is set to 000b. Either Level or SMBus
Alert style can be used. An interrupt will be eneated upon completion of each conversion. The interrupt
threshold registers are ignored. The folowing example illustrates the configuration of a level interrupt:
// Set up end−of−conversion iterupt, Level style
Address = 0x39
Command = 0x83
Data = 0x01
//Slave address − alternatively 0x29 or 0x49
//Interrupt Source Register
//Select Channel 2
WriteByte(Address, Comand, Data)
Command = 0x82
Data = 0x10
//Address Interrupt Register
//Level style, every ADC cycle
WriteByte(Addres, Command, Data)
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APPLICATION INFORMATION: SOFTWARE
The following example pseudo code illustrates the configuration of an SMB-Alert style interrupt when the light
intensity changes 20% from the current value, and persists for 2.5 seconds:
//Assume Interrupt Source as Channel 1
//Read current light level
Address = 0x39
Command = 0xB0
//Slave address − alternatively 0x29 or 0x49
//Set Command bit and SMBus Word read
ReadWord (Address, Command, DataLow, DataHigh)
Channel1 = (256 * DataHigh) + DataLow
//Calculate upper and lower thresholds
T_Upper = Channel1 + (0.2 * Channel1)
T_Lower = Channel1 − (0.2 * Channel1)
//Write the lower threshold register
Command = 0xA8
//Address lower threshold register, seWord Bit
WriteWord (Address, Command, T_Lower.LoByte, T_Lower.HiByte)
//Write the upper threshold register
Command = 0xAA
//Address upper threshold reistr, set Word bit
WriteWord (Address, Command, T_Upper.LoByte, T_Upper.HiByte)
//Enable interrupt
Command = 0x82
//Address interrupt regiser
Data = 0x24
//SMAlert style, Persist 25 seconds
WriteByte(Address, Command, Data)
In order to generate an interrupt on demand during stem test or debuga test mode (INTR = 11) can be used.
The following example illustrates how to generate n interrupt on demand:
// Generate an interrupt
Address = 0x39
Command = 0x82
Data = 0x30
//Se address alternately 0x29 or 0x49
/Adress Interrupt Control Register
//est interrupt
WriteByte(Address, Command, Data)
//Interrupt line shoulow be low
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DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
APPLICATION INFORMATION: HARDWARE
Power Supply Decoupling and Application Hardware Circuit
The power supply lines must be decoupled with a 0.1 μF capacitor placed as close to the device package as
possible (Figure 28). The bypass capacitor should have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents caused by internal logic switching.
V
V
BUS
DD
0.1 ꢀ F
TCS3404/14
R
P
R
P
R
PI
INT
SCL
SDA
Figure 28. Bus PuResistors
Pull-up resistors (Rp) maintain the SDA and SCL lines at a high level whn the bus is free and ensure the signals
2
are pulled up from a low to a high level within the required rise time. For a complete description of I C maximum
2
and minimum Rp values, please review the NXP I C design specifon at http://www.i2c−bus.org/references/.
A pull-up resistor (R ) is also required for he interrupt (INT), wich functions as a wired-AND signal in a similar
PI
fashion to the SCL and SDA lines. A tyical impedance valubetween 10 kΩ and 100 kΩ can be used. Please
note that while the figure above shos INT being pulled p to V , the interrupt can optionally be pulled up to
DD
V
BUS
.
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TAOS137A − APRIL 2011
APPLICATION INFORMATION: HARDWARE
PCB Pad Layout for CS Package
Suggested PCB pad layout guidelines for the CS package are shown in Figure 29.
0.61
0.61
6
ꢁ ꢂ 0.30
0.95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Figure 29. Suggested S Package PCB Lyout
PCB Pad Layout for FN Package
Suggested PCB pad layout guideinefor the Dual Flat N-Lead (FN) surface mount package are shown in
Figure 30.
1.25
1.25
0.40
0.95
0.5
2.30
0.40
NOTES: All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Figure 30. Suggested FN Package PCB Layout
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TCS3404, TCS3414
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TAOS137A − APRIL 2011
MECHANICAL DATA
PACKAGE CS
Six-Lead Chipscale
TOP VIEW
PINOUT
TOP VIEW
2095
SCL SYNC GND
A1
A2
A3
1565
ꢃ 10
1875
B1
B2
B3
SDA
V
IN
DD
350
ꢃ
1
0
PHOTODIODE ARRAY
END VIEW
405 ꢃ 20
685 ꢃ 45
6
ꢁ
1
6
0
ꢃ
3
0
BOTTOM VIEW
C
L of Photodiode
of Solder Bumps
C
L
Array Area
128 Nominal
6
ꢁ
ꢂ
3
0
0
ꢃ
3
0
463 ꢃ 30
950
Nominal
of Solder Bumps and
C
L Photodiode Array Area
Pb
Lead Free
610 Nominal
438 ꢃ 30
NOTESA. All liear dimensions are in micrometers. Dimension tolerance is 25 μm unless otherwise noted.
B. Solder bumps are formed of Sn (96.5%), Ag (3%), and Cu (0.5%).
C. The layer above the photodiode is glass and epoxy with an index of refraction of 1.53.
D. This drawing is subject to change without notice.
Figure 31. Package CS — Six-Lead Chipscale Packaging Configuration
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TAOS137A − APRIL 2011
MECHANICAL DATA
PACKAGE FN
TOP VIEW
Dual Flat No-Lead
PIN OUT
TOP
VIEW
350 ꢃ 10
PIN 1
SCL 1
6 GND
5 Vdd
4 IT
SYNC 2
SDA 3
1565
ꢃ 10
3000
ꢃ 100
3000
ꢃ 100
PHOTODIODE ARRAY
END VIEW
SIDE VIEW
295
Nominal
650 ꢃ 50
203 ꢃ 8
950
300
ꢃ 50
BOTTOM VIEW
C
L of Photodiode
C
L of Soldeontacts
Array Area
(Note B)
128 Nominal
C of Solder Contacts and
L Photodiode Array Area (Note B)
PIN 1
Pb
Lead Free
950 ꢃ 150
NOTES: All linear dimensions are in micrometers. Dimension tolerance is 20 μm unless otherwise noted.
Thdie is centered within the package within a tolerance of 3 mils.
C. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55.
D. Contact finish is copper alloy A194 with pre-plated NiPdAu lead finish.
E. This package contains no lead (Pb).
F. This drawing is subject to change without notice.
Figure 32. Package FN — Dual Flat No-Lead Packaging Configuration
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TCS3404, TCS3414
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MECHANICAL DATA
TOP VIEW
2.00 ꢃ 0.05
1.75
ꢂ 1.50
4.00
4.00
B
+ 0.30
8.00
− 0.10
3.50 ꢃ 0.05
B
A
A
DETAIL A
DETAIL B
5ꢀ Max
5ꢀ Max
0.254
ꢃ 0.02
2.30 ꢃ 0.05
2.12 ꢃ 0.05
1.02 ꢃ 0.05
B
o
A
o
K
o
NOTES: A. All liner imesions are in millimeters. Dimension tolerance is 0.10 mm unless otherwise noted.
B. The dimesions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
C. Symbols on rawing A , B , and K are defined in ANSI EIA Standard 481−B 2001.
o
o
o
D. Eah reeis 178 millimeters in diameter and contains 3500 parts.
E. AOS packaging tape and reel conform to the requirements of EIA Standard 481−B.
n accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape
G. This drawing is subject to change without notice.
Figure 33. Package CS Carrier Tape
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MECHANICAL DATA
TOP VIEW
2.00 ꢃ 0.05
1.75
ꢂ 1.50
4.00
4.00
B
+ 0.30
8.00
− 0.10
3.50 ꢃ 0.05
B
A
A
DETAIL A
DETAIL B
12ꢀ Max
3.30
10ꢀ Max
0.254
ꢃ 0.0
3.30
0.8
A
o
B
o
K
o
NOTES: H. Alineadimensions are in millimeters. Dimension tolerance is 0.10 mm unless otherwise noted.
I. The imensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
J. Symbs on drawing A , B , and K are defined in ANSI EIA Standard 481−B 2001.
o
o
o
KEah reel is 178 millimeters in diameter and contains 3500 parts.
L. TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B.
M. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape
N. This drawing is subject to change without notice.
Figure 34. Package FN Carrier Tape
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TCS3404, TCS3414
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TAOS137A − APRIL 2011
MANUFACTURING INFORMATION
The CS and FN packages have been tested and has demonstrated an ability to be reflow soldered to a PCB
substrate.
The solder reflow profile describes the expected maximum heat exposure of components during the solder
reflow process of product on a PCB. Temperature is measured on top of component. The components should
be limited to a maximum of three passes through this solder reflow profile.
Table 12. Solder Reflow Profile
PARAMETER
Average temperature gradient in preheating
REFERENCE
TCS3404/14
2.5°C/sec
Soak time
t
2 to 3 minutes
Max 60 sc
soak
Time above 217°C (T1)
Time above 230°C (T2)
t
1
t
Max 50 se
2
Time above T
−10°C (T3)
t
Max 10 sec
peak
3
Peak temperature in reflow
T
20° C −0°C/+5°C)
Max −5°C/sec
peak
Temperature gradient in cooling
Not to scale — for reference only
T
peak
T
3
T
T
2
1
Time (sec)
t
t
t
3
2
1
t
sok
Figure 35. Solder Reflow Profile Graph
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TAOS137A − APRIL 2011
MANUFACTURING INFORMATION
Moisture Sensitivity
Optical characteristics of the device can be adversely affected during the soldering process by the release and
vaporization of moisture that has been previously absorbed into the package molding compound. To ensure the
package molding compound contains the smallest amount of absorbed moisture possible, each device is
dry-baked prior to being packed for shipping. Devices are packed in a sealed aluminized envelope with silica
gel to protect them from ambient moisture during shipping, handling, and storage before use.
CS Package
The CS package has been assigned a moisture sensitivity level of MSL 2 and the devices should be stored under
the following conditions:
Temperature Range
Relative Humidity
Floor Life
5°C to 50°C
60% maximum
1 year out of bag at ambient < 30°C / 60% RH
Rebaking will be required if the aluminized envelope has been open for more than 1 year. f rebaking is required,
it should be done at 50°C for 12 hours.
FN Package
The FN package has been assigned a moisture seity level of MSL and the devices should be stored under
the following conditions:
Temperature Range
Relative Humidity
Total Time
5°C to 50°C
60% maximum
12 monthfrom the date ode n te aluminized envelope — if unopened
168 hors or fewer
Opened Time
Rebaking will be required if the devices have been stred unopened for more than 12 months or if the aluminized
envelope has been open for mothan 168 hours. If reaking is required, it should be done at 50°C for 12 hours.
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TAOS137A − APRIL 2011
PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
LEAD-FREE (Pb-FREE) and GREEN STATEMENT
Pb-Free (RoHS) TAOS’ terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current
RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous
materials. Where designed to be soldered at high temperatures, TAOS Pb-Free products are suitable for use in specified
lead-free processes.
Green (RoHS & no Sb/Br) TAOS defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and
Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
Important Information and Disclaimer The information provided in this statement represents TAOS’ knowlege and
belief as of the date that it is provided. TAOS bases its knowledge and belief on information provided by third parties,
and makes no representation or warranty as to the accuracy of such information. Efforts are underway better integrate
information from third parties. TAOS has taken and continues to take reasonable steps to proide epresentative
and accurate information but may not have conducted destructive testing or chemical analysis on comng materials and
chemicals. TAOS and TAOS suppliers consider certain information to be proprietary, and thCAS numbers and other
limited information may not be available for release.
NOCE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reservs the right to make chages to the products contained in this
document to improve performance or for any other purpose, or to discontinue tem without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders r designing TAOS products into systems.
TAOS assumes no responsibility for the use f ay products or cicuits scibed in this document or customer product
design, conveys no license, either expressed oimplied, under any paent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no aim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liility arising out of the se of any product or circuit, and specifically disclaims any
and all liability, including without limitatconsequential oncidntal damages.
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, IC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH TE FILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
LUMENOLOGY, TAOS, the TAOS logo, and Ts Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced
Optoelectronic Solutions Incorpoated
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
r
r
40
www.taosinc.com
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