AM93LC56N [ANACHIP]
2048-bits Serial Electrically Erasable PROM; 2048位的串行电可擦除的PROM
| 型号： | AM93LC56N |
| 厂家： | 
ANACHIP CORP |
| 描述： | 2048-bits Serial Electrically Erasable PROM |
| 文件： | 总10页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ATC
2048-bits Serial Electrically Erasable PROM
AM93LC56
ꢀ Features
ꢀ General Description
• State-of-the-art architecture
The AM93LC56 is the 2048-bit non-volatile serial
EEPROM. It is manufactured by using ATC's
advanced CMOS EEPROM technology. The
AM93LC56 provides efficient non-volatile read/write
memory arranged as 128 words of 16 bits each
when the ORG Pin is connected to VCC and 256
words of 8 bits each when it is tied to ground. The
instruction set includes read, write, and write
enable/disable functions. The data out pin (DO)
indicates the status of the device during the
self-timed non-volatile programming cycle.
- Non-volatile data storage
- Standard voltage and low voltage operation
Vcc: 2.7V ~ 5.5V
- Full TTL compatible inputs and outputs
- Auto increment read for efficient data dump
• Hardware and software write protection
- Defaults to write-disabled state at power up
- Software instructions for write-enable/disable
- VCC level verification before self-timed
programming cycle
•
Advanced low voltage CMOS EEPROM
technology
The self-timed write cycle includes an automatic
erase-before-write capability. Only when the chip is
in the WRITE ENABLE state and proper VCC
operation range is the WRITE instruction accepted
and thus to protect against inadvertent writes. Data
is written in 16 bits per write instruction into the
selected register. If Chip Select (CS) is brought
HIGH after initiation of the write cycle, the Data
Output (DO) pin will indicate the READY/BUSY
status of the chip.
• Versatile, easy-to-use interface
- Self-timed programming cycle
- Automatic erase-before-write
- Programming status indicator
- Word and chip erasable
- Stop SK anytime for power savings
• Durability and reliability
- 40 years data retention
- Minimum of 1M write cycles per word
- Unlimited read cycles
The AM93LC56 is available in space-saving 8-lead
PDIP, 8-lead SOP and rotated 8-lead SOP package.
- ESD protection
ꢀ Pin Assignments
ꢀ Connection Diagram
Name
CS
Description
Chip Select
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
CS
SK
DI
1
2
3
VCC
NC
1
2
3
ORG
GND
DO
8
8
DI
VCC
7
6
NC
7
6
DO
GND
VCC
NC
ORG
GND
CS
SK
Power Supply
DO
4
5
4
5
DI
No Connection
Internal Organization
ORG
PDIP-8L / SOP-8L
Rotated SOP-8L
ꢀ Ordering Information
X
AM 93 L C 56 X XX
Operating Voltage
LC : 2.7~5.5V,CMOS
Type
56: 2K
Temp. grade
o
Package
: SOP-8L
Packing
o
0 C ~ +70 C
S
Blank : Tube
Blank :
o
o
I
:
:
− 40 C ~ +85 C
A
: Taping
GS8: SOP-8L,G type
o
o
V
N : PDIP-8L
− 40 C ~ +125 C
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev.A1 Oct 20, 2003
1/10
ATC
2048-bits Serial Electrically Erasable PROM
AM93LC56
ꢀ Block Diagrams
DUMMY BIT
R/W AMPS
DO
DATA
REGISTER
INSTRUCTION
REGISTER
DI
(10 BITS)
DECODER
ADDRESS
INSTRUCTION
REGISTER
DECODE
EEPROM
ARRAY
(128 X 16)
OR
CONTROL
CS
AND
CLOCK
GENERATION
(256 X 8)
VCC RANGE
DETECTOR
SK
HIGH VOLTAGE
GENERATOR
WRITE ENABLE
ORG
ꢀ Absolute Maximum Ratings
Characteristics
Symbol
Values
-65 to + 125
-0.3 to + 6.5
Unit
°C
V
Storage Temperature
TS
Voltage with Respect to Ground
NOTE:These are STRESS rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage the
part. Prolonged exposure to maximum ratings may affect device reliability.
ꢀ Operating Conditions
Temperature under bias
Values
Unit
AM93LC56
AM93LC56I
AM93LC56V
0 to + 70
-40 to + 85
-40 to +125
°C
°C
°C
o
ꢀ DC Electrical Characteristics (Vcc =2.7~5.5V, Ta = 25 C , unless otherwise noted)
Parameter
Symbol
Conditions
Min
Max
Units
Operating current**
Standby current
Input leakage
ICC
ISB
IIL
CS=VIH, SK=1MHz CMOS input levels
CS=DI=SK=0V
3
mA
µA
µA
µA
10
VIN = 0V to VCC(CS,SK,DI)
VOUT = 0V to VCC, CS=0V
VCC = 3V + 10%
-1
-1
1
1
Output leakage
IOL
-0.1
-0.1
0.15 VCC
0.8
Input low voltage**
VIL
V
V
CC = 5V + 10%
VCC = 3V + 10%
CC = 5V + 10%
0.8 VCC VCC +0.2
Input high voltage**
VIH
V
V
2
VCC +0.2
0.4
Output low voltage
Output high voltage
Output low voltage
Output high voltage
VOL1
VOH1
IOL = 2.1mA TTL, VCC=5V + 10%
IOH = -400uA TTL, VCC=5V + 10%
IOL = 10uA CMOS
V
V
V
V
2.4
0.2
VOL2
I
OH = -10uA CMOS
VCC -0.2
Note **: ICC , VIL min and VIH max are for reference only and are not tested
Anachip Corp.
www.anachip.com.tw
2/10
Rev. A1 Oct 20, 2003
ATC
2048-bits Serial Electrically Erasable PROM
AM93LC56
o
(Vcc = 2.7V ~ 5.5V, Ta = 25 C , unless otherwise noted)
ꢀ AC Electrical Characteristics
AM93LC56
Parameter
Symbol
Conditions
Units
Min
0
Max
SK Clock Frequency
SK High Time
FSK
TSKH
TSKL
1
MHz
250
250
250
50
ns
SK Low Time
ns
Minimum CS Low Time
CS Setup Time
TCS
ns
TCSS
TDIS
Relative to SK
Relative to SK
Relative to SK
Relative to SK
AC Test
AC Test
AC Test CL = 100pF
CS = VIL
ns
DI Setup Time
100
0
ns
CS Hold Time
TcSH
ns
DI Hold Time
TDIH
100
ns
Output Delay to "1"
Output Delay to "0"
CS to Status Valid
CS to DO in 3-state
Write Cycle Time
5V, 25ºC, Page Mode
TpD1
500
500
500
100
10
ns
TpD0
ns
TSV
ns
ns
TdF
TwP
ms
Endurance**
1M
write cycles
Note** : The parameter is characterized and isn’t 100% tested.
1.247V
(1 TTL Gate Load)
632 ohm
DO
100PF
FIGURE 1. AC TEST CONDITIONS
ꢀ Instruction Set
Address
Input Data
× 8 × 16
Start
Bit
OP
Instruction
Code
× 8
× 16
READ
WEN (Write Enable)
WRITE
1
1
1
1
1
1
1
10
00
01
00
00
11
00
A7 - A0
A6 - A0
11 XXXXXX
A7 - A0
11XXXXX
A6 - A0
D7 – D0 D15 - D0
D7 – D0 D15 - D0
WRALL (Write All Registers)
WDS (Write Disable)
ERASE
01XXXXXX
00 XXXXXX
A7 - A0
01XXXXX
00XXXXX
A6 - A0
ERAL (Erase All Registers)
10 XXXXXX
10XXXXX
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
3/10
ATC
2048-bits Serial Electrically Erasable PROM
AM93LC56
(Ta=25°C , f=1MHz )
ꢀ Pin Capacitance **
Symbol
COUT
Parameter
Max
5
Units
pF
Output capacitance
Input capacitance
CIN
5
pF
Note ** : The parameter is characterized and isn’t 100% tested.
ꢀ Functional Descriptions
addressed word have been clocked out, the data in
consecutively higher address locations is output.
The address will wrap around continuously with CS
high until the chip select (CS) control pin is brought
low. This allows for single instruction data dumps to
be executed with a minimum of firmware overhead.
Applications
The AM93LC56 is ideal for high volume applications
requiring low power and low density storage. This
device uses a low cost, space saving 8-pin package.
Typical applications include robotics, alarm devices,
electronic locks, meters and instrumentation settings
such as LAN cards, monitors and MODEM.
Write Enable (WEN)
Before any device programming (WRITE, WRALL,
ERASE, and ERAL) can be done, the WRITE
ENABLE (WEN) instruction must be executed first.
When Vcc is applied, this device powers up in the
WRITE DISABLE state. The device then remains in
a WRITE DISABLE state until a WEN instruction is
executed. Thereafter the device remains enabled
until a WDS instruction is executed or until Vcc is
removed. (NOTE: Neither the WEN nor the WDS
instruction has any effect on the READ instruction.)
(Shown in Figure 4.)
Endurance and Data Retention
The AM93LC56 is designed for applications
requiring up to 1M programming cycles (WRITE,
WRALL, EARSE and ERALL). It provides 40 years
of secure data retention.
Device Operation
The AM93LC56 is controlled by seven 10-bit
instructions. Instructions are clocked in (serially) on
the DI pin. Each instruction begins with a logical "1"
(the start bit). This is followed by the opcode (2 bits),
the address field (7 bits), and data, if appropriate.
The clock signal (SK) may be halted at any time and
the AM93LC56 will remain in its last state. This
allows full static flexibility and maximum power
conservation.
Write Disable (WDS)
The WRITE DISABLE (WDS) instruction disables all
programming capabilities. This protects the entire
part against accidental modification of data until a
WEN instruction is executed. (When Vcc is applied,
this part powers up in the WRITE DISABLE state.)
To protect data, a WDS instruction should be
executed upon completion of each programming
operation. (NOTE: Neither the WEN nor the WDS
instruction has any effect on the READ instruction.)
(Shown in Figure 5.)
Read (READ)
The READ instruction is the only instruction that
outputs serial data on the DO pin. After the read
instruction and address have been decoded, data is
transferred from the selected memory register into a
8-bit or 16-bit serial shift register. (Please note that
one logical "0" bit precedes the actual 8-bit or 16-bit
output data string.) The output on DO changes
during the rising edge transitions of SK. (Shown in
Figure 3.)
Auto Increment Read Operations
Sequential read is possible, since the AM93LC56
has been designed to output a continuous stream of
memory content in response to a single read
operation instruction. To utilize this function, the
system asserts a read instruction specifying a start
location address. Once the 8-bit or 16-bit of the
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
4/10
ATC
2048-bits Serial Electrically Erasable PROM
AM93LC56
ꢀ Functional Description (Continued)
HIGH after a minimum wait of 250ns (tcs), the DO
pin indicates the READY/BUSY status of the chip.
(Shown in Figure 7.)
Write (WRITE)
The WRITE instruction includes 8-bit or 16-bit of
data to be written into the specified register. After
the last data bit has been applied to DI, and before
the next rising edge of SK, CS must be brought
LOW. The falling edge of CS initiates the self-timed
programming cycle.
Erase (ERASE)
After the erase instruction is entered, CS must be
brought LOW. The falling edge of CS initiates the
self-timed internal programming cycle. Bringing CS
HIGH after minimum of tcs, will cause DO to indicate
the READ/BUSY status of the chip. To explain this,
a logical "0" indicates the programming is still in
progress while a logical "1" indicates the erase cycle
is complete and the part is ready for another
instruction. (Shown in Figure 8.)
After a minimum wait of 250ns (5V operation) from
the falling edge of CS (tcs), DO will indicate the
READY/BUSY status of the chip if CS is brought
HIGH. This means that logical "0" implies the
programming is still in progress while logical "1"
indicates the selected register has been written, and
the part is ready for another instruction. (See Figure
6)
Erase All (ERALL)
Full chip erase is provided for ease of programming.
Erasing the entire chip involves setting all bits in the
entire memory array to a logical "1". (Shown in
Figure 9.)
Note: The combination of CS HIGH, DI HIGH and the rising edge
of the SK clock, resets the READY/BUSY flag. Therefore, it is
important if you want to access the READY/BUSY flag, not to
reset it through this combination of control signals.
Security Consideration
Before a WRITE instruction can be executed, the
device must be in the WRITE ENABLE (WEN) state.
To protect the entire part against accidental
modification of data, each programming instruction
(WRITE, WRALL, ERASE, and ERALL) must satisfy
two conditions before user initiate self-timed
programming cycle (the falling edge of CS). One is
that the AM93LC56 is at WEN status. The other is
that the Vcc value must exceed a lock-out value
which can be adjusted by ANALOG TECHNOLOGY
INC.
Write All (WRALL)
The Write All (WRALL) instruction programs all
registers with the data pattern specified in the
instruction. While the WRALL instruction is being
loaded, the address field becomes a sequence of
DON'T-CARE bits. (Shown in Figure 7.)
As with the WRITE instruction, if CS is brought
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
5/10
ATC
2048-bits Serial Electrically Erasable PROM
AM93LC56
ꢀ Timing Diagram (1)
T
CS
tSKH
tSKL
tCSS
tCSH
SK
DI
tDIS
tDIH
tPD1
tDF
tPDO
DO(READ)
tSV
tDF
STATUS VALID
DO(WRITE)
(WRALL)
(ERASE)
(ERALL)
FIGURE 2. SYNCHRONOUS DATA TIMING
tCS
CS
SK
+
AN
AO
O
0
1
1
DI
TRI-STATE
*
DO
DN
DO
+For all instructions, SK cycles before start bit don't care.
*Address Pointer Cycle to the Next Register.
FIGURE 3. DATA READ CYCLE TIMING
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
6/10
ATC
2048-bits Serial Electrically Erasable PROM
AM93LC56
ꢀ Timing Diagram (2)
tCS
CS
SK
**
X- - - - - - - - - - - X
1
0
0
1
1
DI
DO = TRI-STATE
**AN-2~A0 don't care.
FIGURE 4. WRITE ENABLE(WEN) CYCLE TIMING
tCS
CS
SK
**
X- - - - -- - - - X
1
0
0
0
0
DI
DO = TRI-STATE
**AN-2~A0 don't care.
FIGURE 5. WRITE DISABLE(WDS) CYCLE TIMING
tCS
CS
SK
AN
AO
DN
DO
0
1
1
DI
tSV
tDF
TRI-STATE
BUSY
DO
READY
tWP
FIGURE 6. WRITE(WRITE) CYCLE TIMING
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
7/10
ATC
2048-bits Serial Electrically Erasable PROM
AM93LC56
ꢀ Timing Diagram (3)
tCS
CS
SK
**
DN
X- - - - - - - - - - - -X
DO
1
1
0
0
0
DI
tSV
TRI-STATE
READY
BUSY
DO
**AN-2~A0 don't care.
tWP
FIGURE 7. WRITE ALL(WRALL) CYCLE TIMING
tCS
CS
SK
AN
AO
1
1
1
DI
tSV
tDF
TRI-STATE
READY
DO
BUSY
tWP
FIGURE 8. ERASE(ERASE) CYCLE TIMING
tCS
CS
SK
DI
**
1
0
0
1
0
X- - - - - - - - - X
tSV
tDF
TRI-STATE
READY
BUSY
DO
tWP
**AN-2~A0 don't care.
FIGURE 9. ERASE ALL(ERALL) CYCLE TIMING
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
8/10
ATC
2048-bits Serial Electrically Erasable PROM
AM93LC56
ꢀ Package Diagrams
(1) Plastic Dual-in-line Package: PDIP-8L
D
E-PIN O0.118 inch
E
(4X)
15
PIN #1 INDENT O0.025 DEEP 0.006-0.008 inch
C
7
(4X)
eB
B
B1
e
S
B2
Dimensions in millimeters
Dimensions in inches
Symbol
Min.
-
Nom.
-
Max.
5.33
-
Min.
Nom.
-
Max.
A
A1
A2
B
B1
B2
C
D
E
E1
e
L
-
0.210
-
0.38
3.1
0.36
1.4
0.81
0.20
9.02
7.62
6.15
-
2.92
8.38
0.71
-
0.015
0.122
0.014
0.055
0.032
0.008
0.355
0.300
0.242
-
-
3.30
0.46
1.52
0.99
0.25
9.27
7.94
6.35
2.54
3.3
3.5
0.130
0.018
0.060
0.039
0.010
0.365
0.313
0.250
0.100
0.130
0.350
0.033
0.138
0.022
0.065
0.045
0.014
0.375
0.325
0.258
-
0.56
1.65
1.14
0.36
9.53
8.26
6.55
-
3.81
9.40
0.97
0.115
0.330
0.028
0.150
0.370
0.038
eB
S
8.89
0.84
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
9/10
ATC
2048-bits Serial Electrically Erasable PROM
AM93LC56
(2) JEDEC Small Outline Package: SOP-8L
L
VIEW "A"
D
0.015x45
(4X)
e
(4X)
7
7
B
VIEW "A"
y
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min.
1.40
0.10
1.30
0.33
0.19
4.80
3.70
-
Nom.
1.60
-
Max.
1.75
0.25
1.50
0.51
0.25
5.30
4.10
-
6.20
1.27
0.10
8O
Min.
Nom.
0.063
-
Max.
0.069
A
A1
A2
B
C
D
E
e
H
L
0.055
0.040
0.051
0.013
0.0075
0.189
0.146
-
0.100
0.059
0.020
0.010
0.209
0.161
-
0.244
0.050
0.004
8O
1.45
0.41
0.20
5.05
3.90
1.27
5.99
0.71
-
0.057
0.016
0.008
0.199
0.154
0.050
0.236
0.028
-
5.79
0.38
-
0.228
0.015
-
y
θ
0O
-
0O
-
ꢀ Marking Information
Top view
Part Number (X:ID Code)
ATC
Logo
Blank : PDIP-8L & SOP-8L (Commercial)
I : PDIP-8L & SOP-8L (Industrial)
93LC56X
YYWW X
Date & ID Code
YY : Year
V : PDIP-8L & SOP-8L (Automotive)
G : Rotated SOP-8L
B : Rotated SOP-8L
D : Rotated SOP-8L
(Commercial)
(Industrial)
WW : Week
X: Internal
(Automotive)
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
10/10
相关型号：
©2020 ICPDF网 联系我们和版权申明