ALT6725Q7_技术文档

ALT6725

HELP3E^TMDual-band Cellular & PCS LTE

3.4 V Linear Power Ampliﬁer Module

PRELIMINARY DATA SHEET - Rev 1.0

FEATURES

is designed for use both with and without average

power tracking (APT). APT can be used to optimize

the Vcc level for the desired output power level and

linearity, which greatly reduces the total current

drawn from the battery. This feature, in conjunction

with selectable operating modes, enables signiﬁcant

improvements in overall power added efﬁciency of the

ALT6725 across the entire dynamic range of operating

powers. APT requires use of an external variable

voltage supply (DC-DC converter), which is used to

provide the variable voltage to Vcc pad of the ampliﬁer.

A low-leakage shutdown mode increases standby

time. This PAhas built-in directional couplers for each

band, with a common coupler output port CPL_OUT.

The 3 mm x 5 mm x 0.9 mm surface mount package

incorporates matching networks optimized for output

power, efﬁciency and linearity in a 50 Ω system. The

device is manufactured on an advanced InGaP HBT

MMIC technology offering state-of-the-art reliability,

temperature stability, and ruggedness.

•

InGaP HBT Technology

•

High Efﬁciency:

•

35 % @ P^OUT= +27.5 dBm

16 % @ P^OUT= +15 dBm

8 % @ P^OUT= +9 dBm

•

Low Quiescent Current: 4 mA

Internal Voltage Regulation

Built-in Directional Coupler

Common V^MODEControl Line

Suitable for SMPS and average power tracking

systems with variable supply voltages

•

APT can reduce TS.09 average power

consumption more than 25%

•

Reduced External Component Count

Thin Package: 0.9 mm

RoHS Compliant Package, 260 ^oC MSL-3

APPLICATIONS

•

Dual-band Wireless Handsets and Data Devices

for LTE/CDMA/EVDO networks:

V

EN_CELL

1

2

14

13

12

11

10

9

GND

•

UMTS Band 5, 6, 18, 19, & 26

UMTS Band 2 & 25

Bias Control

Voltage Regulation

Cellular BC 0 and 10

PCS BC 1 and 14

RFIN_CELL

CPL

RFOUT_CELL

V

MODE1

3

4

5

V

CC

PRODUCT DESCRIPTION

ALT6725 addresses the demand for increased

integration in dual-band handsets for LTE networks.

The small footprint 3 mm x 5 mm x 0.9 mm surface

mount RoHS compliant package contains independent

RF PA paths to ensure optimal performance in both

frequency bands in less board area than two single

band PAs. The package pinout was chosen to enable

handset manufacturers to independently provide

bias to both power ampliﬁers and simplify control

with common mode pins. The ALT6725 is part of

ANADIGICS’ 3rd generation of High-Efﬁciency-at-

Low-Power (HELP3E™) family of power ampliﬁers,

which deliver low quiescent currents and signiﬁcantly

greater efﬁciency through selectable bias modes for

high, medium and low power operation. TheALT6725

VBATT

V

A

V

MODE2

CPLOUT

GND

RFIN_PCS

CPL

6

7

Bias Control

Voltage Regulation

V

EN_PCS

8

RFOUT_PCS

GND at Slug (pad)

Figure 1: Block Diagram

07/2012

ALT6725

VMODE1

CPLOUT

VMODE2

Figure 2: Pinout

Table 1: Pin Description

NAME

DESCRIPTION

1

2

V^EN_CELL

RF^IN_CELL

V^MODE1

V^BATT

Enable Voltage for Cell Band

RF Input for Cell Band

Mode Control Voltage 1

Battery Voltage

3

4

5

V^MODE2

RF^IN_PCS

V^EN_PCS

Mode Control Voltage 2

RF Input for PCS Band

6

7

Enable Voltage for PCS Band

8

RF^OUT_PCSRF Output for PCS Band

9

GND

CPL^OUT

V^CCA

V^CC

Ground

10

11

12

13

14

Coupler Output Port

Supply Voltage A

Supply Voltage

RF^OUT_CELLRF Output for Cell Band

GND Ground

PRELIMINARY DATA SHEET - Rev 1.0

2

07/2012

ALT6725

ELECTRICAL CHARACTERISTICS

Table 2: Absolute Minimum and Maximum Ratings

PARAMETER

MIN

0

MAX

+5

UNIT

V

Supply Voltage (V^BATT, VCC, VCCA)

Mode Control Voltage (V^MODE1,2, VEN)

RF Input Power (P^IN)

0

+3.5

+10

+150

V

-

dBm

°C

Storage Temperature (T^STG)

-40

Stresses in excess of the absolute ratings may cause permanent damage.

Functional operation is not implied under these conditions. Exposure

to absolute ratings for extended periods of time may adversely affect

reliability.

Table 3: Operating Ranges

PARAMETER

MIN

TYP

MAX UNITS

COMMENTS

UMTS Band 5, 6, 18, 19, & 26

UMTS Band 2 & 25

814

1850

-

849

MHz

1915

Operating Frequency (f)

Supply Voltage (VCC, VCCA)

Battery Voltage (V^BATT)

+0.8

+3.4 +4.35

V

+3.2

+1.35

0

+1.8

0

+3.1

+0.5

PA “on”

PA “shut down”

Enable Voltage (V^EN_CELL, VEN_PCS)

Mode Control Voltage (VMODE1,2)

V

+1.35

0

+1.8

0

+3.1

+0.5

Logic High

Logic Low

Cellular RF Output Power UMTS

LTE, HPM

LTE, MPM

26.7 ⁽¹⁾

27.5

15

9

-

dBm

TS 36.101 Rel 8 for LTE

CDMA 2000, RC-1

LTE, LPM

Cellular RF Output Power CDMA

CDMA, HPM

CDMA, MPM

27.5 ⁽¹⁾

28.0

16.0

10.0

-

CDMA, LPM

PCS RF Output Power UMTS

LTE, HPM

LTE, MPM

26.5 ⁽¹⁾

27.3

15

9

-

TS 36.101 Rel 8 for LTE

CDMA 2000, RC-1

LTE, LPM

PCS RF Output Power CDMA

CDMA, HPM

CDMA, MPM

27.5 ⁽¹⁾

28.0

16.0

10.0

-

dBm

CDMA, LPM

Case Temperature (T^C)

-30

-

+90

°C

The device may be operated safely over these conditions; however, parametric performance is guaranteed only

over the conditions deﬁned in the electrical speciﬁcations.

Notes:

(1) For operation at V^CC= +3.2 V, POUT is derated by 0.5 dB.

PRELIMINARY DATA SHEET - Rev 1.0

3

07/2012

ALT6725

Table 4: Electrical Speciﬁcations – LTE Operation (Band 5, 6, 18, 19 & 26)

(10 MHz QPSK, 12 RB, START = 0) (TC = +25 °C, VBATT = VCC = +3.4 V, VEN = +1.8 V, 50 Ω system)

COMMENTS

PARAMETER

MIN

TYP

MAX

UNIT

POUT

VMODE1

VMODE2

-

28

17

12

-

+27.5 dBm 0 V

0 V

1.8 V

Gain

dB

+15 dBm

+9 dBm

1.8 V

-

-39.5

-42

-

+27.5 dBm 0 V

0 V

1.8 V

ACLR E-UTRA at ± 10 MHz offset

ACLR UTRA at ± 7.5 MHz offset

ACLR UTRA at ± 12.5 MHz offset

Power-Added Efﬁciency ⁽¹⁾

dBc

+15 dBm

+9 dBm

1.8 V

-

-40

-42

-

+27.5 dBm 0 V

0 V

1.8 V

+15 dBm

+9 dBm

1.8 V

-

-62

-58

-

+27.5 dBm 0 V

0 V

1.8 V

+15 dBm

+9 dBm

1.8 V

-

35

16

8

-

+27.5 dBm 0 V

0 V

1.8 V

%

+15 dBm

+9 dBm

1.8 V

Quiescent Current (Icq)

Low Bias Mode

through V^CC

-

4

-

mA

1.8 V

Mode Control Current

BATT Current

-

0.5

1.5

0.3

-

mA

through V^MODEpins, VMODE1,2 = +1.8 V

through V^BATT, VMODE1,2 = +1.8V

Enable Current

through V^EN_CELLpin, VMODE1,2 = +1.8 V

Total Decoder Current on

V^BATT(in Shutdown mode)

VBATT = +4.35 V, VCC = +4.35 V,

VEN_CELL = 0 V, VMODE1,2 = 0 V

-

7

-

µA

HBT Leakage Current (V^CC)

(Shutdown mode)

VBATT = +4.35 V, VCC = +4.35 V,

VEN_CELL = 0 V, VMODE1,2 = 0 V

-

<1

-

mA

Noise In Receive Band

-133

dBm/Hz 869 MHz to 894 MHz

Harmonics

2f^O

3fO, 4fO

-

-35

dBc

POUT < +27.5 dBm

Input Impedence

Coupling Factor

-

2:1

VSWR

dB

22

-

POUT < +27.5 dBm

Spurious Output Level

(all spurious outputs)

In-band load VSWR < 5:1

Out-of-band load VSWR < 10:1

Applies over all operating conditions

-

-65

-

dBc

Load mismatch stress with no

permanent degradation or failure

8:1

VSWR Applies over full operating range

Notes:

(1) ACLR and Efﬁciency measured at 836.5 MHz.

PRELIMINARY DATA SHEET - Rev 1.0

4

07/2012

ALT6725

Table 5: Electrical Speciﬁcations - Cellular Band (BC 0, 10)

(TC

= +25 °C, VBATT = VCC = +3.4 V, VEN_CELL = +1.8 V, 50 Ω system, CDMA2000 RC-1 waveform)

COMMENTS

PARAMETER

MIN

TYP

MAX

UNIT

POUT

VMODE1

VMODE2

-

28

17

12

-

+28 dBm

+16 dBm

+10 dBm

0 V

1.8 V

0 V

Gain

dB

0 V

1.8 V

Adjacent Channel Power

at 1.2ꢀ ꢁMH oꢂꢂset ⁽¹⁾

-

-48.ꢀ

-ꢀ2

-ꢀ3.ꢀ

+28 dBm

+16 dBm

+10 dBm

0 V

1.8 V

0 V

-

Primary Channel BW = 1.23 ꢁMH

Adjacent Channel BW = 30 kMH

dBc

0 V

1.8 V

Adjacent Channel Power

at 1.ꢃ8 ꢁMH oꢂꢂset ⁽¹⁾

-

-ꢀ8

-ꢀꢃ

-68

-

+28 dBm

+16 dBm

+10 dBm

0 V

1.8 V

0 V

Primary Channel BW = 1.23 ꢁMH

Adjacent Channel BW = 30 kMH

dBc

0 V

1.8 V

-

37.5

19.5

10

-

+28 dBm

+16 dBm

+10 dBm

0 V

1.8 V

0 V

(1)

%

0 V

1.8 V

Quiescent Current (Icq)

Mode Control Current

BATT Current

-

4

-

mA

through V^CCpins, VMODE1,2 = +1.8 V

through VMODE pin, VMODE1,2 = +1.8 V

through V^BATTpin, VMODE1,2 = +1.8V

through V^EN_CELLpin, VMODE1,2 = +1.8 V

0.5

1.5

0.3

Enable Current

Total Decoder Current on

V^BATT(in Shutdown mode)

VBATT = +4.35 V, VCC = +4.35 V,

V^EN_CELL= 0 V, V^MODE1,2= 0 V

-

7

-

µA

HBT Leakage Current (V^CC)

(Shutdown mode)

VBATT = +4.35 V, VCC = +4.35 V,

V^EN_CELL= 0 V, VMODE1,2 = 0 V

-

<1

-

µA

Noise In Receive Band

-133

dBm/Hz 869 MHz to 894 MHz

Harmonics

2f^O

3fO, 4fO

-

-35

dBc

POUT < +28 dBm

-

Input Impedence

Coupling Factor

-

2:5:1

22

VSWR

dB

POUT < +28 dBm

Spurious Output Level

(all spurious outputs)

In-band load VSWR < 5:1

Out-of-band load VSWR < 10:1

Applies over all operating conditions

-

-65

-

dBc

Load mismatch stress with no

permanent degradation or failure

8:1

VSWR Applies over full operating range

Notes:

(1) PAE and ACP measured at 836.5 MHz.

PRELIMINARY DATA SHEET - Rev 1.0

5

07/2012

ALT6725

Table 6: Electrical Speciﬁcations – LTE Operation (Band 2 & 25) (10 MHz QPSK, 12 RB, START = 0)

(TC = +25 °C, VBATT = VCC = +3.4 V, VEN = +1.8 V, 50 Ω system)

COMMENTS

PARAMETER

MIN

TYP

MAX

UNIT

POUT

VMODE1

VMODE2

-

27

13

9

-

+27.3 dBm 0 V

0 V

1.8 V

Gain

dB

+15 dBm

+9 dBm

1.8 V

-

-37.5

-41

-40

-

+27.3 dBm 0 V

0 V

1.8 V

ACLR E-UTRA at ± 10 MHz offset

ACLR UTRA at ± 7.5 MHz offset

ACLR UTRA at ± 12.5 MHz offset

Power-Added Efﬁciency ⁽¹⁾

dBc

+15 dBm

+9 dBm

1.8 V

-

-38

-41

-

+27.3 dBm 0 V

0 V

1.8 V

+15 dBm

+9 dBm

1.8 V

-

-63

-64

-

+27.3 dBm 0 V

0 V

1.8 V

+15 dBm

+9 dBm

1.8 V

-

34

17

8

-

+27.3 dBm 0 V

0 V

1.8 V

%

+15 dBm

+9 dBm

1.8 V

Quiescent Current (Icq)

Low Bias Mode

through V^CC

-

4

-

mA

1.8 V

Mode Control Current

BATT Current

-

0.5

1.5

0.3

-

mA

through V^MODEpins, VMODE1,2 = +1.8 V

through V^BATT, VMODE1,2 = +1.8 V

through V^EN_PCS, VMODE1,2 = +1.8 V

Enable Current

Total Decoder Current on

V^BATT(in Shutdown mode)

VBATT = +4.35 V, VCC = +4.35 V,

VEN_CELL = 0 V, VMODE1,2 = 0 V

-

7

-

µA

HBT Leakage Current (V^CC)

(Shutdown mode)

VBATT = +4.35 V, VCC = +4.35 V,

VEN_CELL = 0 V, VMODE1,2 = 0 V

-

<1

-

mA

Noise in Receive Band

-133

dBm/Hz 1930 MHz to 1990 MHz

Harmonics

2f^O

3fO, 4fO

-

-30

dBc

POUT < +27.3 dBm

Input Impedence

Coupling Factor

-

2:1

VSWR

dB

22

-

POUT < +27.3 dBm

Spurious Output Level

(all spurious outputs)

In-band load VSWR < 5:1

Out-of-band load VSWR < 10:1

Applies over all operating conditions

-

-65

-

dBc

Load mismatch stress with no

permanent degradation or failure

8:1

VSWR Applies over full operating range

Notes:

(1) ACLR and Efﬁciency measured at 1880 MHz.

PRELIMINARY DATA SHEET - Rev 1.0

6

07/2012

ALT6725

Table 7: Electrical Speciﬁcations - PCS Band (BC 1, 14)

(TC

= +25 °C, VBATT = VCC = +3.4 V, VEN_PCS = +1.8 V, 50 Ω system, CDMA2000 RC-1 waveform)

COMMENTS

PARAMETER

MIN

TYP

MAX

UNIT

POUT

VMODE1

VMODE2

-

27

13

9

-

+28 dBm

+16 dBm

+10 dBm

0 V

1.8 V

0 V

1.8 V

Gain

dB

Adjacent Channel Power

at ± 1.25 MHz offset ⁽¹⁾

Primary Channel BW = 1.23 MHz

Adjacent Channel BW = 30 kHz

-

-48

-52.5

-53

-

+28 dBm

+16 dBm

+10 dBm

0 V

1.8 V

0 V

1.8 V

dBc

Adjacent Channel Power

at ± 1.98 MHz offset ⁽¹⁾

Primary Channel BW = 1.23 MHz

Adjacent Channel BW = 30 kHz

-

-55

-60

-63

-

+28 dBm

+16 dBm

+10 dBm

0 V

1.8 V

0 V

1.8 V

dBc

-

37

20

10

-

+28 dBm

+16 dBm

+10 dBm

0 V

1.8 V

0 V

1.8 V

Power-Added Efﬁciency ⁽¹⁾

%

Quiescent Current (Icq)

Mode Control Current

BATT Current

-

4

-

mA

through V^CCpins, VMODE1,2 = +1.8 V

through VMODE pin, VMODE1,2 = +1.8 V

through V^BATTpin, VMODE1,2 = +1.8V

through V^EN_PCSpin, VMODE1,2 = +1.8 V

0.5

1.5

0.3

Enable Current

Total Decoder Current on VBATT

(in Shutdown mode)

VBATT = +4.35 V, VCC = +4.35 V,

V^EN_CELL= 0 V, VMODE1,2 = 0 V

-

7

-

µA

HBT Leakage Current on V^CC

(in Shutdown mode)

VBATT = +4.35 V, VCC = +4.35 V,

V^EN_CELL= 0 V, VMODE1,2 = 0 V

-

<1

-

Noise In Receive Band

-133

dBm/Hz 1930 MHz to 1990 MHz

Harmonics

2f^O

3fO, 4fO

-

-30

dBc

POUT < +28 dBm

Input Impedence

Coupling Factor

-

2:1

VSWR

dB

22

-

POUT < +28 dBm

Spurious Output Level

(all spurious outputs)

In-band load VSWR < 5:1

Out-of-band load VSWR < 10:1

Applies over all operating conditions

-

-65

-

dBc

Load mismatch stress with no

permanent degradation or failure

8:1

VSWR Applies over full operating range

Notes:

(1) ACPRs and Efﬁciency measured at 1880 MHz.

PRELIMINARY DATA SHEET - Rev 1.0

7

07/2012

ALT6725

APPLICATION INFORMATION

mode by applying logic low levels (see Operating

Ranges table) to the V^ENABLEand VMODE pads.

To ensure proper performance, refer to all related

Application Notes on the ANADIGICS web site: http://

www.anadigics.com along with Figure 3, which shows

the recommended ON/OFF timing sequence for RFIN,

control voltages, and supply voltages.

Bias Modes

The power ampliﬁer may be placed in Low, Medium,

or High Bias modes by applying the appropriate logic

level (see Operating Ranges table) to the V^MODEpin.

The Bias Control table lists the recommended modes

of operation for various applications.

Shutdown Mode

The power ampliﬁer may be placed in a shutdown

Vcontrols

Venable/Vmode(s)

Rise/Fall Max 1µS

Defined at 10% to 90%

of Min/Max Voltage

On Sequence Start

T_0N=0µ

Off Sequence Start

T_0FF=0µ

ON Sequence

OFF Sequence

RFIN_CELL, PCS

notes 1,2

VEN_CELL, PCS

VCC/VCCA

note 1

T_0N+1µS

T_0N+3µS

T_0FF+2µS T_0FF+3µS

Referenced After 90%of Rise

Time

Referenced Before10%of Fall

Time

Figure 3: Recommended ON/OFF Timing Sequence

Notes:

(1) Level might be changed after RF is ON.

(2) RF OFF deﬁned as P^IN≤ -30 dBm.

(3) Switching simultaneously between VMODE and VEN is not recommended.

Table 8: Bias Control

P

OUT

BIAS

MODE

VEN_CELL

V

EN_PCS

APPLICATION

V

MODE1

V

MODE2

V

CC

V

BATT

LEVELS

< +9 dBm

Low

+1.8 V

+1.8

+1.8 V 0.8 - 4.35 V

> 3.2 V

Low Bias Mode

> +9 dBm

< +15 dBm

Medium Bias Mode

Medium

+1.8 V +1.8 V

0 V

0.8 - 4.35 V

> +15 dBm

-

High

+1.8 V

0 V

1.3 - 4.35 V

3.2 - 4.35 V

> 3.2 V

High Bias Mode

Shutdown

PRELIMINARY DATA SHEET - Rev 1.0

8

07/2012

ALT6725

V

EN_CELL

1

2

14

13

12

11

10

9

Bias Control

Voltage Regulation

RFIN_CELL

CPL

RFOUT_CELL

VMODE1

3

4

5

V

CC

1000 pF

68 pF

V

BATT

V

CCA

68pF

2.2 µF

V

MODE2

CPLOUT

RFIN_PCS

CPL

6

7

Bias Control

Voltage Regulation

VEN_PCS

8

RFOUT_PCS

GND at Slug (pad)

Figure 4: Application Circuit

PRELIMINARY DATA SHEET - Rev 1.0

9

07/2012

ALT6725

PACKAGE OUTLINE

Figure 5: Package Outline - 14 Pin 3 mm x 5 mm x 1 mm Surface Mount Module

Pin 1 Identifier

Part Number

Lot Number

6725

LLLLNN

Date Code

Country Code(CC)

YY= Year WW= Work Week

YYWWCC

Figure 6: Branding Speciﬁcation

PRELIMINARY DATA SHEET - Rev 1.0

10

07/2012

ALT6725

PCB BOARD DESIGN GUIDELINES

and the PCB-to-device interconnect pattern. The

PCB metal design recommendations primarily deal

with te PCB-to-device interconnection. Speciﬁc

board-level electrical and thermal performance re-

quirements will be dictated by the physical geometry

of the speciﬁc application and are the responsibility

of the end product manufacturer.

Refer to Figure 7 for the recommended PCB metal

design, soldermask design, and stencil print patterns

when assembling with ANADIGICS modules [5].

It is important to note that the PCB metal design is

dependent upon several factors: the electrical and

thermal performance requirements of the product,

Figure 7: PCB Board Design Guidelines

PRELIMINARY DATA SHEET - Rev 1.0

11

07/2012

ALT6725

Figure 8: Carrier Tape Drawing

Ø50.8

0.2

Ø177.8

MIN.

Ø54.2

0.1

MADE IN USA

(2X)SLOT 3.0 .1

12.4

.

(3X)1.78 .25

Ø13.0 0.2

DIMENSIONS ARE IN MILLIMETERS

Ø20.6 0.13

CENTER HOLE DETAIL

ENLARGED FOR CLARITY

NOTES:

MATERIAL:

BLACK CARBON POLYSTYRENE

1X10⁴TO 1X10⁵ohms/square

1.

SURFACE RESISTIVITY:

DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994

Figure 9: Reel Drawing

PRELIMINARY DATA SHEET - Rev 1.0

12

07/2012

ALT6725

ORDERING INFORMATION

TEMPERATURE

RANGE

PACKAGE

DESCRIPTION

ORDER NUMBER

COMPONENT PACKAGING

RoHS Compliant 14 Pin

-30 °C to +90 °C 3 mm x 5 mm x 0.9 mm Ta pe and Reel, 2500 pieces per Reel

Surface Mount Module

ALT6725Q7

RoHS Compliant 14 Pin

-30 °C to +90 °C 3 mm x 5 mm x 0.9 mm

Surface Mount Module

ALT6725P9

Partial Tape and Reel

anaDigiCS, iꢀc.

141 Mount Bethel Road

Warren, New Jersey 07059, U.S.A.

Tel: +1 (908) 668-5000

Fax: +1 (908) 668-5132

URL: http://www.anadigics.com

iMPOrTanT nOTiCE

ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice.

The product speciﬁcations contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to

change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed

to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers

to verify that the information they are using is current before placing orders.

warning

ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of anANADIGICS product

in any such application without written consent is prohibited.

PRELIMINARY DATA SHEET - Rev 1.0

13

07/2012


型号：	ALT6725Q7
厂家：	ANADIGICS, INC
描述：	HELP3E Dual-band Cellular & PCS LTE 3.4 V Linear Power Amplifier Module HELP3E双频蜂窝和PCS LTE 3.4 V线性功率放大器模块放大器功率放大器过程控制系统 PCS 蜂窝 LTE
文件：	总13页 (文件大小：881K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ALT6725Q7 [ANADIGICS]

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ALTADS3

ALTADS30VA001-T

ALTADS30VA002-T

ALTAIR04-900

ALTAIR04-900TR

ALTAIR05T-800

ALTAIR05T-800TR