AWT1921 [ANADIGICS]
Integrated High Power Amp 1610 MHz; 内建高功率放大器1610兆赫
| 型号： | AWT1921 |
| 厂家： | 
ANADIGICS, INC |
| 描述： | Integrated High Power Amp 1610 MHz |
| 文件： | 总12页 (文件大小：457K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AWT1921
Integrated High PowerAmp 1610 MHz
PRELIMINARY DATA SHEET - Rev 1.0
FEATURES
High Output Intercept Point
High Linearity
True Surface Mount Package
Internal Bias Circuit Requiring Nominal Input
Voltages + 10%
Low Cost
Off Chip Output Matching Circuit Allows
Application Optimization
PRODUCT DESCRIPTION
The AWT1921 is a four stage monolithic amplifier for
use in communication systems that require high gain
and output intercept point. The device has been
specifically designed for fixed satellite access
equipment and handset booster amplifier
applications.
S11
SSOP-28
28 Pin Wide Body w/ Heat Slug
Table 1: Pin Description
PIN
NAME
DESCRIPTION
1,14,1-
5,28,
slug
GND
AC and RF Ground
Pin 28
Pin 1
2
27
VGS1 & RFIN First Stage Gate terminal & RF Input
GND
VGS1/RFIN
VD1
GND
VDD
VREF
VD4
VD4
VD4
VDD
VD2
Positive Supply of Bias Circuit(+5V)
Second Stage drain supply (+9V
First Stage drain supply (+9V)
First and Second Stage Source ground
Third Stage drain supply (+9V)
Second Stage Gate Terminal
Bias control Pin (+5V)
VD2
4
GND
GND
GND
GND
VD3
VD3
VGS2
VSS
3
VD1
VD4
VD4
VD4
VD4
VD4
5,6,7,8
9,10
11
GND
VD3
VGS4
VGS4
GND
VGS3
VGS2
VREF
VSS
GND
26
Pin 14
Pin 15
12
Negative Supply for Bias Circuit (-5V)
Third Stage Gate terminal
Figure 1: Pin Layout
13
VGS3
VGS4
16,17
Fourth Stage Gate terminal
Fourth Stage drain supply (+9V) & RF
out
18-25
VD4
08/2001
AWT1921
ELECTRICAL CHARACTERISTICS
Table 2: Electrical Specifications(1)
(Pin with CDMA modulation, fo = 1610 1626.5 MHz, VDS1 = VDS2 = VDS3
= VDS4 = 9.0V,VSS = -5V,VREF=+5V,VDD=+5V, Tc=25C, 50 W System(2))
PARAMETER
MIN
TYP
MAX
UNIT
Frequency
1610
MHz
1626.5
Power Output
Power Added Efficiency
Gain(3)
35
-
36
25
30
dBm
%
27
dB
ACPR(3)
0.730 MHz
1.23 MHz
-
-
25
-28
100
dBc
dBc
Harmonics
2nd
3rd
4th
-
-
-
-45
-52
-45
Stability: - 60 dBc all spurious outputs
relative to desired signal
VSWR load, all
phase angles
-
-
3:1
Bias Supply Currents
ISS
IREF
IDD
-
-
-
15
5
15
mA
mA
Quiescent Currents
-
-
-
-
-
-
-
-
60
90
150
200
IDQ1
IDQ2
IDQ3
IDQ4
Input Return Loss
-
-
-
11
0.8
4.5
-
-
-
dB
dB
Gain Flatness(3) @ POUT = +35 dBm
(4)
Thermal Resistance
C/W
Notes:
1. As measured in ANADIGICS test fixture, see application section.
2. 50W Measurement system after off chip matching circuit, input terminated in 50W.
3. Measured at POUT= +35 dBm
4. Thermal Resistance for junction to bottom of slug
Tj −Tc
Θjc
(ID1 +ID2 +ID3 +ID4)VSUP −POUT
PRELIMINARY DATA SHEET - Rev 1.0
2
08/2001
AWT1921
Table 3: Absolute Max Ratings
PIN
2
NAME
VDD
MAX RATING
+7VDC
PIN
11
NAME MAX RATING
VREF
VSS
+7 VDC
-7 VDC
3
RFIN
+20 dBm
12
18,19,-
20,21,-
22,23,-
24,25
4,5
8,9
VD1
VD2
+10 VDC
VD3
+10 VDC
+10 VDC
Stresses in excess of the absolute ratings may cause permanent
damage. Functional operation is not implied under these conditions.
Exposure to absolute ratings for extended periods of time may
adversely affect reliability.
Operating Temperature: - 30 to + 85 °C
Storage Temperature: - 55 to +100 °C
PRELIMINARY DATA SHEET - Rev 1.0
3
08/2001
AWT1921
PERFORMANCE DATA
Figure 2: ACPR @ POUT = 35 dBm
Figure 3: ACPR @ POUT = 35 dBm
Figure 4: POUT & Eff vs Pin
Figure 5: POUT vs Supply Voltage
40
35
30
25
20
15
40
39
38
37
36
35
34
90
80
70
60
50
40
30
20
10
0
Pout
Eff
Pout
-15
-10
-5
0
5
10
15
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
Pin (dBm)
Vsup(v)
PIN = 10 dBm, with CDMA Modulation
* POUT with CDMA Modulation
PRELIMINARY DATA SHEET - Rev 1.0
4
08/2001
AWT1921
Figure 7: S11 Forward Reflection Impedance
Figure 6: S11 Forward Reflection Impedance
Impedance as seen by VDS1
Impedance as seen by VDS2
IMPEDANCE
1
CH 1 - S11
REFERENCE PLANE
6.3507 cm
1
- S11
CH 1
REFERENCE PLANE
6.3507 cm
2
2
3
.5
2
.5
2
MARKER 2
1.615750000 GHz
542.467 m
MARKER 2
1.615750000 GHz
4.443
4
34.621 j
86.992 j
.2
5
MARKER TO MAX
MARKER TO MIN
.2
5
MARKER TO MAX
MARKER TO MIN
1
1
3
0.100000000 GHz
45.066
1
0.100000000 GHz
46.485
-10.839 j
0
1
0
2
.2
1
.2
.5
1
2
5
5
8.658 j
.5
3.225500000 GHz
3
3.225500000 GHz
13.359
4
7.790
-31.442 j
112.368 j
4.800000000 GHz
6.663
16.669 j
-5
4
-.2
4.800000000 GHz
164.733
-244.870 j
-5
4
-.2
3
-.5
-2
-.5
-2
MARKER READOUT
FUNCTIONS
MARKER READOUT
FUNCTIONS
-1
-1
0.100000000 -
4.800000000 GHz
0.100000000 - 4.800000000 GHz
Figure 8: S11 Forward Reflection Impedance
Figure 9: S11 Forward Reflection Impedance
Impedance as seen by VDS4
Impedance as seen by VDS3
1
CH 1
- S11
REFERENCE PLANE
2
6.3507 cm
.5
MARKER 2
4
3
1.615750000 GHz
423.067 m
4.971 j
.2
2
5
MARKER TO MAX
MARKER TO MIN
1
3
4
0.100000000 GHz
46.696
1
1
.2
-381.126 jm
3.225500000 GHz
2.436
0
.5
2
5
18.889 j
4.800000000 GHz
2.544
-5
-.2
31.529 j
-.5
-2
MARKER READOUT
FUNCTIONS
-1
4.800000000 GHz
0.100000000 -
PRELIMINARY DATA SHEET - Rev 1.0
5
08/2001
AWT1921
F3
F2
C1
C4
C7
C3
AWT1921S11
F1
10
9
VD3
C10
C5
25
24
4
VD2
RFOUT
23
22
21
C11
3
2
VD1
RFIN/VGS1
RFIN
VD4
C19
C18
L5
20
5
6
7
8
GND
R5
19
18
C23
VGS2
VSS
VREF
V
13 VG3
26
27 DD
11
R4
C12
VD3
VD2
R2
12
C20
C21
VGS4
C17
16
C16
C15
GND
17
C13
F5
F4
R3
VD1
C14
VDD/VREF
VG4
VSS
C22
VD4
Figure 10: 1610 - 1626.5 MHz Test Circuit Schematic
Table 4: Pin Designations
GND
Procedure for Amplifier Operation and Test
1) Slug must be thermally and electrically connected
to obtain rated performance.
2) The VSS voltage should be applied first to the
amplifier prior to VD1, VD2, VD3, or VD4 voltages.
3) VGS1, VGS2, VGS3, VGS4 may be used as monitor points
to verify that the bias circuit is working properly. These
pins should measure as negative voltage potential,
after VSS is applied.
DESIGNATION
C1,C3,C5,C22
C2,C7,C9,C24
C4
VALUE
2.2
F
Not Used
15 pF
C6, C10
10 pF
C11,C19
27 pF
4) The Bias Pins VDD and VREF may be applied with no
VSS voltage present.
5) Always follow ESD precautions when handling
these devices.
C12,C13,C20,C21 33 pF
C14,C16,C17,C23 0.01 uF
C15
22 pF
4.7 pF
Feritte
Shim
2.7 nH
8 nH
C18
F1,F2,F3,F4,F5
L1,L3
L2
L4
L5
47 nH
5600
R2, R5
R3
1500
R4
2200
PRELIMINARY DATA SHEET - Rev 1.0
6
08/2001
AWT1921
Notes:
1. Material 6 layer FR4
2. 1 oz. copper
3. 14 mil layers
4. Gerber files available
Figure 11: 1610 - 1626.5 MHz Test Circuit Layout
Table 5: Parts List Table
DESIGNATION
C1,C3,C5,C22
C2,C7,C9,C24
C4
VALUE
2.2
MANUFACTURE
MANUFACTURE PART # WEB ADDRESS
m
F
Panasonic
ECS-H1AY225R
www.panasonic.com
Not Used
15 pF
Murata
Murata
Murata
Murata
Murata
Murata
GRM36COG150J50
GRM36COG100J50
GRM36COG270J50
GRM36COG330J50
GRM36X7R103K16
GRM36COG220J50
www.murata.com
C6,C10
10 pF
C11,C19
27 pF
www.murata.com
www.murata.com
www.murata.com
www.murata.com
C12,C13,C20,C21
C14,C16,C17, C23
C15
33 pF
0.01 uF
22 pF
American Technical
Ceramics
C18
4.7 pF
ATC100A4R7CW150X
BK2125HS470
www.atc-cap.com
www.t-yuden.com
Ferrite 47 @ 100
MHz, 1A Rating
W
F1,F2,F3,F4,F5
Taiyo Yuden
L1, L3
L2
Shim
2.7 nH
Toko
LL2012-F2N7S
A03T
www.tokoam.com
www.coilcraft.com
www.coilcraft.com
www.panasonic.com
www.panasonic.com
www.panasonic.com
L4
8 nH
Coilcraft
Coilcraft
Panasonic
Panasonic
Panasonic
L5
47 nH
0805CS470XMBC
ERJ-36SYJ562V
ERJ-36SYJ302V
ERJ-36SYJ512V
R2,R5
R3
5600
1500
2200
W
W
R4
W
PRELIMINARY DATA SHEET - Rev 1.0
7
08/2001
AWT1921
D
T
C
L
LE
HEAT SINK
SLUG
S
E
h
a
A2
A
A1
e
Notes:
1. Controlling dimensions : inches
2. Dimension "d" does not include mold flash, protrusions or gate burrs. Mold flash, rotrusions and gate burrs shall
not exceed 0.006 (0.16mm)
3. Dimension "e" does not include inter-lead or protrusions. Inter-lead flash and protrusions shall not exceed
4. 0.010 (0.25mm) per side.
5. Maximum lead twist/skew to be 0.002 (0.05mm)
6. Mold flash shall not extend more than 0.010 (0.25mm) on any edge of heat slug
Figure 12: Package Outline Drawing
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.093
0.004
0.089
0.012
0.009
0.408
0.296
BSC
MIN
2.21
0.00
2.21
0.36
0.18
10.16
7.42
0.64
10.41
0.48
0.86
1.37
0
MAX
2.36
0.10
2.25
0.46
0.25
10.36
7.52
BSC
40.62
0.61
0.97
NOTE
A
A1
A2
B
0.087
0.000
0.087
0.008
0.007
0.400
0.292
0.025
0.410
0.018
0.034
0.84
C
D
E
2
2
4
e
H
h
0.418
0.024
0.038
L
LE
a
0
8
8
S
0.139
0.349
0.141
0.351
3.54
8.86
3.55
8.92
5
5
T
PRELIMINARY DATA SHEET - Rev 1.0
8
08/2001
AWT1921
NOTES
PRELIMINARY DATA SHEET - Rev 1.0
9
08/2001
AWT1921
NOTES
PRELIMINARY DATA SHEET - Rev 1.0
10
08/2001
AWT1921
NOTES
PRELIMINARY DATA SHEET - Rev 1.0
11
08/2001
AWT1921
ORDERING INFORMATION
ORDER NUMBER
PACKAGE
DESCRIPTION
COMPONENT PACKAGING
AWT1921S11
S11
28 Pin Body with Heat Slug
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: Mktg@anadigics.com
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without
notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are
subject to change prior to a products formal introduction. Information in Data Sheets have been carefully checked and are
assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges
customers to verify that the information they are using is current before placing orders.
WARNING
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
PRELIMINARY DATA SHEET - Rev 1.0
12
08/2001
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