APL158125G5C-TRG [ANPEC]
nullDUAL INPUT LOW DROPOUT REGULATOR; nullDUAL输入低压差稳压器
| 型号： | APL158125G5C-TRG |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | nullDUAL INPUT LOW DROPOUT REGULATOR |
| 文件： | 总20页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APL1581
DUAL INPUT LOW DROPOUT REGULATOR
Features
General Description
The APL1581 series of high performance positive volt-
age regulators are designed for use in applications re-
quiring very low dropout voltage at 5Amp.
·
·
Adjustable or Fixed Output
520mV typ. Dropout at 5A in Dual Power
Voltage Mode
The superior dropout characteristics result in reducing
heat dissipation compared to regular LDOs. The APL1581
also provides excellent regulation over line, load, and tem-
perature variations.
·
·
·
·
·
Remote Sense Pin Available
2% Accuracy Over Temperature Range
Built-In Over-Temperature Protection
Built-In Current Limit
Current limit is trimmed to ensure specified output cur-
rent and controlled short-circuit current. On-chip thermal
limiting provides protection against any combination of
overload that would create excessive junction
temperature.
5 Pin TO-263 and TO-252, SOP-8P, TO-252-4
Packages
·
Lead Free and Green Devices Available
(RoHS Compliant)
The APL1581 is available in both the through-hole and
surface mount versions of the industry standard 5-Pin
TO-263 and TO-252, SOP-8P, TO-252-4 power packages.
Applications
·
·
·
·
Microprocessor Supplies
Chip Set Supplies
VGA Card Power
LCD Monitor Power
Ordering and Marking Information
Package Code
APL1581
G5 : TO-263-5 U5 :TO-252-5 KA : SOP-8P
U4 : TO-252-4
Temperature Range
Assembly Material
Handling Code
C : 0 to 70 oC
Handling Code
TR : Tape & Reel
Voltage Code :
Temperature Range
15 : 1.5V
25 : 2.5V
Assembly Material
18 : 1.8V
Blank : Adjustable Version
Package Code
Voltage Code
G : Halogen and Lead Free Device
15
APL1581-15 G5/U5/U4 :
APL1581-15 KA :
XXXXX - Date Code
APL1581
XXXXX
APL1581
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. B.8 - Jan., 2012
APL1581
Pin Configuration
5
4
VIN
VIN
VCNTL
4
3
VCNTL
VOUT
TAB is VOUT
TAB is VOUT
3
2
1
2
1
ADJ
VSENSE
ADJ (or GND)
VSENSE
Front View of TO-263-5
Front View of TO-252-4
VSENSE
ADJ (or GND)
VCNTL
1
2
3
4
8
7
6
5
VOUT
VOUT
VOUT
VOUT
5
4
3
2
1
VIN
VCNTL
VOUT
TAB is VOUT
ADJ(or GND)
VIN
VSENSE
Front View of TO-252-5
SOP-8P (Top View)
NC = No internal connection
= Thermal Pad
(connected to VOUT plane for better heat
dissipation)
Pin 5~8 must be connected together by a shortest
wide track or plane.
Absolute Maximum Ratings (Note 1, 2)
Symbol
Parameter
Rating
Unit
VIN
Input Voltage
7
V
V
VCNTL
PD
Control Voltage
7
Internally Limited
150
Power Dissipation
Junction Temperature
Storage Temperature Range
W
°C
°C
°C
TJ
TSTG
TSDR
-65 to +150
260
Maximum Lead Soldering Temperature, 10 Seconds
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Note 2 : The maximum allowable power dissipation at any TA (ambient temperature) is calculated using: PD (max) = (TJ – TA) / qJA; TJ
= 125°C. Exceeding the maximum allowable power dissipation will result in excessive die temperature.
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
Junction-to-Ambient Resistance in free air (Note 3)
TO-263-5 (Toplayer plane size : 15mm x 15 mm)
TO-252-4/TO-252-5 (Toplayer plane size : 10mm x 10 mm)
SOP-8P (Toplayer plane size : 10mm x 10 mm)
28
42
68
oC/W
qJA
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Rev. B.8 - Jan., 2012
APL1581
Thermal Characteristics (Cont.)
Symbol
Parameter
Junction-to-Case Resistance (Note 4)
Typical Value
Unit
TO-263-5
TO-252-4/TO-252-5
4
5
oC/W
qJC
Note 3 : qJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The sizes of the
rectangular plane, where the devices are mounted, are shown in the table.
Note 4: The case temperature is measured on the TAB of the device mounted on the test board described in Note 3 except the
package TO-220-5. The case temperature of the TO-220-5 is measured on the bottom of the case directly below the die.
Electrical Characteristics
Unless otherwise noted , these specifications apply over CIN=10mF, CCNTL=1mF, COUT=10mF, and TA=0 to 70°C. Typical values refer to
TA=25°C. VOUT=VSENSE
.
APL1581
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
Reference Voltage
Output Voltage
VCNTL=2.75~5.5V, VIN=2.05~5.5V,
APL1581 IO =10mA~5A, VADJ=0V
VREF
1.225
1.250
1.275
V
(IO =0~5A for fixed versions)
APL1581-15 VCNTL=3~5.5V , VIN=2.3~5.5V
APL1581-18 VCNTL=3.3~5.5V , VIN=2.6~5.5V
APL1581-25 VCNTL=4~5.5V , VIN=3.3~5.5V
(IO =0A for fixed versions)
1.470
1.764
2.450
1.500
1.800
2.500
1.530
1.836
2.550
VOUT
V
Line Regulation
APL1581 VCNTL=2.75~5.5V, VIN=1.75~5.5V,
IO =10mA, VADJ=0V
APL1581-15 VCNTL=3~5.5V, VIN=2.3~5.5V
APL1581-18 VCNTL=3.3~5.5V, VIN=2.6~5.5V
APL1581-25 VCNTL=4~5.5V, VIN=3~5.5V
(IO =0~5A for fixed versions)
APL1581 VCNTL=2.75V, VIN=2.1V, VADJ =0V,
IO =10mA~5A
APL1581-15 VCNTL=3V, VIN=2.35V
APL1581-18 VCNTL=3.3V, VIN=2.65V
APL1581-25 VCNTL=4V, VIN=3.35V
IO =5A for all versions
REGLINE
-
-
-
-
3
5
mV
Load Regulation (Note 5)
REGLOAD
mV
Dropout Voltage (Note 6)
APL1581 VIN=2.05V, VADJ =0V
APL1581-15 VIN=2.3V
APL1581-18 VIN=2.6V
VCNTL-VOUT
-
-
1.20
0.52
1.35
0.75
V
V
APL1581-25 VIN=3.3V
Dropout Voltage (Note 6)
IO =5A for all versions
APL1581 VCNTL=2.75V, VADJ =0V
APL1581-15 VCNTL=3V
VIN-VOUT
APL1581-18 VCNTL=3.3V
APL1581-25 VCNTL=4V
ILIMIT
ILMIN
5
-
-
-
10
-
A
Current Limit
VCNTL-VOUT=1.5V, VIN-VOUT=0.6V
Minimum Load Current (Note7)
APL1581 VCNTL=5V, VIN=3.3V, VADJ =0V
0.8
0.01
mA
REGTHERMAL
-
%/W
30ms Pulse
Thermal Regulation
Power Supply Ripple Rejection
VRIPPLE=1VPP at 120Hz, IO=5A
APL1581 VCNTL=5V, VIN=5V, VADJ =0V
APL1581-15 VCNTL=5.25V, VIN=5.25V
APL1581-18 VCNTL=5.55V, VIN=5.55V
APL1581-25 VCNTL=6.25V, VIN=6.25V
PSRR
60
70
-
dB
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Rev. B.8 - Jan., 2012
APL1581
Electrical Characteristics (Cont.)
Unless otherwise noted , these specifications apply over CIN = 10mF, CCNTL = 1mF, COUT = 10mF, and TA = 0 to 70°C. Typical values refer
to TA = 25°C. VOUT = VSENSE
.
APL1581
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
VCNTL-VOUT=1.5V, VIN-VOUT=0.8V,
IO =5A
ICNTL
IGND
IADJ
-
45
120
mA
CNTL Pin Current
Ground Pin Current
APL1581-15 VCNTL =3V, VIN =2.3V
APL1581-18 VCNTL =3.3V, VIN =2.6V
APL1581-25 VCNTL =4V, VIN =3.3V
-
-
8
13
mA
Adjust Pin Current
50
120
mA
APL1581 VCNTL=2.75V, VIN=2.05V , VADJ =0V
Note 5 : Low duty cycle pulse test with Kelvin connections are required to maintain data accuracy .
Note 6 : Dropout voltage is defined as the minimum difference between VIN and VOUT required to maintain 1% VOUT regulation.
Note 7 : Minimum load current is defined as the minimum current required at the output to maintain VOUT regulation.
Copyright ã ANPEC Electronics Corp.
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Rev. B.8 - Jan., 2012
APL1581
Typical Operating Characteristics
Reference Voltage vs. Junction Temperature
Adjust Pin Current vs. Junction Temperature
1.275
1.270
1.265
1.260
1.255
1.250
1.245
1.240
1.235
1.230
1.225
80
70
60
50
40
30
20
10
0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Junction Temperature (°C)
Junction Temperature (°C)
Minimum Load Current vs. Junction Temperature
VIN-VOUT Dropout Voltage vs. Output Current
700
1.2
TJ=125oC
600
500
400
300
200
100
0
1.0
VCNTL-VOUT=10.75V
0.8
TJ=25oC
VCNTL-VOUT=1.45V
0.6
TJ=-50oC
0.4
0.2
0.0
-50 -25
0
25 50 75 100 125 150
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Junction Temperature (°C)
Output Current (A)
Short-Circuit Current vs. Junction Temperature
VCONTROL-VOUT Dropout Voltage vs. Output Current
1.4
14
TJ=-50oC
VIN=5.0V
12
TJ=0oC
1.3
1.2
1.1
10
VIN=3.3V
8
TJ=25oC
6
4
2
0
1.0
0.9
0.8
0.7
TJ=125oC
-50 -25
0
25 50 75 100 125 150
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Current (A)
Junction Temperature (°C)
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Rev. B.8 - Jan., 2012
APL1581
Typical Operating Characteristics (Cont.)
Control Pin Current vs. Output Current
Control Pin Current vs. Output Current
VIN-VOUT=0.8V
VIN-VOUT=0.6V
80
70
60
50
40
30
20
10
0
160
140
120
100
80
TJ=-50oC
TJ=125oC
TJ=25oC
TJ=0oC
TJ=25oC
TJ=75oC
TJ=0oC
60
TJ=-50oC
40
TJ=125oC
20
TJ=75oC
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Current (A)
Output Current (A)
Control Pin Current vs. Output Current
Control Pin Current vs. Output Current
VIN-VOUT=1.0V
VIN-VOUT=4.25V
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
TJ=-50oC
TJ=-50oC
TJ=0oC
TJ=0oC
TJ=25oC
TJ=25oC
TJ=75oC
TJ=75oC
TJ=125oC
TJ=125oC
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Current (A)
Output Current (A)
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Rev. B.8 - Jan., 2012
APL1581
Pin Description
PIN
FUNCTION
NAME
I/O
Positive side of the reference voltage, which allows remote sensing to obtain excellent load
regulation.
VSENSE
I
Negative side of the reference voltage, which allows to use resistor divider to set an expect
output voltage. A small bypass capacitor can be connected from this pin to ground to improve
PSRR performance.
ADJ
O
GND
O
O
For fixed voltage devices, this is the bottom of the resistor divider that sets the output voltage.
Output pin of the regulator, which connects to the TAB. A minimum of 10mF capacitor must be
connected from this pin to ground to ensure the stability.
VOUT
Supply pin of the control circuitry, which must be always higher than VOUT for the device to
regulate. (See electrical characteristics)
VCNTL
VIN
I
I
Power input pin of the regulator, which must be always higher than VOUT for the device to
regulate. (See electrical characteristics)
Block Diagram
VOUT
VIN
VCNTL
Current Limit
VSENSE
ADJ/GND
Thermal
Protection
Voltage
Regulation
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Rev. B.8 - Jan., 2012
APL1581
Typical Application Circuit
(1) Adjustable Output VoltageDevice
VIN
VIN
VOUT
APL1581
(Adj.)
VSENSE
ADJ
VOUT
+3.3V
+2.5V/5A
VCNTL
+5V
VCNTL
R1
120
VREF
COUT
470mF
CCNTL
10mF
CIN
100mF
R2
120
GND
GND
* VOUT = VREF ( 1+ R2 / R1 ) + IADJ x R2
where VREF =1.25V (typical)
IADJ=50mA (typical)
* R1 is typically in range of 100W to 125W to satisfy the minimum load current requirement.
(2) Fixed Output VoltageDevice
VIN
+3.3V
VIN
VOUT
VOUT
+2.5V/5A
APL1581-25
VCNTL
+5V
VCNTL
VSENSE
GND
COUT
470mF
CCNTL
10mF
CIN
100mF
GND
GND
(3) With Enable Control Application
VIN
VIN
VOUT
APL1581
(Adj.)
VSENSE
ADJ
VOUT
+3.3V
+2.5V/5A
Q1
VCNTL
+5V
VCNTL
10k
10k
R1
120
VREF
COUT
470mF
CCNTL
10mF
CIN
100mF
Q2
Enable
GND
R2
120
GND
Q1 : APM2301A
Q2 : APM2300A
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Rev. B.8 - Jan., 2012
APL1581
Application Information
General
The recommended R1 is in range of 100W to125W to
satisfy the minimum load current requirement. Proper
sizes of R2 and R1 are also concerned for power
dissipation.
The APL1581 (adjustable or fixed) regulator is a 5 termi-
nal device designed specifically to provide extremely low
dropout voltages comparable to the PNP type without the
disadvantage of the extra power dissipation due to the
base current associated with PNP regulators. This is done
by bringing out the control pin of the regulator that pro-
vides the base current to the power NPN and connecting
it to a voltage that is greater than the voltage present at
the VIN pin. This flexibility makes APL1581 ideal for appli-
cations where dual inputs are available, such as a com-
puter motherboard with an ATX power supply that pro-
vides 5V and 3.3V to the board.
VIN
VIN
VOUT
VOUT
APL1581
VCNTL
VSENSE
VCNTL
ADJ
R1
R2
VREF
IADJ=50mA
APL1581 is equipped with a 1.25V reference, precision
and fast voltage regulations, on-chip current and thermal
limits, and remote sensing capability to reduce system
total cost.
Figure 1. Setting Output Voltage
Grounding and Output Sensing
APL1581 is available in SOP-8P, TO-252-5, and TO-263-
5 packages to meet different power dissipation
applications.
The APL1581 allows true Kelvin sensing for both the high
and low side of the load. Figure 2 shows the device con-
nected to take advantage of the remote sense feature.
The SENSE pin and the top of the resistor divider are
connected to the top of the load; the bottom of the resistor
divider is connected to the bottom of the load. Typically,
the load is a microprocessor and parasitic resistance RP
is made up of the PC traces and /or connector resistance
between the regulator and the processor. RP is now con-
nected inside the regulation loop of the APL1581 and for
reasonable values of RP the load regulation at the load
will be negligible. Voltage drops due to RP are not
eliminated; they will add to the dropout voltage of the regu-
lator regardless of whether they are inside or outside the
regulation loop.
Output Voltage Setting
See Figure 1 Adjustable APL1581 develops a 1.25V ref-
erence voltage between the VSENSE pin and the ADJ pin.
Placing a resistor between these two terminals causes a
constant current to flow through R1 and down through R2
to set the overall output voltage. In general, R1 is chosen
so that this current is the specified minimum load current
of 10mA. The current out of the ADJ pin is small, typically
50mA and itadds to the current from R1. Because IADJ is
very small, it needs to be considered only when very pre-
cise output voltage setting is required. For best regulation,
the top of the resistor divider should be connected di-
rectly to the SENSE pin. The adjustable APL1581 can be
programmable to any voltages in the range of 1.25V to
5.5V according to the following formula:
VOUT
VIN
VOUT
VIN
APL1581
VSENSE
VCNTL
VCNTL
R2
Load
ADJ
R1
R2
VOUT = VREF x (1+
) + IADJ x R2
R1
Adjustable
Device
where
VREF = 1.25V (typical)
IADJ = 50mA (typical)
RP
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Rev. B.8 - Jan., 2012
APL1581
Application Information (Cont.)
Grounding and Output Sensing (Cont.)
The output capacitors are also used to reduce the slew
rate of load current and help the APL1581 to minimize
variations of the output voltage, improving transient
response. For this purpose, the low-ESR capacitors are
recommended.
VOUT
VIN
VOUT
APL1581
VIN
VSENSE
VCNTL
VCNTL
Load
Input Capacitors
GND
The input capacitors of VCNTL and VIN pins are not re-
quired for stability but for supplying surge currents during
large load transients, and this will prevent the input rail
from drooping and improve the performance of the
APL1581. Because parasitic inductors from voltage
sources or other bulk capacitors to the VCNTL and VIN
pins will limit the slew rate of the surge currents during
large load transients, resulting in voltage drop at VIN and
VCNTL pins.
Fixed Voltage
Device
RP
Figure 2. Remote Voltage Sensing
Stability and Output Capacitors
The circuit design of using the APL1581 series requires
an output capacitor as part of the device frequency
compensation. The following chart shows a stable re-
gion to select output capacitor for APL1581. This region
above the curve indicates minimum required ESR and
capacitance to maintain stability. However, the output ca-
pacitor should have an ESR less than 1W.
A capacitor of 1mF (ceramic chip capacitor) or greater
(aluminum electrolytic capacitor) is recommended and
connected near VCNTL pin. For VIN pin, an aluminum
electrolytic capacitor (>33mF) is recommended. It is not
necessary to use low-ESR capacitors. More capacitance
reduces the variations of the input voltage at VIN pin.
Layout and Thermal Consideration
100
80
The APL1581 series have internal power and thermal
limiting (TJ=150oC typical) circuitry designed to protect
the device under overload conditions. However, maximum
junction temperature ratings should not be exceeded
under continuous normal load conditions. Careful con-
sideration must be given to all sources of thermal resis-
tance from junction to ambient, including junction-to-case,
case-to-heat sink interface, and heat sink resistance itself.
See Figure 3, the SOP-8P is a cost-effective package
featuring a small size as a standard SOP-8 and a bottom
thermal pad to minimize the thermal resistance of the
package, being applicable to high current applications.
The thermal pad is soldered to the top VOUT plane which
may be connected to internal or bottom VOUT plane by
vias to reduce the heat sink thermal resistance. Therefore,
the printed circuit board (PCB) forms a heat sink and
dissipates heat into ambient air.
Stable Region
60
40
20
0
1
10
100
1000
Capacitance(mF)
A low-ESR solid tantalum and aluminum electrolytic ca-
pacitor (ESR<1W) works extremely well and provides good
transient response and stability over temperature. Ultra-
low-ESR capacitors, such as ceramic chip capacitors, may
promote unstable or under-damped transient response,
but proper ceramic chip capacitors placed near loads can
be used as decoupling capacitors.
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Rev. B.8 - Jan., 2012
APL1581
Application Information (Cont.)
Layout and Thermal Consideration (Cont.)
Top layer
VOUT plane
for Heat Dissipation
(Larger area is better)
COUT
8
1
7
2
6
5
4
Load
Vias
Vias
3
Soldering area
(140mil x 110mil)
for bottom pad
CIN
CCNTL
Figure 3. Recommended SOP-8P Layout
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Rev. B.8 - Jan., 2012
APL1581
Package Information
TO-263-5
A
c2
E
E1
b
e
c
SEE VIEW A
GAUGE PLANE
SEATING PLANE
L
VIEW A
TO-263-5
S
Y
M
B
O
L
MILLIMETERS
INCHES
MIN.
MAX.
4.83
0.25
0.99
0.74
MIN.
MAX.
0.190
0.010
0.039
0.029
0.065
0.380
0.354
0.450
0.354
A
4.06
0.160
0.000
0.020
0.015
0.045
0.330
0.236
0.380
0.245
0.00
0.51
0.38
A1
b
c
c2
1.14
8.38
6.00
9.65
6.22
1.65
D
9.65
9.00
11.43
9.00
D1
E
E1
e
1.70 BSC
0.067 BSC
0.575
0.070
0.625
0.110
0.066
8o
14.61
1.78
15.88
2.79
1.68
8o
H
L
L1
0
0o
0o
Note : Follow JEDEC TO-263 BB.
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Rev. B.8 - Jan., 2012
APL1581
Package Information
TO-252-5
E
A
c2
E1
b3
c
b
e
SEE VIEW A
SEATING PLANE
GAUGE PLANE
L
VIEW A
TO-252-5
S
Y
M
B
O
L
MILLIMETERS
MIN.
INCHES
MAX.
2.39
0.13
0.89
5.46
MIN.
MAX.
0.094
0.005
0.035
0.215
0.024
0.035
0.245
A
2.18
0.086
A1
b
0.020
0.170
0.018
0.018
0.210
0.180
0.250
0.150
0.50
4.32
b3
c
0.46
0.46
5.33
4.57
6.35
3.81
0.61
c2
0.89
6.22
6.00
6.73
D
D1
E
0.236
0.265
E1
e
6.00
0.236
1.27 BSC
0.050 BSC
0.370
0.055
0.035
0.410
0.070
0.080
9.40
1.40
0.89
10.41
1.78
H
L
L3
0
2.03
8
0
8
0
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Rev. B.8 - Jan., 2012
APL1581
Package Information
TO-252-4
E
A
c2
E1
b3
c
b
e
SEE VIEW A
GAUGE PLANE
SEATING PLANE
L
VIEW A
TO-252-4
S
Y
M
B
O
L
MILLIMETERS
MIN.
INCHES
MAX.
2.39
0.13
0.71
5.46
MIN.
MAX.
0.094
0.005
0.028
0.215
0.024
0.035
0.245
0.236
0.265
0.236
A
2.18
0.086
A1
b
0.020
0.170
0.018
0.018
0.210
0.180
0.250
0.150
0.50
4.32
b3
c
0.46
0.46
5.33
4.57
6.35
3.81
0.61
c2
0.89
6.22
6.00
6.73
D
D1
E
E1
e
6.00
1.27 BSC
0.050 BSC
0.370
0.055
0.035
0.410
0.070
0.080
0.040
9.40
1.40
0.89
10.41
1.78
2.03
1.02
H
L
L3
L4
0
°
°
°
°
8
0
8
0
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Rev. B.8 - Jan., 2012
APL1581
Package Information
SOP-8P
-T- SEATING PLANE < 4 mils
SEE VIEW A
D
D1
THERMAL
PAD
c
b
e
GAUGE PLANE
SEATING PLANE
L
VIEW A
SOP-8P
S
Y
M
B
O
L
MILLIMETERS
INCHES
MAX.
MIN.
MAX.
1.60
MIN.
A
0.063
0.000
0.049
0.012
0.007
0.189
0.098
0.228
0.150
0.079
0.006
0.15
A1
A2
0.00
1.25
0.31
0.17
4.80
2.50
5.80
3.80
2.00
b
0.020
0.010
0.197
0.138
0.244
0.157
0.118
0.51
0.25
5.00
3.50
6.20
4.00
3.00
c
D
D1
E
E1
E2
e
h
L
1.27 BSC
0.050 BSC
0.020
0.010
0.016
0oC
0.25
0.40
0.50
1.27
8oC
0.050
8oC
0oC
q
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright ã ANPEC Electronics Corp.
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Rev. B.8 - Jan., 2012
APL1581
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
TO-252-4
A
H
T1
16.4+2.00 13.0+0.50
-0.00 -0.20
P2 D0
C
d
D
W
E1
F
7.50±0.05
K0
330.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN. 16.0±0.30 1.75±0.10
P0
4.0±0.10
A
P1
8.0±0.10
H
T
A0
B0
1.5+0.10
-0.00
0.6+0.00
-0.40
2.0±0.05
1.5 MIN.
d
6.80±0.20 10.40±0.20 2.50±0.20
Application
TO-252-5
T1
C
D
W
E1
F
7.50±0.05
K0
16.4+2.00 13.0+0.50
-0.00 -0.20
330.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN. 16.0±0.30 1.75±0.10
P0
4.0±0.10
A
P1
8.0±0.10
H
P2 D0
T
A0
B0
1.5+0.10
-0.00
0.6+0.00
-0.40
2.0±0.05
1.5 MIN.
d
6.80±0.20 10.40±0.20 2.50±0.20
Application
TO-263-5
T1
C
D
W
E1
F
11.5±0.10
K0
24.4+2.00 13.0+0.50
-0.00 -0.20
330.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN. 24.0±0.30 1.75±0.10
P0
4.0±0.10
A
P1
16.0±0.10
H
P2 D0
T
A0
10.8±0.20 16.1±0.20
E1
B0
1.5+0.10
-0.00
0.6+0.00
-0.40
2.0±0.10
1.5 MIN.
d
5.2±0.20
F
Application
SOP-8P
T1
C
D
W
12.4+2.00 13.0+0.50
-0.00 -0.20
330.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN. 12.0±0.30 1.75±0.10
5.5±0.05
K0
P0
P1
P2 D0
T
A0
B0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10
8.0±0.10
2.0±0.05
1.5 MIN.
6.40±0.20 5.20±0.20 2.10±0.20
(mm)
Copyright ã ANPEC Electronics Corp.
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Rev. B.8 - Jan., 2012
APL1581
Devices Per Unit
Package Type
TO-252-4
TO-252-5
TO-263-5
SOP-8P
Unit
Devices Per Reel
Type & Reel
Type & Reel
Type & Reel
Type & Reel
2500
2500
800
2500
Taping Direction Information
TO-252-4
USER DIRECTION OF FEED
TO-252-5
USER DIRECTION OF FEED
Copyright ã ANPEC Electronics Corp.
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Rev. B.8 - Jan., 2012
APL1581
Taping Direction Information
TO-263-5
USER DIRECTION OF FEED
SOP-8P
USER DIRECTION OF FEED
Copyright ã ANPEC Electronics Corp.
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Rev. B.8 - Jan., 2012
APL1581
Classification Reflow Profiles
Profile Feature
Preheat & Soak
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
³ 2.5 mm
Volume mm3
<350
235 °C
220 °C
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
PCT
TCT
HBM
MM
VMM≧200V
10ms, 1tr≧100mA
Latch-Up
Copyright ã ANPEC Electronics Corp.
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Rev. B.8 - Jan., 2012
APL1581
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
Rev. B.8 - Jan., 2012
20
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