APL3206AQBI-TRG [ANPEC]
Li+ Charger Protection IC with Integrated P-MOSFET; Li +电池充电器保护IC，集成P-MOSFET
| 型号： | APL3206AQBI-TRG |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Li+ Charger Protection IC with Integrated P-MOSFET |
| 文件： | 总19页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APL3206/A
Li+ Charger Protection IC with Integrated P-MOSFET
Features
General Description
The APL3206/A provides complete Li+ charger protection
against input over-voltage, input over-current, and battery
over-voltage. When any of the monitored parameters are
·
·
·
·
·
·
·
·
Input Over-Voltage Protection
Input Over-Current Protection
Battery Over-Voltage Protection
High Immunity of False Triggering
High Accuracy Protection Threshold
A Built-In P-MOSFET
over the threshold, the IC removes the power from the
charging system by turning off an internal switch. All pro-
tections also have deglitch time against false triggering
due to voltage spikes or current transients.
The APL3206/A integrates a P-MOSFET with the body di-
ode reverse protection to replace the external P-MOSFET
and Schottky diode for charger function of cell phone’s
PMIC. When the CHRIN voltage drops below VBAT+20mV,
the internal power select circuit will reverse the body
diode’s terminal to prevent a reverse current flowing from
the battery back to CHRIN pin.
Thermal Shutdown Protection
Compliance to IEC61000-4-2 (Level 4)
± 8kV (Contact Discharge)
± 15kV (Air Discharge)
·
·
Available in a TDFN2x2-8 and TSOT-23-6A
Packages
The APL3206/A provides complete Li+ charger protec-
tions and saves the external MOSFET and Schottky diode
for the charger of cell phone’s PMIC. The above features
and small package make the APL3206/A an ideal part for
cell phones applications.
Lead Free and Green Devices Available
(RoHS Compliant)
Applications
Pin Configuration
·
Cell Phones
ACIN 1
ACIN 2
GND 3
VBAT 4
8 OUT
7 OUT
EP
6 CHRIN
5 GATDRV
Simplified Application Circuit
TDFN2x2-8
(Top View)
5V Adapter or USB
ACIN
CHRIN
CHRIN
= Exposed Pad (connected to ground
plane for better heat dissipation)
EP
APL3206/A
PMIC
GATDRV
OUT
GATDRV
ISENS
6 VIN
OUT 1
GND
CHRIN 2
5 GND
4 VBAT
VBAT
VBAT
Li+
Battery
GATDRV 3
TSOT-23-6A
(Top View)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Jul., 2009
APL3206/A
Ordering and Marking Information
Package Code
APL3206
QB : TDFN2x2-8 CT : TSOT-23-6A
Operating Ambient Temperature Range
I : -40 to 85 oC
APL3206A
Assembly Material
Handling Code
Handling Code
Temperature Range
Package Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
L06
X
APL3206 QB:
X - Date Code
X - Date Code
L6A
X
APL3206A QB:
APL3206 CT:
L06X
L6AX
X - Date Code
X - Date Code
APL3206A CT:
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings(Note 1)
Symbol
VACIN
VCHRIN
VGATDRV
VBAT
Parameter
Rating
-0.3 ~ 30
-0.3 ~ 7
-0.3 ~ VCHRIN
-0.3 ~ 7
-0.3 ~ 7
1.5
Unit
V
ACIN Input Voltage (ACIN to GND)
CHRIN to GND Voltage
V
GATDRV to GND Voltage
VBAT to GND Voltage
V
V
VOUT
IOUT
OUT to GND Voltage
V
OUT Output Current
A
TJ
Maximum Junction Temperature
Storage Temperature
150
oC
oC
oC
TSTG
-65 ~ 150
260
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristic
Symbol
Parameter
Typical Value
Unit
Junction-to-Ambient Resistance in Free Air (Note 2)
TDFN2x2-8
TSOT-23-6A
80
oC/W
qJA
235
Note 2: qJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed
pad of TDFN2x2-8 is soldered directly on the PCB.
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Rev. A.3 - Jul., 2009
APL3206/A
Recommended Operating Conditions (Note 3)
Symbol
VACIN
IOUT
Parameter
Range
4.5 ~ 5.5
0 ~ 700
Unit
V
ACIN Input Voltage
Output Current
mA
oC
oC
TA
Ambient Temperature
Junction Temperature
-40 ~ 85
-40 ~ 125
TJ
Note 3: Refer to the typical application circuit
Electrical Characteristics
Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC.
APL3206/A
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
ACIN INPUT CURRENT AND POWER-ON-RESET (POR)
IACIN ACIN Supply Current IOUT=0A, ICHRIN=0A
VACIN rising
-
250
-
350
2.8
300
-
mA
V
VACIN ACIN POR Threshold
ACIN POR Hysteresis
2.4
200
-
250
8
mV
ms
TB(ACIN) ACIN Power-On Blanking Time
INTERNAL SWITCH ON RESISTANCE
ACIN to OUT On Resistance
IOUT=0.7A
-
-
0.5
-
-
W
W
CHRIN Discharge On Resistance
500
INPUT OVER-VOLTAGE PROTECTION (OVP)
APL3206
6
6.6
200
-
6.17
6.8
300
-
6.35
VOVP
Input OVP Threshold
VACIN rising
V
APL3206A
7
400
1
Input OVP Hysteresis
mV
ms
Input OVP Propagation Delay
TON(OVP) Input OVP Recovery Time
-
8
-
ms
OVER-CURRENT PROTECTION (OCP)
IOCP
OCP Threshold
1
-
-
1.5
A
TB(OCP) OCP Blanking Time
TON(OCP) OCP Recovery Time
BATTERY OVER-VOLTAGE PROTECTION
VBOVP Battery OVP Threshold
Battery OVP Hysteresis
176
64
-
-
ms
ms
-
VBAT rising
4.32
4.35
270
-
4.38
320
20
V
220
mV
nA
ms
IVBAT
TB(BOVP) Battery OVP Blanking Time
INTERNAL P-MOSFET (CHRIN, OUT, AND GATDRV PINS)
VBAT Pin Leakage Current
VBAT = 4.4V
-
-
176
-
VCHRIN from low to high, P-MOSFET is controlled
by GATDRV
-
150
-
VCHRIN-VBAT Lockout Threshold
mV
VCHRIN from high to low, P-MOSFET is off
VCHRIN=0V, VOUT=4.2V, GATDRV=GND
VACIN=VCHRIN= VOUT=5V, VGATDRV=0V
VACIN=VCHRIN= VGATDRV =5V, VOUT=0V
-
-
-
-
20
-
-
OUT Input Current
1
1
1
mA
mA
mA
GATDRV Leakage Current
OUT Leakage Current
-
-
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Rev. A.3 - Jul., 2009
APL3206/A
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC.
APL3206/A
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
INTERNAL P-MOSFET (CHRIN, OUT, AND GATDRV PINS) (CONT.)
P-MOSFET Input Capacitance
-
-
200
15
-
-
pF
GATDRV Input Resistance
W
OVER-TEMPERATURE PROTECTION (OTP)
TOTP
Over-Temperature Threshold
Over-Temperature Hysteresis
TJ rising
-
-
160
40
-
-
°C
°C
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APL3206/A
Typical Operating Characteristics
Input OVP Threshold vs. Junction
OCP Threshold vs. Junction
Temperature
Temperature
6.25
1.30
6.15
1.25
1.20
1.15
1.10
1.05
1.00
VACIN Increasing
6.05
5.95
5.85
5.75
5.65
VACIN Decreasing
-50
-25
0
25
50
75
100
)
125
-50
-25
0
25
50
75
100 125
Junction Temperature (oC)
o
Junction Temperature (
C
Battery OVP Threshold vs.
Junction Temperature
ACIN to OUT On Resistance vs.
Junction Temperature
1000
900
800
700
600
500
400
300
4.40
4.35
4.30
4.25
4.20
4.15
4.10
4.05
4.00
VBAT Increasing
ACIN to OUT On Resistance
VBAT Decreasing
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
Junction Temperature (oC)
Junction Temperature (oC)
POR Threshold vs. Junction
Temperature
ACIN Supply Current vs.
Junction Temperature
2.8
2.7
2.6
2.5
2.4
2.3
2.2
350
300
250
200
150
VACIN Increasing
VACIN Decreasing
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
Junction Temperature (oC)
Junction Temperature (oC)
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Rev. A.3 - Jul., 2009
APL3206/A
Operating Waveforms
The test condition is VACIN=5V, VBAT=3.8V, CACIN=1mF, CCHRIN=1mF, TA= 25oC unless otherwise specified.
OVP at Power On
Normal Power On
VACIN
VOUT
1
VACIN
VCHRIN
VOUT
1
2
VCHRIN
2,3
4
IOUT
3
VACIN = 0 to 12V, VGATDRV = VCHRIN
VGATDRV = VCHRIN
CH1: VACIN, 5V/Div, DC
CH2: VOUT, 2V/Div, DC
CH3: VCHRIN, 2V/Div, DC
CH4: IOUT, 0.2A/Div, DC
TIME: 2ms/Div
CH1: VACIN, 10V/Div, DC
CH2: VCHRIN, 2V/Div, DC
CH3: VOUT, 2V/Div, DC
TIME: 2ms/Div
Input Over-Voltage Protection
Recovery from Input OVP
VACIN
VACIN
1
1
VCHRIN
VCHRIN
2
2
VACIN =5V to 12V
VACIN= 12V to 5V
CH1: VACIN, 5V/Div, AC
CH2: VCHRIN, 2V/Div, DC
TIME:20ms/Div
CH1: VACIN, 5V/Div, AC
CH2: VCHRIN, 2V/Div, DC
TIME: 2ms/Div
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Rev. A.3 - Jul., 2009
APL3206/A
Operating Waveforms (Cont.)
The test condition is VACIN=5V, VBAT=3.8V, CACIN=1mF, CCHRIN=1mF, TA= 25oC unless otherwise specified.
Battery Over-Voltage Protection
Battery Over-Voltage Protection
VBAT
VBAT
VCHRIN
1
2
1
2
VCHRIN
VBAT = 3.6V to 4.4V
VBAT = 3.6V to 4.4V to 3.6V
CH1: VBAT, 2V/Div, DC
CH2: VCHRIN, 2V/Div, DC
TIME: 200ms/Div
CH1: VBAT, 2V/Div, AC
CH2: VCHRIN, 2V/Div, DC
TIME: 50ms/Div
Over-Current Protection
Over-Current Protection
VCHRIN
VACIN
VOUT
1
VCHRIN
1
2
VOUT
2
3
IOUT
IOUT
3
ROUT=10W to 2.4W, VBAT = 0V, VGATDRV=0V
ROUT=2.5W, VBAT = 0V, VGATDRV=0V
CH1: VCHRIN, 2V/Div, DC
CH2: VOUT, 2V/Div, DC
CH3: IOUT, 0.5A/Div, DC
TIME: 100ms/Div
CH1: VACIN, 5V/Div, DC
CH2: VCHRIN, 5V/Div, DC
CH3: VOUT, 5V/Div, DC
CH4: IOUT, 1A/Div, DC
TIME: 200m s/Div
Note: OUT pin connected with a resistor to ground.
Note: OUT pin connected with a resistor to ground.
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Rev. A.3 - Jul., 2009
APL3206/A
Pin Description
PIN
FUNCTION
NO.
1
NAME
ACIN
ACIN
GND
Power Supply Input. Connect this pin to external DC supply. Bypass to GND with a 1mF (minimum)
ceramic capacitor.
2
3
Ground Terminal.
4
VBAT
Battery Voltage Sense Input. Connect this pin to pack positive terminal through a resistor.
5
GATDRV Internal P-MOSFET Gate Input.
Output Pin. This pin provides supply voltage to the PMIC input. Bypass to GND with a 1mF (minimum)
ceramic capacitor.
6
CHRIN
7
8
-
OUT
OUT
EP
Output Pins. These pins provide supply source current in series with a resistor to battery.
Exposed Thermal Pad. Must be electrically connected to the GND pin.
Block Diagram
ACIN
CHRIN
OUT
POR
Charge
Pump
OCP
ACIN
OVP
Gate Driver and
Control Logic
VBAT
OVP
0.5V
GATDRV
VBAT
1V
GND
Thermal
Shutdown
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Rev. A.3 - Jul., 2009
APL3206/A
Typical Application Circuit
5V Adapter/USB
6
1, 2
ACIN
CHRIN
CHRIN
CACIN
CCHRIN
1mF
APL3206/A
1mF
PMIC
5
GATDRV
OUT
GATDRV
ISENS
7, 8
0.2W
3
4
GND
VBAT
VBAT
RBAT
200kW
Li+
Battery
Designation
Description
1mF, 25V, X5R, 0603
CACIN
Murata GRM188R61E105K
1mF, 10V, X5R, 0603
Murata GRM188R61A105K
CCHRIN
Murata website: www.murata.com
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Rev. A.3 - Jul., 2009
APL3206/A
Function Description
ACIN Power-On-Reset (POR)
Over-Temperature Protection
The APL3206/A has a built-in power-on-reset circuit to
keep the output shutting off until internal circuitry is oper-
ating properly. The POR circuit has hysteresis and a de-
glitch feature so that it will typically ignore undershoot
transients on the input. When input voltage exceeds the
POR threshold and after 8ms blanking time, the output
voltage starts a soft-start to reduce the inrush current.
When the junction temperature exceeds 160oC, the inter-
nal thermal sense circuit turns off the power FET and
allows the device to cool down. When the device’s junc-
tion temperature cools by 40oC, the internal thermal
sense circuit will enable the device, resulting in a pulsed
output during continuous thermal protection. Thermal pro-
tection is designed to protect the IC in the event of over
temperature conditions. For normal operation, the junc-
tion temperature cannot exceed TJ=+125oC.
ACIN Over-Voltage Protection (OVP)
The input voltage is monitored by the internal OVP circuit.
When the input voltage rises above the input OVP
threshold, the internal FET will be turned off within 1ms to
protect connected system on OUT pin. When the input
voltage returns below the input OVP threshold minus the
hysteresis, the FET is turned on again after 8ms recovery
time. The input OVP circuit has a 300mV hysteresis and
a recovery time of TON(OVP) to provide noise immunity against
transient conditions.
Internal P-MOSFET
The APL3206/A integrates a P-channel MOSFET with the
body diode reverse protection to replace the external P-
MOSFET and Schottky diode for cell phone’s PMIC. The
body diode reverse protection prevents a reverse current
flowing from the battery back to CHRIN pin. During power-
on, when CHRIN voltage rises above the VBAT voltage by
more than 150mV, the body diode of the P-channel
MOSFET is forward biased from OUT to CHRIN, and P-
MOSFET is controlled by the external GATDRV voltage.
When the CHRIN voltage drops below VBAT+20mV, the
body diode of the P-channel MOSFET is forward biased
from CHRIN to OUT and P-channel MOSFET is turned
off. When any of input OVP, OCP, battery OVP, is detected,
the internal P-channel MOSFET is also turned off.
Over-Current Protection (OCP)
The output current is monitored by the internal OCP circuit.
When the output current reaches the OCP threshold, the
device limits the output current at OCP threshold level. If
the OCP condition continues for a blanking time of TB(OCP)
,
the internal power FET is turned off. After the recovery
time of TON(OCP), the FET will be turned on again. The
APL3206/A has a built-in counter. When the total count of
OCP fault reaches 16, the FET is turned off permanently,
requiring a VACIN POR again to restart.
ESD Tests
The APL3206/A VIN input pin fully supports the IEC61000-
4-2. That means the VIN pin has immunity of ±15kV ESD
discharge in Air condition, and immunity of ±8kV ESD dis-
charge in Contact condition.
Battery Over-Voltage Protection
The APL3206/A monitors the VBAT pin voltage for battery
over-voltage protection. The battery OVP threshold is in-
ternally set to 4.35V. When the VBAT pin voltage exceeds
the battery OVP threshold for a blanking time of TB(BOVP)
,
the internal power FET is turned off. When the VBAT volt-
age returns below the battery OVP threshold minus the
hysteresis, the FET is turned on again. The APL3206/A
has a built-in counter. When the total count of battery OVP
fault reaches 16, the FET is turned off permanently, re-
quiring a VACIN POR again to restart.
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Rev. A.3 - Jul., 2009
APL3206/A
Function Description (Cont.)
VOVP
VPOR
VACIN
VCHRIN -VBAT = 150mV
VCHRIN -VBAT = 150mV
VCHRIN
VOUT
GATDRV is pulled low
P-MOS Gate
Control
Controlled
by GATDRV
Controlled by
GATDRV
Turn Off Internal
P-MOSFET
Turn Off Internal P-MOSFET
TB(ACIN)
ACIN OVP
TON(OVP)
Figure 1. OVP Timing Diagram
IOCP
IOUT
GATDRV is pulled low
VCHRIN
Count 13
times
Turn Off
Internal P-
MOSFET
Turn Off
Internal P-
MOSFET
Controlled
by
GATDRV
Controlled by
GATDRV
Turn Off Internal
P-MOSFET
Controlled by
GATDRV
P-MOS Gate
Control
Total count 16
times, IC is
latched off
TB(OCP)
TON(OCP)
TB(OCP)
TB(OCP)
Figure 2. OCP Timing Diagram
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Rev. A.3 - Jul., 2009
APL3206/A
Function Description (Cont.)
VBAT
VBOVP
VBOVP
VCHRIN -VOUT
150mV
=
VCHRIN
Count 13
times
Turn Off
Internal P-
MOSFET
P-MOS Gate Controlled
Turn Off Internal
P-MOSFET
Controlled by
GATDRV
Controlled
by GATDRV
Turn Off Internal
P-MOSFET
Control
by GATDRV
Total count 16
times, IC is
latched off
TB(BOVP)
TB(BOVP)
TB(BOVP)
Figure 3. Battery OVP Timing Diagram
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Rev. A.3 - Jul., 2009
APL3206/A
Application Information
tion at TA = 25oC can be calculated by following formula :
PD(MAX) = (125oC-25oC) / (165oC/W) = 0.606W
for TDFN2x2-8 packages
RBAT Selection
Connect the VBAT pin to the positive terminal of battery
through a resistor RBAT for battery OVP function. The RBAT
limits the current flowing from VBAT to battery in case of
VBAT pin is shortened to ACIN pin under a failure mode.
The recommended value of RBAT is 200kW. In the worse
case of an IC failure, the current flowing from the VBAT
pin to the battery is:
PD(MAX) = (125oC-25oC) / (220oC/W)= 0.455W
for TSOT-23-6A packages
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal resis-
tance qJA. For APL3206/A packages, the Figure 4 of derat-
ing curves allows the designer to see the effect of rising
ambient temperature on the maximum power allowed.
(30V-3V) / 200kW =135mA
where the 30V is the maximum ACIN voltage and the 3V
is the minimum battery voltage. The current is so small
and can be absorbed by the charger system.
0.8
Signal Layer PCB
0.7
Capacitor Selection
TDFN2x2-8
0.6
The input capacitor is for decoupling and prevents the
input voltage from overshooting to dangerous levels. In
the AC adapter hot plug-in applications or load current
step-down transient, the input voltage has a transient
spike due to the parasitic inductance of the input cable. A
25V, X5R, dielectric ceramic capacitor with a value be-
tween 1mF and 4.7mF placed close to the ACIN pin is
recommended.
0.5
0.4
0.3
0.2
0.1
0.0
TSOT-23-6A
0
25
50
75
100
125
The output capacitor of CHRIN is for CHRIN voltage
decoupling. And also can be as the input capacitor of the
charging circuit. At least, a 1mF, 10V, X5R capacitor is
recommended.
Ambient Temperature ( oC)
Figure 4. Derating Curves for APL3206/A Packages
Layout Consideration
Thermal Considerations
In some failure modes, a high voltage may be applied to
the device. Make sure the clearance constraint of the PCB
layout must satisfy the design rule for high voltage. The
exposed pad of the TDFN2x2-8 performs the function of
channeling heat away. It is recommended that connect
the exposed pad to a large copper ground plane on the
backside of the circuit board through several thermal vias
to improve heat dissipation. The input and output capaci-
tors should be placed close to the IC. The high current
traces like input trace and output trace must be wide and
short.
The maximum power dissipation depends on the ther-
mal resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula:
PD(MAX) = (TJ(MAX)-TA) / qJA
Where TJ(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the qJA is
the junction to ambient thermal resistance. For recom-
mended operating conditions specification of APL3206/
A, where TJ(MAX) is 125oC and TA is the operated ambient
temperature. The junction to ambient thermal resistance
qJA for TDFN2x2-8 package is 165oC/W and TSOT-23-6A
package is 220oC/W on the standard JEDEC 51-3 single-
layer thermal test board. The maximum power dissipa-
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Rev. A.3 - Jul., 2009
APL3206/A
Package Information
TDFN2x2-8
A
D
D2
A1
A3
Pin 1 Corner
e
S
Y
TDFN2x2-8
M
B
O
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
0.031
0.002
L
A
0.70
0.00
0.80
0.05
0.028
0.000
A1
A3
b
0.20 REF
0.008 REF
0.007
0.075
0.039
0.075
0.024
0.012
0.083
0.063
0.083
0.039
0.18
1.90
0.30
2.10
D
D2
E
1.00
1.90
0.60
1.60
2.10
E2
e
1.00
0.50 BSC
0.020 BSC
0.012
0.018
L
0.30
0.45
Note : 1. Follow from JEDEC MO-229 WCCD-3.
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Rev. A.3 - Jul., 2009
APL3206/A
Package Information
TSOT-23-6A
D
e
SEE VIEW A
b
c
e1
GAUGE PLANE
SEATING PLANE
L
VIEW A
S
Y
M
B
O
L
TSOT-23-6A
MILLIMETERS
INCHES
MIN.
MAX.
1.00
0.10
0.90
0.50
0.20
3.10
3.00
1.80
MIN.
MAX.
0.039
0.004
0.035
0.020
0.008
0.122
0.118
0.071
A
0.70
0.01
0.70
0.30
0.08
2.70
2.60
1.40
0.028
0.000
0.028
0.012
0.003
0.106
0.102
0.055
A1
A2
b
c
D
E
E1
e
0.95 BSC
1.90 BSC
0.037 BSC
0.075 BSC
e1
L
0.012
0°
0.024
8°
0.30
0°
0.60
8°
0
Note : Dimension D and E1 do not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil
per side.
Copyright ã ANPEC Electronics Corp.
Rev. A.3 - Jul., 2009
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APL3206/A
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
TDFN2x2-8
Application
TSOT-23-6A
A
H
T1
C
d
D
W
E1
F
3.50±0.05
K0
8.4+2.00 13.0+0.50
-0.00 -0.20
178.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN.
8.0±0.20 1.75±0.10
P0
4.0±0.10
A
P1
4.0±0.10
H
P2 D0
T
A0
3.35 MIN
W
B0
1.5+0.10
-0.00
0.6+0.00
-0.4
2.0±0.05
1.5 MIN.
d
3.35 MIN 1.30±0.20
T1
C
D
20.2 MIN.
T
E1
F
3.5±0.05
K0
8.4+2.00 13.0+0.50
-0.00 -0.20
178.0±2.00 50 MIN.
1.5 MIN.
D1
8.0±0.30 1.75±0.10
A0 B0
P0
P1
P2 D0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10
4.0±0.10
2.0±0.05
1.0 MIN.
3.20±0.20 3.10±0.20 1.50±0.20
(mm)
Devices Per Unit
Package Type
TDFN2x2-8
Unit
Quantity
3000
Tape & Reel
Tape & Reel
TSOT-23-6A
3000
Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Jul., 2009
APL3206/A
Taping Direction Information
TDFN2x2-8
USER DIRECTION OF FEED
TSOT-23-6A
USER DIRECTION OF FEED
AAAX
AAAX
AAAX
AAAX
AAAX
AAAX
AAAX
Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Jul., 2009
APL3206/A
Classification Profile
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Jul., 2009
APL3206/A
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
³ 2.5 mm
Volume mm3
<350
235 °C
220 °C
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
PCT
TCT
HBM
MM
VMM≧200V
10ms, 1tr≧100mA
Latch-Up
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
Rev. A.3 - Jul., 2009
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