APW7057KC-TRL [ANPEC]
High Power Step-Down Synchronous DC/DC Controller; 高功率降压型同步DC / DC控制器
| 型号： | APW7057KC-TRL |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | High Power Step-Down Synchronous DC/DC Controller |
| 文件： | 总15页 (文件大小：419K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7057
High Power Step-Down Synchronous DC/DC Controller
Features
General Description
·
·
Operates from +5V Input
The APW7057 is a 300kHz constant frequency voltage
mode synchronous switching controller that drives exter-
nal N-channel MOSFETs. When the input supply drops
close to output, the upper MOSFET remains on, achiev-
ing 100% duty cycle. Internal loop compensation is opti-
mized for fast transient response, eliminating external
compensation network. The precision 0.8V reference
makes this part suitable for a wide variety of low voltage
applications. Soft-start is internally set to 2ms, limiting
the input in-rush current and preventing the output from
overshoot during powering up.
0.8V Internal Reference Voltage
- ±1.5% Accuracy Over Line, Load and
Temperature
·
·
0.8V to VCC Output Range
Full Duty Cycle Range
- 0% to 100%
·
·
Internal Loop Compensation
Internal Soft-Start
The APW7057 has over current and short circuit
protections. Over current protection is achieved by moni-
toring the voltage drop across the high side MOSFET,
eliminating the need for a current sensing resistor and
short circuit condition is detected through the FB pin. If
either fault conditions occur, the APW7057 would initiate
the soft-start cycle. After three cycles and if the fault condi-
tion persists, the controller will be shut down. To restart
the controller, either recycle the VCC supply or momen-
tarily pull the OSCSET pin below 1.25V.
- Typical 2ms
·
Programmable Over-Current Protection
- Lossless Sensing Using MOSFET RDS (ON)
Under-Voltage Protection
Drives External N-Channel MOSFETs
Shutdown Control
·
·
·
·
·
Small SOP-8 Package
Lead Free and Green Devices Avaliable
(RoHS Compliant)
The APW7057 can be shutdown by pulling the OCSET
pin below 1.25V. In shutdown, both gate drive signals will
be low. The controller is available in a small SOP-8
package.
Applications
·
·
·
·
·
·
·
Motherboard
Pin Configuration
Graphics Cards
Cable or DSL Modems, Set Top Boxes
DSP Supplies
PHASE
OCSET
BOOT
1
2
3
4
8
7
UGATE
Memory Supplies
6
5
GND
FB
5V Input DC-DC Regulators
Distributed Power Supplies
LGATE
VCC
SOP-8 (Top View )
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.5 - Jun., 2008
APW7057
Ordering and Marking Information
Package Code
K : SOP-8
Operating Junction Temperature Range
APW7057
°
C : 0 to 70 C
Handling Code
Assembly Material
Handling Code
TR : Tape & Reel
Assembly Material
Temperature Range
Package Code
L : Lead Free Device G : Halogen and Lead Free Device
APW7057
XXXXX
APW7057 K :
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
Parameter
Rating
-0.3 ~ 7
Unit
V
VCC Supply Voltage (VCC to GND)
VCC
BOOT Supply Voltage (BOOT to GND)
PHASE, OCSET to GND Input Voltage
FB to GND Input Voltage
VBOOT
-0.3 ~ 15
-0.3 ~ 12
-0.3 ~ VCC+0.3
125
V
V
V
oC
oC
oC
Maximum Junction Temperature
Storage Temperature
TSTG
TSDR
-65 ~ 150
260
Maximum Lead Soldering Temperature, 10 Seconds
Thermal Characteristics
Symbol
Parameter
Junction-to-Ambient Resistance in Free Air
Typical Value
Unit
qJA
oC/W
SOP-8
160
Recommended Operating Conditions
Symbol
VCC
VOUT
VIN
Parameter
Range
Unit
V
VCC Supply Voltage
±
5
5%
Output Voltage of the Switching Regulator (Note)
Input Voltage of the Switching Regulator (Note)
Ambient Temperature
0.8 ~ VCC
3.3 ~ VCC
0 ~ 70
V
V
TA
oC
oC
Junction Temperature
TJ
0 ~ 125
Note : Refer to the typical application circuit
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Rev. A.5 - Jun., 2008
APW7057
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC=5V, VBOOT=12V and TA= 0~70 oC. Typical values are
at T =25oC.
A
APW7057
Unit
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
SUPPLY CURRENT
IVCC
VCC Nominal Supply Current
BOOT Nominal Supply Current
UGATE and LGATE Open
-
-
2.1
2.1
-
-
mA
mA
IBOOT
UGATE Open
UNDER VOLTAGE LOCKOUT (UVLO)
Rising VCC Threshold
4.0
3.8
4.2
4.0
4.4
4.2
V
V
Falling VCC Threshold
OSCILLATOR
FOSC
Free Running Frequency
Ramp Upper Threshold
Ramp Lower Threshold
Ramp Amplitude
250
300
2.85
0.95
1.9
340
kHz
V
-
-
-
-
-
-
V
D
VOSC
VP-P
REFERENCE VOLTAGE
VREF Reference Voltage
Reference Voltage Accuracy
-
0.8
-
-
V
-1.5
+1.5
%
ERROR AMPLIFIER
DC Gain
-
-
75
10
1
-
-
dB
Hz
kHz
%
FP
FZ
First Pole Frequency
First Zero Frequency
UGATE Duty Range
FB Input Current
-
-
0
-
-
100
0.1
-
mA
PWM CONTROLLER GATE DRIVERS
UGATE Source
VUAGTE=1V
VUGATE=1V
VLGATE=1V
VLGATE=1V
-
-
-
-
-
0.6
7.3
0.6
1.8
50
-
-
-
-
-
A
W
A
UGATE Sink
LGATE Source
LGATE Sink
W
nS
TD
Dead Time
PROTECTION
IOCSET
UVFB
OCSET Sink Current
VOCSET=4.5V
FB falling
34
-
40
0.5
15
46
-
mA
V
FB Under-Voltage Level
FB Under-Voltage Hysteresis
-
-
mV
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Rev. A.5 - Jun., 2008
APW7057
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC=5V, VBOOT=12V and TA= 0~70 oC. Typical values are
at T =25oC.
A
APW7057
Unit
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
SOFT-START AND SHUTDOWN
TSS
Soft-Start Interval
-
-
-
2
-
-
-
mS
V
Shutdown Threshold
OCSET Shutdown Hysteresis
VOCSET Falling
1.25
20
mV
Function Pin Description
BOOT (Pin 1)
OCSET (Pin 7)
This pin provides the supply voltage to the high side
MOSFET driver. A voltage no greater than 13V can be con-
nected to this pin as a supply to the driver. For driving
logic level N-channel MOSEFT, a bootstrap circuit can be
use to create a suitable driver’s supply.
This pin serves two functions: as a shutdown control and
for setting the over current limit threshold. Pulling this pin
below 1.25V shuts the controller down, forcing the UGATE
and LGATE signals to be at 0V. A soft-start cycle will be
initiated upon the release of this pin.
A resistor (Rocset) connected between this pin and the drain
of the high side MOSFET will determine the over current
limit. An internally generated 40mA current source will flow
through this resistor, creating a voltage drop. This volt-
age will be compared with the voltage across the high
side MOSFET. The threshold of the over current limit is
therefore given by:
UGATE(Pin 2)
This pin provides gate drive for the high-side MOSFET.
GND (Pin 3)
Signal and power ground for the IC. All voltage levels are
measured with respect to this pin. Tie this pin to the ground
plane through the lowest impedance connection available.
40uA x ROCSET
IOI =
LGATE(Pin 4)
RDS(ON)
This pin provides the gate drive signal for the low side
MOSFET.
An over current condition will cycle the soft-start function.
After three consecutive cycles and if the fault condition
persists, the controller will be shut down. To restart the
controller, either recycle the VCC supply or momentarily
pull the OSCSET pin below 1.25V.
VCC (Pin 5)
This is the main bias supply for the controller and its low
side MOSFET driver. Must be closely decoupled to GND
(Pin 3). DO NOT apply a voltage greater than 5.5V to this
pin.
PHASE (Pin 8)
This pin is connected to the source of the high-side
MOSFET and is used to monitor the voltage drop across
the high-side MOSFET for over-current protection.
FB (Pin 6)
This pin is the inverting input of the error amplifier and it
receives the feedback voltage from an external resistive
divider across the output (VOUT). The output voltage is de-
termined by:
ROUT
RGND
VOUT = 0.8V(1+
)
where ROUT is the resistor connected between VOUT
and FB while RGND is the resistor connected from FB to
GND.
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Rev. A.5 - Jun., 2008
APW7057
Block Diagram
VCC
BOOT
Shutdown
UnderVoltage
Lockout
OCSET
IOCSET
40mA
OC
UVLO
Comparator
Soft-Start
and Fault
Logic
OCP
PHASE
UGATE
0.5V
UVP
Soft-Start
Inhibit
Gate
Control
PWM
COMP
FB
-
VCC
+
+
-
Error
Amplifier
REF
V
LGATE
GND
0.8V
OSC
F
Oscillator
300kHz
Figure 1.
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Rev. A.5 - Jun., 2008
APW7057
Typical Application Circuit
R3
2.2
C3
1uF
V
IN
+5V
5
+
C2
1000uF x2
C1
1uF
D1
C7
R4
VCC
1N4148
470pF
8.2k
1
2
8
BOOT
7
OCSET
C4
0.1uF
Q3
Q1
Q2
UGATE
PHASE
L1
3.3uH
VOUT
+2.5V/10A
Shutdown
+
U1
APW7057
LGATE
C5
1000uF x2
4
6
FB
GND
3
R1
5.1k
R2
2.4k
C6
0.1uF
Q1: APM2014N UC
Q2: APM2014N UC
Q3: 2N7002
C2: 1000uF/10V, ESR = 25mW
C5: 1000uF/6.3V, ESR = 25mW
Figure 2.
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Rev. A.5 - Jun., 2008
APW7057
Typical Operating Characteristics
Switching Frequency vs. Junction Temperature
Reference Voltage vs. Junction Temperature
350
340
330
320
310
300
290
280
270
260
250
0.812
0.808
0.804
0.800
0.796
0.792
0.788
-50
-25
0
25
50
75
100 125 150
-50 -25
0
25
50
75 100 125 150
Junction Temperature (oC)
Junction Temperature (°C)
OCSET Current vs. Junction Temperature
46
45
44
43
42
41
40
39
38
37
36
35
34
-50
-25
0
25
50
75
100 125 150
Junction Temperature (oC)
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Rev. A.5 - Jun., 2008
APW7057
Operating Waveforms (Refer to the typical application circuit)
1. Load Transient Response : IOUT = 0A -> 10A -> 0A
- IOUT slew rate = ±10A/mS
IOUT = 0A -> 10A
IOUT = 0A -> 10A -> 0A
IOUT = 10A -> 0A
VOUT
VOUT
VOUT
VUGATE
VUGATE
10A
IOUT
IOUT
IOUT
0A
Ch1 : VOUT, 100mV/Div, DC,
Offset = 2.50V
Ch1 : VOUT, 100mV/Div, DC,
Offset = 2.50V
Ch1 : VOUT, 100mV/Div, DC,
Offset = 2.50V
Ch2 : VUGATE, 10V/Div, DC
Ax1 : IOUT, 5A/Div
Time : 10mS/Div
Ax1 : IOUT, 5A/Div
Time : 100mS/Div
BW = 20MHz
Ch2 : VUGATE, 10V/Div, DC
Ax1 : IOUT, 5A/Div
Time : 10mS/Div
BW = 20MHz
BW = 20MHz
2. UGATE and LGATE
UGATERising
UGATEFalling
IOUT=10A
IOUT=10A
VUGATE
VUGATE
VLGATE
VLGATE
Ch1 : VUGATE, 2V/Div, DC
Time : 125nS/Div
Ch2 : VLGATE, 2V/Div, DC
BW = 500MHz
Ch1 : VUGATE, 2V/Div, DC
Time : 125nS/Div
Ch2 : VLGATE, 2V/Div, DC
BW = 500MHz
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Rev. A.5 - Jun., 2008
APW7057
Operating Waveforms (Cont.)
(Refer to the typical application circuit)
3. Powering ON / OFF
Soft-Start at Powering ON
VIN
PoweringOFF
VIN
VOUT
VOUT
Ch1 : VIN, 2V/Div, DC
Time : 5mS/Div
Ch2 : VOUT, 1V/Div, DC
BW = 20MHz
Ch1 : VIN, 2V/Div, DC
Time : 1mS/Div
Ch2 : VOUT, 1V/Div, DC
BW = 20MHz
4. Short-Circuit Protection
Under-Voltage (UVP)
UVP
and Over-Current Protection (OCP)
OCP
OCP
Ch1 : VOUT, 1V/Div, DC
Ax1 : IOUT, 10A/Div
Time : 1mS/Div
VOUT
BW = 20MHz
IOUT
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Rev. A.5 - Jun., 2008
APW7057
Application Information
Component Selection Guidelines
Output Capacitor Selection
The maximum ripple current occurs at the maximum in-
put voltage. A good starting point is to choose the ripple
current to be approximately 30% of the maximum output
current.
The selection of COUT is determined by the required effec-
tive series resistance (ESR) and voltage rating rather than
the actual capacitance requirement. Therefore, select high
performance low ESR capacitors that are intended for
switching regulator applications. In some applications,
multiple capacitors have to be paralled to achieve the
desired ESR value. If tantalum capacitors are used, make
sure they are surge tested by the manufactures. If in doubt,
consult the capacitors manufacturer.
Once the inductance value has been chosen, select an
inductor that is capable of carrying the required peak cur-
rent without going into saturation. In some types of
inductors, especially core that is make of ferrite, the ripple
current will increase abruptly when it saturates. This will
result in a larger output ripple voltage.
MOSFETSelection
Input Capacitor Selection
The selection of the N-channel power MOSFETs are de-
termined by the RDS(ON), reverse transfer capacitance (CRSS
)
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select
the capacitor voltage rating to be at least 1.3 times higher
than the maximum input voltage. The maximum RMS
current rating requirement is approximately IOUT/2 , where
IOUT is the load current. During power up, the input capaci-
tors have to handle large amount of surge current. If tanta-
lum capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capacitors
and maximum output current requirement.The losses in
the MOSFETs have two components: conduction loss and
transition loss. For the upper and lower MOSFET, the
losses are approximately given by the following equations:
PUPPER = Io2ut (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
PLOWER = Io2ut (1+ TC)(RDS(ON))(1-D)
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tsw is the switching interval
manufacturer.
For high frequency decoupling, a ceramic capacitor be-
tween 0.1mF to 1mF can be connected between VCC and
ground pin.
D is the duty cycle
Inductor Selection
Note that both MOSFETs have conduction losses while
the upper MOSFET includes an additional transition loss.
The switching internal, tsw, is the function of the reverse
transfer capacitance CRSS. Figure 3 illustrates the switch-
ing waveform internal of the MOSFET.
The inductance of the inductor is determined by the out-
put voltage requirement. The larger the inductance, the
lower the inductor’s current ripple. This will translate into
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
VIN - VOUT
Fs x L
VOUT
VIN
Layout Consideration
x
IRIPPLE
=
In high power switching regulator, a correct layout is im-
portant to ensure proper operation of the regulator. In
general, interconnecting impedances should be mini-
mized by using short, wide printed circuit traces. Signal
and power grounds are to be kept separate and finally
combined using ground plane construction or single point
grounding. Figure 4 illustrates the layout, with bold lines
indicating high current paths. Components along the bold
lines should be placed close together.
DVOUT = IRIPPLE x ESR
where Fs is the switching frequency of the regulator.
There is a tradeoff exists between the inductor’s ripple
current and the regulator load transient response time. A
smaller inductor will give the regulator a faster load tran-
sient response at the expense of higher ripple current
and vice versa.
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Rev. A.5 - Jun., 2008
APW7057
Application Information
Layout Consideration (Cont.)
V
IN
Below is a checklist for your layout:
CHF
· Keep the switching nodes (UGATE, LGATE, and
PHASE) away from sensitive small signal nodes since
these nodes are fast moving signals. Therefore, keep
traces to these nodes as short as possible.
C
IN
5
1
VCC
BOOT
+
· Decoupling capacitor CIN provides the bulk capacitance
4
and needs to be placed close to the IC since it will
provide the MOSFET drivers transient current
requirement.
LGATE
APW7057
2
8
COUT
UGATE
Q1
Q2
+
· The ground return of CIN must return to the combine
COUT (-) terminal.
PHASE
L1
V
OUT
· Capacitor CBOOT should be connected as close to the
BOOT and PHASE pins as possible.
Figure 4. Recommended Layout Diagram
· Capacitor CHF is to improve noise performance and a
small 1mF ceramic capacitor will be sufficient.
VDS
t
Time
sw
Figure 3. Switching waveform across MOSFET
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Rev. A.5 - Jun., 2008
APW7057
Package Information
SOP-8
D
SEE VIEW A
°
b
c
e
GAUGE PLANE
SEATING PLANE
L
VIEW A
SOP-8
S
Y
M
B
O
L
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
0.069
0.010
A
1.75
0.25
0.004
0.049
0.012
0.007
0.10
1.25
0.31
0.17
4.80
5.80
3.80
A1
A2
b
0.020
0.010
0.51
0.25
5.00
6.20
4.00
c
D
0.189
0.228
0.150
0.197
0.244
0.157
E
E1
e
1.27 BSC
0.050 BSC
0.010
0.016
0.020
0.050
0.25
0.40
0.50
1.27
h
L
°
°
0
0
8
0
8
Note: 1. Follow JEDEC MS-012 AA.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
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Rev. A.5 - Jun., 2008
APW7057
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
SOP-8
A
H
T1
C
d
D
W
E1
F
12.4+2.00 13.0+0.50
330.0±
2.00
50 MIN.
1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00
-0.20
P0
P1
P2
D0
D1
T
A0
6.40±0.20 5.20±0.20 2.10±0.20
(mm)
B0
K0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10 8.0±0.10 2.0±0.05
1.5 MIN.
Devices Per Unit
Package Type
SOP-8
Unit
Tape & Reel
Quantity
2500
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Rev. A.5 - Jun., 2008
APW7057
Reflow Condition (IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
°
t 25 C to Peak
Time
Reliability Test Program
Test item
SOLDERABILITY
Method
Description
245°C, 5 sec
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
HOLT
PCT
TST
ESD
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Latch-Up
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Average ramp-up rate
(TL to TP)
Preheat
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
183°C
60-150 seconds
217°C
60-150 seconds
- Time (tL)
Peak/Classification Temperature (Tp)
See table 1
See table 2
Time within 5°C of actual
Peak Temperature (tp)
10-30 seconds
20-40 seconds
Ramp-down Rate
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package. Measured on the body surface.
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Rev. A.5 - Jun., 2008
APW7057
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350
<2.5 mm
³ 2.5 mm
240 +0/-5°C
225 +0/-5°C
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350-2000
Volume mm3
>2000
<1.6 mm
1.6 mm – 2.5 mm
³ 2.5 mm
260 +0°C*
260 +0°C*
250 +0°C*
260 +0°C*
250 +0°C*
245 +0°C*
260 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the
stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C)
at the rated MSL level.
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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www.anpec.com.tw
Rev. A.5 - Jun., 2008
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