APW7065 [ANPEC]
Synchronous Buck PWM Controller; 同步降压PWM控制器
| 型号： | APW7065 |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Synchronous Buck PWM Controller |
| 文件： | 总19页 (文件大小：763K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7065
Synchronous Buck PWM Controller
Features
General Description
TheAPW7065usesfixed300KHzswitchingfrequency,
voltage mode, synchronous PWM controller which
drivesdualN-channelMOSFETs. Thedeviceintegrates
the control, monitoring and protection functions into a
single package, provides one controlled power output
with under-voltage and over-current protections.
·
·
Single 12V Power Supply Required
Fast Transient Response
- 0~90% Duty Ratio
·
·
0.8V Reference with 1% Accuracy
Shutdown Function by Controlling
COMP Pin Voltage
The APW7065 provides excellent regulation for output
load variation. The internal 0.8V temperature-
compensated reference voltage is designed to meet
the requirement of low output voltage applications. An
built-in digital soft-start with fixed soft-start interval
prevents the output voltage from overshoot as well as
limiting the input current.
·
·
·
·
Internal Soft-Start (3.4ms) Function
Voltage Mode PWM Control Design
Under-VoltageProtection
Over-CurrentProtection
- Sense Low Side MOSFET’s RDS(ON)
300KHz Fixed Switching Frequency
·
·
·
The APW7065 with excellent protection functions:
POR, OCP and UVP. The Power-On Reset (POR)
circuit can monitor VCC supply voltage exceeds its
threshold voltage while the controller is running, and a
built-in digital soft-start provides output with controlled
voltage rise. The Over-Current Protection (OCP)
monitors the output current by using the voltage drop
across the lower MOSFET’s RDS(ON), comparing with
internal VOCP (0.27V), when the output current reaches
the trip point, the controller will run the soft-start
function until the fault events are removed. The Under-
Voltage Protection (UVP) monitors the voltage of FB
pin for short-circuit protection, when the VFB is less
than 50% of VREF (0.4V), the controller will shutdown
the IC directly.
SOP-8 Package
Lead FreeAvailable (RoHSCompliant)
Applications
·
·
Graphics Card
Mother Board
Pinouts
BOOT
UGATE
GND
PHASE
COMP
FB
1
2
8
7
6
5
3
4
LGATE
VCC
SOP-8
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
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APW7065
Ordering and Marking Information
PackageCode
APW 7065
K : SOP-8
OperatingAmbientTemp. Range
E : -20 to 70 °C
LeadFreeCode
HandlingCode
Temp.Range
PackageCode
HandlingCode
TU : Tube
TR : Tape & Reel
LeadFreeCode
L : Lead Free Device
Blank : Original Device
APW7065
XXXXX
APW7065 K :
XXXXX-DateCode
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.
Block Diagram
VCC
GND
BOOT
Power-On
Reset
UGATE
Sense Low Side
O.C.P
Comparator
Digital
Soft Start
PHASE
0.27V
U.V.P
50%VREF
Comparator
:
2
Error Amp
PWM
Comparator
Gate Control
LGATE
VREF
Sawtooth
Wave
Oscillator
FOSC
300KHz
FB
COMP
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APW7065
Application Circuit
1N4148
12V
VIN (12V)
1uH
2.2R
1uF
1uF
470uFx2
470uF
5
1
VCC
BOOT
0.1uF
Q1
2
8
APM2509
UGATE
PHASE
1uH
(1.2V)
VOUT
Q3
2N7002
7
6
COMP
FB
Q2
APM2506
ON/OFF
4
470uFx2
LGATE
33nF
8.2nF
GND
3
2.7K
1K
2K
18R
68nF
Absolute Maximum Ratings
Symbol
VCC
Parameter
Rating
Unit
V
VCC to GND
-0.3 ~ 16
-0.3 ~ 16
V
BOOT
BOOT to PHASE
UGATE to PHASE
<400nS pulse width
>400nS pulse width
-5 ~ BOOT+5
-0.3 ~ BOOT+0.3
UGATE
V
LGATE to GND
PHASE to GND
<400nS pulse width
>400nS pulse width
<400nS pulse width
>400nS pulse width
-5 ~ VCC+5
-0.3 ~ VCC+0.3
-5 ~ 21
LGATE
PHASE
V
V
-0.3 ~ 16
-0.3 ~ 7
-20 ~ 150
-65 ~ 150
300
V
COMP, FB
TJ
COMP, FB to GND
oC
oC
oC
kV
Junction Temperature Range
TSTG
Storage Temperature
TSDR
Maximum Soldering Temperature, 10 Seconds
VESD
Minimum ESD Rating (Human Body Mode) (Note 2)
±2
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 2: The device is ESD sensitive. Handling precautions are recommended.
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APW7065
Recommended Operating Conditions
Symbol
VCC
VOUT
VIN
Parameter
VCC Supply Voltage
Range
10.8 ~ 13.2
0.8 ~ 5
Unit
V
Converter Output Voltage
Converter Input Voltage
V
V
2.9 ~ 13.2
0 ~ 20
IOUT
TA
A
Converter Output Current
Ambient Temperature Range
Junction Temperature Range
-20 ~ 70
-20 ~ 125
oC
oC
TJ
Electrical Characteristics
Unless otherswise specified, these specifications apply over VCC=12V, and TA=-20~70oC. Typlcal values are at
TA=25oC.
APW7065
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max
SUPPLY CURRENT
UGATE and LGATE Open
5
1
10
2
mA
mA
IVCC
VCC Nominal Supply Current
VCC Shutdown Supply Current UGATE, LGATE = GND
POWER-ON RESET
Rising VCC Threshold
9
9.5
8
10
V
V
V
Falling VCC Threshold
7.5
8.5
COMP Shutdown Threshold
COMP Shutdown Hysteresis
1.2
0.1
V
OSCILLATOR
FOSC Free Running Frequency
Ramp Amplitude
255
-1.0
300
1.6
345
kHz
VP-P
D
VOSC
REFERENCE VOLTAGE
VREF Reference Voltage
Accuracy
Measured at FB Pin
0.8
V
+1.0
%
°
TA =-20~70 C
ERROR AMPLIFIER
Gain Open Loop Gain
L
L
R =10k, C =10pF(Note3)
88
15
6
dB
MHz
V/us
uA
GBWP
SR
L
L
Open Loop Bandwidth
Slew Rate
R =10k, C =10pF(Note3)
L
L
R =10k, C =10pF(Note3)
FB Input Current
COMP High Voltage
VFB = 0.8V(Note3)
0.1
5.5
0
1
VCOMP
V
VCOMP COMP Low Voltage
V
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APW7065
Electrical Characteristics (Cont.)
Unless otherswise specified, these specifications apply over VCC=12V and TA =-20~70oC. Typlcal values are
atTA=25oC.
APW7065
Unit
Symbol
Parameter
Test Conditions
Min Typ Max
ERROR AMPLIFIER (Cont.)
ICOMP
COMP Source Current
VCOMP=2V
5
5
mA
mA
ICOMP COMP Sink Current
VCOMP=2V
GATE DRIVERS
IUGATE Upper Gate Source Current
IUGATE Upper Gate Sink Current
BOOT = 12V, VUGATE -VPHASE = 2V
BOOT = 12V, VUGATE -VPHASE = 2V
2.6
A
A
1.05
ILGATE Lower Gate Source Current
ILGATE Lower Gate Sink Current
VCC = 12V, VLGATE = 2V
VCC = 12V, VLGATE = 2V
4.9
1.4
A
A
Upper Gate Source Impedance BOOT = 12V, IUGATE = 0.1A
2
RUGATE
RUGATE
3
W
W
W
W
nS
Upper Gate Sink Impedance
BOOT = 12V, IUGATE = 0.1A
1.6
2.4
RLGATE Lower Gate Source Impedance VCC = 12V, ILGATE = 0.1A
1.3 1.95
Lower Gate Sink Impedance
Dead Time
VCC = 12V, ILGATE = 0.1A
1.25
20
RLGATE
TD
1.88
PROTECTIONS
VOCP Over-Current Reference Voltage
0.23 0.27 0.31
V
TA =-20~70°C
Under-Voltage Threshold
Trip Point
VUVP
Percent of VREF
45
50
55
%
SOFT-START
TSS Soft-Start Interval
2
3.4
5
ms
Note 3: Guaranteed by design.
Functional Pin Description
GND (Pin 3)
BOOT (Pin 1)
TheGNDterminal providesreturnpathfor theIC’sbias
current and the low-side MOSFET driver’s pull-low
current. Connect thepin to the system ground viavery
low impedance layout on PCBs.
A bootstrap circuit with a diode connected to VCC is
used to create a voltage suitable to drive a logic-level
N-channel MOSFET.
UGATE (Pin 2)
LGATE(Pin 4)
Connect thispintothehigh-sideN-channel MOSFET’s
gate. This pin provides gate drive for the high-side
MOSFET.
Connect thispinto thelow-side N-channel MOSFET’s
gate. This pin provides gate drive for the low-side
MOSFET.
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APW7065
Functional Pin Description (Cont.)
VCC (Pin 5)
FB pin is also monitored for under voltage events.
Connect this pin to a 12V supply voltage. This pin
provides bias supply for the control circuitry and the
low-side MOSFET driver. The voltage at this pin is
monitored for the Power-On Reset (POR) purpose. It
is recommended that a decoupling capacitor (1 to
10uF) be connected to GNDfor noise decoupling.
COMP (Pin 7)
Thispin isthe output of PWM error amplifier. It isused
to set the compensation components. In addition, if
the pin is pulled below 1.2V, it will disable the device.
PHASE (Pin 8)
FB (Pin 6)
This pin is the return path for the upper gate driver.
This pin is the inverting input of the internal error Connect this pin to the upper MOSFET source. This
amplifier. Connect this pin to the output (VOUT) of the pin isalso used to monitor the voltage drop acrossthe
converter via an external resistor divider for closed- MOSFET for over-current protection.
loop operation. The output voltage set by the resistor
divider is determined using the following formula :
R1
R2
æ
ö
VOUT = 0.8 ´ 1+
ç
÷
è
ø
where R1 is the resistor connected from VOUT to FB ,
and R2 is the resistor connected from FB toGND. The
Typical Characteristics
Power On
PowerOff
VCC=12V, Vin=12V
Vo=1.2V, L=1uH
CH1
CH2
VCC=12V, Vin=12V
Vo=1.2V, L=1uH
CH1
CH2
CH3
CH3
CH4
CH4
CH1: VCC (5V/div)
CH2: VFB (1V/div)
CH3: Vo (1V/div)
CH4: Ug (20/Vdiv)
Time: 10ms/div
CH1: VCC (5V/div)
CH2: VFB (1V/div)
CH3: Vo (1V/div)
CH4: Ug (20/Vdiv)
Time: 10ms/div
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APW7065
Typical Characteristics (Cont.)
Shutdown
EN
VCC=12V, Vin=12V
Vo=1.2V, L=1uH
VCC=12V, Vin=12V
Vo=1.2V, L=1uH
CH1
CH1
CH2
CH3
CH2
CH3
CH4
CH4
CH1: VCOMP (2V/div)
CH2: Vo (1V/div)
CH3: Ug (20V/div)
CH4: Lg (10Vdiv)
Time: 5ms/div
CH1: VCOMP (2V/div)
CH2: Vo (1V/div)
CH3: Ug (20V/div)
CH4: Lg (10Vdiv)
Time: 20us/div
UGATE Rising
UGATE Falling
VCC=12V, Vin=12V
Vo=1.2V, L=1uH
Iout=5A
VCC=12V, Vin=12V
Vo=1.2V, L=1uH
Iout=5A
CH1
CH1
CH2
CH3
CH2
CH3
CH1: IL (10A/div)
CH2: Vo (1V/div)
CH3: Ug (20V/div)
CH4: Lg(10V/div)
Time: 100us/div
CH1: Ug (20V/div)
CH2: Lg (5V/div)
CH3: Phase (10V/div)
Time: 50ns/div
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APW7065
Typical Characteristics (Cont.)
Load Transient Response
Under Voltage Protection
VCC=12V, Vin=12V
Vo=1.2V, L=1uH
VCC=12V, Vin=12V
Vo=1.2V, L=4.7uH
CH1
CH2
CH1
0
10A
CH3
CH4
0A
CH2
CH1: IL (10A/div)
CH2: Vo (1V/div)
CH3: Ug (20V/div)
CH4: Lg (10V/div)
Time: 100us/div
CH1: Vo (500mV/div,AC)
CH2:Io (5A/div)
Time: 1ms/div
1
2
1
2
Over Current Protection
Short Test
VCC=12V, Vin=12V,Vo=1.2V, L=1uH,
L_side: APM2023, Rds(on)=17mΩ
VCC=12V, Vin=12V
Vo=1.2V, L=1uH
CH1
CH2
CH1
CH2
CH3
CH4
CH3
CH4
CH1: IL (10A/div)
CH2: Vo (2V/div)
CH3: Ug (20V/div)
CH4: Lg (10V/div)
Time: 2ms/div
CH1: IL (10A/div)
CH2: Vo (2V/div)
CH3: Ug (20V/div)
CH4: Lg (10V/div)
Time: 5ms/div
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APW7065
Typical Characteristics (Cont.)
Switching Frequency vs. Junction Temperature
ReferenceVoltage vs. JunctionTemperature
0.804
310
VCC=12V
VCC=12V
305
300
295
290
285
280
275
0.802
0.8
0.798
0.796
0.794
0.792
-40 -20
0
20 40 60 80 100 120
-40
-20
0
20
40
60
80
100
120
Junction Temperature (°C)
Junction Temperature (°C)
UGATE Source Current vs. UGATE Voltage
UGATE Sink Current vs. UGATEVoltage
3.5
3
VBOOT=12V
VBOOT=12V
PHASE=2V
2.5
3
PHASE=2V
2.5
2
2
1.5
1
1.5
1
0.5
0
0.5
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
UGATEVoltage (V)
UGATEVoltage (V)
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APW7065
Typical Characteristics (Cont.)
LGATE Sink Current vs. LGATE Voltage
LGATE Source Current vs. LGATEVoltage
6
3.5
3
2.5
2
VCC=12V
5
VCC=12V
4
3
2
1
0
1.5
1
0.5
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
LGATEVoltage (V)
LGATEVoltage (V)
Functional Description
Power On Reset (POR)
seconds and then begin soft start. During soft-start,
an internal ramp connected to the one of the positive
inputs of the Gm amplifier rises up from 0V to 2V to
replace the reference voltage (0.8V) until the ramp
voltage reaches the reference voltage. The soft-start
interval is decided by the oscillator frequency
(300kHz). The formulation is given by:
The Power-On Reset (POR) function of APW7065
continually monitors the input supply voltage (VCC)
and the COMP pin. The supply voltage (VCC) must
exceed its rising POR threshold voltage. The POR
function initiates soft-start operation after VCC and
COMP voltages exceed their POR thresholds. For
operation with a single +12V power source, VIN and
VCC are equivalent and the +12V power source must
exceed the rising VCC threshold. The POR function
inhibits operation at disabled status (VCOMP is less
than 1.2V). With both input supplies above their POR
thresholds, the device initiates a soft-start interval.
Tdelay = t2 - t1 = 2048/FOSC = 6.8ms
Tsoft- start = t3 - t2 =1024/FOSC =3.4ms
Soft-Start
Figure 2. shows more detail of the FB voltage ramp.
The FB voltage soft-start ramp is formed with many
small steps of voltage. The voltage of one step is about
12.5mV in FB, and the period of one step is about 16/
FOSC. This method provides a controlled voltage rise
The APW7065 has a built-in digital soft-start to con-
trol the output voltage rise and limit the current surge
during the start-up. In Figure 1, when VCC exceeds
rising POR threshold voltage, it will delay 2048/Fosc
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APW7065
Functional Description (Cont.)
Soft-Start (Cont.)
- TheMOSFET’sRDS(ON) isvariedbytemperatureand
gate to source voltage, the user should de-
termine the maximum RDS(ON) in manufacturer’s
datasheet.
and prevents the large peak current to charge output
capacitor.
Voltage(V)
- The minimum Vocset should be usedin the above
equation.
- Note that the ILIMIT is the current flow through the
lower MOSFET; ILIMIT must be greater than maxi-
mum output current add the half of inductor ripple
current.
VCC
VOUT
Shutdown and Enable
Pulling the COMP voltage to GND by an open drain
transistor, shown in typical application circuit,
shutdown theAPW7065PWM controller. In shutdown
mode, the UGATE and LGATE turn off and pull to
PHASE andGNDrespectively.
Time
t1
t2 t3
Figure 1.
Voltage(V)
FB
Under Voltage Protection
12.5mV
The FB pin is monitored during converter operation by
the internal Under Voltage (UV) comparator. If the FB
voltage drops below 50% of the reference voltage (50%
of 0.8V = 0.4V), a fault signal is internally generated,
and the device turns off both high-side and low-side
MOSFET and the converter’s output is latched to be
floating.
16/Fosc
Time
Figure 2.
Over-Current Protection
Theover-current protectionmonitorsthe output current
by using the voltage drop acrossthe lower MOSFET’s
Application Information
RDS(ON) and thisvoltage dropwill be compared with the Output Voltage Selection
internal 0.27V reference voltage. If the voltage drop
The output voltage can be programmed with a resistive
across the lower MOSFET’s RDS(ON) is larger than
0.27V, an over-current condition is detected. The
threshold of the over current limit is given by:
divider. Use 1% or better resistors for the resistive
divider is recommended. The FB pin is the inverter
input of the error amplifier, and the reference voltage
is 0.8V. The output voltage is determined by:
0.27
ILimit
=
RDS(ON)
æ
ç
è
ö
R OUT
R GND
ç
÷
÷
ø
VOUT = 0.8 ´ 1 +
For the over-current is never occurred in the normal
operating load range; the variation of all parameters in
the above equation should be determined.
Where ROUT is the resistor connected from VOUT to FB
and RGND is the resistor connected from FB to GND.
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APW7065
Application Information (Cont.)
Output Inductor Selection
capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capacitors
manufacturer.
The inductor value determines the inductor ripple
current and affects the load transient response. Higher
inductor value reduces the inductor’s ripple current and Input Capacitor Selection
induces lower output ripple voltage. The ripple current
The input capacitor is chosen based on the voltage
and ripple voltage can be approximated by:
rating and the RMS current rating. For reliable
operation, select the capacitor voltage rating to be at
least 1.3 times higher than the maximum input voltage.
The maximum RMS current rating requirement is
approximately IOUT/2, where IOUT is the load current.
During power up, the input capacitors have to handle
large amount of surge current. If tantalum capacitors
are used, make sure they are surge tested by the
manufactures. If in doubt, consult the capacitors
manufacturer. For high frequency decoupling, a ceramic
capacitor 1uF can be connected between the drain of
upper MOSFET and the source of lower MOSFET.
VIN - VOUT
FS ´ L
VOUT
VIN
IRIPPLE
=
´
DVOUT = IRIPPLE ´ ESR
where FS is the switching frequency of the regulator.
Although increase of the inductor value reduces the
ripple current and voltage, a tradeoff willexist between
the inductor’s ripple current and the regulator load
transient response time.
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple
current. The maximum ripple current occurs at the
maximum input voltage. A good starting point is to
choose the ripple current to be approximately 30%
of the maximum output current. Once the inductance
value has been chosen, select an inductor that is ca-
pable of carrying the required peak current without
going into saturation. In some types of inductors, es-
pecially core that is made of ferrite, the ripple current
will increase abruptly when it saturates. This will re-
sult in a larger output ripple voltage.
MOSFET Selection
The selection of the N-channel power MOSFETs are
determined by the RDS(ON), reverse transfer capacitance
(CRSS)andmaximumoutputcurrentrequirement. There
are two components of loss in the MOSFETs:
conduction loss and transition loss. For the upper
and lower MOSFET, the losses are approximately
given by the following:
PUPPER = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FS
PLOWER = IOUT (1+ TC)(RDS(ON))(1-D)
Output Capacitor Selection
Where IOUT is the load current
Higher capacitor value and lower ESR reduce the
output ripple and the load transient drop. Therefore,
selecting high performance low ESR capacitors is
intended for switching regulator applications. In some
applications, multiple capacitors have to be parallel to
achieve the desired ESR value. A small decoupling
capacitor in parallel for bypassing the noise is also
recommended, and the voltage rating of the output
capacitors also must be considered. If tantalum
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tSW is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction loss while
the upper MOSFET include an additional transition
loss. The switching internal, tSW, is a function of the
reverse transfer capacitance CRSS. The (1+TC) term is
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APW7065
Application Information (Cont.)
MOSFET Selection (Cont.)
FLC
to factor in the temperature dependency of the RDS(ON)
and can be extracted from the “RDS(ON) vs Temperature”
curve of the power MOSFET.
-40dB/dec
PWM Compensation
FESR
The output LC filter of a step down converter introduces
a double pole, which contributes with -40dB/decade
gain slope and 180 degrees phase shift in the control
loop. A compensation network among COMP, FB and
VOUT should be added. The compensation network is
shown in Fig. 6. The output LC filter consists of the
output inductor and output capacitors. The transfer
-20dB/dec
Frequency(Hz)
Figure 4. The LC Filter GAIN and Frequency
function of the LC filter is given by:
The PWM modulator is shown in Figure 5. The input
is the output of the error amplifier and the output is the
PHASE node. The transfer function of the PWM
modulator is given by:
VIN
GAIN
=
PWM
DVOSC
1 + s ´ ESR ´ COUT
s2 ´ L ´ COUT + s ´ ESR ´ COUT + 1
GAIN
=
LC
VIN
Driver
The poles and zero of this transfer functions are:
1
OSC
PWM
Comparator
ΔVOSC
FLC
=
2 ´ p ´ L ´ COUT
PHASE
Output of
Error Amplifier
1
FESR
=
2 ´ p ´ ESR ´ COUT
Driver
The FLC is the double poles of the LC filter, and FESR is
the zero introduced by the ESR of the output capacitor.
Figure 5. The PWM Modulator
The compensation network is shown in Figure 6. It
provides a close loop transfer function with the highest
zero crossover frequency and sufficient phase margin.
The transfer function of error amplifier is given by:
PHASE
L
OUTPUT
COUT
1
1
sC2
1
æ
ö
÷
// R2 +
ç
VCOMP
VOUT
sC1
è
æ
ø
GAIN
=
=
AMP
ö
ESR
R1// R3 +
ç
÷
sC3
è
ø
æ
ö
ö
1
1
æ
s +
´ çs +
÷
÷
ç
÷
ç
R2 ´ C2
(
R1+ R3
)
´ C3
R1+ R3
è
ø
è
ø
=
´
Figure 3. The Output LC Filter
C1+ C2
1
R1´ R3 ´ C1
æ
ö æ
ö
s s +
´
s +
ç
÷ ç
÷
R2 ´ C1´ C2
R3 ´ C3
è
ø è
ø
Copyright ã ANPEC Electronics Corp.
13
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Rev. A.1 - Feb., 2006
APW7065
Application Information (Cont.)
PWM Compensation (Cont.)
Calculate the C2 by the equation:
1
The poles and zeros of the transfer function are:
1
C2 =
2 ´ p ´ R2 ´ FLC ´ 0.75
FZ1
=
4.Set the pole at the ESR zero frequency FESR
FP1 = FESR
:
2 ´ p ´ R2 ´ C2
1
FZ2
=
2 ´ p ´
(
R1 + R3 ´ C3
)
Calculate the C1 by the equation:
C2
1
FP1
=
C1 =
C1´ C2
C1 + C2
æ
ö
÷
2 ´ p ´ R2 ´ C2 ´ FESR - 1
2 ´ p ´ R2 ´
ç
è
ø
5.Set the second pole FP2 at the half of the switching
frequency and also set the second zero FZ2 at the
output LC filter double pole FLC. The compensation
gain should not exceed the error amplifier open loop
gain, check the compensation gain at FP2 with the
capabilities of the error amplifier.
1
FP2
=
2 ´ p ´ R3 ´ C3
C1
R3
C3
C2
R2
VOUT
FB
VCOMP
R1
FP2 = 0.5 X FO
FZ2 = FLC
VREF
Figure 6. Compensation Network
Combine the two equations will get the following
component calculations:
The closed loop gain of the converter can be written
as:
R1
FS
R3 =
GAINLC X GAINPWM X GAINAMP
- 1
2 ´ FLC
Figure 7. shows the asymptotic plot of the closed loop
converter gain, and the following guidelines will help
to design the compensation network. Using the below
guidelines should give a compensation similar to the
curve plotted. A stable closed loop has a -20dB/ decade
slope and a phase margin greater than 45 degree.
1
C3 =
p ´ R3 ´ FS
FZ1 FZ2 FP1
FP2
1.Choose a value for R1, usually between 1K and 5K.
2.Select the desired zero crossover frequency FO:
(1/5 ~ 1/10) X FS >FO>FESR
Compensation
Gain
20log
(R2/R1)
20log
(VIN/ΔVOSC)
Use the following equation to calculate R2:
FLC
DVOSC FO
FESR
R2 =
´
´ R1
Converter
Gain
VIN
F
LC
PWM & Filter
Gain
3.Place the first zero FZ1 before the output LC filter
double pole frequency FLC.
Frequency(Hz)
Figure 7. Converter Gain and Frequency
FZ1 = 0.75 X FLC
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Feb., 2006
APW7065
Application Information (Cont.)
the resistor dividers, and boot capacitors should
be close their pins. (For example, place the
decoupling ceramic capacitor near the drain of the
high-side MOSFET as close as possible. The bulk
capacitors are also placed near the drain).
LayoutConsiderations
In any high switching frequency converter, a correct
layout is important to ensure proper operation of the
regulator. With power devices switching at 300KHz,
the resulting current transient will cause voltage spike
across the interconnecting impedance and parasitic
circuit elements. As an example, consider the turn-off
transition of the PWM MOSFET. Before turn-off, the
MOSFET is carrying the full load current. During
turn-off, current stops flowing in the MOSFETand is
free-wheeling by the lower MOSFET and parasitic
diode. Any parasitic inductance of the circuit generates
a large voltage spike during the switching interval. In
general, using short, wide printed circuit traces
should minimize interconnecting impedances and
the magnitude of voltage spike. And signal and power
grounds are to be kept separate till combined using
ground plane construction or single point grounding.
Figure 8. illustrates the layout, with bold lines indicating
high current paths; these traces must be short and
wide. Components along the bold lines should be
placed lose together. Below is a checklist for your
layout:
- The input capacitor should be near the drain of
the upper MOSFET; the output capacitor should
be near the loads. The input capacitor GND should
be close to the output capacitor GND and the lower
MOSFETGND.
- The drain of the MOSFETs (VIN and PHASE
nodes) should be a large plane for heat sinking.
APW7065
VIN
VCC
BOOT
L
O
A
D
UGATE
PHASE
LGATE
VOUT
Figure 8.Layout Guidelines
- Keep the switching nodes (UGATE, LGATE and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals.
Therefore, keep traces to these nodes as short as
possible.
- The traces from the gate drivers to the MOSFETs
(UG, LG) should be short and wide.
- Place the source of the high-side MOSFET and
the drain of the low-side MOSFET as close
possible. Minimizing the impedance with wide
layout plane between the two pads reduces the
voltage bounce of the node.
- Decoupling capacitor, compensation component,
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Feb., 2006
APW7065
Package Information
SOP-8 pin (Reference JEDEC Registration MS-012)
E
H
e1
e2
D
A1
A
1
L
0.004max.
Millimeters
Inches
Dim
Min.
1.35
0.10
4.80
3.80
5.80
0.40
0.33
Max.
1.75
0.25
5.00
4.00
6.20
1.27
0.51
Min.
Max.
0.069
0.010
0.197
0.157
0.244
0.050
0.020
A
A1
D
0.053
0.004
0.189
0.150
0.228
0.016
0.013
E
H
L
e1
e2
1.27BSC
0.50BSC
0°
8°
0°
8°
f
1
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Feb., 2006
APW7065
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition (IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
°
t 25 C to Peak
Time
Classificatin Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Sn-Pb Eutectic Assembly
Pb-Free Assembly
°
°
3 C/second max.
3 C/second max.
Preheat
°
°
150 C
100 C
-
-
-
Temperature Min (Tsmin)
Temperature Max (Tsmax)
Time (min to max) (ts)
°
°
150 C
200 C
60-120 seconds
60-180 seconds
Time maintained above:
°
°
183 C
217 C
-
Temperature (TL)
Time (tL)
60-150 seconds
60-150 seconds
-
Peak/Classificatioon Temperature (Tp)
See table 1
See table 2
°
Time within 5 C of actual
10-30 seconds
20-40 seconds
Peak Temperature (tp)
Ramp-down Rate
°
°
6 C/second max.
6 C/second max.
6 minutes max.
8 minutes max.
°
Time 25 C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Feb., 2006
APW7065
Classification Reflow Profiles (Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350
<2.5 mm
°
°
240 +0/-5 C
225 +0/-5 C
³ 2.5 mm
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350-2000
Volume mm3
>2000
<1.6 mm
1.6 mm – 2.5 mm
³ 2.5 mm
°
°
°
260 +0 C*
260 +0 C*
260 +0 C*
260 +0°C*
250 +0°C*
250 +0°C*
245 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
°
including the stated classification temperature (this means Peak reflow temperature +0 C.
°
°
For example 260 C+0 C) at the rated MSL level.
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
Description
245 C, 5 SEC
1000 Hrs Bias @125 C
°
°
%
°
168 Hrs, 100 RH, 121 C
TST
ESD
Latch-Up
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
°
°
-65 C~150 C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Carrier Tape & Reel Dimensions
t
D
P
Po
E
P1
Bo
F
W
Ko
Ao
D1
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Rev. A.1 - Feb., 2006
APW7065
Carrier Tape & Reel Dimensions (Cont.)
T2
J
C
A
B
T1
Reel Dimensions
Application
A
B
C
J
T1
330 ± 1 62 +1.5 12.75+ 0.15 2 ± 0.5 12.4 ± 0.2 2 ± 0.2
D1 Po P1 Ao
T2
W
P
E
12± 0. 3
8± 0.1 1.75±0.1
Ko
SOP- 8
F
D
Bo
t
5.5± 1 1.55 +0.1 1.55+ 0.25 4.0 ± 0.1 2.0 ± 0.1 6.4 ± 0.1 5.2± 0. 1 2.1± 0.1 0.3±0.013
(mm)
Cover Tape Dimensions
Application
SOP- 8
Carrier Width
Cover Tape Width
Devices Per Reel
12
9.3
2500
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright ã ANPEC Electronics Corp.
Rev. A.1 - Feb., 2006
19
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