APW7068ME-TUL [ANPEC]
Synchronous Buck PWM and Linear Controller with 0.8V Reference Out Voltage; 同步降压PWM和线性控制器具有0.8V参考输出电压
| 型号： | APW7068ME-TUL |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Synchronous Buck PWM and Linear Controller with 0.8V Reference Out Voltage |
| 文件： | 总26页 (文件大小：1600K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7068
Synchronous Buck PWM and Linear Controller with 0.8V Reference Out Voltage
General Description
Features
The APW7068 integrates synchronous buck
PWM, linear controller, and 0.8V Reference Out Voltage,
as well as the monitoring and protection functions
into a single package. The fixed 300KHz switching
frequency synchronous PWM controller drives
dualN-channelMOSFETs, whichprovidesonecontrolled
power output with over-voltage and over-current
protections. Linear controller drives an external
N-channel MOSFET with under-voltage protection.
·
Two Regulated Voltages and REF_OUT
- Synchronous Buck Converter
- Linear Regulator
- REF_OUT = 0.8V±1% with 3mA source current
·
·
Single 12V Power Supply Required
Excellent Both Output Voltage Regulation
- 0.8V Internal Reference
- ±1% Over Line Voltage and Temperature
·
·
·
Integrated Soft-Start for PWM and Linear Outputs
300KHz Fixed Switching Frequency
The APW7068 provides excellent regulation for
output load variation. An internal 0.8V temperature-
compensated reference voltage is designed to meet
the requirement of low output voltage applications.
Voltage Mode PWM Control Design and Up to
89%(Typ.) Duty Cycle
·
Under-Voltage Protection Monitoring Linear
Output
The APW7068 with excellent protection functions:
POR, OCP, OVP and UVP. The Power-On Reset
(POR) circuit can monitor VCC12 supply voltage
exceeds its threshold voltage while the controller is
running, and a built-in digital soft-start provides both
outputs with controlled rising voltage. The Over-Current
Protection (OCP) monitors the output current by using
·
·
Over-Voltage Protection Monitoring PWM Output
Over-Current Protection for PWM Output
- Sense Low-side MOSFET’s RDS(ON)
SOP-14, QSOP-16 and QFN-16 packages
·
·
Lead FreeAvailable (RoHS Compliant)
the voltage drop across the lower MOSFET’s RDS(ON)
,
comparing with the voltage of OCSET pin. When the out-
put current reaches the trip point, the controller will
shutdown the IC directly, and latch the converter’s
output. The Under-Voltage Protection (UVP) monitors
the voltage of FBL pin for short-circuit protection. When
the VFBL is less than 50% of VREF, the controller will
shutdown the IC directly. The Over-Voltage Protection
(OVP) monitors the voltage of FB. When the VFB is
over 135% of VREF, the controller will make Low-
side gate signal fully turn on until the fault events are
removed.
Applications
·
Graphic Cards
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Jun., 2006
APW7068
Pinouts
16 15
14 13
BOOT
FS_DIS
COMP
FB
UGATE
PHASE
PGND
BOOT
FS_DIS
COMP
FB
UGATE
PHASE
PGND
1
2
3
4
5
6
7
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COMP
1
2
12
11
PGND
FB
LGATE
Metal GND
Pad
(Bottom)
LGATE
LGATE
DRIVE
3
4
10
9
OCSET
DRIVE
FBL
OCSET
OCSET
DRIVE
FBL
REF_OUT
REF_OUT
FBL
REF_OUT
GND
VCC12
GND
VCC12
VCC12
8
5
6
7
8
GND
SOP-14
TOP VIEW
QSOP-16
TOP VIEW
QFN-16
TOP VIEW
Ordering and Marking Information
Package Code
APW7068
K : SOP - 14 M : QSOP - 16 QA : QFN - 16
Temp. Range
E : -20 to 70 C
Lead Free Code
°
Handling Code
TU : Tube
TY : Tray (for QFN only)
Lead Free Code
L : Lead Free Device Blank : Original Device
Handling Code
Temp. Range
Package Code
TR : Tape & Reel
APW7068
APW7068 K :
APW7068 M :
XXXXX - Date Code
XXXXX - Date Code
XXXXX
APW7068
XXXXX
XXXXX - Date Code
APW7068 Q :
APW7068
XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for
MSL classification at lead-free peak reflow temperature.
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Rev. A.2 - Jun., 2006
APW7068
Block Diagram
OCSET
VCC12
IOCSET
40uA
Reference
REF_OUT
Buffer
Power-On
Reset
Regulator
BOOT
GND
UGATE
O.C.P
Comparator
10V
VREF
(0.8V)
Soft Start
and
Fault
135%VREF
X1.35
O.V.P
Comparator
PHASE
Logic
Sense Low Side
Gate Control
LGATE
PGND
Error
Amp 1
PWM
U.V.P
Comparator
Comparator
FBL
10V
:
2
50%VREF
DRIVE
VREF
Error
Amp 2
Oscillator
FS_DIS
VREF
Sawtooth Wave
(300KHz)
COMP
FB
Absolute Maximum Ratings
Symbol
VCC12
BOOT
Parameter
Rating
Unit
V
-0.3 to +16
-0.3 to +16
VCC12 to GND
V
BOOT to PHASE
UGATE to PHASE <400ns pulse width
>400ns pulse width
-5 to BOOT+5
-0.3 to BOOT+0.3
V
V
UGATE
LGATE
LGATE to PGND
PHASE to GND
DRIVE to GND
<400ns pulse width
>400ns pulse width
-5 to VCC12+5
-0.3 to VCC12+0.3
<400ns pulse width
>400ns pulse width
-5 to +21
-0.3 to 16
PHASE
DRIVE
V
V
V
12
FB, FBL, COMP,
FS_DIS
-0.3 to 7
FB, FBL, COMP, FS_DIS to GND
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Rev. A.2 - Jun., 2006
APW7068
Absolute Maximum Ratings (Cont.)
Symbol
Parameter
Rating
Unit
PGND
TJ
PGND to GND
-0.3 to +0.3
-20 to +150
-65 ~ 150
300
V
Junction Temperature Range
Storage Temperature
°C
°C
TSTG
TSDR
VESD
°C
Soldering Temperature (10 Seconds)
Minimum ESD Rating
KV
±2
NOTE1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTE2: The device is ESD sensitive. Handling precautions are recommended.
Recommended Operating Conditions
Symbol
VCC12
VIN1
Parameter
Rating
10.8 to 13.2
2.9 to 13.2
0.9 to 5
Unit
V
IC Supply Voltage
V
Converter Input Voltage
Converter Output Voltage
Converter Output Current
Linear Output Current
V
VOUT1
IOUT1
IOUT2
TA
0 to 30
A
0 to 3
A
-20 to 70
-20 to 125
°C
°C
Ambient Temperature Range
Junction Temperature Range
TJ
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC12=12V, and TA =-20~70°C. Typical values
are at TA=25°C.
APW7068
Symbol
Parameter
Test Conditions
Unit
Min
Typ Max
INPUT SUPPLY CURRENT
VCC12 Supply Current
UGATE, LGATE and DRIVE
open; FS_DIS=GND
4
8
6
mA
mA
(Shutdown mode)
ICC12
UGATE, LGATE and DRIVE
open
VCC12 Supply Current
12
POWER-ON RESET
Rising VCC12 Threshold
Falling VCC12 Threshold
OSCILLATOR
7.7
7.2
7.9
7.4
8.1
7.6
V
V
Accuracy
-15
+15
345
%
FOSC
VOSC
Duty
Oscillator Frequency
255
300
1.5
89
KHz
(nominal 1.2V to 2.7V)
(NOTE3)
Ramp Amplitude
V
Maximum Duty Cycle
%
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Rev. A.2 - Jun., 2006
APW7068
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC12=12V, and TA =-20~70°C. Typical values
are at TA=25°C.
APW7068
Symbol
Parameter
Test Conditions
Unit
Min
Typ Max
REFERENCE
VREF
Reference Voltage
for Error Amp1 and Amp2
0.792 0.80 0.808
V
Reference Voltage Tolerance
PWM Load Regulation
-1
+1
1
%
%
%
IOUT1=0 to 10A
IOUT2=0 to 3A
Linear Load Regulation
1
PWM ERROR AMPLIFIER
Gain
GBWP
SR
Open Loop Gain
RL=10k, CL=10pF (NOTE3)
RL=10k, CL=10pF (NOTE3)
RL=10k, CL=10pF (NOTE3)
VFB=0.8V
93
20
8
dB
MHz
V/us
uA
Open Loop Bandwidth
Slew Rate
FB Input Current
0.1
5
1
VCOMP
VCOMP
ICOMP
ICOMP
COMP High Voltage
COMP Low Voltage
COMP Source Current
COMP Sink Current
V
0
V
COMP=2V
COMP=2V
12
12
mA
mA
GATE DRIVERS
IUGATE
IUGATE
ILGATE
ILGATE
RUGATE
RUGATE
RLGATE
RLGATE
TD
Upper Gate Source Current
2.5
2
A
A
BOOT=12V,
UGATE-PHASE = 2V
Upper Gate Sink Current
Lower Gate Source Current
Lower Gate Sink Current
2.5
3.5
2.25
0.7
2.25
0.4
20
A
A
VCC12=12V, LGATE=2V
Upper Gate Source Impedance BOOT=12V, IUGATE=0.1A
Upper Gate Sink Impedance BOOT=12V, IUGATE=0.1A
Lower Gate Source Impedance VCC12=12V, ILGATE=0.1A
3.375
1.05
3.375
0.6
W
W
W
W
nS
Lower Gate Sink Impedance
Dead Time
VCC12=12V, ILGATE=0.1A
LINEAR REGULATOR
Open Loop Gain
RL=10k, CL=10pF (NOTE3)
RL=10k, CL=10pF (NOTE3)
RL=10k, CL=10pF (NOTE3)
VFBL=0.8V
dB
MHz
V/us
uA
Gain
GBWP
SR
70
19
6
Open Loop Bandwidth
Slew Rate
FBL Input Current
DRIVE High Voltage
DRIVE Low Voltage
DRIVE Source Current
DRIVE Sink Current
0.1
10
0
1
V
VDRIVE
VDRIVE
IDRIVE
IDRIVE
V
DRIVE=5V
DRIVE=5V
mA
mA
4
3
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Rev. A.2 - Jun., 2006
APW7068
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC12=12V, and TA =-20~70°C. Typical values
are at TA=25°C.
APW7068
Symbol
Parameter
Test Conditions
Unit
Min
Typ Max
PROTECTION
FB Over Voltage Protection Trip Point
Percent of VREF
%
%
VFB-OV
VFBL-UV
IOCSET
135
50
FBL Under Voltage Protection Trip Point Percent of VREF
OCSET Current Source
36
40
44
uA
SOFT START
TSS
Internal Soft-Start Interval (NOTE3)
FOSC=300kHz
8.5
ms
REF_OUT
VREF_OUT Output Voltage
Offset Voltage
0.800
0.792
-8
0.808
+8
V
mV
mA
mA
uF
IREF_OUT Source Current
Sink Current
3
0.5
1
1.5
0.25
0.4
Output Capacitance
2.2
NOTE3: Guaranteed by design.
Typical Application Circuit
C1
2.2nF
VIN1
Q3
CIN1
470uFx2
12V
ON/OFF
2N7002
R2
C2
Q1
APM2509
0.01uF
3.9K
L
VOUT1
1.2V
C4
R1
VOUT1
1uH
0.1uF
1.5K
R3
C3
22nF
22W
UGATE
1
2
3
4
5
6
7
14
13
12
11
10
9
BOOT
FS_DIS
COMP
FB
PHASE
PGND
RGND1
3K
VIN2
3.3V
COUT1
470uFx2
C6
Q2
2.2nF
LGATE
OCSET
APM2506
CIN2
Q4
APM3055
470uF
R6
DRIVE
FBL
2.2W
R5
C5
REF_OUT
VCC12
8
GND
R4
VOUT2
2.5V
C8
1uF
2.5K
APW7068
R7
12V
COUT2
470uF
RGND2
1.17K
2.2W
R8
C7
1uF
* C5, R5 for specific application
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Rev. A.2 - Jun., 2006
APW7068
Function Pin Descriptions
LGATE
VCC12
This pin is the gate driver for the lower MOSFET of
PWM output.
Power supply input pin. Connect a nominal 12V power
supplyto this pin. The power-on reset function monitors
the input voltage at this pin. It is recommended that a
decoupling capacitor (1 to 10mF) be connected toGND
for noise decoupling.
DRIVE
This pin drives the gate of an external N-channel
MOSFET for linear regulator. It is also used to set the
compensation for some specific applications,for
example, with low values of output capacitance and
ESR.
BOOT
This pin provides the bootstrap voltage to the upper
gate driver for driving the N-channel MOSFET. An
external capacitor from PHASE to BOOT, an internal
diode, and the power supplyvaltage VCC12, generates
thebootstrap voltagefor theupper gatediver (UGATE).
FBL
This pin is the inverting input of the linear regulator
error amplifier. It is used to set the output voltage.
This pin is also monitored for under-voltage protection.
When the FBL voltage is under 50% of reference
voltage (0.4V), both outputs will be shutdown
immediately.
PHASE
This pin is the return path for the upper gate driver.
Connect this pin to the upper MOSFET source, and
connect a capacitor to BOOT for the bootstrap voltage.
This pin is also used to monitor the voltage drop across
the lower MOSFET for over-current protection.
OCSET
Connect a resistor (Rocset) from this pin to GND, an
internal 40uA current source will flow through this
resistor and create a voltage drop. When VCC12
reaches the POR rising threshold voltage, the voltage
drop of Rocset will be memoried and compared with
the voltage across the lower MOSFET. The threshold
of the over current limit is therefore given by:
GND
This pin is the signal ground pin. Connect theGNDpin
to a good ground plane.
PGND
This pin is the power ground pin for the lower gate
driver. It should be tied to GND pin on the board.
I
OCSET ´ ROCSET
I
LIMIT
=
COMP
RDS(ON)(LOW - Side)
This pin is the output of PWM error amplifier. It is used
to set the compensation components.
REF_OUT
This pin provides a buffed voltage, which is from internal
reference voltage. It is recommended that a 1uF
capacitor is connected to ground for stability.
FB
ThispinistheinvertinginputofthePWMerror amplifier.
It is used to set the output voltage and the compensation
components. This pin is also monitored for over-voltage FS_DIS
protection. When the FB voltage is over 135% of
This pin provides shutdown function. Use an open drain
reference voltage, the controller will make Low-side
gate signal fully turn on until the fault events are
removed.
logic signal to pull this pin low to disable both outputs,
leave open to enable both outputs.
UGATE
This pin is the gate driver for the upper MOSFET of
PWM output.
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Rev. A.2 - Jun., 2006
APW7068
Typical Characteristics
PowerOff
Power On
VCC12=12V,Vin1=12V,Vin2=3.3V
VCC12=12V,Vin1=12V,Vin2=3.3V
Vo1=1.2V,Vo2=2.5V,L=1uH
Vo1=1.2V,Vo2=2.5V,L=1uH
CH1
CH1
CH2
CH2
CH3
CH3
CH1: VCC12 (10V/div)
CH2: Vo1 (1V/div)
CH3: Vo2 (2V/div)
Time: 10ms/div
CH1: VCC12 (10V/div)
CH2: Vo1 (1V/div)
CH3: Vo2 (2V/div)
Time: 10ms/div
EN
Shutdown(FS_DIS=GND)
VCC12=12V,Vin1=12V,Vin2=3.3V
Vo1=1.2V,Vo2=2.5V,L=1uH
VCC12=12V,Vin1=12V,Vin2=3.3V
Vo1=1.2V,Vo2=2.5V,L=1uH
CH1
CH2
CH1
CH2
CH3
CH4
CH3
CH4
CH1: FS_DIS (1V/div)
CH2: Drive (5V/div)
CH3: Vo1 (1V/div)
CH4: Vo2 (2V/div)
Time: 10ms/div
CH1: FS_DIS (1V/div)
CH2: Drive (5V/div)
CH3: Vo1 (1V/div)
CH4: Vo2 (2V/div)
Time: 10ms/div
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Rev. A.2 - Jun., 2006
APW7068
Typical Characteristics
(Cont.)
UGATE Falling
UGATE Rising
Vcc12=12V,Vin1=12V, Vo1=1.2V
Vcc12=12V,Vin1=12V,Vo1=1.2V
CH1
CH1
CH2
CH3
CH2
CH3
CH1: Ug (20V/div)
CH1: Ug (20V/div)
CH2: Phase (10V/div)
CH3: Lg (10V/div)
Time: 50ns/div
CH2: Phase (10V/div)
CH3: Lg (10V/div)
Time: 50ns/div
OVP_PWM Controller (FB > 135% VREF
)
UVP_Linear Regulator (FBL< 50% VREF)
Vcc12=12V,Vin1=12V
VCC12=12V,Vin2=3.3V
Vo2=2.5V,Io2=3A
Vo1=1.2V,Vo2=2.5V,L=1uH
CH1
CH2
CH1
CH2
CH3
CH3
CH4
CH1: VCC (20V/div)
CH2: LG (10V/div)
CH3: Vo1 (500mV/div)
CH4: Vo2 (2V/div)
Time: 10ms/div
CH1: FBL (1V/div)
CH2: Drive (5V/div)
CH3: Vo2 (2V/div)
Time: 100us/div
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Rev. A.2 - Jun., 2006
APW7068
Typical Characteristics
(Cont.)
Load Transient Response(PWM Controller)
- VCC12=12V, Vin1=12V, Vo1=2V, Fosc=300KHz
- Io1 slew rate= ± 10 A/us
Io1=0Aà10Aà0A
Io1=10Aà0A
Io1=0Aà10A
CH1
CH1
CH1
CH2
CH3
CH2
CH3
CH2
CH3
CH1: Vo1 (100mV/div,AC)
CH2: Ug (20V/div)
CH1: Vo1 (100mV/div,AC)
CH2: Ug (20V/div)
CH1: Vo1 (100mV/div,AC)
CH2: Ug (20V/div)
CH3: Io1(10A/div)
CH3: Io1(10A/div)
CH3: Io1(10A/div)
Time: 20us/div
Time: 50us/div
Time: 20us/div
Load Transient Response(Linear Regulator)
- VCC12=12V, Vin2=3.3V, Vo2=2.5V
- Io2 slew rate= ± 3A/us
Io2=0Aà3Aà0A
Io2=3Aà0A
Io2=0Aà3A
CH1
CH1
CH1
CH2
CH2
CH2
CH1: Vo2 (100mV/div,AC)
CH2: Io2(2A/div)
CH1: Vo2 (100mV/div,AC)
CH2: Io2(2A/div)
CH1: Vo2 (100mV/div,AC)
CH2: Io2(2A/div)
Time: 1us/div
Time: 10us/div
Time: 1us/div
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Rev. A.2 - Jun., 2006
APW7068
Typical Characteristics
(Cont.)
Short Test after Power Ready
Over Current Protection
VCC12=12V, Vin1=12V,
Vo1=1.2V,Vin2=3.3V,
Vo2=2.5V, L=1uH,
COUT=470uFx2
Rocset=1KΩ , Rds(on)=4mΩ
VCC12=12V, Vin1=12V,
Vo1=1.2V,Vin2=3.3V,
COUT=470uFx2
Vo2=2.5V, L=1uH,
Rocset=1KΩ , Rds(on)=4mΩ
CH1
CH2
CH1
CH2
CH3
CH4
CH3
CH4
CH1: Vo1 (1V/div)
CH2:Drive (5V/div)
CH3: Ug (20V/div)
CH4: IL (10A/div)
Time: 50us/div
CH1: Vo1 (1V/div)
CH2:Drive (5V/div)
CH3: Ug (20V/div)
CH4: IL (10A/div)
Time: 50us/div
Short Test before Power On
VREF vs. Junction Temperature
0.804
0.8035
0.803
VCC12=12V, Vin1=12V,Vin2=3.3V
Vo1=1.2V,Vo2=2.5V,L=1uH
COUT=470uFx2
CH1
CH2
0.8025
0.802
VREF
CH3
CH4
0.8015
0.801
0.8005
-40
-20
0
20
40
60
80
100 120
CH1: VCC12 (10V/div)
CH2: Vo1 (1V/div)
CH3: Ug (20V/div)
CH4: IL (10A/div)
Time: 2ms/div
Junction Temperature (°C )
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Rev. A.2 - Jun., 2006
APW7068
Typical Characteristics
(Cont.)
UGATE Source Current vs. UGATE Voltage
UGATE Sink Current vs. UGATE Voltage
3
3.5
3
2.5
2
VBOOT=12V
PHASE=0V
VBOOT=12V
PHASE=0V
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
2
4
6
8
10
12
0
0.5
1
1.5
2
2.5
3
UGATE Voltage (V)
UGATE Voltage (V)
LGATE Source Current vs. LGATE Voltage
LGATE Sink Current vs. LGATE Voltage
7
3
6
2.5
VCC=12V
VCC=12V
5
4
3
2
1
0
2
1.5
1
0.5
0
0
2
4
6
8
10
12
0
1
2
3
4
LGATE Voltage (V)
LGATE Voltage (V)
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Rev. A.2 - Jun., 2006
APW7068
Function Descriptions
Power On Reset (POR)
Voltage(V)
The Power-On Reset (POR) function of APW7068
continually monitors the input supply voltage (VCC12),
ensures the supply voltage exceed its rising POR
threshold voltage. The POR function initiates soft-start
interval operation while VCC12 voltages exceed their
POR threshold and inhibits operation under disabled
status.
VCC12
POR
VOUT1
VOUT2
Soft-Start
Figure 1. shows the soft-start interval. When VCC12
reaches the rising POR threshold voltage, the internal
reference voltage is controlled to follow a voltage pro-
portional to the soft-start voltage. The soft-start inter-
val is variable by the oscillator frequency. The formu-
lation is given by:
t0
t1
t2
Time
Figure 1. Soft-Start Interval
Voltage(V)
FB
1
TSS = D(t2 - t1) =
´ 2560
FOSC
FBL
20mV
32/Fosc
Figure 2. shows more detail of the FB and FBL voltage
ramps. The FB and FBL voltage soft-start ramps are
formed with many small steps of voltage. The voltage
of one step is about 20mV in FB and FBL, and the
period of one step is about 64/FOSC. This method pro-
vides a controlled voltage rise and prevents the large
peak current to charge output capacitor. The FB volt-
age compares the FBLvoltage to shift to an earlier time
theestablishmentasFigure2.Thevoltageestabilishment
32/Fosc
20mV
Time
t3
t4
Figure 2. The Controlled Stepped FB and FBL
Voltage during Soft-Start
Over-Current Protection
time difference for FB and FBL is variable by the Connect a resistor (Rocset) from this pin to GND, an
internal 40uA current source will flow through this
resistor and create a voltage drop, which will be
compared with the voltage across the lower MOSFET.
When the voltage across the lower MOSFET exceeds
the voltage drop across the ROCSET, an over-current
condition is detected and the controller will shut-
down the IC directly, and the converter's output is
latched.
oscillator. The formulation is given by:
1
1
D(t4 - t3) =
´ 640 = ´ TSS
FOSC
4
Copyright ã ANPEC Electronics Corp.
13
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Rev. A.2 - Jun., 2006
APW7068
Function Descriptions
Over-Current Protection (Cont.)
voltage is over 135% of the reference voltage, the
controller will make Low-Side gate signal fully turn on
until the fault events are removed.
The threshold of the over current limit is therefore
given by:
Under Voltage Protection
I
OCSET ´ ROCSET
I
LIMIT
=
R
DS(ON)(LOW - Side)
The FBL pin is monitored during converter opera-
tion by its own Under Voltage(UV) comparator. If
the FBL voltage drop below 50% of the reference
voltage (50% of 0.8V = 0.4V), a fault signal is inter-
nally generated, and the device turns off both high-
side and low-side MOSFET and the converter’s out-
put is latched to be floating. The controller will shut-
down the IC directly.
For the over-current is never occurred in the normal
operating load range; the variation of all parameters in
the above equation should be determined.
· The MOSFET’s RDS(ON) is varied by temperature and
gate to source voltage, the user should determine the
maximum RDS(ON) in manufacturer’s datasheet.
· The minimum IOCSET (36uA) and minimum ROCSET
should be used in the above equation.
Shutdown and Enable
Pulling the FS_DIS voltage to GND by an open drain
transistor, shown in typical application circuit,
· Note that the ILIMIT is the current flow through the
lower MOSFET; ILIMIT must be greater than maximum
output current add the half of inductor ripple current.
shutdown theAPW7068 PWM controller. In shutdown
mode, the UGATE and LGATE turn off and pull to
PHASE and GND respectively.
Over Voltage Protection
The FB pin is monitored during converter operation
by its own Over Voltage(OV) comparator. If the FB
Application Information
Output Voltage Selection
The linear regulator output voltage VOUT2 is also set by
means of an external resistor divider. The FBL pin is
the inverter input of the error amplifier, and the reference
voltage is 0.8V. The output voltage is determined by:
TheoutputvoltageofPWMconvertercanbeprogrammed
with a resistive divider. Use 1% or better resistors for
the resistive divider is recommended. The FB pin is
the inverter input of the error amplifier, and the reference
voltage is 0.8V. The output voltage is determined by:
æ
ç
è
ö
÷
÷
ø
R4
ç
VOUT2 = 0.8 ´ 1+
RGND2
æ
ç
è
ö
÷
÷
ø
R1
ç
VOUT1 = 0.8 ´ 1+
RGND1
Where R4 is the resistor connected from VOUT2 to
FBL and RGND2 is the resistor connected from FBL to
GND.
Where R1 is the resistor connected from VOUT1 to FB
and RGND1 is the resistor connected from FB to GND.
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Jun., 2006
APW7068
Application Information (Cont.)
Linear Regulator Input/Output Capacitor Selection
loop. A compensation network among COMP, FB and
VOUT1 should be added. The compensation network is
shown in Fig. 9. The output LC filter consists of the
output inductor and output capacitors. The transfer
function of the LC filter is given by:
The input capacitor is chosen based on its voltage
rating. Under load transient condition, the input
capacitor will momentarily supply the required transient
current. The output capacitor for the linear regulator is
chosen to minimize any droop during load transient
condition. In addition, the capacitor is chosen based
on its voltage rating.
1+ s´ ESR´ COUT1
GAINLC
=
s2 ´ L´ COUT1 + s´ ESR´ COUT1 +1
The poles and zero of this transfer functions are:
Linear Regulator Input/Output MOSFET Selection
The maximum DRIVE voltage is about 10V when
VCC12 is equal 12V. Since this pin drives an external
N-channel MOSFET, therefore the maximum output
voltage of the linear regulator is dependent upon the
1
FLC
=
2 ´ p ´ L ´ COUT1
1
FESR
=
2 ´ p ´ ESR ´ COUT1
VGS.
= 10 - VGS
The FLC is the double poles of the LC filter, and FESR is
the zero introduced by the ESR of the output capacitor.
VOUT2MAX
Another criterion is its efficiency of heat removal. The
power dissipated by the MOSFET is given by:
PHASE
L
OUTPUT1
Pd = IOUT2 x (VIN – VOUT2
)
COUT1
Where IOUT2 is the maximum load current, VOUT2 is the
nominal output voltage.
ESR
In some applications, heatsink might be required to
help maintain the junction temperature of the MOSFET
below its maximum rating.
Figure 6. The Output LC Filter
Linear Regulator Compensation Selection
FLC
The linear regulator is stable over all loads current.
However, thetransientresponsecanbefurtherenhanced
by connecting a RC network between the FBL and
DRIVE pin. Depending on the output capacitance and
load current of the application, the value of this RC
network is then varied.
-40dB/dec
FESR
-20dB/dec
PWM Compensation
The output LC filter of a step down converter introduces
a double pole, which contributes with -40dB/decade
gain slope and 180 degrees phase shift in the control
Frequency(Hz)
Figure 7. The LC Filter GAIN and Frequency
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Jun., 2006
APW7068
Application Information (Cont.)
PWM Compensation (Cont.)
C1
The PWM modulator is shown in Figure 8. The input
is the output of the error amplifier and the output is the
R3
C3
R2
C2
VOUT1
PHASE node. The transfer function of the PWM
modulator is given by:
FB
VCOMP
R1
VREF
V
IN1
GAINPWM
=
Figure 9. Compensation Network
DVOSC
VIN
The closed loop gain of the converter can be written
as:
Driver
OSC
PWM
ΔVOSC
Comparator
GAINLC X GAINPWM X GAINAMP
PHASE
Output of
Error Amplifier
Figure 10. shows the asymptotic plot of the closed
loop converter gain, and the following guidelines will
help to design the compensation network. Using the
below guidelines should give a compensation similar
to the curve plotted. A stable closed loop has a -20dB/
decade slope and a phase margin greater than 45
degree.
Driver
Figure 8. The PWM Modulator
The compensation network is shown in Figure 9. It
provides a close loop transfer function with the highest
zero crossover frequency and sufficient phase margin.
The transfer function of error amplifier is given by:
1.Choose a value for R1, usually between 1K and 5K.
2.Select the desired zero crossover frequency FO:
(1/5 ~ 1/10) X FS >FO>FESR
1
1
æ
ö
÷
// R2+
ç
VCOMP
VOUT1
sC1
sC2
è
ø
GAINAMP
=
=
1
æ
ö
Use the following equation to calculate R2:
R1// R3 +
ç
÷
sC3
è
ø
DVOSC FO
æ
ö
1
1
æ
ö
÷
R2 =
´
´ R1
s +
´ çs +
÷
÷
ç
ç
VIN
FLC
R2 ´ C2
(
R1+ R3
)
´ C3
R1+ R3
è
ø
è
ø
=
´
C1+ C2
1
R1´ R3 ´ C1
æ
ö
æ
ö
3.Place the first zero FZ1 before the output LC filter
double pole frequency FLC.
s s +
´ s +
÷ ç
ç
÷
R2 ´ C1´ C2
R3 ´ C3
è
ø
è
ø
FZ1 = 0.75 X FLC
The poles and zeros of the transfer function are:
1
Calculate the C2 by the equation:
FZ1
=
2 ´ p ´ R2 ´ C2
1
1
C2 =
FZ2
=
2 ´ p ´ R2 ´ FLC ´ 0.75
2 ´ p ´
(
R1 + R3 ´ C3
)
1
4.Set the pole at the ESR zero frequency FESR
FP1 = FESR
:
FP1
=
C1´ C2
æ
ö
÷
2´ p ´ R2 ´
ç
C1+ C2
è
ø
Calculate the C1 by the equation:
1
FP2
=
C2
C1 =
2 ´ p ´ R3 ´ C3
2 ´ p ´ R2 ´ C2 ´ FESR - 1
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Jun., 2006
APW7068
Application Information (Cont.)
PWM Compensation (Cont.)
and ripple voltage can be approximated by:
IN1 - VOUT1 VOUT1
5.Set the second pole FP2 at the half of the switching
frequency and also set the second zero FZ2 at the
output LC filter double pole FLC. The compensation
gain should not exceed the error amplifier open loop
gain, check the compensation gain at FP2 with the
capabilities of the error amplifier.
V
IRIPPLE
=
´
FS ´ L
DVOUT1 = IRIPPLE ´ ESR
V
IN1
where Fs is the switching frequency of the regulator.
Although increase of the inductor value and frequency
reduces the ripple current and voltage, a tradeoff will
exist between the inductor’s ripple current and the
regulator load transient response time.
FP2 = 0.5 X FS
FZ2 = FLC
Combine the two equations will get the following A smaller inductor will give the regulator a faster load
component calculations:
transient response at the expense of higher ripple
current. Increasing the switching frequency (FS) also
reduces the ripple current and voltage, but it will
increase the switching loss of the MOSFET and the
power dissipation of the converter. The maximum ripple
current occurs at the maximum input voltage. A good
starting point is to choose the ripple current to be
approximately 30% of the maximum output current.
Once the inductance value has been chosen, select
an inductor that is capable of carrying the required
peak current without going into saturation. In some
types of inductors, especially core that is made of
ferrite, the ripple current will increase abruptly when it
saturates. This will result in a larger output ripple
voltage.
R1
R3 =
FS
- 1
2 ´ FLC
1
C3 =
p ´ R3 ´ FS
FZ1 FZ2 FP1
FP2
Compensation
Gain
20log
(R2/R1)
20log
(VIN/ΔVOSC)
Output Capacitor Selection
FLC
FESR
Converter
Gain
Higher capacitor value and lower ESR reduce the
output ripple and the load transient drop. Therefore,
selecting high performance low ESR capacitors is
intended for switching regulator applications. In some
applications, multiple capacitors have to be parallel to
achieve the desired ESR value. A small decoupling
capacitor in parallel for bypassing the noise is also
recommended, and the voltage rating of the output
capacitors also must be considered. If tantalum
capacitors are used, make sure they are surge tested
PWM & Filter
Gain
Frequency(Hz)
Figure 10. Converter Gain and Frequency
Output Inductor Selection
The inductor value determines the inductor ripple
current and affects the load transient response. Higher
inductor value reduces the inductor’s ripple current and
induces lower output ripple voltage. The ripple current
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Jun., 2006
APW7068
Application Information (Cont.)
Output Capacitor Selection (Cont.)
by the manufactures. If in doubt, consult the capacitors
manufacturer.
capacitor 1uF can be connected between the drain of
upper MOSFET and the source of lower MOSFET.
MOSFET Selection
Input Capacitor Selection
The selection of the N-channel power MOSFETs are
determined by the RDS(ON), reverse transfer capacitance
(CRSS) and maximum output current requirement. There
are two components of loss in the MOSFETs:
conduction loss and transition loss. For the upper
and lower MOSFET, the losses are approximately
given by the following:
The input capacitor is chosen based on the voltage
rating and the RMS current rating. For reliable
operation, select the capacitor voltage rating to be at
least 1.3 times higher than the maximum input voltage.
The maximum RMS current rating requirement is
approximately IOUT1/2, where IOUT1 is the load current.
During power up, the input capacitors have to handle
large amount of surge current. If tantalum capacitors
are used, make sure they are surge tested by the
manufactures. If in doubt, consult the capacitors
manufacturer. For high frequency decoupling, a ceramic
capacitor 1uF can be connected between the drain of
upper MOSFET and the source of lower MOSFET.
applications, multiple capacitors have to be parallel to
achieve the desired ESR value. A small decoupling
capacitor in parallel for bypassing the noise is also
recommended, and the voltage rating of the output
capacitors also must be considered. If tantalum
capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capacitors
manufacturer.
PUPPER = IOUT1 (1+ TC)(RDS(ON))D + (0.5)( IOUT1)(V )( tSW)FS
IN1
PLOWER = IOUT1 (1+ TC)(RDS(ON))(1-D)
Where IOUT1 is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tSW is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction loss while
the upper MOSFET include an additional transition
loss. The switching internal, tSW, is a function of the
reverse transfer capacitance CRSS. The (1+TC) term is
to factor in the temperature dependency of the RDS(ON)
and can be extracted from the “R DS(ON) vs Temperature”
curve of the power MOSFET.
Input Capacitor Selection
Layout Considerations
The input capacitor is chosen based on the voltage
rating and the RMS current rating. For reliable
operation, select the capacitor voltage rating to be at
least 1.3 times higher than the maximum input voltage.
The maximum RMS current rating requirement is
approximately IOUT1/2, where IOUT1 is the load current.
During power up, the input capacitors have to handle
large amount of surge current. If tantalum capacitors
are used, make sure they are surge tested by the
manufactures. If in doubt, consult the capacitors
manufacturer. For high frequency decoupling, a ceramic
In any high switching frequency converter, a correct
layout is important to ensure proper operation of the
regulator. With power devices switching at 300KHz or
above, the resulting current transient will cause volt-
age spike across the interconnecting impedance and
parasitic circuit elements. As an example, consider
the turn-off transition of the PWM MOSFET. Before
turn-off, the MOSFET is carrying the full load current.
During turn-off, current stops flowing in the MOSFET
and is free-wheeling by the lower MOSFET and para-
sitic diode. Any parasitic inductance of the circuit gen-
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Jun., 2006
APW7068
Application Information (Cont.)
Layout Considerations (Cont.)
the upper MOSFET; the output capacitor should be
erates a large voltage spike during the switching
interval. In general, using short, wide printed circuit
traces should minimize interconnecting imped-
ances and the magnitude of voltage spike. And signal
and power grounds are to be kept separate till com-
bined using ground plane construction or single point
grounding. Figure 11. illustrates the layout, with bold
lines indicating high current paths; these traces must
be short and wide. Components along the bold lines
should be placed lose together. Below is a checklist
for your layout:
near the loads. The input capacitor GND should
be close to the output capacitor GND and the lower
MOSFET GND.
- The drain of the MOSFETs (VIN1 and PHASE nodes)
should be a large plane for heat sinking.
APW7068
VIN1
VCC12
VIN2
BOOT
L
DRIVE
O
A
D
UGATE
- The metal plate of the bottom of the packages
(QFN-16) must be soldered to the PCB and con-
nected to the GND plane on the backside through
several thermal vias.
VOUT2
PHASE
FBL
L
O
A
D
LGATE
VOUT1
REF_OUT
- Keep the switching nodes (UGATE, LGATE and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals.
Therefore, keep traces to these nodes as short as
possible.
Figure 11. Layout Guidelines
- The traces from the gate drivers to the MOSFETs
(UG, LG, DRIVE) should be short and wide.
- Place the source of the high-side MOSFET and
the drain of the low-side MOSFET as close as
possible. Minimizing the impedance with wide
layout plane between the two pads reduces the
voltage bounce of the node.
- Decoupling capacitor, compensation component,
the resistor dividers, boot capacitors, and
REF_OUT capacitors should be close their pins.
(For example, place the decoupling ceramic
capacitor near the drain of the high-side MOSFET
as close as possible. The bulk capacitors are also
placed near the drain).
- The input capacitor should be near the drain of
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Jun., 2006
APW7068
Package Information
SOP – 14 (150mil)
C
D
A
GAUGE PLANE
SEATING PLANE
e
B
A1
L
Millimeters
Inches
Dim
Min.
1.477
0.102
0.331
0.191
8.558
3.82
Max.
Min.
0.058
0.004
0.013
0.0075
0.336
0.150
Max.
0.068
0.010
0.020
0.0098
0.344
0.157
A
A1
B
1.732
0.255
0.509
0.2496
8.762
3.999
C
D
E
e
1.274
0.050
H
L
5.808
0.382
0°
6.215
1.274
8°
0.228
0.015
0°
0.244
0.050
8°
q°
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Jun., 2006
APW7068
Package Information
QSOP-16
D
GAUGE
PLANE
E
E1
1
2
3
A
L
1
A1
b
e
Millimeters
Inches
Dim
Min.
1.35
0.10
0.20
4.80
5.79
3.81
Max.
1.75
0.25
0.30
5.00
6.20
3.99
Min.
0.053
0.004
0.008
0.189
0.228
0.150
Max.
A
A1
b
0.069
0.010
0.012
0.197
0.244
0.157
D
E
E1
e
0.635 TYP.
0.025 TYP.
0.41
1.27
L
0.016
0.050
f 1
0°
8°
0°
8°
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Jun., 2006
APW7068
Packaging Information
QFN-16
e
b
D
D2
Millimeters
Inches
Dim
Min.
Max.
0.84
0.04
0.63
Min.
0.030
0.00
Max.
0.033
0.0015
0.025
A
A1
A2
A3
D
0.76
0.00
0.57
0.022
0.20 REF.
0.650 BSC
0.008 REF.
0.0257BSC
3.90
3.90
0.25
2.05
2.05
4.10
4.10
0.35
2.15
2.15
0.154
0.154
0.010
0.081
0.081
0.161
0.161
0.014
0.085
0.085
E
b
D2
E2
e
L
0.50
0.60
0.002
0.024
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Jun., 2006
APW7068
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition (IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
°
t 25 C to Peak
Time
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
Preheat
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
183°C
60-150 seconds
217°C
60-150 seconds
- Time (tL)
Peak/Classificatioon Temperature (Tp)
See table 1
See table 2
Time within 5°C of actual
Peak Temperature (tp)
10-30 seconds
20-40 seconds
Ramp-down Rate
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package. Measured on the body surface.
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Jun., 2006
APW7068
Classification Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350
<2.5 mm
³ 2.5 mm
240 +0/-5°C
225 +0/-5°C
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350-2000
Volume mm3
>2000
<1.6 mm
1.6 mm – 2.5 mm
³ 2.5 mm
260 +0°C*
260 +0°C*
250 +0°C*
260 +0°C*
250 +0°C*
245 +0°C*
260 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C.
For example 260°C+0°C) at the rated MSL level.
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 SEC
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Latch-Up
Carrier Tape & Reel Dimensions
t
D
P
Po
E
F
P1
Bo
W
Ko
Ao
D1
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Jun., 2006
APW7068
Carrier Tape & Reel Dimensions(Cont.)
T2
J
C
A
B
T1
Application
A
B
C
J
T1
T2
W
P
8
t
E
13.0 + 0.5
- 0.2
330REF 100REF
2 ± 0.5 16.5REF 2.5 ± 025 16.0 ± 0.3
1.75
SOP-14
(150mil)
F
D
D1
Po
P1
Ao
Ko
7.5
4.0
2.0
6.5
T2
2.10
W
f 0.50 + 0.1 f 1.50 (MIN)
0.3±0.05
Application
QSOP- 16
A
B
C
J
T1
P
E
330 ± 1 62 +1.5 12.75+ 0.15 2 ± 0.5 12.4 ± 0.2
D1 Po P1
2 ± 0.2
12± 0. 3
8± 0.1 1.75±0.1
Ko
F
D
Ao
Bo
t
5.5± 1 1.55 +0.1 1.55+ 0.25 4.0 ± 0.1 2.0 ± 0.1 6.4 ± 0.1 5.2± 0. 1 2.1± 0.1 0.3±0.013
(mm)
4x4 Shipping Tray
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Jun., 2006
APW7068
4x4 Shipping Tray (Cont.)
Cover Tape Dimensions
Application
SOP- 14
Carrier Width
Cover Tape Width
Devices Per Reel
24
12
21.3
9.3
2500
2500
QSOP- 16
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright ã ANPEC Electronics Corp.
Rev. A.2 - Jun., 2006
26
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