APW7073A [ANPEC]
Synchronous Buck PWM Controller; 同步降压PWM控制器
| 型号： | APW7073A |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Synchronous Buck PWM Controller |
| 文件： | 总20页 (文件大小：732K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7073A
Synchronous Buck PWM Controller
General Description
Features
·
·
·
·
Single 12V Power Supply Required
0.6V Reference with 1% Accuracy
Shutdown and Soft-Start Function
The APW7073A is a voltage mode and synchronous
PWM controller which drives dual N-channel MOSFETs.
The device integrates all of the controlling, monitoring,
and protecting functions into a single package, and pro-
vides one controlled power output with over-current
protection.
Programmable Frequency Range from 50 kHz to
1000kHz
·
·
·
·
·
Voltage Mode PWM Control Design
Up to 100% Duty Cycle
The APW7073A provides excellent regulation for output
load variation. The internal 0.6V temperature-compen-
sated reference voltage is designed to meet the require-
ment of low output voltage applications. The device in-
cludes a 200kHz free-running triangle-wave oscillator that
is adjustable from 50kHz to 1000kHz.
Over-Current Protection (OCP)
SOP-14 Package
Lead Free and Green Devices Available
(RoHS Compliant)
The APW7073A has been equipped with excellent pro-
tection functions: Power-On-Reset (POR) and Over-Cur-
rent Protection (OCP). The POR circuit can monitor the
VCC, EN, and OCSET voltages to make sure the supply
voltages exceed their threshold voltage while the con-
troller is running. The OCP monitors the output current
by using the voltage drop across the upper MOSFET’s RDS
(ON). When the output current reaches the trip point, the IC
shuts off the converter and initiates a new soft-start
process. After two over-current events are counted, the
device turns off both high-side and low-side MOSFETs
and the converter output is latched to be floating. It re-
quires a POR of VCC to restart.
Typical Application Circuit
12V
VIN
R
OCSET
RFS
VOUT
APW7073A
L
CSS
Applications
Pin Configuration
·
DC-DC Power Supply
RT 1
OCSET 2
SS 3
14 VCC
13 PVCC
12 LGATE
11 PGND
10 BOOT
9 UGATE
8 PHASE
COMP 4
FB 5
SOP-14
EN 6
GND 7
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
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Rev. A.5 - Nov., 2012
APW7073A
Ordering and Marking Information
Package Code
K : SOP - 14
APW7073A
Operating Ambient Temperature Range
Assembly Material
Handling Code
°
E : -20 to 70 C
Handling Code
TR : Tape & Reel
Temperature Range
Package Code
Assembly Material
L : Lead Free Device G : Halogen and Lead Free Device
APW7073A
APW7073A K :
XXXXX - Date Code
XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
VCC, VPVCC
VBOOT
Parameter
Rating
-0.3 to +16
Unit
V
VCC, PVCC to GND
BOOT to PHASE
-0.3 to +16
V
UGATE to PHASE <400ns pulse width
>400ns pulse width
-5 to VBOOT +5
-0.3 to VBOOT +0.3
-5 to VPVCC +5
-0.3 to VPVCC +0.3
-10 to +30
VUGATE
VLGATE
VPHASE
V
V
V
LGATE to PGND <400ns pulse width
>400ns pulse width
PHASE to GND
<400ns pulse width
>400ns pulse width
-0.3 to 16
VRT, VOCSET, VEN
RT, OCSET, EN to GND
-0.3 to VCC+0.3
-0.3 to 7
V
V
VFB, VCOMP, VSS
FB, COMP, SS to GND
VPGND
TJ
PGND to GND
-0.3 to +0.3
-20 to 150
V
Junction Temperature Range
Storage Temperature
°C
°C
°C
TSTG
TSDR
-65 to 150
260
Maximum Lead Soldering Temperature, 10 Seconds
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under
"recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Thermal Characteristics (Note 2)
Symbol
Parameter
Typical Value
Unit
Junction-to-Ambient Thermal Resistance in Free Air
qJA
oC/W
SOP-14
160
Note2: qJA is measured with the component mounted on a high effective the thermal conductivity test board in free air. The
exposed pad of package is soldered directly on the PCB.
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Rev. A.5 - Nov., 2012
APW7073A
Recommended Operating Conditions
Symbol
Parameter
Rating
10.8 to 13.2
2.2 to 13.2
0.6 to 5
Unit
V
VCC, VPVCC IC Supply Voltage
VIN
VOUT
IOUT
TA
Converter Input Voltage
V
Converter Output Voltage
Converter Output Current
Ambient Temperature Range
Junction Temperature Range
V
0 to 30
A
-20 to 70
-20 to 125
°C
°C
TJ
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at TA=25°C.
APW7073A
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
INPUT SUPPLY CURRENT
VCC Supply Current (Shutdown Mode) UGATE, LGATE and EN = GND
VCC Supply Current UGATE and LGATE Open
POWER-ON-RESET
Rising VCC Threshold
-
0.5
5
1
mA
mA
ICC
-
10
9
9.5
8
10.0
V
V
V
V
V
V
Falling VCC Threshold
7.5
8.5
Rising VOCSET Threshold
VOCSET Hysteresis Voltage
Rising EN threshold Voltage
EN Hysteresis Voltage
-
-
-
-
1.3
0.1
1.3
0.1
-
-
-
-
OSCILLATOR
Accuracy
-15
-
-
+15
-
%
FOSC
Free Running Frequency
RT = open
200
kHz
RT pin: resistor to GND;
resistor to VCC
Adjustment Range
50
-
1000
kHz
VOSC
Duty
Ramp Amplitude
Duty Cycle Range
(nominal 1.35V to 2.95V)
-
1.6
-
-
V
0
100
%
REFERENCE
VREF Reference Voltage
Reference Voltage Tolerance
PWM ERROR AMPLIFIER
Gain Open Loop Gain
GBWP Open Loop Bandwidth
-
0.60
-
-
V
-1
+1
%
RL = 10k, CL = 10pF(Note3)
RL = 10k, CL = 10pF (Note3)
RL = 10k, CL = 10pF (Note3)
VFB = 0.6V
-
-
-
-
-
-
-
-
88
15
6
-
-
dB
MHz
V/ms
SR
Slew Rate
-
FB Input Current
COMP High Voltage
COMP Low Voltage
COMP Source Current
COMP Sink Current
0.1
5.5
0
1
-
m
A
VCOMP
VCOMP
ICOMP
ICOMP
V
-
V
VCOMP = 2V
VCOMP = 2V
5
-
mA
mA
5
-
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Rev. A.5 - Nov., 2012
APW7073A
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at TA=25°C.
APW7073A
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
GATE DRIVERS
IUGATE
RUGATE Upper Gate Sink Impedance
ILGATE Lower Gate Source Current
RLGATE Lower Gate Sink Impedance
TD Dead Time
PROTECTION
Upper Gate Source Current
VBOOT = 12V, VUGATE -VPHASE = 2V
VBOOT = 12V, IUGATE = 0.1A
VPVCC = 12V, VLGATE = 2V
-
-
-
-
-
2.6
1.6
3.0
1.25
50
-
2.4
-
A
W
A
VPVCC = 12V, ILGATE = 0.1A
1.88
-
W
ns
IOCSET
OCSET Source Current
VOCSET = 11.5V
170
24
200
30
250
36
mA
mA
ENABLE/SOFT-START
ISS
Soft-Start Charge Current
Note 3 : Guaranteed by design
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APW7073A
Typical Operating Characteristics
Switching Frequency vs.
Reference Voltage vs. Junction Temperature
Junction Temperature
205
0.602
0.601
200
195
190
185
180
0.6
0.599
0.598
0.597
0.596
0.595
0.594
80 100 120
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
Junction Temperature (°C)
Junction Temperature (°C)
Operating Waveforms
Power On
Power Off
Vcc=12V, Vin=12V
VOUT=1.5V, L=1uH
Vcc=12V, Vin=12V
VOUT=1.5V, L=1uH
1
1
2
2
3
3
CH1: VCC (5V/div)
CH2: VSS (2V/div)
CH3: VOUT (1V/div)
Time: 10ms/div
CH1: VCC (5V/div)
CH2: VSS (2V/div)
CH3: VOUT (1V/div)
Time: 2ms/div
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Rev. A.5 - Nov., 2012
APW7073A
Operating Waveforms (Cont.)
EN (VEN=VCC)
Shutdown (VEN=VGND
)
Vcc=12V, Vin=12V
VOUT=1.5V, L=1uH
Vcc=12V, Vin=12V
VOUT=1.5V, L=1uH
1
1
2
3
2
3
CH1: VEN (5V/div)
CH2: VSS (5V/div)
CH3: VOUT (1V/div)
CH1: VEN (5V/div)
CH2: VSS (5V/div)
CH3: VOUT (1V/div)
Time: 10ms/div
Time: 10ms/div
UGATE Rising
UGATE Falling
Vcc=12V, Vin=12V
VOUT=1.5V, L=1uH
Vcc=12V, Vin=12V
VOUT=1.5V, L=1uH
1
1
2
3
2
3
CH1: VUGATE (20V/div)
CH2: VLGATE (5V/div)
CH3: VPHASE (10V/div)
Time: 50ns/div
CH1: VUGATE (20V/div)
CH2: VLGATE (5V/div)
CH3: VPHASE (10V/div)
Time: 50ns/div
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Rev. A.5 - Nov., 2012
APW7073A
Operating Waveforms (Cont.)
Load Transient Response
Short Test before Power On
VCC =12V, VIN =12V, VOUT =1.5V, L=1 mH,
ROCSET = 1kW , RDS(ON) = 8.5mW
Vcc=12V, Vin=12V
VOUT=1.5V, L=1uH
1
1
2
3
2
4
CH1: VOUT (500mV/div)
CH4: IOUT (5A/div)
Time: 200ms/div
CH1: VSS (5V/div)
CH2: IL (10A/div)
CH3: VOUT (1V/div)
CH4: VUGATE (20V/div)
Time: 20ms/div
Short Test after Power On
1
VCC =12V, VIN =12V, VOUT =1.5V, L=1 mH,
ROCSET = 1kW , RDS(ON) = 8.5mW
2
3
4
CH1: VSS (5V/div)
CH2: IL (10A/div)
CH3: VOUT (1V/div)
CH4: VUGATE (20V/div)
Time: 20ms/div
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Rev. A.5 - Nov., 2012
APW7073A
Function Pin Description
VCC
SS
Power supply input pin. Connect a nominal 12V power
supply to this pin. The power-on-reset function monitors
the input voltage by this pin. It is recommended that a
decoupling capacitor (1 to 10mF) be connected to the
GND for noise decoupling.
Connect a capacitor to theGND and a 30mAcurrent source
charges this capacitor to set the soft-start time.
OCSET
This pin serves two functions: a shutdown control and
the setting of over current limit threshold. Pulling this pin
below 1.3V will shutdown the controller, forcing the
UGATE and LGATE signals to be low.
PVCC
This pin provides a supply voltage for the lower gate
drive. Connect this pin to VCC pin in normal use.
A resistor (Rocset) connected between this pin and the
drain of the high side MOSFET will determine the over
current limit. An internal 200mA current source will flow
through this resistor, creating a voltage drop, which will
be compared with the voltage across the high side
MOSFET. The threshold of the over current limit is
therefore given by:
BOOT
This pin provides the bootstrap voltage to the upper gate
driver for driving the N-channel MOSFET.
PHASE
This pin is the return path for the upper gate driver.
Connect this pin to the upper MOSFET source. This pin
is also used to monitor the voltage drop across the
MOSFET for over-current protection.
IOCSET (200uA)´ ROCSET
IPEAK
=
RDS(ON)
GND
EN
This pin is the signal ground pin. Connect the GND to a
good ground plane.
Pull this pin above 1.3V to enable the device and pull
this pin below 1.2V to disable the device. In shutdown,
the SS is discharged and the UGATE and LGATE pins
are held low. Note that don’t leave this pin open.
PGND
This pin is the power ground pin for the lower gate driver.
It should be tied to the GND on the board.
RT
COMP
This pin allows adjusting the switching frequency.
Connect a resistor from RT pin to the ground to increase
the switching frequency. Conversely, connect a resistor
from RT to the VCC to decrease the switching frequency.
This pin is the output of PWM error amplifier. It is used to
set the compensation components.
FB
This pin is the inverting input of the PWM error amplifier.
It is used to set the output voltage and the compensation
components.
UGATE
This pin is the gate driver for the upper MOSFET of PWM
output.
LGATE
This pin is the gate driver for the lower MOSFET of PWM
output.
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APW7073A
Block Diagram
VCC
GND
OCSET
Power-On-
Reset
EN
IOCSET
200mA
BOOT
UGATE
ISS
30mA
Soft-Start
15K
O.C.P
Comparator
SS
PHASE
PVCC
PWM
Comparator
Gate
Control
LGATE
VREF
15K
Error Amp
PGND
Sawtooth
Wave
Oscillator
FB
RT
COMP
Typical Application Circuit
1mF
12V
5.1
1N4148
VIN
Zener
15V
1nF
3K
PVCC VCC
OCSET
BOOT
2.2
1mF
10mF
10mF
NC
1500mFx2
NC
RT
0.1mF
ON
2.2
2.2
UGATE
PHASE
7.2mH
APM2510
VOUT
APM2510
APM2556
EN
SS
OFF
1nF
1nF
1mF
2200mFx2
0.1mF
LGATE
PGND
APM2556
2.2
COMP
FB
10nF
3.3k
GND
8.2k
1.8k
3.3k
10nF
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Rev. A.5 - Nov., 2012
APW7073A
Function Description
Power-On-Reset (POR)
Voltage
The Power-On-Reset (POR) function of APW7073A continu-
ally monitors the input supply voltage (VCC), the enable
(EN) pin, and the OCSET pin. The supply voltage (VCC)
must exceed its rising POR threshold voltage. The volt-
age at OCSET pin is equal to VIN less a fixed voltage
drop (VOCSET = VIN- VROCSET). The EN pin can be pulled
high with connecting a resistor to the VCC. The POR
function initiates soft-start operation after VCC, EN, and
OCSET voltages exceed their POR thresholds. For op-
eration with a single +12V power source, VIN and Vcc are
equivalent and the +12V power source must exceed the
rising VCC threshold. The POR function inhibits opera-
tion at disabled status (EN pin low). With both input sup-
plies above their POR thresholds, the device initiates a
soft-start interval.
VSS
4.2V
VOUT
1.8V
Time
t0
t1
t2
Figure 1. Soft-Start Internal
Over-Current Protection (monitor upper MOSFET)
Soft-Start/EN
The APW7073A monitors the voltage across the upper
MOSFET and uses the OCSET pin to set the over-current
trip point.
The SS/EN pins control the soft-start and enable or
disable the controller. Connect a soft-start capacitor
from SS pin to GND to set the soft-start interval. Figure1.
shows the soft-start interval. When VCC reaches its Power-
On-Reset threshold (9.5V), internal 30mA current source
starts to charge the capacitor. When the VSS reaches the
enabled threshold about 1.8V, the internal 0.6V reference
starts to rise and follows the VSS; the error amplifier
output (VCOMP) suddenly raises to 1.35V, which is the
valley of the triangle wave of the oscillator, leads the VOUT
to start-up. Until the VSS reaches about 4.2V, the internal
reference completes the soft-start interval and reaches
to 0.6V, and then VOUT is in regulation. The SS still rises
to 5.5V and then stops.
A resistor (ROCSET) connected between OCSET pin and
the drain of the upper MOSFET will determine the over
current limit. An internal 200mA current source will flow
through this resistor, creating a voltage drop, which will
be compared with the voltage across the upper MOSFET.
When the voltage across the upper MOSFET exceeds the
voltage drop across the ROCSET, an over-current will be
detected. The threshold of the over current limit is
therefore given by:
IOCSET ´ ROCSET
ILIMIT
=
RDS
(ON)
For the over-current, it is never occurred in the normal
operating load range; the variation of all parameters in
the above equation should be determined.
CSS
TSoft- Start = t2 - t1 =
×2.4V
ISS
Where:
- The MOSFET’s RDS(ON) is varied by temperature and
gate to source voltage, the user should determine
the maximum RDS(ON) in manufacturer’s datasheet.
CSS = external Soft-Start capacitor
ISS = Soft-Start current=30mA
- The minimum IOCSET (170mA) and minimum ROCSET
should be used in the above equation.
- Note that the ILIMIT is the current flow through the
upper MOSFET; ILIMIT must be greater than maximum
output current add the half of inductor ripple current.
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Rev. A.5 - Nov., 2012
APW7073A
Function Description (Cont.)
1000
900
800
700
600
500
400
300
200
100
0
Over-Current Protection (Cont.)
An over current condition will shut down the device and
discharge the CSS with a 30mA sink current and then
initiate the soft-start sequence. After two over-current
events are counted, the device turns off both high-side
and low-side MOSFETs and the converter output is latched
to be floating. It requires a POR of VCC to restart.
Switching Frequency
The APW7073A provides the oscillator switching fre-
quency adjustment. The device includes a 200kHz free-
running triangle wave oscillator. If operating in higher
frequency than 200kHz, connect a resistor from RT pin
to the ground to increase the switching frequency.
Conversely, if operating in lower frequency than 200kHz,
connect a resistor from RT to the VCC to decrease the
switching frequency.
10
1000
Frequency (kHz)
Figure 2. Oscillator Frequency vs. RT Resistance
1000
900
800
700
600
500
400
300
200
100
Figure 2. shows how to select the resistor for the desired
frequency. Figure 3 shows more detail for the higher
frequencies and Figure 4 shows the lower frequency
detail.
0
200 300 400 500 600 700 800 900 1000
Frequency (kHz)
Figure 3. Oscillator Frequency vs. RT Resistance
(High Frequency)
1000
900
800
700
600
500
400
300
200
50
70
90
110
130
150
170
Frequency (kHz)
Figure 4. Oscillator Frequency vs. RT Resistance
(Low Frequency)
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APW7073A
Application Information
Output Voltage Selection
Output Capacitor Selection
The output voltage can be programmed with a resistive
divider. Use 1% or better resistors for the resistive divider
is recommended. The FB pin is the inverter input of the
error amplifier, and the reference voltage is 0.6V. The
output voltage is determined by:
Higher capacitor value and lower ESR reduce the output
ripple and the load transient drop. Therefore, selecting high
performance low ESR capacitors is intended for switch-
ing regulator applications. In some applications, mul-
tiple capacitors have to be parallelled to achieve the
desired ESR value. A small decoupling capacitor in
parallel for bypassing the noise is also recommended,
and the voltage rating of the output capacitors also must
be considered. If tantalum capacitors are used, make
sure they are surge tested by the manufactures. If in doubt,
consult the capacitors manufacturer.
æ
ç
è
ö
÷
÷
ø
ROUT
RGND
ç
VOUT = 0.6´ 1+
Where ROUT is the resistor connected from VOUT to FB, and
RGND is the resistor connected from FB to GND.
Output Inductor Selection
Input Capacitor Selection
The inductor value determines the inductor ripple current
and affects the load transient response. Higher inductor
value reduces the inductor’s ripple current and induces
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select
the capacitor voltage rating to be at least 1.3 times higher
than the maximum input voltage. The maximum RMS
current rating requirement is approximately IOUT/2,
where IOUT is the load current. During power up, the input
capacitors have to handle large amount of surge current.
If tantalum capacitors are used, make sure they are surge
tested by the manufactures. If in doubt, consult the
capacitors manufacturer. For high frequency decoupling,
a ceramic capacitor 1mF can be connected between the
drain of upper MOSFET and the source of lower MOSFET.
V - VOUT VOUT
IN
IRIPPLE
=
´
FS ´ L
V
IN
DVOUT = IRIPPLE ´ ESR
where Fs is the switching frequency of the regulator.
Although increase of the inductor value and frequency
reduces the ripple current and voltage, a tradeoff will
exist between the inductor’s ripple current and the
regulator load transient response time.
MOSFET Selection
The selection of the N-channel power MOSFETs are
determined by the RDS(ON), reverse transfer capacitance
(CRSS) and maximum output current requirement. There
are two components of loss in the MOSFETs: conduction
loss and transition loss. For the upper and lower
MOSFET, the losses are approximately given by the fol-
lowing equations:
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple current.
Increasing the switching frequency (FS) also reduces the
ripple current and voltage, but it will increase the
switching loss of the MOSFET and the power dissipation
of the converter. The maximum ripple current occurs at
the maximum input voltage. A good starting point is to
choose the ripple current to be approximately 30% of
the maximum output current. Once the inductance value
has been chosen, select an inductor that is capable of
carrying the required peak current without going into
saturation. In some types of inductors, especially core
that is made of ferrite, the ripple current will increase
abruptly when it saturates. This will result in a larger
output ripple voltage.
PUPPER = IOUT 2 ( 1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FS
PLOWER = IOUT 2 (1+ TC)(RDS(ON))(1-D)
Where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tSW is the switching interval
D is the duty cycle
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APW7073A
Application Information (Cont.)
MOSFET Selection (Cont.)
The PWM modulator is shown in Figure 7. The input is
the output of the error amplifier and the output is the
PHASE node. The transfer function of the PWM modula-
tor is given by:
Note that both MOSFETs have conduction loss while the
upper MOSFET includes an additional transition loss.
The switching internal, tSW, is the function of the reverse
transfer capacitance CRSS. The (1+TC) term is to factor
in the temperature dependency of the RDS(ON) and can be
extracted from the “RDS(ON) vs Temperature” curve of the
power MOSFET.
V
IN
GAINPWM
=
DVOSC
VIN
Driver
OSC
PWM
Comparator
PWM Compensation
ΔVOSC
The output LC filter of a step down converter introduces a
double pole, which contributes with -40dB/decade gain
slope and 180 degrees phase shift in the control loop. A
compensation network among COMP, FB, and VOUT
should be added. The compensation network is shown in
Figure 8. The output LC filter consists of the output induc-
tor and output capacitors. The transfer function of the LC
PHASE
Output of
Error Amplifier
Driver
Figure 7. The PWM Modulator
The compensation network is shown in Figure 8. It
provides a close loop transfer function with the highest
zero crossover frequency and sufficient phase margin.
The transfer function of error amplifier is given by:
filter is given by:
1
F
=
ESR
2´ p ´ ESR´ COUT
1
1
æ
ö
The FLC is the double poles of the LC filter, and FESR is the
zero introduced by the ESR of the output capacitor.
// R2 +
ç
÷
VCOMP
VOUT
sC1
sC2
è
ø
GAINAMP
=
=
1
æ
ö
R1// R3 +
ç
÷
VPHASE
L
VOUT
sC3
è
ø
æ
ö
ö
1
1
æ
ç
´ s +
÷
÷
s +
ç
÷
ç
R2´ C2
(
R1+ R3
)
´ C3
R1+ R3
è
ø
è
C1+ C2
ø
COUT
ESR
=
´
1
R1´ R3´ C1
æ
ö æ
ö
s s +
´
s +
ç
÷ ç
÷
R2´ C1´ C2
R3´ C3
è
ø è
ø
The poles and zeros of the transfer function are:
1
FZ1
=
Figure 5. The Output LC Filter
FLC
2´ p ´ R2´ C2
1
FZ2
=
2´ p ´
(
R1+ R3
)
´ C3
-40dB/dec
1
F
=
=
P1
C1´ C2
æ
ö
÷
ø
2´ p ´ R2´
ç
C1+ C2
è
1
F
FESR
P2
2´ p ´ R3´ C3
C1
-20dB/dec
R3
C3
R2
C2
VOUT
FB
VCOMP
R1
Frequency(Hz)
VREF
Figure 6. The LC Filter GAIN and Frequency
Figure 8. Compensation Network
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Copyright ã ANPEC Electronics Corp.
13
Rev. A.5 - Nov., 2012
APW7073A
Application Information (Cont.)
PWM Compensation (Cont.)
The poles and zero of this transfer functions are:
1
The closed loop gain of the converter can be written as:
F
=
LC
2´ p ´ L´ COUT
GAINLC X GAINPWM X GAINAMP
R1
FS
Figure 9. shows the asymptotic plot of the closed loop
converter gain, and the following guidelines will help to
design the compensation network. Using the below
guidelines should give a compensation similar to the
curve plotted. A stable closed loop has a -20dB/ decade
slope and a phase margin greater than 45 degree.
R3 =
C3 =
- 1
2´ F
LC
1
p ´ R3´ FS
1. Choose a value for R1, usually between 1K and 5K.
2. Select the desired zero crossover frequency
FO: (1/5 ~ 1/10) X FS >FO>FESR
FZ1 FZ2 FP1 FP2
Use the following equation to calculate R2:
Compensation
Gain
20log
(R2/R1)
DVOSC FO
R2 =
´
´ R1
20log
(VIN/ΔVOSC
V
F
LC
IN
)
3. Place the first zero FZ1 before the output LC filter double
pole frequency FLC.
FLC
FZ1 = 0.75 X FLC
FESR
Converter
Gain
Calculate the C2 by the equation:
PWM & Filter
Gain
1
C2 =
2´ p ´ R2´ FLC ´ 0.75
Frequency(Hz)
Figure 9. Converter Gain and Frequency
4. Set the pole at the ESR zero frequency FESR
FP1 = FESR
:
Calculate the C1 by the equation:
C2
C1=
2´ p ´ R2´ C2´ FESR - 1
5. Set the second pole FP2 at the half of the switching
frequency and also set the second zero FZ2 at the output
LC filter double pole FLC. The compensation gain should
not exceed the error amplifier open loop gain, check the
compensation gain at FP2 with the capabilities of the error
amplifier.
FP2 = 0.5 X FS
FZ2 = FLC
Combine the two equations will get the following component
calculations:
1+ s´ ESR´ COUT
s2 ´ L´ COUT + s´ ESR´ COUT +1
GAINLC
=
Copyright ã ANPEC Electronics Corp.
14
www.anpec.com.tw
Rev. A.5 - Nov., 2012
APW7073A
Layout Consideration
Layout Consideration
the loads. The input capacitor GND should be close
to the output capacitor GND and the lower MOSFET
GND.
In any high switching frequency converter, a correct layout
is important to ensure proper operation of the regulator.
With power devices switching at 300kHz, the resulting
current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off, the MOSFET is
carrying the full load current. During turn-off, current
stops flowing in the MOSFET and is free-wheeling by
the lower MOSFET and parasitic diode. Any parasitic
inductance of the circuit generates a large voltage spike
during the switching interval. In general, using short, wide,
and printed circuit traces should minimize interconnect-
ing impedances and the magnitude of voltage spike.
And signal and power grounds are to be kept separating
till combined using ground plane construction or single
point grounding. Figure 10 illustrates the layout, with
bold lines indicating high current paths; these traces
must be short and wide. Components along the bold
lines should be placed lose together. Below is a check-
list for your layout:
- The drain of the MOSFETs (VIN and PHASE nodes)
should be a large plane for heat sinking.
APW7073A
VIN
VCC
PVCC
BOOT
L
O
A
D
UGATE
PHASE
LGATE
VOUT
Figure 10. Layout Guidelines
- Keep the switching nodes (UGATE, LGATE, and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. Therefore,
keep traces to these nodes as short as possible.
- The traces from the gate drivers to the MOSFETs
(UGATE, LGATE) should be short and wide.
- Place the source of the high-side MOSFET and the
drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane
between the two pads reduces the voltage bounce of
the node.
- Decoupling capacitor, compensation component,
the resistor dividers, boot capacitors, and SS capacitors
should be close their pins. (For example, place the
decoupling ceramic capacitor near the drain of the
high-side MOSFET as close as possible. The bulk
capacitors are also placed near the drain).
- The input capacitor should be near the drain of the
upper MOSFET; the output capacitor should be near
Copyright ã ANPEC Electronics Corp.
15
www.anpec.com.tw
Rev. A.5 - Nov., 2012
APW7073A
Package Information
SOP–14
D
SEE VIEW A
c
e
b
GAUGE PLANE
SEATING PLANE
L
VIEW A
SOP-14
S
Y
M
B
O
L
MILLIMETERS
INCHES
MIN.
MAX.
1.75
0.25
MIN.
MAX.
A
0.069
0.010
0.004
0.049
0.012
0.007
A1
A2
b
0.10
1.25
0.31
0.17
8.55
5.80
3.80
0.020
0.010
0.51
0.25
8.75
6.20
4.00
c
D
0.337
0.228
0.150
0.344
0.244
0.157
E
E1
e
1.27 BSC
0.050 BSC
0.010
0.016
0.020
0.050
0.25
0.40
0.50
1.27
h
L
°
°
0
0
8
0
8
Note: 1. Follow JEDEC MS-012 AB.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright ã ANPEC Electronics Corp.
16
www.anpec.com.tw
Rev. A.5 - Nov., 2012
APW7073A
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
SOP-14
A
H
T1
C
d
D
W
E1
F
16.4+2.00 13.0+0.50
330.0±
2.00
50 MIN.
1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.10
-0.00
P2
-0.20
D0
P0
P1
D1
T
A0
B0
K0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10 8.0±0.10 2.0±0.10
1.5 MIN.
6.40±0.20 9.00±0.20 2.10±0.20
(mm)
Devices Per Unit
Package Type
SOP- 14
Unit
Tape & Reel
Quantity
2500
Copyright ã ANPEC Electronics Corp.
17
www.anpec.com.tw
Rev. A.5 - Nov., 2012
APW7073A
Taping Direction Information
SOP–14
USER DIRECTION OF FEED
Classification Profile
Copyright ã ANPEC Electronics Corp.
18
www.anpec.com.tw
Rev. A.5 - Nov., 2012
APW7073A
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
³ 2.5 mm
Volume mm3
<350
235 °C
220 °C
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
PCT
TCT
HBM
MM
VMM≧200V
10ms, 1tr≧100mA
Latch-Up
Copyright ã ANPEC Electronics Corp.
19
www.anpec.com.tw
Rev. A.5 - Nov., 2012
APW7073A
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
Rev. A.5 - Nov., 2012
20
www.anpec.com.tw
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