APW7093N [ANPEC]
3A, 1MHz, Step Down DC/DC Regulator; 3A ， 1MHz时，降压型DC / DC稳压器
| 型号： | APW7093N |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | 3A, 1MHz, Step Down DC/DC Regulator |
| 文件： | 总20页 (文件大小：725K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7093
3A, 1MHz, Step Down DC/DC Regulator
General Description
Features
·
·
·
·
Source/Sink 3A
The APW7093 is a reversible energy flow, constant-
off-time, pulse-width modulated (PWM), step-down
DC-DC converter. It is ideal for use in notebook and
sub-notebook computers that require 1.1V to 5V
activetermination power supplies. Thisdevice features
an internal PMOS power switch and internal
synchronous rectifier for high efficiency and reduced
Up to 1MHz Switches Frequency
Up to 94% Efficiency
Internal PMOS/NMOS Switches
- 70mW/40mW On-Resistance at VIN = 4.5V
- 90mW/60mW On-Resistance at VIN = 3V
±1% Output Accuracy
·
·
·
·
·
·
·
·
·
component count. The internal 90mW PMOS power
1.1V to VIN Adjustable Output Voltage
3V to +5.5V Input Voltage Range
<1mA Shutdown Supply Current
switchand 60mW NMOS synchronous-rectifier switch
easily deliver continuous load currents up to 3A. The
APW7093 accurately tracks an external reference
voltage, produces an adjustable output from 1.1V to
VIN, and achieves efficiencies as high as 94%.
Programmable Constant-Off-Time Operation
Thermal Shutdown
The APW7093 uses a unique current-mode,
constant-off-time, PWM control scheme that allows
the output to source or sink current. This feature
allows energy to return to the input power supply that
otherwise would be wasted. The programmable
constant-off-timearchitecturesetsswitchingfrequencies
upto1MHz, allowingthe user tooptimizeperformance
trade-offs between efficiency, output switching noise,
component size, and cost. TheAPW7093 features an
adjustable soft-start to limit surge currents during
startup, a 100% duty-cycle mode for low-dropout
operation, and alow-power shutdown mode that disables
the power switches and reduces supply current below
1µA. TheAPW7093 is available in a 32-pin QFN with
an exposed backside pad or a 16-pin SSOP.
Adjustable Soft-Start Inrush Current Limiting
Output Short-Circuit Protection
Lead Free Available (RoHS Compliant)
Applications
·
·
·
·
·
·
·
Motherboard
Graphics Cards
Cable or DSL Modems, Set Top Boxes
DSP Supplies
Memory Supplies
5V Input DC-DC Regulators
Distributed Power Supplies
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.5 - Jun., 2005
APW7093
Pin Description
32
25
1
24
PGND
N.C
PGND
LX
IN
LX
IN
1
2
3
4
16
15
14
13
LX
SHDN
IN
PGND
LX
IN
LX
LX
APW7093
PGND
VCC
GND
REF
APW7093
PGND
N.C
SS
SS
5
6
7
8
12
11
10
9
N.C
EXTREF
TOFF
FB
VCC
N.C
GND
EXTREF
8
GND
17
16
9
SSOP - 16
QFN - 32
Ordering and Marking Information
Package Code
N : SSOP-16
APW7093
QA : QFN -32
Operating Ambient Temp. Range
Lead Free Code
°
I : -45 to 85 C
Handling Code
Temp. Range
Package Code
Handling Code
TR : Tape & Reel
TU : Tube
Lead Free Code
L : Lead Free Device Blank : Original Device
APW7093
XXXXX
APW7093 N :
XXXXX - Date Code
APW7093 QA :
APW7093
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.
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Rev. A.5 - Jun., 2005
APW7093
Block Diagram
0.01m F
SS
VIN
VIN
VCC
FB
IN
+3.0V TO +5.5V
CIN
CURRENT
SENSE
+
_
PWM
LOGIC
AND
L
EXTREF
LX
DRIVERS
COUT
SHDN
REF
REF
TIMER
GND
RTOFF
PGND
Fig1. Block Diagram
Absolute Maximum Ratings
Parameter
Rating
-0.3 ~ +6
Unit
V
VCC to GND
IN to VCC
V
±
±
0.3
0.3
GND to PGND
V
CC
-0.3 ~ V +0.3
V
SHDN
, SS, FB, TOFF, VREF to GND
EXTREF to GND
-0.3 ~ VIN-1.7
1.6
V
W
W
A
Power dissipation; Part mount on 1in2 of 1oz copper; QFN-28
Power dissipation; Part mount on 1in2 of 1oz copper; SSOP-16
LX Current
1
-3.5 ~ +4.1
-40 ~ +85
+150
Operating Temperature Range
Junction Temperature
°
°
°
°
C
C
C
C
Storage Temperature Range
-65~+150
+300
Lead Temperature (soldering,10s)
Recommend Operating Condition
Recommend Operating Condition
Symbol
VIN
Parameter
Input Voltage Range
Output Voltage Range
Output Capacitor
Input Capacitor
MIN
3
TYP
MAX
UNIT
NOTE
5.5
V
V
VOUT
1.1
220
22
VIN
VEXTREF<= VIN-1.7V
Low ESR Capacitor
OUT
C
330
33
1
uF
uF
uH
CIN
L
Inductor
0.56
Refer to Application section
for further Information.
–
–
–
RTOFF Programmed off-time Resistance
KW
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Rev. A.5 - Jun., 2005
APW7093
Electrical Characteristics
(VIN=VCC=3.3V, VEXTREF=+1.1V, TA=-45 to +85oC, unless otherwise noted, Typical values are at TA =+25oC.)
APW7093
Symbol
Parameter
Test Conditions
Unit
Min Typ Max
IN
CC
V , V
Input Voltage
Feedback Voltage Accuracy
3.0
-12
5.5
V
IN
CC
V =V =+3.0V to +5.5V,
+12 mV
mV
LOAD
EXTREF
I
=0,V
=1.25V (Note2)
FB
EXTREF
(V –V
)
D
V
FB
LOAD
EXTREF
Feedback Load Regulation Error
I
=-3A to +3A, V
=+1.25V
20
REF
IN
V -
V
-
EXTREF
IN
CC
V
External Reference Voltage Range V =V =+3.0 to +5.5V
V
0.01
1.7
1.07 1.10 1.12
REF
V
Reference Voltage
V
8
0
2
REF
m
m
Reference Load Regulation
PMOS Switch On-Resistance
I
= -1 A to +10 A
0.3
2
mV
IN
V =+4.5V
70 140
90 180
50 100
60 120
PMOS
W
W
R
R
ILX=0.5A
m
m
IN
V =+3.0V
IN
V =+4.5V
NMOS
LX
NMOS Switch On-Resistance
I =0.5A
IN
V =+3.0V
LIMIT
IN
LX
I
Current Limit Threshold
Switching Frequency
V > V
3.5 4.1 4.7
1
A
fSW
(Note3)
MHz
mA
CC
I
fSW =500kHz
fSW =500kHz
1
No Load Supply Current
IN
I
32
SHDN
CC
IN
m
A
I
Shutdown Supply Current
SHDN = GND, I + I
<1
15
°
°
C
Thermal Shutdown Threshold
Hysteresis =15 C
150
CC
UVLO Under Voltage Lockout Threshold
V
falling, hysteresis = 90mV
2.5 2.6 2.7
V
FB
FB
EXTREF
I
FB Input Current
V =V
+0.1V
0
60 250 nA
0.48
W
TOFF
TOFF
TOFF
0.40
R
R
R
=30.1k
0.44
m
s
TOFF Off-Time
W
=110k
=499k
1.10 1.20 1.30
4.3 4.8 5.3
W
´
m
s
Startup Off-Time
On-Time
4 TOFF
m
s
TON
(Note3)
0.34
m
A
SS
I
SS Source Current
SS Sink Current
4
2
5
6
SS
I
SS
V =1V
mA
SHDN
CC
=0, V
m
A
SHDN Input Current
V
-1
+1
IL
V
0.8
V
SHDN Logic Levels
IH
V
2.0
OUT(RMS)
I
RMS
Maximum Output RMS Current
3.1 A
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Rev. A.5 - Jun., 2005
APW7093
Electrical Characteristics (Cont.)
(VIN=VCC=3.3V, VEXTREF=+1.1V, TA = -45 to +85oC, unless otherwise noted, Typical values are at TA =+25oC.)
APW7093
Unit
Symbol
Parameter
Test Conditions
Min Typ Max
IL
0.8
V
V
SHDN Logic Levels
IH
V
2.0
OUT(RMS)
RMS
I
Maximum Output RMS Current
3.1
A
Note2: The output voltage will have aDC-regulationlevel lower than the feedback error comparator threshold
by 50% of the ripple.
Note3: Recommended operating frequency, not production tested.
Functional Pin Description
Name
PIN (QFN)
PIN (QSOP)
FUNCTION
1,5,7,9,11,13,16,19,
25,26,28,30,32
N.C
X
No Connection, Not internally connected.
Supply Voltage Input for the internal PMOS Power Switch.
Not internally connected. Externally connect all pins for
proper operation.
IN
2,4
2,4
Inductor Connection. Connection for the drains of the PMOS
power switch and NMOS synchronous-rectifier switch.
LX
3,21,22,27,29
3,14,16 Connect the inductor from this node to the output filter
capacitor and load. Not internally connected. Externally
connect all pins for proper operation.
Soft-Start Connect a capacitor from SS to GND to limit inrush
current during startup.
External Reference Input Feedback input regulates to
VEXTREF. The PWM controller remains off until EXTREF is
greater than REF.
Off-Time Select Input. Sets the PMOS power switch
constant-off-time. Connect a resistor from TOFF to GND to
adjust the PMOS switch off-time.
Feedback Input. Connect directly to output for fixed-voltage
operation or to a resistive-divider for adjustable operating
modes.
SS
6
8
5
EXTREF
6
7
TOFF
10
12
FB
8
9
14,17,backside pad,
corner tabs
Analog Ground. Connect exposed backside pad and corner
tabs to analog GND.
GND
m
Reference Output. Bypass REF to GND with a 0.1 F
capacitor.
REF
GND
15
17
10
11
Tie to GND (pin 13 QFN; pin 9 SSOP)
Analog Supply Voltage Input. Supplies internal analog
CC
V
18
20,23,24
31
12
13,15
1
W
m
CC
circuitry. Bypass V with a 10 and 1 F low-pass filter. See
Figure2.
Power Ground. Internally connected to the internal NMOS
synchronous-rectifier switch.
Shutdown control Input Drive SHDN low to disable the
reference, control circuitry, and internal MOSFETs. Drive
PGND
SHDN
CC
high or connect to V for normal operation.
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Rev. A.5 - Jun., 2005
APW7093
Typical Application
APW7093
L
VOUT
VIN
LX
PGND
GND
FB
IN
33mF
10W
220mF
15mW
VCC
R2
1mF
SHDN
VEXTREF
REF
SS
EXTREF
TOFF
50KW
0.1mF
RTOFF
0.01mF
FORVIN =5V: L=1mH, RTOFF=100kW
FOR VIN=3.3V: L=0.68mH, RTOFF=68kW
Fig2. Typical Applicatin Circuit
Typical Characteristics
(Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68mH, RTOFF=68kW; for VIN=5V: L=1mH, TOFF=100kW. TA=25C
if not specially)
Effienciency vs. Output Current
No Load Supply Current vs. Input Voltage
100
95
50
VIN=5V, VOUT=3.3V
90
85
80
75
70
65
60
55
50
45
40
40
30
20
10
0
VOUT=1.25V
RTOFF=68kW
VIN=5V, VOUT=1.25V
VIN=5V, VOUT=2.5V
VIN=3.3V, VOUT=1.25V
0
1
2
3
4
5
6
0
1
2
3
Output Current(A)
Input Voltage(V)
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Rev. A.5 - Jun., 2005
APW7093
Typical Characteristics (Cont.)
(Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68mH, RTOFF=68kW; for VIN=5V: L=1mH, TOFF=100kW. TA=25C
if not specially)
Switching Frequency vs. Output Current
OFF-TIME vs. RTOFF
900
6
5
4
800
700
600
500
400
300
200
100
0
VIN=3.3V
VIN=5V
3
2
1
0
0
1
2
3
0
100
200
300
400
500
600
RTOFF(kW)
Output Current(A)
Start Up and Shut Down
VREF vs. Input Voltage
1.114
1.113
1.112
1.111
1.110
SHDN=2V/DIV
VSS=2V/DIV
IN=1A/DIV
TIME2ms/DIV
3.0
3.5
4.0
4.5
5.0
5.5
VIN=3.3V, VOUT=1.25V, ROUT=0.4W
Input Voltage(V)
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Rev. A.5 - Jun., 2005
APW7093
Typical Characteristics (Cont.)
(Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L= 0.68mH, RTOFF=68kW; for VIN=5V: L=1mH, TOFF=100kW. TA=25°C
if not specially)
Load Transient Response
Load Transient Response
IOUT=3A
IOUT=3A
IOUT=0A
IOUT=0A
VOUT 100mV/DIV
VOUT 100mV/DIV
TIME 20ms/DIV
TIME 20ms/DIV
di 3A
di 3A
=
=
VIN=5V, VOUT=2.5V,
VIN=5V, VOUT=1.25V,
dt
ms
dt
ms
Load Transient Response
Line Transient Response
IOUT=3A
VIN=5.0V
IOUT=0A
VIN=3.0V
VOUT 100mV/DIV
VOUT 100mV/DIV
TIME 20ms/DIV
TIME 40ms/DIV
VIN=3.3V, VOUT=1.25V,
di 3A
=
dt
ms
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Rev. A.5 - Jun., 2005
APW7093
Typical Characteristics (Cont.)
(Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L= 0.68mH, RTOFF=68kW; for VIN=5V: L=1mH, TOFF=100kW. TA=25°C
if not specially)
LightLoadWaveform
HeavyLoadWaveform
VLX 5V/DIV
VLX 5V/DIV
ILX 1A/DIV
ILX 1A/DIV
VOUT 50mV/DIV
VOUT 50mV/DIV
TIME1ms/DIV
TIME1ms/DIV
IOUT=100mA
IOUT=3A
VREF vs. Temperature
Output Voltage vs. Temperature
1.118
1.116
1.114
1.112
1.110
1.108
1.106
1.104
1.255
1.253
1.251
1.249
1.247
VIN=3.3V
VIN=3.3V
IOUT=0A
1.102
1.100
1.098
1.245
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature(°C)
Temperature(°C)
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Rev. A.5 - Jun., 2005
APW7093
Function Descriptions
path for current to flow when the inductor is discharging.
Replacing the Schottky diode with a low-resistance
NMOS synchronous switch reduces conduction losses
and improves efficiency. The NMOS synchronous-rectifier
switch turns on following a short delay (typ. 20ns) af-
ter the PMOS power switch turns off, thus preventing
cross-conduction or “shoot-through.” In constant-off-
time mode, the synchronous-rectifier switch turns off
just prior to the PMOS power switch turning on. While
both switches are off, inductor current flows through
the internal body diode of the NMOS switch.
The APW7093 synchronous, current-mode, constant
off-time, PWM DC-DC converter steps down input
voltages of 3V to 5.5V to an adjustable output voltage
from 1.1V to VIN, as set by the voltage applied at
EXTREF. It sources and sinks up to 3A of output
current. Internal switches composed of a 90mΩPMOS
power switch and a 60m ΩNMOS synchronous-rectifier
switch improve efficiency, reduce component count,
and eliminate the need for an external Schottky diode
across the synchronous switch.
The APW7093 operates in a constant-off-time mode
under all loads. A single resistor-programmable
constant- tradeoffs in efficiency, switching noise,
component size, and cost. When power is drawn from
a regulated supply, constant-off-time PWM architecture
essentially provides constant-frequency operation. This
architecture has the inherent advantage of quick
response to line and load transients. The APW7093’s
current-mode, constant-off-time PWM architecture
regulates the output voltage by changing the PMOS
switch on-time relative to the constant off-time.
Current Sourcing and Sinking
By operating in a constant-off-time, pseudo-fixed-
frequency mode, the APW7093 can both source and
sink current. Depending on the output current
requirement, the circuit operates in two modes. In the
first mode the output draws current and the APW7093
behaves as a regular buck controller, sourcing current
to the output from the input supply rail. However, when
the output is supplied by another source, the APW7093
operates in a second mode as a synchronous boost,
taking power from the output and returning it to the
input.
Constant-Off-TimeOperation
In the constant-off-time architecture, the FB voltage
comparator turns the PMOS switch on at the end of
each off-time, keeping the device in continuous-
conduction mode. The PMOS switch remains on until
the feedback voltage exceeds the external reference
voltage (VEXTREF) or the positive current limit is reached.
When the PMOS switch turns off, it remains off for the
programmed off-time (TOFF). To control the current
under short-circuit conditions, the PMOS switch
remains off for approximately 4 x TOFF when VFB <
VEXTREF / 4.
Thermal Resistance
Junction-to-ambient thermal resistance, θJA, is highly
dependent on the amount of copper area immediately
surrounding the IC leads. The APW7093 QFN pack-
age has 1in square of copper area and a thermal
resistance of 50°C/W with no forced airflow. The
APW7093 16-pin SSOP evaluation kit has 0.5 in
square of copper area and a thermal resistance of 80°C/
W with no forced airflow. Airflow over the board
significantly reduces the junction-to-ambient thermal
resistance. For heat sinking purposes, it is essential
to connect the exposed backside pad of the QFN
package to a large analog ground plane.
SynchronousRectification
In a step-down regulator without synchronous
rectification, an external Schottky diode provides a
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Rev. A.5 - Jun., 2005
APW7093
Function Descriptions(Cont.)
Shutdown
PD(CAP) = C ´ VIN2 ´ fSW
Drive SHDN to a logic-level low to place the APW7093
in low-power shutdown mode and reduce supply
current less than 1µA. In shutdown, all circuitry and
internal MOSFETs turn off, so the LX node becomes
where C = 500pF and fSW is the switching frequency.
Resistive losses in the two power switches are
approximated by:
PD(RES) = IO2 UT ´ RPMOS
high impedance. Drive SHDN to a logic-level high or
connect to VCC for normal operation.
where RPMOS is the on-resistance of the PMOS switch.
The junction-to-ambient thermal resistance required
to dissipate this amount of power is calculated by:
θJA = (TJ,MAX - TA,MAX) / (PD(CAP) + PD(RES))
where:
Power Dissipation
Power dissipation in the APW7093 is dominated by
conduction losses in the two internal power switches.
Power dissipation due to charging and discharging the
gate capacitance of the internal switches (i.e., switching
losses) is approximately:
θJA = junction-to-ambient thermal resistance
TJ,MAX = maximum junction temperature
TA,MAX = maximum ambient temperature
Application Information
For typical applications, use the recommended
component values in Figure 2. For other applications,
take the following steps:
Setting the Output Voltage
An external voltage applied to the EXTREF pin sets
the output voltage of the APW7093. This can come
directly from another voltage source or external
reference. When FB is directly tied to the output
(Figure 4), the output voltage range is limited by the
external reference’s input voltage limits. VEXTREF
should be limited to less than VIN-1.7V. Failure to
comply can cause the part to operate abnormally and
may cause part damage. Alternatively, the output can
be adjusted up to VIN by connecting FB to a resistor-
divider between the output voltage and ground (Figure
5). Use 50k Ωfor R1. R2 is given by:
1. Select the desired PWM-mode switching frequency.
See Figure 3 for maximum operating frequency.
2. Select the constant off-time as a function of input
voltage, output voltage, and switching frequency.
3. Select RTOFF as a function of off-time.
4. Select the inductor as a function of output voltage,
off-time, and peak-to-peak inductor current.
1400
VOUT=2.5V
1200
VOUT=3.3V
1000
800
600
400
200
0
V
æ
è
ö
÷
ø
OUT
R2 = R1×
- 1
ç
V
EXTREF
VOUT=1.1V
VOUT=1.25V
2.8
3.3
3.8
4.3
4.8
5.3
Input Voltage(V)
Fig3.Maximum RecommendedOperationFrequency
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Rev. A.5 - Jun., 2005
APW7093
Application Information(Cont.)
Setting the Output Voltage (Cont.)
VOUT=VEXTREF where:
fSW
V
- VOUT - VPMOS
IN
TOFF
=
(
)
V - VPMOS + VNMOS
IN
TOFF = the programmed off-time
VIN = the input voltage
LX
APW7093
VOUT = the output voltage
VPMOS = the voltage drop across the internal PMOS
power switch |IOUT X RPMOS|
VNMOS = the voltage drop across the internal NMOS
synchronous-rectifier switch |IOUT X RNMOS|
VEXTREF
EXTREF
FB
fSW = switching frequency
1.1V £ V
£ V - 1.7V
EXTREF
IN
Make sure that TON and TOFF are greater than 400ns
when sourcing current. Select RTOFF according to the
formula:
FIG.4 Adjsting the Output Voltage using EXTREF
VOUT
RTOFF = (TOFF - 0.18 ms) ´ (109k W/1.00 ms)
LX
Recommended values for RTOFF range from 24k Ωto
410k Ωfor off-times of 0.4µs to 4µs. Often the switching
frequency is set as high as possible, and the inductor value
is reduced to minimize the energy transferred from
inductor to capacitor during load-step recovery.
The operating frequency of the APW7093 is determined
primarily by TOFF (set by RTOFF), VIN, and VOUT as
shown in the following formula:
APW7093
R2
FB
EXTREF
REF
R1
æ
ö
V
- VOUT - VPMOS
V
OUT
IN
ç
÷
R2 = R1×
- 1
fSW
=
ç
÷
V
TOFF
(
V
- VPMOS + VNMOS
)
EXTREF
è
ø
IN
where VEXTREF = VREF = 1.1V
However, as the output current increases, the voltage
drop across the NMOS and PMOS switches increases
and the voltage across the inductor decreases. This
causes the frequency to drop. Assuming RPMOS =
RNMOS, the change in frequency can be approximated
with the following formula:
FIG.5 Adjsting the Output Voltage using FB
Programming the Switching Frequency and
Off-Time and On-Time
The APW7093 features a programmable PWM-mode
switching frequency, which is set by the input and
output voltage and the value of RTOFF, connected from
TOFF to GND. RTOFF sets the PMOS power switch
off-time in PWM mode. Use the following equation to
select the off-time while sourcing current according to
the desired switching frequency in PWM mode:
- DIOUT ´ RPMOS
DfSW
=
V ´ TOFF
IN
where RPMOS is the resistance of the internal
MOSFETs (70m Ωtyp).
Copyright ã ANPEC Electronics Corp.
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Rev. A.5 - Jun., 2005
APW7093
Application Information(Cont.)
Programming the Switching Frequency and Low-ESR and low-ESL Tantalum or ceramic capacitor
Off-Time and On-Time (Cont.)
should be suitable.
When sinking current, the switching frequency
increases due to the on-resistances of the internal
switches adding to the voltage across the inductor,
reducing the on-time. Calculate TON when sinking
current using the equation:
Output Capacitor Selection
The output filter capacitor affects the output voltage
ripple, output load-transient response, and feedback
loop stability. The output filter capacitor must have low
enough ESR to meet output ripple and load transient
requirements, yet have high enough ESR to satisfy
stability requirements. Also, the capacitance value must
be high enough to guarantee stability and absorb the
inductor energy going from a full-load sourcing to full
load sinking condition without exceeding the maximum
output tolerance.
æ
ö
VOUT - VNMOS
ç
ç
÷
÷
TON = TOFF
V
- VOUT + VPMOS
IN
è
ø
Inductor Selection
The key inductor parameters must be specified: inductor
value (L) and peak current (IPEAK). A lower value of
inductor allows smaller size but results in higher losses
and ripple. A good compromise between size and
losses is found at approximately a 25% ripple current
In applications where the output is subject to large
load transients, the output capacitor’s size typically
depends on how much ESR is needed to prevent the
output from dipping too low under a load transient.
to load current ratio (DI/IOUT = 0.25).
VOUT ´ TOFF
L =
IOUT ´ 0.25
RESR £ DVOUT /DIOUT(MAX)
The peak inductor current at full load is calculated by:
The actual microfarad capacitance value required is
defined by the physical size needed to achieve low
ESR, and by the chemistry of the capacitor technology.
Thus, the capacitor is usually selected by ESR, size
and voltage rating rather than by capacitance value.
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually
determined by the capacity needed to prevent overshoot
and undershoot from causing problems during load
transients. Generally, once enough capacitance is
added to meet the overshoot requirement, undershoot
at the rising-load edge is no longer a problem.
VOUT ´ TOFF
IPEAK = IOUT
+
2 ´ L
where IOUT is the maximum source or sink current.
Choose an inductor with a saturation current at least
as high as the peak inductor current. Additionally, verify
the peak inductor current while sourcing output
current (IOUT = ISOURCE) does not exceed the positive
current limit. The inductor selected should exhibit low
losses at the chosen operating frequency.
Input Capacitor Selection
The input filter capacitor reduces peak currents and
noise at the voltage source. A 22µF to 47µF capacitor
may be required for higher power and dynamic loads.
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Rev. A.5 - Jun., 2005
APW7093
Application Information(Cont.)
Soft-Start
Input Source
The output of the APW7093 can accept current due
to the reversible properties of the buck and the boost
converter. When voltage at the output of the APW7093
(low-voltage port) exceeds or equals the output set
voltage the flow of energy reverses, going from the
output to the input (high-voltage port). If the input (high
voltage port) is not connected to a low-impedance
source capable of absorbing energy, the voltage at
the input will rise. This voltage can violate the abso-
lute maximum voltage at the input of the APW7093
and destroy the part. This occurs when sinking current
because the topology acts as a boost converter,
pumping energy from the low-voltage side (the output),
to the high-voltage side (the input). The input (high-
voltage side) voltage is limited only by the clamping
effect of the voltage source connected there. To avoid
this problem, make sure the input to the APW7093 is
connected to a low impedance, two quadrant supply
or that the load (excluding the APW7093) connected
to that supply consumes more power than the amount
being transferred from the APW7093 output to the
input.
Soft-start allows a gradual increase of the internal
current limit to reduce input surge currents at startup
and at exit from shutdown. A timing capacitor, CSS,
placed from SS to GND sets the rate at which the
internal current limit is changed. Upon power-up, when
the device comes out of under-voltage lockout (2.6V
typ.) or after the SHDN pin is pulled high, a 4.7µA
constant current source charges the soft-start capacitor
and the voltage on SS increases. When the voltage
on SS is less than approximately 0.7V, the current
limit is set to zero. As the voltage increases from
0.7V to approximately VIN, the current limit is adjusted
from 0V to the current-limit threshold. The voltage
across the soft-start capacitor changes with time
according to the equation:
4.7mA ´ t
VSS
=
CSS
The output current limit during soft-start varies with
the voltage on the soft-start pin, SS, according to the
equation:
(V - 0.7V)
SS
ILIIM(SS)
=
´ ILIMIT ,VSS£1.8V
1.1V
Current Limit and Short Circuit Protection
where ILIMIT is the current-limit threshold from the
Electrical Characteristics. The constant-current source
stops charging once the voltage across the soft-start
capacitor reaches 1.8V.
The APW7093 monitors sourcing and sinking current,
and limits the maximum output current to prevent
damages during overload or short-circuit.
Circuit Layout and Grounding
SHDN
Good layout is necessary to achieve the APW7093’s
intended output power level, high efficiency, and low
noise. Good layout includes the use of ground planes,
careful component placement, and correct routing of
traces using appropriate trace widths. The following
points are in order of decreasing importance:
0
VIN
VSS(A)
1.8V
0.7V
0
ILIMIT(A)
0
ILIMIT
t
Fig6. Soft-Start Current Limit
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Rev. A.5 - Jun., 2005
APW7093
Application Information(Cont.)
Circuit Layout and Grounding (Cont.)
1. Minimize switched-current and high-current ground
loops. Connect the input capacitor’s ground, the
output capacitor’s ground, and PGND close
together. Split the ground connections. Use separate
tracesor planesfor thePGNDandGNDand tie them
together at a single point.
2. The output capacitor should be placed close to the
output terminals to obtain better smoothing effect
on the output ripple.
3. Connect the input filter capacitor less than 5mm
away from IN. The connecting copper trace carries
large currents and must be at least 1mm wide,
preferably 2.5mm.
4.Place the LX node components as close together
and as near to the device as possible. This reduces
resistive and switching losses as well as noise.
5.Ground planes are essential for optimum
performance. In most applications, the circuit is
located on a multilayer board and full use of the four
or more layers is recommended. For heat
dissipation, connect the exposed backside pad of
the QFN package to a large analog ground plane,
preferably on a surface of the board that receives
good airflow. If the ground plane is located on the
top layer, make use of the N.C. pins adjacent to
GND to lower thermal resistance to the ground plane.
If the ground is located elsewhere, use several vias
to lower thermal resistance. Typical applications use
multiple ground planes to minimize thermal
resistance. Avoid large AC currents through the
analog ground plane.
Copyright ã ANPEC Electronics Corp.
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Rev. A.5 - Jun., 2005
APW7093
Packaging Information
SSOP-16
S
D
N
GAUGE
PLANE
H
E
1
2
3
A
L
1
A1
B
e
Millimeters
Inches
Dim
Min.
Max.
1.75
0.25
0.30
5.05
4.05
Min.
0.053
0.004
0.008
0.187
0.147
Max.
0.069
0.010
0.012
0.199
0.160
A
A1
B
1.350
0.10
0.20
4.75
3.75
D
E
e
0.625 TYP.
0.025 TYP.
5.75
0.4
6.25
1.27
0.18
H
L
0.226
0.016
0.002
0.246
0.050
0.007
S
0.05
f
°
0
°
8
°
0
°
8
1
Copyright ã ANPEC Electronics Corp.
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Rev. A.5 - Jun., 2005
APW7093
Packaging Information
QFN-32
D
D2
32
31
30
29
28
27
26
25
1
2
24
23
31 32
L
1
2
3
4
22
21
20
19
E
E2
5
6
18
17
7
8
9
10
11
12
13
14
15
16
e
b
A
A3
A1
Millimeters
Inches
Dim
Min.
-
Max.
0.84
0.04
Min.
-
Max.
0.033
0.0015
A
A1
A3
D
0.00
0.00
0.20 REF.
0.008 REF.
4.90
4.90
0.18
3.50
3.50
5.10
5.10
0.28
3.60
3.60
0.192
0.192
0.007
0.138
0.138
0.200
0.200
0.011
0.142
0.142
E
b
D2
E2
e
0.500 BSC
0.020 BSC
L
0.35
0.45
0.014
0.018
Copyright ã ANPEC Electronics Corp.
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Rev. A.5 - Jun., 2005
APW7093
Physical Specifications
Terminal Material
Lead Solderability
Packaging
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
2500 devices per reel
Reflow Condition (IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
°
t 25 C to Peak
Time
Classificatin Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Sn-Pb Eutectic Assembly
Pb-Free Assembly
°
°
3 C/second max.
3 C/second max.
Preheat
°
°
150 C
100 C
-
-
-
Temperature Min (Tsmin)
Temperature Max (Tsmax)
Time (min to max) (ts)
°
°
150 C
200 C
60-120 seconds
60-180 seconds
Time maintained above:
°
°
183 C
217 C
-
Temperature (TL)
Time (tL)
60-150 seconds
60-150 seconds
-
Peak/Classificatioon Temperature (Tp)
See table 1
See table 2
°
Time within 5 C of actual
10-30 seconds
20-40 seconds
Peak Temperature (tp)
Ramp-down Rate
°
°
6 C/second max.
6 C/second max.
6 minutes max.
8 minutes max.
°
Time 25 C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright ã ANPEC Electronics Corp.
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Rev. A.5 - Jun., 2005
APW7093
Classificatin Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350
<2.5 mm
°
°
225 +0/-5 C
240 +0/-5 C
³
°
°
2.5 mm
225 +0/-5 C
225 +0/-5 C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350-2000
Volume mm3
>2000
<1.6 mm
1.6 mm – 2.5 mm
³ 2.5 mm
260 +0°C*
260 +0°C*
250 +0°C*
260 +0°C*
250 +0°C*
245 +0°C*
260 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C.
For example 260°C+0°C) at the rated MSL level.
Reliability test program
Test item
SOLDERABILITY
HOLT
PCT
TST
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C , 5 SEC
1000 Hrs Bias @ 125 °C
168 Hrs, 100 % RH , 121°C
-65°C ~ 150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms , Itr > 100mA
ESD
Latch-Up
Carrier Tape & Reel Dimension
t
D
P
Po
E
P1
Bo
F
W
Ao
D1
Ko
Copyright ã ANPEC Electronics Corp.
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Rev. A.5 - Jun., 2005
APW7093
Carrier Tape & Reel Dimension
T2
J
C
A
B
T1
Application
SSOP-16
A
6.95
B
D0
D1
E
F
P0
P1
P2
5.4
T2
2.2
1.55±0.05 1.55±0.1 1.75±0.1 5.5±0.05 4.0±0.1
8.0±0.1 2.0±0.05
T
W
W1
C1
C2
T1
T2
C
0.3±0.05
12.0±0.3
9.5
13±0.3
21±0.8
13.5±0.5 2.0±0.2
80±1
(mm)
Cover Tape Dimensions
Application
SSOP- 16
Carrier Width
Cover Tape Width
Devices Per Reel
16.8
12.3
2500
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright ã ANPEC Electronics Corp.
Rev. A.5 - Jun., 2005
20
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