APW8724 [ANPEC]
Common single PWM Controller with Multiform supply Voltage; 常见的单PWM控制器，多形式的供应电压
| 型号： | APW8724 |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Common single PWM Controller with Multiform supply Voltage |
| 文件： | 总22页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW8724
Common single PWM Controller with Multiform supply Voltage
Features
General Description
·
Adjustable Output Voltage from +0.6V to +5.0V
The APW8724 is a single-phase, constant on-time, syn-
chronous PWM controller, which drives N-channel
MOSFETs. The APW8724 steps down high voltage to
generate low-voltage chipset, RAM supplies in notebook
computers or mother board applications.
- 0.6V Reference Voltage
- +0.6% Accuracy
·
·
Operates from An Input Battery Voltage Range of
+3V to +25V
The APW8724 provides excellent transient response and
accurate DC voltage output in either PFM or PWM Mode.
In Pulse Frequency Mode (PFM), the APW8724 provides
very high efficiency over light to heavy loads with loading-
modulated switching frequencies. In PWM Mode, the con-
verter works nearly at constant frequency for low-noise
requirements. The unique ultrasonic mode maintains the
switching frequency above 37kHz, which eliminates noise
in audio application. APW8724 is built in remote sense
function for applications that require remote sense.
The APW8724 is equipped with accurate positive current
limit, output under-voltage, and output over-voltage
protections, perfect for multiform applications. The Power-
On-Reset function monitors the voltage on VCC to pre-
vent wrong operation during power-on. The APW8724 has
an internal 4ms digital soft start that ramps up the output
voltage with programmable slew rate to reduce the start-
up current. The enable function can let user easy to apply
APW8724.
Multiform Purpose Input Voltage Collocation
- VCC=5V / VIN=8~19V For NB application
- VCC=5~12V / VIN=5~12V For table PC application
Remote Feedback Sense for Excellent Output
Voltage Regulation
·
·
·
·
·
·
·
·
·
·
·
·
·
Power-On-Reset Monitoring on VCC pin
Excellent line and load transient responses
Ultrasonic Operation Eliminated Audio Noise
PFM mode for increased light load efficiency
300kHz Constant PWM Switching Frequency
Integrated MOSFET Drivers
Integrated Bootstrap Forward P-CH MOSFET
Adjustable Integrated Soft-Start
Power Good Monitoring
70% Under-Voltage Protection
125% Over-Voltage Protection
Adjustable Current-limit protection
- Using Sense Low-Side MOSFET’s RDS(ON)
Over-Temperature Protection
The APW8724 is available in 10pin TDFN 3x3 package
respectively.
·
·
·
TDFN3x3-10 Package
Lead Free and Green Devices Available
(RoHS Compliant)
Simplified Application Circuit
5~12V
VIN
RPOK
EN
POK
VCC
Applications
UGATE
Q1
·
·
·
·
·
Notebook
APW8724
L
VOUT
Table PC
PHASE
Hand-Held Portable
AIO PC
FBRTN
LGATE/
OCSET
Q2
Wide input DC/DC Regulators
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jan., 2013
APW8724
Ordering and Marking Information
APW8724
Package Code
QB:TDFN3x3-10
Assembly
Meterial
Temperature Range
I : -40 to 85 oC
Handling Code
Handling
Code
Te.mperature
Range
TR: Tape & Reel
Assembly Meterial
:
G : Halogen and Lead Free Device
L
Lead Free Device
Package Code
APW
APW8724QB:
XXXXX - Date Code
8724
XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
BOOT 1
UGATE 2
10 PHASE
9 EN
POK 3
8 FB
GND 4
7 FBRTN
6 VCC
LGATE/OCSET 5
TDFN-10 3X3
(top view)
= GND and Thermal Pad (connected to GND plane for better heat dissipation)
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
VCC Supply Voltage (VCC to GND)
BOOT Supply Voltage (BOOT to GND)
BOOT Supply Voltage (BOOT to PHASE)
EN to GND
Rating
-0.3 ~ 16
-0.3 ~ 44
-0.3 ~ 16
-0.3 ~ VCC+0.3
-0.3~7
Unit
V
VCC
VBOOT-GND
VBOOT
VEN
V
V
V
All Other Pins (POK, FBRTN and FB to GND)
UGATE Voltage (UGATE to PHASE)
V
<20ns pulse width
-5 ~ VBOOT+0.3
V
V
>20ns pulse width
-0.3 ~ VBOOT+0.3
LGATE Voltage (LGATE to GND)
PHASE Voltage (PHASE to GND)
<20ns pulse width
>20ns pulse width
-5 ~ VCC+0.3
-0.3 ~ VCC+0.3
<20ns pulse width
>20ns pulse width
VPHASE
-5 ~ 35
V
-0.3~ 28
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APW8724
Absolute Maximum Ratings (Cont.) (Note 1)
Symbol
TJ
Parameter
Maximum Junction Temperature
Rating
150
Unit
oC
Storage Temperature
TSTG
TSDR
-65 ~ 150
260
oC
oC
Maximum Soldering Temperature, 10 Seconds
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
Thermal Resistance -Junction to Ambient (Note 2)
°C/W
qJA
TDFN3x3-10
55
Note 2: qJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of package is soldered directly on the PCB.
Recommended Operating Conditions (Note 3)
Symbol
Parameter
Range
3 ~ 25
Unit
V
VIN
Converter Input Voltage
VCC Supply Voltage
VCC
VOUT
IOUT
4.5 ~ 13.2
0.6~5
V
Converter Output Voltage
Converter Output Current
Ambient Temperature
Junction Temperature
V
0~25
A
-40 ~ 85
-40 ~ 125
oC
oC
TA
TJ
Note 3: Refer to the application circuit for further information.
Electrical Characteristics
These specifications apply for TA = -40oC to +85oC, unless otherwise stated. All typical specifications TA= +25oC, VCC
= 12V
APW8724
Symbal
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Reference VOLTAGE
Reference Voltage
-
0.6
-
-
V
TA = 25 oC
-0.6
+0.6
%
VREF
TA = -40 oC ~ 85 oC, Line / Load
Transient
Regulation Accuracy
-1.0
-
+1.0
%
IFB
FB Input Bias Current
FB=0.5V
-
-
-
-
1
1
mA
mA
IFBRTN
FBRTN Leakage Current
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Rev. A.1 - Jan., 2013
APW8724
Electrical Characteristics
These specifications apply for TA = -40oC to +85oC, unless otherwise stated. All typical specifications TA= +25oC, VCC
= 12V
APW8724
Symbal
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY CURRENT
VCC Current, EN=5V, VFB=0.7V,
PHASE=0.5V
IVCC
VCC Input Bias Current
VCC Shutdown Current
-
-
2
-
3
mA
IVCC_SHD
EN=GND, VCC=5V
10
mA
N
SWITCHING FREQUENCY AND DUTY
TON
PWM On Time
Vin=12V, VOUT=1V
222
-
278
100
400
333
-
ns
ns
ns
TON(MIN)
TOFF(MIN)
Minimum on time
Minimum off time
VFB=0.45V, VPHASE=-0.1V
300
500
Minimum Ultrasonic Skip
Operating Frequency
25
37
-
kHz
Power On Timing
Maximum Current Limit
Setting Time
ROCSET is open
-
-
-
500
-
ms
ms
From POR_R to Internal sample
clock start
IOCSET Early Sourcing Timing
150
Positive Offset 60mV(Typ.), When
TSS is about 4ms, the first pulse
delays from sample & hold
completed
D1 only
TSS
The First Pulse Delay by EA
Offset
-
-
350
4
-
-
ms
Internal Soft Start Time
VOUT=0% to VOUT Regulation(95%)
ms
GATE DRIVER
5V UG Pull-Up Resistance
VCC=5V, BOOT-UG=1V
-
-
-
-
-
-
-
-
-
-
-
-
5
3
-
-
-
-
-
-
-
-
-
-
-
-
W
W
W
W
W
W
W
W
ns
ns
ns
ns
12V UG Pull-Up Resistance
5V UG Sink Resistance
12V UG Sink Resistance
5V LG Pull-Up Resistance
12V LG Pull-Up Resistance
5V LG Sink Resistance
12V LG Sink Resistance
UG to LG Dead time
VCC=12V, BOOT-UG=1V
VCC=5V, UG-PHASE=1V
VCC=12V, UG-PHASE=1V
VCC=5V, VCC-LG=1V
2
1.3
5
VCC=12V, VCC-LG=1V
3
VCC=5V, LG-GND=1V
2
VCC=12V, LG-GND=1V
1.3
40
20
40
20
UG falling to LG rising at VCC=5V
UG falling to LG rising at VCC=12V
LG falling to UG rising at VCC=5V
LG falling to UG rising at VCC=12V
LG to UG Dead time
BOOTSTRAP SWITCH
VF
IR
Ron
VVCC – VBOOT-GND, IF = 10mA
-
-
0.2
-
0.4
0.5
V
VBOOT-GND = 30V, VPHASE = 25V,
VVCC = 5V
Reverse Leakage
mA
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APW8724
Electrical Characteristics
These specifications apply for TA = -40oC to +85oC, unless otherwise stated. All typical specifications TA= +25oC, VCC
= 12V
APW8724
Symbal
Parameter
Test Condition
Min.
Typ.
Max.
Unit
VCC POR THRESHOLD
Rising VCC POR Threshold
VVCC_THR
4.25
-
4.35
300
4.45
-
V
Voltage
VCC POR Hysteresis
mV
CONTROL INPUTS
Shutdown
Enable
-
0.83
-
-
-
0.4
-
EN Threshold
V
EN Leakage
EN=0V
0.1
1.0
mA
POWER-OK INDICATOR
POK in from Lower (POK Goes
High)
87
90
70
93
75
%
%
%
POK out from normal falling (POK
Goes Low)
VPOK
POK Threshold
65
POK out from normal rising (POK
Goes Low)
120
125
130
IPOK
POK Leakage Current
POK Sink Current
VPOK=5V
-
5
-
0.1
15
1
-
mA
mA
ms
VPOK=0.5V
POK Enable Delay Time
VOUT from 0% to POK High
5.5
-
CURRENT SENSE
IOCSET
IOCSET OCP Threshold
IOCSET Sourcing
22.5
-
25
27.5
-
mA
IOCSET Temperature
Coefficient
ppm/
oC
TCIOCSET
On The Basis of 25°C
2780
Maximum Current Limit
Threshold
VROCSET
ROCSET open
360
-3
400
0
440
3
mV
mV
Zero Crossing Comparator
Offset
VGND-PHASE Voltage
PROTECTION
VUV
UVP Threshold
65
70
30
75
-
%
ms
ms
%
UVP Debounce Interval
UVP Enable Delay
-
VOUT from 0% to UVP enable
VFB rising, LG fully turn on
VFB falling, Driver both off
VFB Rising
-
5.5
125
105
2
VOVR
OVP Rising Threshold
OVP Falling Threshold
OVP Propagation Delay
120
130
-
-
-
-
%
ms
OTP Rising Threshold (Note
4)
TOTR
-
-
150
25
-
-
oC
oC
OTP Hysteresis (Note 4)
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APW8724
Pin Description
PIN
FUNCTION
No.
1
Name
BOOT
UGATE
POK
Supply Input for The UGATE Driver and An Internal Level-shift Circuit. Connect to an external
capacitor to create a boosted voltage suitable to drive a logic-level N-channel MOSFET.
2
Output of The High-side MOSFET Driver. Connect this pin to Gate of the high-side MOSFET.
Power Good Output. POK is an open drain output used to indicate the status of the output
voltage. Connect the POK in to +5V through a pull-high resistor.
3
4
GND
Signal Ground for The IC
Output of The Low-side MOSFET Driver And Current-Limit Setting Input. Connect this pin to
Gate of the low-side MOSFET. There is an internal source current 25mA through a resistor from
LGATE/OCSET pin to GND before power on. This action is used to monitor the voltage drop
across the Drain and Source of the low-side MOSFET for current limit.
5
LGATE/OCSET
Supply Voltage Input Pin for Control Circuitry. Connect +5V~+12V from the VCC pin to the
GND. Decoupling at least 1µF of a MLCC capacitor from the VCC pin to the GND.
6
7
VCC
This pin is the negative node of the differential remote voltage sensing. The RTN pin should be
connected to the remote GND sense point directly.
FBRTN
Output Voltage Feedback Pin. This pin is connected to the resistive divider in remote side that
set the desired output voltage. The POK, UVP, and OVP circuits detect this signal to report
output voltage status.
8
9
FB
EN
Enable/Shutdown Pin. When EN=1, enable the PWM controller, EN=0, shutdown the PWM
controller.
Junction Point of The High-side MOSFET Source, Output Filter Inductor and The Low-side
MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves as the
lower supply rail for the UG high-side gate driver.
10
PHASE
GND
Exposed pad
Signal Ground for The IC
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APW8724
Typical Operating Characteristics
Efficiency vs. Load Current
FSW=300KHz, VOUT=1.05V
Reference Voltage vs. Junction
Temperature
0.61
VCC = 12V
90
85
80
0.605
0.6
0.595
0.59
75
70
VIN=19V
VIN=8V
H-Side: SM4370NSKP*1
L-Side: SM4373NSKP*1
65
60
0.1
1
10.0
100
-20
0
20
40
60
80 100 120
Junction Temperature (oC)
Input Voltage vs Switching
Frequency
Switching Frequency vs. Junction
Temperature
400
350
340
330
320
310
300
290
280
270
260
250
350
300
250
200
150
Vout=1.05V ,Iout=5A(PWM)
3
5
7
9
11 13 15 17 19 21 23 25
Input Voltage(V)
-20
0
20
40
60
80 100 120
(oC)
Junction Temperature
Input Voltage vs Output Voltage
IOCSET vs. Junction Temperature
1.070
32
30
1.060
1.050
28
26
24
22
20
18
1.040
1.030
0
5
10
15
20
25
-20
0
20
40
60
80 100 120
Input Voltage(V)
Junction Temperature (oC)
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APW8724
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified.
PowerOff
PowerOn
VIN
VIN
1
1
2
3
VOUT
VOUT
2
3
VPHASE
VPHASE
CH1:VIN ,10V/Div
CH2:Vout, 500m V/Div
CH3:VPHASE , 10V/Div
CH1:VIN ,10V/Div
CH2:Vout, 500m V/Div
CH3:VPHASE , 10V/Div
TIM E:2m s/Div
TIM E:50m s/Div
Enable
Shutdown
VEN
1
2
1
VOUT
VEN
RLOAD=12Ω
VOUT
2
3
VPHASE
VPHASE
3
CH1:VEN ,5V/Div
CH1:VEN , 5V/Div
CH2:Vout,500m V/Div
CH3:VPHASE ,10V/Div
CH2:Vout,500m V/Div
CH3:VPHASE , 10V/Div
TIM E:1m s/Div
TIM E:5m s/Div
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APW8724
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified.
Under-Voltage Protection
Over-CurrentProtection
ROCSET=5.1k,RDS(low
=8.4m Ω
Side)
VFB
VOUT
1
2
3
1
2
VLGATE
VLAGTE
VUGATE
3
4
VUAGTE
I
L
CH1:VFB , 500m V/Div
CH2:VLGATE ,10V/Div
CH3:VUGATE ,20V/Div
TIM E:10us/Div
CH1:VOUT , 10V/Div
CH2:VLGATE , 10V/Div
CH3:VUGATE ,20V/Div
CH4:I ,10A/Div
L
TIM E:20m s/Div
Load Transient
PowerOK
VOUT
1
VOUT
1
POK
2
I
OUT
2
CH1:VOUT ,50m V/Div
CH1:VOUT ,500m V/Div
CH2:VPOK ,5V/Div
TIM E:1m s/Div
CH2:I ,5A/Div
OUT
TIM E:200us/Div
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APW8724
Block Diagram
POK
FBRTN
GND
VREF x 125%
VREF
Sense Low-Side
VROCSET
Vcompare
VREF x 70%
FB
Current Limit
125% VREF
OV
UV
Fault
Latch
Logic
BOOT
UGATE
PHASE
70% VREF
Thermal
Shutdown
Vcompare
On-Time
Generator
Error
Comparator
VCC
VCC
Digital Soft Start
LGATE
VREF
VCC
EN
PHASE
Sample
and Hold
POR
25mA
VROCSET
To LGATE
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APW8724
Typical Application Circuit
VCC Supply 5V to 12V
VIN
RVCC
2R2
CIN
APW8724 (TDFN3*3-10)
CVCC
1µF
560µF
CBOOT
0.1µF
1
2
6
3
BOOT
VCC
POK
Q1
APM4350
L1
5V Pull-High
Source
UGATE
RPOK
100kΩ
VOUT V+_near
V+_remote
Enable signal
10
5
9
7
PHASE
ON
EN
1µH
Q2
APM435
4
L
O
A
D
OFF
COUT
LGATE/
OCSET
COUT
MLCC
FBRTN
R1
15kΩ
820µF
22µFx 4
ROCSET
FB
8
GND
4
V-_near
V-_remote
R2
10kΩ
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APW8724
Function Description
Constant-On-Time PWM Controller with Input Feed-For-
ward
Where FSW is the nominal switching frequency of the con-
verter in PWM mode.
The constant-on-time control architecture is a pseudo-
fixed frequency with input voltage feed-forward. This ar-
chitecture relies on the output filter capacitor’s effective
series resistance (ESR) to act as a current-sense resis-
tor so the output ripple voltage provides the PWM ramp
signal. In PFM operation, the high-side switch on-time is
controlled by the on-time generator is determined solely
by a one-shot whose pulse width is inversely propor-
tional to the input voltage and directly proportional to the
output voltage. In PWM operation, the high-side switch
on-time is determined by a switching frequency control
circuit in the on-time generator block.
The load current at handoff from PFM to PWM mode is
given by:
1
2
V
- VOUT
IN
ILOAD(PFMtoPWM)
=
´
´ TON- PFM
L
V
- VOUT
1
VOUT
IN
=
´
´
L
FSW
V
IN
In this case, APW8724 operates in ultrasonic mode with
PFM when the load is zero. The ultrasonic mode is illus-
trated as below description.
Ultrasonic Mode
The ultrasonic mode activates an unique PFM mode with
a minimum switching frequency of 25kHz. The minimum
frequency 25kHz of ultrasonic mode eliminates audio-
frequency interference in light load condition. It will transit
to unique PFM mode when output loading makes the
frequency bigger than ultrasonic frequency.
The switching frequency control circuit senses the switch-
ing frequency of the high-side switch and keeps regulat-
ing it at a constant frequency in PWM mode. The design
improves the frequency variation and is more outstand-
ing than a conventional constant-on-time controller, which
has large switching frequency variation over input voltage,
output current, and temperature. Both in PFM and PWM,
the on-time generator, which senses input voltage on
PHASE pin, provides very fast on-time response to input
line transients.
In ultrasonic mode, the controller automatically transits
to fixed-frequency PWM operation when the load reaches
the same critical conduction point (ILOAD(PFM to PWM)).
When the controller detects that no switching has oc-
curred within about 40ms (Typical), an ultrasonic pulse
will be occurred. The ultrasonic controller turns on the
low-side MOSFET firstly to reduce the output voltage. Af-
ter feedback voltage drops below the internal reference
voltage, the controller turns off the low-side MOSFET and
triggers a constant-on-time. When the constant-on-time
has expired, the controller turns on the low-side MOSFET
again until the inductor current is below the zero-cross-
ing threshold. The behavior is the same as PFM mode.
Another one-shot sets a minimum off-time (typical:
400ns). The on-time one-shot is triggered if the error com-
parator is high, the low-side switch current is below the
current-limit threshold, and the minimum off-time one-
shot has timed out.
Pulse-Frequency Modulation (PFM)
In PFM mode, an automatic switchover to pulse-frequency
modulation (PFM) takes place at light loads. This
switchover is affected by a comparator that truncates the
low-side switch on-time at the inductor current zero
crossing. This mechanism causes the threshold between
PFM and PWM operation to coincide with the boundary
between continuous and discontinuous inductor-current
operation (also known as the critical conduction point).
The on-time of PFM is given by:
Power-On-Reset (POR)
A Power-On-Reset (POR) function is designed to prevent
wrong logic controls when the VCC voltage is low. The
POR function continually monitors the bias supply volt-
age on the VCC pin if at least one of the enable pins is set
high. When the rising VCC voltage reaches the rising
POR voltage threshold (4.35V, typical), the POR signal
goes high and the chip initiates soft-start operations.
When this voltage drops lower than 4.25V (typical), the
POR disables the chip.
1
VOUT
TON- PFM
=
´
FSW
V
IN
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APW8724
Function Description (Cont.)
Current-Limit
The PCB layout guidelines should ensure that noise and
DC errors do not corrupt the current-sense signals at
PHASE. Place the hottest power MOSEFTs as close to
the IC as possible for best thermal coupling. When com-
bined with the under-voltage protection circuit, this cur-
rent-limit method is effective in almost every circumstance.
The current-limit circuit employs a “valley” current-sens-
ing algorithm (See Figure 1). The APW8724 uses the
low-side MOSFET RDS(ON) of the synchronous rectifier as a
current-sensing element. If the magnitude of the current-
sense signal at PHASE pin is above the current-limit
threshold, the PWM is not allowed to initiate a new cycle.
The actual peak current is greater than the current-limit
threshold by an amount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and maxi-
mum load capability are the functions of the sense
resistance, inductor value, and input voltage.
Under-Voltage Protection
In the operational process, if a short-circuit occurs, the
output voltage will drop quickly. When load current is big-
ger than current-limit threshold value, the output voltage
will fall out of the required regulation range. The under-
voltage protection circuit continually monitors the FB volt-
age after soft-start is completed. If a load step is strong
enough to pull the output voltage lower than the under-
voltage threshold, the under-voltage threshold is 70% of
the nominal output voltage, the internal UVP delay counter
starts to count. After 30ms debounce time, the device turns
off both high-side and low-side MOSEFET with latched
and starts a soft-stop process to shut down the output
gradually. Toggling enable pin to low or recycling VCC,
will clear the latch and bring the chip back to operation.
IPEAK
IOUT
ΔI
ILIMIT
0
Time
Figure 1. Current-Limit Algorithm
Over-Voltage Protection (OVP) of the PWM Converter
The over-voltage protection monitors the FB voltage to
prevent the output from over-voltage condition. When the
output voltage rises above 125% of the nominal output
voltage, the APW8724 turns off the high-side MOSFET
and turns on the low-side MOSFET until the output volt-
age falls below the falling below 105%, the OVP com-
parator is disengaged and both high-side and low-side
drivers turn off.
A resistor (ROCSET), connected from the LGATE/OCSET to
GND, programs the current-limit threshold. Before the IC
initiates a soft-start process, an internal current source,
IOCSET (25mA typical), flowing through the ROCSET develops
a voltage (VOCSET) across the ROCSET. The device holds
VOCSET and stops the current source, IOCSET, during normal
operation. The relationship between the sampled volt-
age VOCSET and the current-limit threshold ILIMIT is given by:
This OVP scheme only clamps the voltage overshoot and
does not invert the output voltage when otherwise acti-
vated with a continuously high output from low-side
MOSFET driver. It’s a common problem for OVP schemes
with a latch. Once an over-voltage fault condition is set, it
can be reset by releasing COMP or toggling VCC power-
on-reset signal.
2´ IOCSET ´ ROCSET
ILIMIT =
RDS(ON)(low - side)
ILIMIT can be expressed as IOUT minus half of peak-to-peak
inductor current.
The APW8724 has an internal current-limit voltage
(VOCSET_MAX), and the value is 0.4V typically. When the ROCSET
x IOCSET exceeds 0.4V or the ROCSET is floating or not
connected, the over current threshold will be the internal
default value 0.4V.
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Rev. A.1 - Jan., 2013
APW8724
Function Description (Cont.)
ENPin Control
When VEN is above the EN high threshold (0.83V,
minimum). th converter is enabled in automatic PFM/
PWM operation mode. When VEN is below the EN low
threshold (0.4V, maximum), the chip is in the shutdown
and only low leakage current is taken from VCC.
Adaptive Shoot-Through Protection of the PWM Con-
verter
The gate drivers incorporate an adaptive shoot-through
protection to prevent high-side and low-side MOSFETs
from conducting simultaneously and shorting the input
supply. This is accomplished by ensuring the falling gate
has turned off one MOSFET before the other is allowed to
rise.
During turn-off the low-side MOSFET, the LGATE voltage
is monitored until it is below 1.5V threshold, at which
time the UGATE is released to rise after a constant delay.
During turn-off of the high-side MOSFET, the UGATE-to-
PHASE voltage is also monitored until it is below 1.5V
threshold, at which time the LGATE is released to rise
after a constant delay.
Remote Sense
APW8724 has a FBRTN pin for applications that require
remote sense. In some applications where high current,
low voltage and accurate output voltage regulation are
needed, FBRTN can sense the negative terminal of re-
mote load capacitor directly, and improve output voltage
drop which is due to the board interconnection loss.
Power OK Indicator
The APW8724 features an open-drain POK output pin to
indicate one of the IC's working statuses including soft-
start, under-voltage fault, over-current fault.
In normal operation, when the output voltage rises 90%
of its target value, the POK goes high. When the output
voltage outruns 50% or 125% of the target voltage, POK
signal will be pulled low immediately.
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jan., 2013
APW8724
Application Information
Output Voltage Selection
saturation. In some types of inductors, especially core
that is made of ferrite, the ripple current will increase
abruptly when it saturates. This results in a larger output
ripple voltage. Besides, the inductor needs to have low
DCR to reduce the loss of efficiency.
The output voltage can be programmed with a resistive
divider. Use 1% or better resistors for the resistive divider
is recommended. The FB pin is the inverter input of the
error amplifier, and the reference voltage is 0.6V. The
output voltage is determined by:
Output Capacitor Selection
æ
ç
è
ö
÷
÷
ø
R1
R2
ç
VOUT = 0.6 ´ 1+
Output voltage ripple and the transient voltage devia-
tion are factors which have to be taken into consider-
ation when selecting an output capacitor. Higher capaci-
tor value and lower ESR reduce the output ripple and
the load transient drop. Therefore, selecting high per-
formance low ESR capacitors is recommended for
switching regulator applications. In addition to high
frequency noise related to MOSFET turn-on and turn-
off, the output voltage ripple includes the capacitance
voltage drop DVCOUT and ESR voltage drop DVESR caused
by the AC peak-to-peak inductor’s current. These two
voltages can be represented by:
Where R1 is the resistor connected from VOUT to FB and
R2 is the resistor connected from FB to the GND.
Output Inductor Selection
The duty cycle (D) of a buck converter is the function of the
input voltage and output voltage. Once an output voltage
is fixed, it can be written as:
VOUT
D =
V
IN
The inductor value (L) determines the inductor ripple
current, IRIPPLE, and affects the load transient reponse.
Higher inductor value reduces the inductor’s ripple cur-
rent and induces lower output ripple voltage. The ripple
current and ripple voltage can be approximated by:
VIN - VOUT VOUT
IRIPPLE
DVCOUT =
8COUTFSW
DVESR = IRIPPLE ´ RESR
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
capacitors have to be paralleled to achieve the desired
ESR value. If the output of the converter has to support
another load with high pulsating current, more capaci-
tors are needed in order to reduce the equivalent ESR
and suppress the voltage ripple to a tolerable level. A
small decoupling capacitor (1mF) in parallel for bypass-
ing the noise is also recommended, and the voltage rat-
ing of the output capacitors are also must be considered.
To support a load transient that is faster than the switch-
ing frequency, more capacitors are needed for reducing
the voltage excursion during load step change. Another
aspect of the capacitor selection is that the total AC cur-
rent going through the capacitors has to be less than the
rated RMS current specified on the capacitors in order to
prevent the capacitor from over-heating.
IRIPPLE =
´
FSW ´ L
VIN
Where FSW is the switching frequency of the regulator.
Although the inductor value and frequency are increased
and the ripple current and voltage are reduced, a tradeoff
exists between the inductor’s ripple current and the regu-
lator load transient response time.
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple current.
Increasing the switching frequency (FSW) also reduces
the ripple current and voltage, but it will increase the
switching loss of the MOSFETs and the power dissipa-
tion of the converter. The maximum ripple current occurs
at the maximum input voltage. A good starting point is to
choose the ripple current to be approximately 30% of the
maximum output current. Once the inductance value has
been chosen, selecting an inductor which is capable of
carrying the required peak current without going into
Input Capacitor Selection
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select-
ing the capacitor voltage rating to be at least 1.3 times
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jan., 2013
APW8724
Application Information (Cont.)
Input Capacitor Selection (Cont.)
Phigh-side = IOUT 2(1+ TC)(RDS(ON))D + (0.5)( IOUT)(V )( tSW)FSW
IN
Plow-side = IOUT 2(1+ TC)(RDS(ON))(1-D)
higher than the maximum input voltage. The maximum
RMS current rating requirement is approximately IOUT/2,
where IOUT is the load current. During power-up, the input
capacitors have to handle great amount of surge current.
For low-duty notebook appliactions, ceramic capacitor is
recommended. The capacitors must be connected be-
tween the drain of high-side MOSFET and the source of
low-side MOSFET with very low-impeadance PCB layout.
Where
I
is the load current
OUT
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
tSW is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction losses while
the high-side MOSFET includes an additional transition loss.
The switching interval, tSW, is the function of the reverse
transfer capacitance CRSS. The (1+TC) term is a factor in
the temperature dependency of the RDS(ON) and can be
extracted from the “RDS(ON) vs. Temperature” curve of the
power MOSFET.
MOSFETSelection
The application for a notebook battery with a maximum
voltage of 24V, at least a minimum 30V MOSFETs should
be used. The design has to trade off the gate charge with
the RDS(ON) of the MOSFET:
For the low-side MOSFET, before it is turned on, the body
diode has been conducting. The low-side MOSFET driver
will not charge the miller capacitor of this MOSFET.
In the turning off process of the low-side MOSFET, the
load current will shift to the body diode first. The high dv/
dt of the phase node voltage will charge the miller capaci-
tor through the low-side MOSFET driver sinking current
path. This results in much less switching loss of the low-
side MOSFETs. The duty cycle is often very small in high
battery voltage applications, and the low-side MOSFET
will conduct most of the switching cycle; therefore, when
using smaller RDS(ON) of the low-side MOSFET, the con-
verter can reduce power loss. The gate charge for this
MOSFET is usually the secondary consideration. The
high-side MOSFET does not have this zero voltage switch-
ing condition; in addition, it conducts for less time com-
pared to the low-side MOSFET, so the switching loss
tends to be dominant. Priority should be given to the
MOSFETs with less gate charge, so that both the gate
driver loss and switching loss will be minimized.
Layout Consideration
In any high switching frequency converter, a correct layout
is important to ensure proper operation of the regulator.
With power devices switching at higher frequency, the
resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off condition, the
MOSFET is carrying the full load current. During turn-off,
current stops flowing in the MOSFET and is freewheeling
by the low side MOSFET and parasitic diode. Any parasitic
inductance of the circuit generates a large voltage spike
during the switching interval. In general, using short and
wide printed circuit traces should minimize interconnect-
ing impedances and the magnitude of voltage spike.
Besides, signal and power grounds are to be kept sepa-
rating and finally combined using ground plane construc-
tion or single point grounding. The best tie-point between
the signal ground and the power ground is at the nega-
tive side of the output capacitor on each channel, where
there is less noise. Noisy traces beneath the IC are not
recommended. Below is a checklist for your layout:
· Keep the switching nodes (UGATE, LGATE, BOOT,
and PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals.
The selection of the N-channel power MOSFETs are
determined by the RDS(ON), reversing transfer capaci-
tance (CRSS) and maximum output current requirement.
The losses in the MOSFETs have two components:
conduction loss and transition loss. For the high-side
and low-side MOSFETs, the losses are approximately
given by the following equations:
Therefore, keep traces to these nodes as short as
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jan., 2013
APW8724
Application Information (Cont.)
Recommended Minimum Footprint
Layout Consideration (Cont.)
possible and there should be no other weak signal
traces in parallel with theses traces on any layer.
· The signals going through theses traces have both
high dv/dt and high di/dt with high peak charging and
discharging current. The traces from the gate drivers
to the MOSFETs (UGATE and LGATE) should be short
and wide.
ThermalVia diameter
12mil X 5
Ground plane for
ThermalPAD
0.275mm
0.75mm
0.30mm
· Place the source of the high-side MOSFET and the
drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane be-
tween the two pads reduces the voltage bounce of
the node. In addition, the large layout plane between
the drain of the MOSFETs (VIN and PHASE nodes) can
get better heat sinking.
0.50mm
1.75mm
TDFN3X3 -10L and Pattern R ecommendation
· The PGND is the current sensing circuit reference
ground and also the power ground of the LGATE low-
side MOSFET. On the other hand, the PGND trace
should be a separate trace and independently go to
the source of the low-side MOSFET. Besides, the cur-
rent sense resistor should be close to OCSET pin to
avoid parasitic capacitor effect and noise coupling.
· Decoupling capacitors, the resistor-divider, and boot
capacitor should be close to their pins. (For example,
place the decoupling ceramic capacitor close to the
drain of the high-side MOSFET as close as possible.)
· The input bulk capacitors should be close to the drain
of the high-side MOSFET, and the output bulk capaci-
tors should be close to the loads. The input capaci-
tor’s ground should be close to the grounds of the
output capacitors and low-side MOSFET.
· Locate the resistor-divider close to the FB pin to mini-
mize the high impedance trace. In addition, FB pin
traces can’t be close to the switching signal traces
(UGATE, LGATE, BOOT, and PHASE).
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jan., 2013
APW8724
Package Information
TDFN3x3-10
D
A
Pin 1
A1
A3
D2
NX
aaa
C
Pin 1 Corner
e
TDFN3x3-10
S
Y
M
B
O
L
MILLIMETERS
INCHES
MIN.
0.70
0.00
MAX.
MIN.
MAX.
0.031
0.002
A
0.80
0.05
0.028
0.000
A1
A3
b
0.20 REF
0.008 REF
0.007
0.114
0.087
0.114
0.055
0.012
0.122
0.106
0.122
0.069
0.18
2.90
2.20
2.90
1.40
0.30
3.10
2.70
3.10
1.75
D
D2
E
E2
e
0.50 BSC
0.08
0.016 BSC
0.012
0.008
0.020
L
0.30
0.20
0.50
K
aaa
0.003
Note : 1. Followed from JEDEC MO-229 VEED-5.
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jan., 2013
APW8724
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
TDFN3x3-10
A
H
T1
12.4+2.00 13.0+0.50
-0.00 -0.20
P2 D0
C
d
D
W
E1
F
5.5±0.05
K0
330.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN. 12.0±0.30 1.75±0.10
P0
P1
T
A0
B0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10
8.0±0.10
2.0±0.05
1.5 MIN.
3.30±0.20 3.30±0.20 1.30±0.20
(mm)
Devices Per Unit
Package Type
TDFN3x3-10
Unit
Quantity
3000
Tape & Reel
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jan., 2013
APW8724
Taping Direction Information
TDFN3x3-10
USER DIRECTION OF FEED
Classification Profile
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jan., 2013
APW8724
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3 °C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
³ 2.5 mm
Volume mm3
<350
235 °C
220 °C
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
PCT
TCT
HBM
MM
VMM≧200V
10ms, 1tr≧100mA
Latch-Up
Copyright ã ANPEC Electronics Corp.
21
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Rev. A.1 - Jan., 2013
APW8724
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
Rev. A.1 - Jan., 2013
22
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