AOZ1025D [AOS]
EZBuck⢠8A Synchronous Buck Regulator; EZBuckâ ?? ¢ 8A同步降压稳压器
| 型号： | AOZ1025D |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | EZBuck⢠8A Synchronous Buck Regulator |
| 文件： | 总15页 (文件大小：650K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOZ1025D
EZBuck™ 8A Synchronous Buck Regulator
General Description
Features
The AOZ1025D is a high efficiency, simple to use, buck
regulator, capable of up to 8A with an external low side
MOSFET. The AOZ1025D works from a 4.75V to 16V
input voltage range,
4.75 to 16V operating input voltage range
Synchronous rectification: Integrated high side
MOSFET
High efficiency: up to 95%
Internal soft start
The AOZ1025D comes in a 5 x 4 DFN-16 package and is
rated over a -40°C to +85°C ambient temperature range.
Output voltage adjustable to 0.8V
Up to 8A continuous output current
Fixed 500kHz PWM operation
Cycle-by-cycle current limit
Short-circuit protection
Thermal shutdown
Small size 5 x 4 DFN-16 package
Applications
Point of load DC/DC conversion
Desktops/graphics cards
PCIe graphics cards
Set top boxes
Blu-Ray and HD-DVD–recorders
LCD TVs
Typical Application
5V DC
VIN = 12V
C1, C2
22µF
Ceramic
VIN
GOOD
L1 2.2µH
EN
VOUT
LX
AOZ1025D
R1
R2
COMP
C3, C4, C5
NGATE
22µF
R
C
Ceramic
FB
C
C
AGND
PGND
Figure 1. 1.2V/8A Synchronous Buck Regulator
Rev. 1.4 June 2012
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Page 1 of 15
AOZ1025D
Ordering Information
Part Number
Ambient Temperature Range
-40°C to +85°C
Package
Environmental
Green Product
AOZ1025DIL
5 x 4 DFN-16
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LX
VIN
LX
LX
LX
VIN
LX
VIN
NGATE
PGOOD
PGND
EN
VIN
AGND
FB
AGND
NC
COMP
5 x 4 DFN-16
(Top Thru View)
Pin Description
Pin Number Pin Name
Pin Function
PWM output connection to inductor. Thermal connection for output stage.
1
2, 3, 4, 5
6
LX
VIN
Supply voltage input. When VIN rises above the UVLO threshold the device starts up.
AGND
Reference connection for controller section. Also used as thermal connection for controller
section. Electrically needs to be connected to PGND
7
FB
The FB pin is used to determine the output voltage via a resistor divider between the output and
GND.
8
NC
COMP
EN
Not connected
9
External loop compensation pin.
10
11
The enable pin is active high. Do not leave it open.
Power ground. Electrically needs to be connected to AGND.
Power Good. Open drain. Use resistor to pull up to 5V supply.
Low side MOSFET driver; Connect it to the gate of external low side MOSFET.
PWM output connection to inductor. Thermal connection for output stage.
PGND
PGOOD
NGATE
LX
12
13
14, 15, 16
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Page 2 of 15
AOZ1025D
Block Diagram
VIN
Internal
+5V
UVLO
& POR
5V LDO
Regulator
OTP
EN
+
ISen
–
Reference
& Bias
Softstart
Q1
ILimit
+
–
+
Level
Shifter
+
FET
Driver
+
–
PWM
Control
Logic
0.8V
PWM
Comp
EAmp
FB
LX
LDRV
500kHz/68kHz
Oscillator
COMP
Frequency
Foldback
Comparator
+
–
0.2V
PGOOD
+
–
0.72V
Over Voltage
Comparator
–
+
0.96V
0.86V
AGND
PGND
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the
device.
Recommend Operating Ratings
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
Parameter
Rating
Parameter
Supply Voltage (VIN)
Rating
Supply Voltage (VIN)
LX to AGND
18V
4.75V to 16V
0.8V to VIN
-0.7V to VIN+0.3V
-0.3V to VIN+0.3V
-0.3V to 6V
Output Voltage Range
EN to AGND
Ambient Temperature (TA)
Package Thermal Resistance
-40°C to +85°C
50°C/W
FB to AGND
)
(2
5 x 4 DFN-16 (JA
)
COMP to AGND
PGND to AGND
Junction Temperature (TJ)
Storage Temperature (TS)
ESD Rating(1)
-0.3V to 6V
Package Thermal Resistance
5°C/W
-0.3V to +0.3V
+150°C
)
(2
5 x 4 DFN-16 (JC
)
Note:
2. The value of
-65°C to +150°C
2kV
JA is measured with the device mounted on 1-in2 FR-4
board with 2oz. Copper, in a still air environment with TA = 25°C. The
value in any given application depends on the user's specific board
design.
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5k
Ω in series with 100pF.
Rev. 1.4 June 2012
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Page 3 of 15
AOZ1025D
Electrical Characteristics
)
TA = 25°C, VIN = VEN = 12V, VOUT = 1.2V unless otherwise specified(3
Symbol
Parameter
Supply Voltage
Conditions
Min.
4.75
Typ. Max. Units
VIN
16
V
V
VUVLO
Input Under-Voltage Lockout Threshold
VIN Rising
VIN Falling
4.1
3.7
IIN
Supply Current (Quiescent)
Shutdown Supply Current
Feedback Voltage
IOUT = 0, VFB = 1.2V, VEN > 1.2V
VEN = 0V
1.2
3
mA
µA
V
IOFF
VFB
30
0.788
0.8
0.5
0.2
0.812
Load Regulation
%
Line Regulation
%
IFB
Feedback Voltage Input Current
EN Input Threshold
200
nA
VEN
Off Threshold
On Threshold
0.6
V
2
VHYS
EN Input Hysteresis
100
500
mV
MODULATOR
fO
Frequency
350
100
600
6
kHz
%
DMAX
DMIN
Maximum Duty Cycle
Minimum Duty Cycle
%
Error Amplifier Voltage Gain
Error Amplifier Transconductance
500
200
V/ V
µA/V
PROTECTION
ILIM
Current Limit
Over-Temperature Shutdown Limit
10
A
TJ Rising
TJ Falling
150
100
°C
VPR
tSS
Output Over-voltage Protection Threshold Off Threshold
On Threshold
960
860
mV
ms
Soft Start Interval
3
4
6.5
POWER GOOD
VOLPG PG LOW Voltage
IOL = 1mA
0.5
1
V
µA
%
PG Leakage
VPGL
PG Threshold Voltage
PG Threshold Voltage Hysteresis
PG Delay Time
-12
-10
3
-8
%
128
µs
OUTPUT STAGE
High-Side Switch On-Resistance
LOW SIDE DRIVER
Pull-up Resistance
Pull-up Resistance
VIN = 12V
43
57
mΩ
20
7
Ω
Ω
Note:
3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Rev. 1.4 June 2012
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Page 4 of 15
AOZ1025D
Maximum Output Current
Maximum output current of buck converters such as AOZ1025D is related with driving capability and thermal condition.
AOZ1025D’s driving voltage varies with the input voltage. When input voltage is higher than 6.5V, the driver inside the
AOZ1025D can drive both high side and low side MOSFETs to deliver 8A output current; but when the input voltage is
5V, the recommended maximum output current is de-rated to 6A.
The output voltage within a fixed input voltage directed determines the turn-on ratio of integrated PMOS, and thus the
thermal condition of AOZ1025D during the operation. The following diagrams show the safe operation region of
AOZ1025 operating at V = 5V, and V = 12V respectively.
IN
IN
V
= 12V Safe Operation Region
V
= 5V Safe Operation Region
IN
IN
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0.8
1.3
1.8
2.3
2.8
3.3
3.8
0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
Output Voltage (V)
Output Voltage (V)
Input Voltage Vs. Maximum Output Current
AOZ1025D’s driving voltage varies with the input voltage.þWhen input voltage is higher than 6.5V, the driver inside the
AOZ1025D can drive both high side and low side MOSFETs to deliver 8A output current; but when the input voltage is
5V, the recommended maximum output current is de-rated to 6A.þThe following diagram shows relations of the input
voltage and the maximum output current of AOZ1025D.
Input Voltage vs. Maximum Output Current
9
8
7
6
5
4
3
2
5
6
7
8
9
10
11
12
13
14
15
16
Voltage (V)
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Page 5 of 15
AOZ1025D
Efficiency
The efficiency was measured based on Figure 1 with the low-side external MOSFET (AO4722).
Efficiency
Efficiency
(V = 5V)
(V = 12V)
IN
IN
100
100
95
95
V
= 5.0V
O
V
= 3.3V
O
90
90
V
= 3.3V
O
85
85
V
= 1.8V
O
V
= 1.8V
O
80
80
V
= 1.1V
O
75
75
V
= 1.1V
O
70
70
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
Current (A)
Current (A)
Rev. 1.4 June 2012
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Page 6 of 15
AOZ1025D
The AOZ1025D uses an external freewheeling
Detailed Description
NMOSFET to realize synchronous rectification. It greatly
improves the converter efficiency and reduces power
loss in the low-side switch.
The AOZ1025D is a current-mode step down regulator
with integrated high-side PMOS switch. It operates from
a 4.75V to 16V input voltage range and supplies up to 8A
of load current. The duty cycle can be adjusted from 6%
to 100% allowing a wide range of output voltage.
Features include enable control, Power-On Reset, input
under voltage lockout, output over voltage protection,
fixed internal soft-start and thermal shut down.
The AOZ1025D uses a P-Channel MOSFET as the
high-side switch. It saves the bootstrap capacitor
normally seen in a circuit which is using an NMOS
switch.
Switching Frequency
Enable and Soft Start
The AOZ1025D switching frequency is fixed and set by
an internal oscillator. The practical switching frequency
could range from 350 kHz to 600 kHz due to device
variation.
The AOZ1025D has internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.0V and voltage
on EN pin is HIGH. In soft start process, the output
voltage is ramped to regulation voltage in typically 4ms.
The 4ms soft start time is set internally.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin by using a resistor divider network. In the
application circuit shown in Figure 1. The resistor divider
The voltage on EN pin must rise above 1.8V to enable
the AOZ1025D. When voltage on EN pin falls below
0.6V, the AOZ1025D is disabled.
network includes R and R . Usually, a design is started
1
2
by picking a fixed R value and calculating the required
2
R with equation:
1
Steady-State Operation
R
1
------
V
= 0.8 1 +
Under steady-state conditions, the converter operates
in fixed frequency and Continuous-Conduction Mode
(CCM).
O
R
2
Some standard value of R1, R2 and most used output
voltage values are listed in Table 1.
The AOZ1025D integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error
voltage, which shows on the COMP pin, is compared
against the current signal, which is sum of inductor
current signal and ramp compensation signal, at PWM
comparator input. If the current signal is less than the
error voltage, the internal high-side switch is on. The
inductor current flows from the input through the inductor
to the output. When the current signal exceeds the error
voltage, the high-side switch is off. The inductor current is
freewheeling through the external low-side N-MOSFET
switch to output. The internal adaptive FET driver
guarantees no turn on overlap of both high-side and
low-side switch.
Table 1.
V (V)
R (k
Ω
)
R (kΩ)
2
O
1
0.8
1.2
1.5
1.8
2.5
3.3
5.0
1.0
4.99
10
Open
10
11.5
10.2
10
12.7
21.5
31.6
52.3
10
10
The combination of R and R should be large enough to
1
2
avoid drawing excessive current from the output, which
will cause power loss.
Rev. 1.4 June 2012
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Page 7 of 15
AOZ1025D
Protection Features
Application Information
The AOZ1025D has multiple protection features to
prevent system circuit damage under abnormal
conditions.
The basic AOZ1025D application circuit is show in
Figure 1. Component selection is explained below.
Input Capacitor
Over Current Protection (OCP)
The input capacitor must be connected to the V pin and
IN
The sensed inductor current signal is also used for over
current protection. Since the AOZ1025D employs peak
current mode control, the COMP pin voltage is propor-
tional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4V and 2.5V internally.
The peak inductor current is automatically limited cycle
by cycle.
PGND pin of AOZ1025D to maintain steady input voltage
and filter out the pulsing input current. The voltage rating
of input capacitor must be greater than maximum input
voltage plus ripple voltage.
The input ripple voltage can be approximated by
equation below:
I
V
V
O
O
O
When the output is shorted to ground under fault
conditions, the inductor current decays very slow during
-----------------
--------
--------
V
=
1 –
IN
f C
V
V
IN
IN
IN
a switching cycle because of V = 0V. To prevent
O
catastrophic failure, a secondary current limit is designed
inside the AOZ1025D. The measured inductor current is
compared against a preset voltage which represents the
current limit. When the output current is more than
current limit, the high side switch will be turned off and
EN pin will be pulled down. The converter will initiate a
soft start once the over-current condition disappears.
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
V
V
O
O
--------
IN
--------
I
= I
1 –
CIN_RMS
O
V
V
IN
Output Over Voltage Protection (OVP)
The AOZ1025D monitors the feedback voltage: when
the feedback voltage is higher than 960mV, it immediate
turns-off the PMOS to protect the output voltage
overshoot at fault condition. When feedback voltage is
lower than 840mV, the PMOS is allowed to turn on in the
next cycle.
if we let m equal the conversion ratio:
V
O
--------
= m
V
IN
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
Under-voltage Lock-out (UVLO)
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4V, the converter starts
operation. When input voltage falls below 3.7V, the
converter will be shut down.
shown in Figure 2. It can be seen that when V is half of
O
V , C is under the worst current stress. The worst
IN
IN
current stress on C is 0.5 x I .
IN
O
0.5
0.4
0.3
0.2
0.1
0
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side PMOS if the junction temperature exceeds
150°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100°C.
ICIN_RMS(m)
IO
Power Good
The output of Power-Good is an open drain N-channel
MOSFET, which supplies an active high power good
stage. A pull-up resistor should connect this pin to a
DC power trail with maximum voltage no higher than 6V.
The AOZ1025D monitors the FB voltage: when FB pin
voltage is lower than 90% of the normal voltage,
N-channel MOSFET turns on and the Power-Good pin
is pulled low, which indicates the power is abnormal.
0
0.5
m
1
Figure 2. ICIN vs. Voltage Conversion Ratio
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Page 8 of 15
AOZ1025D
For reliable operation and best performance, the input
capacitors must have current rating higher than I
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
CIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high current rating. Depending on the application
circuits, other low ESR tantalum capacitor may also be
used. When selecting ceramic capacitors, X5R or X7R
type dielectric ceramic capacitors should be used for
their better temperature and voltage characteristics.
Note that the ripple current rating from capacitor
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck con-
verter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
manufactures are based on certain amount of life time.
Further de-rating may be necessary in practical design.
1
-------------------------
V = I ESR
+
O
L
CO
8 f C
Inductor
O
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
where,
CO is output capacitor value, and
ESRCO is the equivalent series resistance of the output
capacitor.
V
V
O
O
----------
--------
I
=
1 –
L
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
f L
V
IN
The peak inductor current is:
I
L
--------
I
= I +
1
Lpeak
O
-------------------------
V = I
2
O
L
8 f C
O
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20%
to 40% of output current.
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
V = I ESR
CO
O
L
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum are recommended
to be used as output capacitors.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor need to be checked for
thermal and efficiency requirements.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It
can be calculated by:
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
I
L
----------
I
=
CO_RMS
12
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
Rev. 1.4 June 2012
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Page 9 of 15
AOZ1025D
Loop Compensation
To design the compensation circuit, a target crossover
frequency f for close loop must be selected. The system
The AOZ1025D employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
C
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter bandwidth.
Generally a higher bandwidth means faster response to
load transient. However, the bandwidth should not be too
high because of system stability concern. When
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
designing the compensation loop, converter stability
under all line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
AOZ1025D operates at a fixed 500kHz switching
frequency. It is recommended to choose a crossover
frequency equal or less than 40kHz.
1
----------------------------------
f
=
P1
2
R
C
O
L
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
f
= 40kHz
C
1
The strategy for choosing R and C is to set the cross
------------------------------------------------
f
=
C
C
Z1
2 C ESR
over frequency with R and set the compensator zero
O
CO
C
with C . Using selected crossover frequency, f , to calcu-
C
C
where;
late R :
C
CO is the output filter capacitor,
V
2 C
O
O
RL is load resistor value, and
---------- -----------------------------
R
= f
C
C
V
G
G
EA CS
ESRCO is the equivalent series resistance of output capacitor.
FB
where;
The compensation design is actually to shape the
converter control loop transfer function to get desired
gain and phase. Several different types of compensation
network can be used for the AOZ1025D. For most cases,
a series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
fC is the desired crossover frequency. For best performance,
fC is set to be about 1/10 of the switching frequency;
VFB is 0.8V,
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V, and
GCS is the current sense circuit transconductance, which is 10.8
A/V
In the AOZ1025D, FB pin and COMP pin are the
inverting input and the output of internal error amplifier.
A series R and C compensation network connected to
COMP provides one pole and one zero. The pole is:
The compensation capacitor C and resistor R together
make a zero. This zero is put somewhere close to the
dominate pole f but lower than 1/5 of selected
C
C
p1
crossover frequency. C can is selected by:
G
C
EA
------------------------------------------
f
=
P2
2 C G
1.5
C
VEA
-----------------------------------
=
C
C
2 R f
C
P1
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
The previous equation can also be simplified to:
C R
O
L
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is the compensation capacitor.
---------------------
C
=
C
R
C
The zero given by the external compensation network,
capacitor C and resistor R , is located at:
C
C
1
-----------------------------------
=
f
Z2
2 C R
C
C
Rev. 1.4 June 2012
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Page 10 of 15
AOZ1025D
Several layout tips are listed below for the best electric
and thermal performance:
Thermal Management and Layout
Consideration
In the AOZ1025 buck regulator circuit, the major power
dissipating components are the AOZ1025 output
inductor, and low-side NMOSFET. The total power
dissipation of converter circuit can be measured by
input power minus output power:
1. Do not use thermal relief connection to the V and
IN
the PGND pin. Pour a maximized copper area to
the PGND pin and the VIN pin to help thermal
dissipation.
2. Input capacitor should be connected to the V pin
IN
P
= V I – V I
IN IN O O
and the PGND pin as close as possible.
total_loss
3. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and connect them
only at one point to avoid the PGND pin noise
coupling to the AGND pin.
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor:
2
P
= I R
1.1
inductor
inductor_loss
O
4. Make the current trace from LX pins to L to Co to the
PGND as short as possible.
The power dissipation of low-side NMOSFET can be
approximately calculated by output current, Rdson, and
5. Pour copper plane on all unused board area and
duty cycle (V / V ).
connect it to stable DC nodes, like V , PGND or
O
IN
IN
SGND.
V
O
2
6. Keep sensitive signal trace away from switching
node, LX. The copper pour area connected to the
LX pin should be as wide as possible to avoid the
switching noise on the LX pin coupling to other part
of circuit.
--------
P
= I R
1 –
inductor_loss
O
inductor
V
IN
The actual junction temperature can be calculated with
power dissipation in the AOZ1025 and thermal
impedance from junction to ambient.
T
= P
– P
– P
+ T
nmos_loss JA amb
junction
total_loss
inductor_loss
The thermal performance of the AOZ1025D is strongly
affected by the PCB layout. Extra care should be taken
by users during design to ensure that the IC will operate
under the recommended environmental conditions.
Figure 3. AOZ1025D (DFN 5x4) PCB Layout
Rev. 1.4 June 2012
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Page 11 of 15
AOZ1025D
Package Dimensions, DFN-16 5x4
D
A
PIN#1 IDA
L
e
D/2
B
1
E/2
E
E2
2
INDEX AREA
(D/2xE/2)
D2
D3
aaa C
5
TOP VIEW
BOTTOM VIEW
ccc C
A3
C
Seating
Plane
A
4
3
ddd C
A1
b
C A B
bbb
SIDE VIEW
Dimensions in millimeters
Dimensions in inches
Symbols Min. Nom. Max.
Symbols Min. Nom. Max.
A
A1
A3
b
0.80
0.00
0.90
0.02
1.00
0.05
A
A1
A3
b
0.031 0.035 0.039
0.000 0.001 0.002
0.008 REF
RECOMMENDED LAND PATTERN
0.20 REF
0.25
0.25
0.17
0.35
0.007 0.010 0.014
0.197 BSC
0.3
0.5
D
5.00 BSC
1.90
D
0.6
D2
D3
E
1.75
1.85
2.00
2.10
D2
D3
E
0.069 0.075 0.079
0.073 0.079 0.083
0.157 BSC
2.00
1.75
0.15
0.25
2.3
4.00 BSC
2.30
3.5
E2
e
2.15
0.40
2.40
0.60
E2
e
0.085 0.091 0.094
0.020 BSC
0.50 BSC
0.50
L
L
0.016 0.020 0.024
0.012 REF
R
0.30 REF
0.15
R
aaa
bbb
ccc
ddd
–
–
–
–
–
–
–
–
aaa
bbb
ccc
ddd
–
–
–
–
0.006
0.004
0.004
0.003
–
–
–
–
1.9
2.0
0.10
0.10
UNIT: mm
0.08
Notes:
1. All dimensions are in millimeters.
2. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002.
3. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the
optional radius on the other end of the terminal, the dimension b should not be measured in that radius area.
4. Coplanarity applies to the terminals and all other bottom surface metallization.
5. Drawing shown are for illustration only.
Rev. 1.4 June 2012
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Page 12 of 15
AOZ1025D
Tape Dimensions, DFN-16 5x4
Tape
0.20
T
D1
E1
E2
D0
E
B0
Feeding
Direction
K0
P0
A0
Unit: mm
Package
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
1.50
Min.
Typ.
1.50
DFN 5x4
(12 mm)
5.30
0.10
4.30
0.10
1.20
0.10
12.00
0.30
1.75
0.10
5.50
0.10
8.00
0.10
4.00
0.20
2.00
0.10
0.30
0.05
+0.10 / –0
Leader/Trailer and Orientation
Trailer Tape
(300mm Min.)
Components Tape
Orientation in Pocket
Leader Tape
(500mm Min.)
Rev. 1.4 June 2012
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Page 13 of 15
AOZ1025D
Reel Dimensions, DFN-16 5x4
II
I
6.0 1
M
I
Zoom In
R1
P
B
W1
III
Zoom In
3-1.8
0.05
II
Zoom In
A
N=ø100 ꢀ
3-ø1/4"
A A
1.8
6.0
6.45 0.05
6.ꢀ
0.00
-0.05
8.00
R1
ꢀ.ꢀ0
ꢀ.00
8.9 0.1
14 REF
5.0
C
1.8
1ꢀ REF
11.90
46.0 0.1
44.5 0.1
41.5 REF
43.00
44.5 0.1
3.3
4.0
6.50
6.10
40°
10.0
VIEW: C
ꢀ.5
1.80
0.80
3.00
A
8.0 0.1
+0.05
0.00
ꢀ.00
6.50
8.00
10.71
6°
Rev. 1.4 June 2012
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Page 14 of 15
AOZ1025D
Package Marking
Z1025DI
FAYWLT
Part Number Code
Underline Denotes Green Product
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
This data sheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Rev. 1.4 June 2012
www.aosmd.com
Page 15 of 15
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