AOZ1081AI [AOS]
EZBuck⢠1.8A High Efficiency; EZBuckâ ?? ¢ 1.8A高效率
| 型号： | AOZ1081AI |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | EZBuck⢠1.8A High Efficiency |
| 文件： | 总16页 (文件大小：1010K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOZ1081
EZBuck™ 1.8A High Efficiency
Constant Current Regulator for LEDs
General Description
Features
The AOZ1081 is a high efficiency, simple to use, 1.8A
buck regulator for White LED. The AOZ1081 works from
a 4.5V to 16V input voltage range, and provides up to
1.8A of continuous output current with an output voltage
adjustable down to 0.25V.
● 4.5V to 16V operating input voltage range
● 100 mΩ internal PFET switch for high efficiency:
up to 95%
● Internal Schottky Diode
● Internal soft start
The AOZ1081 comes in an SO-8 package and is rated
over a -40°C to +85°C ambient temperature range.
● 0.25V internal reference with ±5% accuracy over
temperature
● 1.8A continuous output current
● Fixed 1MHz PWM operation
● Cycle-by-cycle current limit
● Short-circuit protection
● Under voltage lockout
● Output over voltage protection
● Thermal shutdown
● Small size SO-8 package
Applications
● Buck regulator for white LEDs
● Landscape lighting
● Flashlights
● Battery powered backlight applications
Typical Application
VIN
C1
22µF
VIN
4.7µH
EN
VOUT
LX
FB
AOZ1081
HB
LED
COMP
C3
R
1
22µF
C
R
2
FB
AGND
PGND
Figure 1.
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Page 1 of 16
AOZ1081
VIN
C1
22µF
VIN
4.7µH
EN
VOUT
LX
FB
AOZ1081
COMP
R
1
C3
C
2
AGND
PGND
22µF
R
R2
R3
R4
R5
R6
R7
R8
FB
Figure 2.
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1081AI
-40°C to +85°C
SO-8
RoHS
All AOS products are offered in packages with Pb-free plating and compliant to RoHS standards.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
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Page 2 of 16
AOZ1081
Pin Configuration
1
2
3
4
8
7
6
5
PGND
VIN
LX
LX
AGND
FB
EN
COMP
SO-8
(Top View)
Pin Description
Pin
Number
Pin Name
Pin Function
1
2
3
PGND
VIN
Power ground. Electrically needs to be connected to AGND.
Supply voltage input. When VIN rises above the UVLO threshold the device starts up.
AGND
Reference connection for controller section. Also used as thermal connection for controller
section. Electrically needs to be connected to PGND.
4
FB
LED Current Feedback Input. The FB voltage is regulated at 250mV in normal operation. The FB
sense resistor sets the nominal LED current
5
6
COMP
EN
External loop compensation pin.
The enable pin is active high. Connect EN pin to VIN if not used. Do not leave the EN pin floating.
PWM output connection to inductor. Thermal connection for output stage.
7,8
LX
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AOZ1081
Block Diagram
VIN
Internal
+5V
UVLO
& POR
5V LDO
Regulator
OTP
EN
+
ISen
–
Reference
& Bias
Softstart
Q1
ILimit
+
–
+
Level
Shifter
+
FET
Driver
+
–
PWM
Control
Logic
0.25V
PWM
Comp
EAmp
FB
LX
COMP
1000kHz/76kHz
Oscillator
Frequency
Foldback
Comparator
+
–
0.15V
0.33V
Over Voltage
Protection
Comparator
+
–
AGND
PGND
Absolute Maximum Ratings
Recommend Operating Ratings
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
Exceeding the Absolute Maximum Ratings may damage the
device.
Parameter
Rating
Parameter
Supply Voltage (VIN)
Rating
Supply Voltage (VIN)
LX to AGND
18V
4.5V to 16V
0.25V to VIN
-40°C to +85°C
87°C/W
-0.7V to VIN+0.3V
-0.3V to VIN+0.3V
-0.3V to 6V
Output Voltage Range
EN to AGND
Ambient Temperature (TA)
FB to AGND
Package Thermal Resistance SO-8
(2)
(ΘJA
)
COMP to AGND
PGND to AGND
Junction Temperature (TJ)
Storage Temperature (TS)
ESD Rating(1)
-0.3V to 6V
Note:
-0.3V to +0.3V
+150°C
2. The value of ΘJA is measured with the device mounted on 1-in2
FR-4 board with 2oz. Copper, in a still air environment with TA
=
25°C. The value in any given application depends on the user's spe-
cific board design.
-65°C to +150°C
2kV
Note:
1. Devices are inherently ESD sensitive, handling precautions are required.
Human body model rating: 1.5kΩ in series with 100pF.
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AOZ1081
Electrical Characteristics
)
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified(3
Symbol
Parameter
Supply Voltage
Conditions
Min.
4.5
Typ.
Max.
Units
VIN
16
V
VUVLO
Input Under-Voltage Lockout
Threshold
VIN Rising
IN Falling
4.0
3.7
V
V
IIN
Supply Current (Quiescent)
IOUT = 0, VCOMP = 0.1V, VEN
>1.2V
2
3
mA
IOFF
VFB
Shutdown Supply Current
Feedback Voltage
VEN = 0V
1
10
µA
V
0.2375
0.25
0.5
0.5
0.2625
Load Regulation
%
%
nA
Line Regulation
IFB
Feedback Voltage Input Current
EN Input Threshold
200
VEN
Off Threshold
On Threshold
0.6
V
2.0
VHYS
EN Input Hysteresis
100
mV
MODULATOR
fO
Frequency
850
1000
1150
kHz
%
DMAX
DMIN
Maximum Duty Cycle
100
Minimum Duty Cycle
12
%
Error Amplifier Voltage Gain
Error Amplifier Transconductance
500
200
V/ V
µA/V
PROTECTION
ILIM
Current Limit
2.5
4.0
A
VPR
Output Over-Voltage Protection
Threshold
Off Threshold
On Threshold
330
240
mV
TJ
Over-Temperature Shutdown Limit
Soft Start Interval
150
400
°C
µs
tSS
OUTPUT STAGE
High-Side Switch On-Resistance
VIN = 12V
VIN = 5V
97
166
130
200
mΩ
Note:
3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
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AOZ1081
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Digital Dimming vs. LED Current
200Hz PWM Signal on EN Pin
Normalized Switching Frequency vs. VIN
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
4
6
8
10
12
14
16
0
10
20
30
40
50
60
70
80
90 100
V
IN
(V)
PWM Duty Cycle (%)
Normalized Feedback Voltage Variation vs. VIN
Efficiency (VIN) vs. Load Current
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
100
95
90
85
80
75
V
V
= 7.2V
= 3.6V
OUT
OUT
4
6
8
10
(V)
12
14
16
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V
IN
Load Current (A)
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AOZ1081
Typical Performance Characteristics (Continued)
Typical Switching Waveform
PWM Dimming at 200Hz (90% Duty Cycle)
V
OUT
V
2V/Div
EN
5V/Div
V
OUT
V
2V/Div
LX
5V/Div
I
I
L
OUT
1A/Div
0.5A/Div
PWM Dimming at 200Hz (90% Duty Cycle)
PWM Dimming at 200Hz (90% Duty Cycle)
V
V
EN
5V/Div
EN
5V/Div
V
V
OUT
2V/Div
OUT
2V/Div
I
I
OUT
OUT
0.5A/Div
0.5A/Div
Start Up
V
EN
2.5V/Div
V
OUT
2V/Div
I
OUT
1A/Div
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AOZ1081
Detailed Description
The AOZ1081 is a current-mode step down regulator
with integrated high side PMOS switch and a low side
freewheeling Schottky diode. It operates from a 4.5V to
16V input voltage range and supplies up to 1.8A of load
current. The duty cycle can be adjusted from 12% to
100% allowing a wide range of output voltage. Features
include enable control, Power-On Reset, input under
voltage lockout, fixed internal soft-start and thermal shut
down.
the current signal, which is sum of inductor current signal
and ramp compensation signal, at PWM comparator
input. If the current signal is less than the error voltage,
the internal high-side switch is on. The inductor current
flows from the input through the inductor to the output.
When the current signal exceeds the error voltage, the
high-side switch is off. The inductor current is freewheel-
ing through the internal Schottky diode to output.
The AOZ1081 uses a P-Channel MOSFET as the high
side switch. It saves the bootstrap capacitor normally
seen in a circuit which is using an NMOS switch. It allows
100% turn-on of the upper switch to achieve linear
regulation mode of operation. The minimum voltage drop
The AOZ1081 is available in SO-8 package.
Enable and Soft Start
The AOZ1081 has internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.5V and voltage
on EN pin is HIGH. In soft start process, the output volt-
age is ramped to regulation voltage in typically 400µs.
The 400µs soft start time is set internally.
from V to V is the load current times DC resistance of
IN
O
MOSFET + DC resistance of buck inductor. It can be
calculated by equation below:
V
= V – I × (R
+ R
)
inductor
O_MAX
IN
O
DS(ON)
where,
The EN pin of the AOZ1081 is active HIGH. Connect the
VO_MAX is the maximum output voltage;
VIN is the input voltage from 4.5V to 16V;
IO is the output current from 0A to 1.8A;
EN pin to V if enable function is not used. Pull it to
IN
ground will disable the AOZ1081. Do not leave it open.
The voltage on EN pin must be above 2.0 V to enable the
AOZ1081. When voltage on EN pin falls below 0.6V, the
AOZ1081 is disabled. If an application circuit requires the
AOZ1081 to be disabled, an open drain or open collector
circuit should be used to interface to EN pin.
RDS(ON) is the on resistance of internal MOSFET, the value is
between 97mΩ and 200mΩ depending on input voltage and
junction temperature; and
Rinductor is the inductor DC resistance;
PWM Dimming
Switching Frequency
The AOZ1081 allows dimming up to 200Hz PWM signal
at the EN pin. By forcing a PWM digital waveform to the
EN pin, the system will go into a digital dimming state.
The output switch will be off when PWM waveform is
logic low and it will be on when PWM waveform is logic
high. The duty cycle range is 10% to 100%.
The AOZ1081 switching frequency is fixed and set by an
internal oscillator. The actual switching frequency could
range from 850kHz to 1.15MHz due to device variation.
Protection Features
The AOZ1081 has multiple protection features to prevent
system circuit damage under abnormal conditions.
Steady-State Operation
Under steady-state conditions, the converter operates
in fixed frequency and Continuous-Conduction Mode
(CCM).
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ1081 employs peak
current mode control, the COMP pin voltage is propor-
tional to the peak inductor current. The COMP pin volt-
age is limited to be between 0.4V and 2.5V internally.
The peak inductor current is automatically limited cycle
by cycle.
The AOZ1081 integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error volt-
age, which shows on the COMP pin, is compared against
The cycle by cycle current limit threshold is set between
2.5A and 4A. When the load current reaches the current
limit threshold, the cycle by cycle current limit circuit turns
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AOZ1081
off the high side switch immediately to terminate the
current duty cycle. The inductor current stop rising.
The cycle by cycle current limit protection directly limits
inductor peak current. The average inductor current is
also limited due to the limitation on peak inductor current.
When cycle by cycle current limit circuit is triggered, the
output voltage drops as the duty cycle decreasing.
Input Capacitor
The input capacitor (C1 in Figure 1) must be connected
to the V pin and PGND pin of the AOZ1081 to maintain
IN
steady input voltage and filter out the pulsing input
current. A small decoupling capacitor (Cd in Figure 1),
usually 1µF, should be connected to the V pin and
IN
AGND pin for stable operation of the AOZ1081. The
voltage rating of input capacitor must be greater than
maximum input voltage plus ripple voltage.
The AOZ1081 has internal short circuit protection to
protect itself from catastrophic failure under output short
circuit conditions. The FB pin voltage is proportional to
the output voltage. Whenever FB pin voltage is below
0.15V, the short circuit protection circuit is triggered.
As a result, the converter is shut down and hiccups at a
frequency equals to 1/8 of normal switching frequency.
The converter will start up via a soft start once the short
circuit condition disappears. In short circuit protection
mode, the inductor average current is greatly reduced
because of the low hiccup frequency.
The input ripple voltage can be approximated by equa-
tion below:
I
V
V
O
⎛
⎞
⎟
⎠
O
O
-----------------
--------
--------
ΔV
=
× 1 –
×
⎜
IN
V
f × C
V
⎝
IN
IN
IN
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a
buck circuit, the RMS value of input capacitor current can
be calculated by:
Output Over Voltage Protection (OVP)
The AOZ1081 monitors the feedback voltage: when the
feedback voltage is higher than 330mV, it immediate
turns-off the PMOS to protect the output voltage over-
shoot at fault condition. When feedback voltage is lower
than 240mV, the PMOS is allowed to turn on in the next
cycle.
V
⎛
⎜
⎝
⎞
⎟
⎠
V
O
O
--------
--------
I
= I ×
1 –
CIN_RMS
O
V
V
IN
IN
if let m equal the conversion ratio:
V
O
Power-On Reset (POR)
--------
= m
V
A power-on reset circuit monitors the input voltage. When
the input voltage exceeds 4V, the converter starts opera-
tion. When input voltage falls below 3.7V, the converter
will stop switching.
IN
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2. It can be seen that when V is half
O
Thermal Protection
of V , C is under the worst current stress. The worst
IN
IN
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side PMOS if the junction temperature exceeds
150°C.
current stress on C is 0.5 x I .
IN O
0.5
0.4
0.3
0.2
0.1
0
Application Information
The basic AOZ1081 application circuit is shown in
Figure 1 and 2. Component selection is explained below.
ICIN_RMS(m)
IO
Setting the Maximum LED Current
The AOZ1081 features a programmable LED current
0
0.5
m
1
using a resistor R at the end of the primary chain of
FB
LEDs.
Figure 2. ICIN vs. Voltage Conversion Ratio
250mV
-------------------
I
=
LEDMAX
R
FB
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AOZ1081
For reliable operation and best performance, the input
capacitors must have current rating higher than I
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high ripple current rating. Depending on the
The selected output capacitor must have a higher
rated voltage specification than the maximum desired
output voltage including ripple. De-rating needs to be
considered for long term reliability.
CIN_RMS
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
application circuits, other low ESR tantalum capacitor
or aluminum electrolytic capacitor may also be used.
When selecting ceramic capacitors, X5R or X7R type
dielectric ceramic capacitors are preferred for their better
temperature and voltage characteristics. Note that the
ripple current rating from capacitor manufactures is
based on certain amount of life time. Further de-rating
may be necessary for practical design requirement.
1
⎛
⎞
⎠
-------------------------
ΔV = ΔI × ESR
+
O
L
CO
⎝
8 × f × C
O
Inductor
where;
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
CO is output capacitor value, and
ESRCO is the Equivalent Series Resistor of output capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switch-
ing frequency dominates. Output ripple is mainly caused
by capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
V
V
O
⎛
⎞
⎟
⎠
O
----------
--------
ΔI
=
× 1 –
⎜
L
V
f × L
⎝
IN
The peak inductor current is:
1
-------------------------
ΔV = ΔI ×
ΔI
O
L
L
8 × f × C
O
--------
I
= I +
Lpeak
O
2
If the impedance of ESR at switching frequency
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20%
to 30% of output current.
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
ΔV = ΔI × ESR
CO
O
L
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum are recommended
to be used as output capacitors.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current.
It can be calculated by:
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor needs to be checked
for thermal and efficiency requirements.
ΔI
L
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
----------
I
=
CO_RMS
12
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small
and inductor ripple current is high, output capacitor could
be overstressed.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
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AOZ1081
Loop Compensation
To design the compensation circuit, a target crossover
frequency f for close loop must be selected. The system
C
The AOZ1081 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
crossover frequency is where control loop has unity gain.
The crossover frequency is also called the converter
bandwidth. Generally a higher bandwidth means faster
response to load transient. However, the bandwidth
should not be too high due to system stability concern.
When designing the compensation loop, converter
stability under all line and load condition must be
considered.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
Usually, it is recommended to set the bandwidth to be
less than 1/10 of switching frequency. The AOZ1081
operates at a fixed switching frequency range from
750kHz to 1.15MHz. It is recommended to choose a
crossover frequency less than 75kHz.
1
----------------------------------
f
=
p1
2π × C × R
O
L
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
f
= 75kHz
C
1
------------------------------------------------
f
=
Z1
The strategy for choosing R and C is to set the cross
2π × C × ESR
C
C
O
CO
over frequency with R and set the compensator zero
C
where;
with C . Using selected crossover frequency, f , to
C
C
calculate R :
C
CO is the output filter capacitor,
RL is load resistor value, and
V
2π × C
O
O
---------- -----------------------------
R
= f ×
×
ESRCO is the equivalent series resistance of output capacitor.
C
C
V
G
× G
EA CS
FB
The compensation design is actually to shape the
converter close loop transfer function to get desired gain
and phase. Several different types of compensation
network can be used for AOZ1081. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
where;
fC is desired crossover frequency,
VFB is 0.25V,
GEA is the error amplifier transconductance, which is 200x10-6
A/V, and
GCS is the current sense circuit transconductance, which is
5.64 A/V.
In the AOZ1081, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
amplifier. A series R and C compensation network con-
nected to COMP provides one pole and one zero. The
pole is:
The compensation capacitor C and resistor R together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected
C
C
crossover frequency. C can is selected byy:
C
G
EA
1.5
------------------------------------------
f
=
----------------------------------
=
C
p2
C
2π × C × G
2π × R × f
C
VEA
C
p1
where;
The equation above can also be simplified to:
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
C × R
O
L
---------------------
C
=
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is compensation capacitor.
C
R
C
The zero given by the external compensation network,
capacitor C (C5 in Figure 1) and resistor R (R1 in
C
C
Figure 1), is located at:
1
-----------------------------------
f
=
Z2
2π × C × R
C
C
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AOZ1081
Thermal Management and Layout Consideration
In the AOZ1081 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
Several layout tips are listed below for the best electric
and thermal performance. Figure 3 on the next page
illustrates a single layer PCB layout example as refer-
ence.
starts from the input capacitors, to the V pin, to the
IN
LX pins, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the PGND pin of the
AOZ1081, to the LX pins of the AZO1081. Current flows
in the second loop when the low side diode is on.
1. Do not use thermal relief connection to the V and
IN
the PGND pin. Pour a maximized copper area to
the PGND pin and the V pin to help thermal
IN
dissipation.
2. Input capacitor should be connected to the V pin
IN
and the PGND pin as close as possible.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is recommended to connect input capacitor, output
capacitor, and PGND pin of the AOZ1081.
3. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin. In this case, a decoupling
In the AOZ1081 buck regulator circuit, the two major
power dissipating components are the AOZ1081 and
output inductor. The total power dissipation of converter
circuit can be measured by input power minus output
power.
capacitor should be connected between V pin and
AGND pin.
IN
4. Make the current trace from LX pins to L to Co to the
PGND as short as possible.
5. Pour copper plane on all unused board area and
P
= V × I – V × I
IN IN O O
connect it to stable DC nodes, like V , GND or
total_loss
IN
V
.
OUT
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
6. The two LX pins are connected to internal PFET
drain. They are low resistance thermal conduction
path and most noisy switching node. Connected a
copper plane to LX pin to help thermal dissipation.
This copper plane should not be too larger otherwise
switching noise may be coupled to other part of
circuit.
2
P
= I × R
× 1.1
inductor
inductor_loss
O
The actual AOZ1081 junction temperature can be calcu-
lated with power dissipation in the AOZ1081 and thermal
impedance from junction to ambient.
7. Keep sensitive signal trace such as trace connected
with FB pin and COMP pin far away form the LX pins.
T
=
junction
(P
–P
) × Θ + T
inductor_loss ambient
total_loss
The maximum junction temperature of AOZ1081 is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for the maximum
load current of the AOZ1081 under different ambient
temperature.
The thermal performance of the AOZ1081 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC will
operate under the recommended environmental
conditions.
Rev. 1.1 April 2009
www.aosmd.com
Page 12 of 16
AOZ1081
Vout
GND
Vin
GND
Vf b
Figure 3. AOZ1081 PCB Layout
Rev. 1.1 April 2009
www.aosmd.com
Page 13 of 16
AOZ1081
Package Dimensions, SO-8
D
Gauge Plane
Seating Plane
0.25
e
8
L
E
E1
h x 45°
1
C
θ
7° (4x)
A2
A
0.1
A1
b
Dimensions in millimeters
Dimensions in inches
Symbols Min. Nom. Max.
Symbols Min.
Nom. Max.
0.053 0.065 0.069
0.004 0.010
0.049 0.059 0.065
2.20
A
A1
A2
b
1.35
0.10
1.25
0.31
0.17
4.80
3.80
1.65
—
1.75
0.25
1.65
0.51
0.25
5.00
4.00
A
A1
A2
b
—
1.50
—
0.012
0.007
—
—
0.020
0.010
c
—
c
5.74
D
E1
e
4.90
3.90
1.27 BSC
6.00
—
D
E1
e
0.189 0.193 0.197
0.150 0.154 0.157
0.050 BSC
1.27
E
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
E
0.228 0.236 0.244
h
h
0.010
0.016
0°
—
—
—
0.020
0.050
8°
L
—
L
0.80
θ
—
θ
Unit: mm
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils.
4. Dimension L is measured in gauge plane.
5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Rev. 1.1 April 2009
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Page 14 of 16
AOZ1081
Tape and Reel Dimensions, SO-8
SO-8 Carrier Tape
P1
P2
See Note 3
D1
T
See Note 5
E1
E2
E
See Note 3
B0
K0
D0
P0
A0
Feeding Direction
Unit: mm
Package
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
SO-8
(12mm)
6.40
0.10
5.20
0.10
2.10
0.10
1.60
0.10
1.50
0.10
12.00 1.75
0.10 0.10
5.50
0.10
8.00
0.10
4.00
0.10
2.00
0.10
0.25
0.10
SO-8 Reel
W1
S
G
N
K
M
V
R
H
W
Tape Size Reel Size
M
N
W
W1
H
K
S
G
R
V
12mm
ø330
ø330.00 ø97.00 13.00 17.40
ø13.00
1.00 +0.50/-0.20
10.60
2.00
0.50
—
—
—
0.50
0.10
0.30
SO-8 Tape
Leader/Trailer
& Orientation
Trailer Tape
300mm min. or
Components Tape
Orientation in Pocket
Leader Tape
500mm min. or
75 empty pockets
125 empty pockets
Rev. 1.1 April 2009
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Page 15 of 16
AOZ1081
Package Marking
Z1081AI
FAYWLT
Part Number
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Rev. 1.1 April 2009
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Page 16 of 16
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