AOZ1213 [AOS]
EZBuck⢠3A Simple Buck Regulator with Linear Controller; EZBuckâ ?? ¢ 3A简单的降压稳压器与线性控制器
| 型号： | AOZ1213 |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | EZBuck⢠3A Simple Buck Regulator with Linear Controller |
| 文件： | 总16页 (文件大小：648K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOZ1213
EZBuck™ 3A Simple Buck Regulator
with Linear Controller
General Description
Features
The AOZ1213 is a high efficiency, simple to use, buck
regulator plus one linear regulator controller optimized for
a variety of applications.
● 4.5V to 28V operating input voltage range
● Integrated linear regulator controller
● 70mΩ internal NFET, efficiency: up to 95%
● Internal soft start
The AOZ1213 works from a 4.5V to 28V wide input
voltage range. The buck regulator provides up to 3A of
continuous output current. Each output voltage is
adjustable down to 0.8V.
● Each output voltage adjustable down to 0.8V
● 3A continuous output current
● Fixed 370kHz PWM operation
● Cycle-by-cycle current limit
The AOZ1213 is available in a 4x3 DFN-12 package
and can operate over a -40°C to +85°C ambient
temperature range.
● Short-circuit protection
● Thermal shutdown
● Small size 4x3 DFN-12 packages
Applications
● Point of load DC/DC conversion
● Set top boxes
● LCD Monitors & TVs
● Cable modems
● Telecom/Networking/Datacom equipment
Typical Application
VIN
C5
0.1µF
C1
C4
22µF
1µF
L1
6.8µH
VIN
EN
VBIAS
BS
LX
VOUT1
VOUT1
AOZ1213
C6
R1
LDRV
1µF
31.6k
C2, C3
FB1
GND
22µF x 2
FB2
R3
VOUT2
10k
AGND COMP
R2
10k
C7
4.7µF
R4
RC
8.06k
30k
CC
2.2nF
Figure 1. Typical Application Circuit
Rev. 1.3 November 2009
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Page 1 of 16
AOZ1213
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1213DI
-40°C to +85°C
4x3 DFN-12
RoHS Compliant
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
LX
LX
1
2
3
4
5
6
12 IN
IN
11 BIAS
10 AGND
BST
PGND
EN
9
8
7
LDRV
FB2
AGND
FB1
COMP
DFN-12
(Top View)
Pin Description
Pin Number
Pin Name
Pin Function
1, 2
3
LX
Buck Regulator Switching Node.
BST
Buck Regulator Bootstrap Pin. BST is the high side driver supply. Connect a 0.1µF
capacitor between BST and LX to form a bootstrap circuit.
4
5
6
PGND
EN
Power Ground.
Enable Input. EN is active high. Connect EN to IN if not used. Do not leave EN floating.
FB1
Buck Regulator Feedback Input. FB1 is regulated to 0.8V. Set the buck regulator output
voltage using a resistive voltage divider.
7
8
COMP
FB2
Buck Regulator Compensation Pin. COMP is the output of the internal transconductance
error amplifier. Connect a RC network between COMP and GND to compensate the
control loop.
Linear Regulator Feedback Input. FB2 is regulated to 0.8V. Set the linear regulator
output voltage using a resistive voltage divider.
9
LDRV
AGND
BIAS
IN
Linear Regulator Drive Output. LDRV controls the gate of an external pass transistor.
Analog Ground.
10
11
12
Internal Bias Regulator Output. Connect a 1µF between BIAS and GND.
Input Supply Pin. The input range is between 4.5V and 28V.
Rev. 1.3 November 2009
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Page 2 of 16
AOZ1213
Block Diagram
VIN
+5V
VBIAS
EN
UVLO
& POR
5V LDO
Regulator
OTP
+
ISen
–
Reference
& Bias
Softstart
BST
LX
ILimit
Q1
+
–
+
GM = 200A/V
EAmp
+
–
PWM
Control
Logic
PWM
Comp
0.8V
FB1
COMP
Q2
370kHz Oscillator
Short Detect
Comparator
+
–
0.3V
GM = 2A/V
+
EAmp2
–
FB2
UVP
< 0.6V
LDRV
AGND
PGND
Absolute Maximum Ratings
Recommend Operating Ratings
Exceeding the Absolute Maximum Ratings may damage the
device.
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
Parameter
Supply Voltage (VIN)
Rating
Parameter
Supply Voltage (VIN)
Rating
30V
4.5V to 28V
0.8V to 0.85*VIN
-40°C to +85°C
LX to GND
-0.7V to VIN + 0.3V
-0.3V to VIN + 0.3V
-0.3V to 6V
Output Voltage Range
EN to GND
Ambient Temperature (TA)
Package Thermal Resistance
FB1, 2 to GND
)
(2
COMP to GND
-0.3V to 6V
4 x 3 DFN-12 (ΘJA
4 x 3 DFN-12 (ΘJC
)
64.6°C/W
7.1°C/W
)
BST to GND
VLX + 6V
LDRV to GND
-0.3V to 6V
-0.3V to 30V
+150°C
Note:
2. The value of ΘJA is measured with the device mounted on 1-in2
FR-4 board with 2oz. Copper, in a still air environment with TA = 25°C.
The value in any given application depends on the user's specific board
design.
PG to GND
Junction Temperature (TJ)
Storage Temperature (TS)
ESD Rating: Human Body Model(1)
Note:
-65°C to +150°C
2kV
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Rev. 1.3 November 2009
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Page 3 of 16
AOZ1213
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, unless otherwise specified(3)
Symbol
Parameter
Supply Voltage
Conditions
Min.
4.5
Typ.
Max.
Units
VIN
28
V
V
VUVLO
Input Under-Voltage Lockout
Threshold
VIN Rising
IN Falling
4.0
3.7
2
V
V
IIN
Supply Current (Quiescent)
Shutdown Supply Current
Feedback Voltage
IOUT = 0, VFB = 1.2V, VEN >2V
VEN = 0V
3
mA
μA
V
IOFF
3
20
VFB1, 2
0.788
0.8
0.5
0.1
0.812
Load Regulation
%
Line Regulation
%
IFB1
ENABLE
VEN
Feedback Voltage Input Current
200
nA
EN Input Threshold
Off Threshold
On Threshold
0.6
V
V
2.5
VHYS
EN input Hysteresis
200
mV
nA
IEN
MODULATOR
fO
Enable Sink/Source current
50
Frequency
315
370
85
425
kHz
%
DMAX
Maximum Duty Cycle
Minimum Duty Cycle
DMIN
5
%
GVEA
Error Amplifier Voltage Gain
Error Amplifier Transconductance
500
200
V / V
μA / V
GEA
PROTECTION
ILIM
Current Limit
4
4.5
145
100
6
5
A
Over-Temperature Shutdown Limit
TJ Rising
TJ Falling
°C
°C
ms
tSS
Soft Start Interval
PWM OUTPUT STAGE
RDS(ON) High-Side Switch On-Resistance
High-Side Switch Leakage
70
100
10
mΩ
VEN = 0V, VLX = 0V
µA
LINEAR CONTROLLER
LDRV Vout Drive Output High Voltage
Vfb2 = 0.7V, LDRV, Iout = 20mA,
Iout1 = 0
4
V
LDRV Iout
Drive Output Current
Under Voltage Threshold
Line Regulation
Vfb2 = 0.7V, Iout1 = 0
10
mA
V
0.6
0.5
1
%
Load Regulation
%
IFB2
FB2 Leakage
150
nA
Note:
3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Rev. 1.3 November 2009
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Page 4 of 16
AOZ1213
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Efficiency
Efficiency
Efficiency
(Vin = 24V, L = 6.8µH)
(Vin = 12V, L = 6.8µH)
(Vin = 5V, L = 6.8µH)
100%
95%
90%
85%
80%
75%
70%
100%
95%
90%
85%
80%
75%
70%
100%
95%
90%
85%
80%
75%
70%
8.0V OUTPUT
5.0V OUTPUT
3.3V OUTPUT
3.3V OUTPUT
8.0V OUTPUT
5.0V OUTPUT
3.3V OUTPUT
1.8V OUTPUT
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Load Current (A)
Load Current (A)
Load Current (A)
Frequency vs. Temperature
Frequency vs. Vin
Soft Start Time
(Vin = 12V, Vout = 3.3V, L = 6.8µH)
(Vin = 12V, Vout = 3.3V, L = 6.8µH, 25°C)
( Vin = 12V, Vout = 3.3V, L = 6.8µH, 25°C)
390
380
370
360
350
420
400
380
360
340
320
300
8
7
6
5
4
3
2
1
0
5
10
15
Vin (V)
20
25
30
0
5
10
15
Vin (V)
20
25
30
-45 -30 -15
0
15 30 45 60 75 90
Temperature (°C)
UVLO vs. Temperature
Soft Start Time vs. Temperature
Minimum Vin
(Vin = 12V, Vout = 3.3V, L = 6.8µH, 25°C)
(Vin = 12V, Vout = 3.3V, L = 6.8µH)
(25°C)
6.5
6
15
4.2
4.1
4
14
13
12
11
10
9
8
7
6
5
12V OUTPUT
Vin_rise
3.9
3.8
3.7
3.6
3.5
5.5
5
Vin_fall
5V OUTPUT
3.3V OUTPUT
4
3
4.5
-45 -30 -15
0
15 30 45 60 75 90
-45 -30 -15
0
15 30 45 60 75 90
0
0.5
1
1.5
2
2.5
3
Temperature (°C)
Load (A)
Temperature (°C)
VFB1 vs. Vin
Icc vs. Temperature
Current Limit vs. Vin
(Vin = 12V, Vout = 3.3V, L = 6.8µH, 25°C)
(Vin = 12V, Vout = 3.3V, L = 6.8µH)
(Vin = 12V, Vout = 3.3V, L = 6.8µH, 25°C)
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.85
0.84
0.83
0.82
0.81
0.8
5.5
5
4.5
4
3.5
3
0.79
0.78
0.77
0.76
0.75
2.5
2
4
6
8
10 12 14 16 18 20 22 24 26 28
-45 -30 -15
0
15 30 45 60 75 90
4
6
8
10 12 14 16 18 20 22 24 26 28
Temperature (°C)
Vin (V)
Vin (V)
Rev. 1.3 November 2009
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Page 5 of 16
AOZ1213
Typical Performance Characteristics (Continued)
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Current Limit vs. Temperature
VFB2 vs. Temperature
VFB1 vs. Temperature
(Vin = 12V, Vout = 3.3V, L = 6.8µH)
(Vin = 12V, Vout = 3.3V, L = 6.8µH)
(Vin = 12V, Vout = 3.3V, L = 6.8µH)
0.85
0.84
0.83
0.82
0.81
0.8
5.5
5
0.85
0.84
0.83
0.82
0.81
0.8
4.5
4
3.5
3
0.79
0.78
0.77
0.76
0.75
0.79
0.78
0.77
0.76
0.75
2.5
2
-45 -30 -15
0
15 30 45 60 75 90
-45 -30 -15
0
15 30 45 60 75 90
-45 -30 -15
0
15 30 45 60 75 90
Temperature (°C)
Temperature (°C)
Temperature (°C)
EN vs. Vin
EN On vs. Temperature
EN Off vs. Temperature
(Vin = 12V, Vout = 3.3V, L = 6.8µH, no load, 25°C)
(Vout = 3.3V, L = 6.8µH)
(Vout = 3.3V, L = 6.8µH)
3
2.5
2
2.5
2.4
2.3
2.2
2.1
2
3
2.5
2
24V INPUT
En on
En off
12V INPUT
5V INPUT
1.9
1.8
1.7
1.6
1.5
1.4
24V INPUT
12V INPUT
1.5
1.5
5V INPUT
1
1
-45 -30 -15
0
15 30 45 60 75 90
4
6
8
10 12 14 16 18 20 22 24 26 28
-45 -30 -15
0
15 30 45 60 75 90
Temperature (°C)
Temperature (°C)
Vin (V)
LDRV Output Voltage vs. Source Current
LDRV Source Current vs. Temperature
EN Hysteresis vs Temperature
(FB2 = 0.7V, 25°C)
5
(VFB2 = 0.7V, LDRV = 4V)
(Vout = 3.3V, L = 6.8µH)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
40
35
30
25
20
15
10
5
24V INPUT
4
3
2
1
0
12V INPUT
5V INPUT
0
-45 -30 -15
0
15 30 45 60 75 90
-45 -30 -15
0
15 30 45 60 75 90
0
10
20
30
40
50
60
Temperature (°C)
Temperature (°C)
LDRV source Current (mA)
Load Transient Response
Load Transient Response
(Iout = 0-1.5A, L = 6.8µH)
(Iout = 1.5-3A, L = 6.8µH)
Vo Ripple
Vo Ripple
200mV/Div
200mV/Div
Io
1A/div
Io
1A/div
200µs/div
200µs/div
Rev. 1.3 November 2009
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Page 6 of 16
AOZ1213
Detailed Description
The AOZ1213 is a current-mode step down regulator
with integrated high side NMOS switch. It operates from
a 4.5V to 28V input voltage range and supplies up to 3A
of load current. The duty cycle can be adjusted from 5%
to 85% allowing a wide range of output voltage. Features
include enable control, Power-On Reset, input under
voltage lockout, fixed internal soft-start and thermal shut
down. The linear regulator controller is designed to drive
an external NPN power transistor or an N channel power
MOSFET to provide up to 1A of current to an auxiliary
load.
transconductance error amplifier. The error voltage,
which shows on the COMP pin, is compared against the
current signal, which is the sum of inductor current signal
and ramp compensation signal, at PWM comparator
input. If the current signal is less than the error voltage,
the internal high-side switch is on. The inductor current
flows from the input through the inductor to the output.
When the current signal exceeds the error voltage, the
high-side switch is off. The inductor current is
freewheeling through the Schottky diode to output.
Switching Frequency
The AOZ1213 is available in 4X3 DFN-12 package.
The AOZ1213 switching frequency is fixed and set by an
internal oscillator. The switching frequency is set
370kHz.
Enable and Soft Start
The AOZ1213 has internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.0V and voltage
on EN pin is HIGH. In soft start process, the output
voltage is ramped to regulation voltage in typically 6ms.
The 6ms soft start time is set internally.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin with a resistor divider network. In the
application circuit shown in Figure 1. The resistor divider
network includes R and R . Usually, a design is started
1
2
by picking a fixed R value and calculating the required
2
R with equation below:
1
Connect the EN pin to VIN if the enable function is not
used. Pulling EN to ground will disable the AOZ1213.
Do not leave it open. The voltage on EN pin must be
above 2.5 V to enable the AOZ1213. When voltage on
EN pin falls below 0.6V, the AOZ1213 is disabled. If an
application circuit requires the AOZ1213 to be disabled,
an open drain or open collector circuit should be used to
interface to the EN pin.
R
⎛
⎞
⎟
⎠
1
------
V
= 0.8 × 1 +
⎜
OUT1
R
⎝
2
Some standard values of R , R for most commonly used
output voltage values are listed in Table 1.
1
2
Table 1.
Steady-State Operation
R1 (kΩ)
R2 (kΩ)
Vo (V)
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode
(CCM).
0.8
1.2
1.5
1.8
2.5
3.3
5.0
12.0
1.0
4.99
10
Open
10
11.5
10.2
10
The AOZ1213 integrates an internal N-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to the source of the
high side power MOSFET. Since the N-MOSFET
requires a gate voltage higher than the input voltage, a
boost capacitor connected between LX pin and BST pin
drives the gate. The boost capacitor is charged while LX
is low. An internal 10¾ switch from LX to PGND is used
to ensure that LX is pulled to PGND even with a light
load. Output voltage is divided down by the external
voltage divider at the FB pin. The difference of the FB pin
voltage and reference is amplified by the internal
12.7
21.5
31.6
52.3
140
10
10
10
The combination of R and R should be large enough to
1
2
avoid drawing excessive current from the output, which
will cause power loss.
Rev. 1.3 November 2009
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Page 7 of 16
AOZ1213
The FB2 voltage is monitored by an Under Voltage
Protection circuit, which shutdown LDRV output when
FB2 voltage is under 0.6V.
Protection Features
The AOZ1213 has multiple protection features to prevent
system circuit damage under abnormal conditions.
Thermal Protection
Over Current Protection (OCP)
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side NMOS if the junction temperature exceeds
145°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100°C.
The sensed inductor current signal is also used for over
current protection. Since the AOZ1213 employs peak
current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4V and 2.5V internally.
The peak inductor current is automatically limited cycle
by cycle.
Application Information
The cycle by cycle current limit threshold is internally set.
When the load current reaches the current limit
The basic AOZ1213 application circuit is shown in
Figure 1. Component selection is explained below.
threshold, the cycle by cycle current limit circuit turns off
the high side switch immediately to terminate the current
duty cycle. The inductor current stop rising. The cycle by
cycle current limit protection directly limits inductor peak
current. The average inductor current is also limited due
to the limitation on peak inductor current. When cycle by
cycle current limit circuit is triggered, the output voltage
drops as the duty cycle decreasing.
Buck Regulator Design
Input Capacitor
The input capacitor (C in Figure 1) must be connected to
1
the V pin and GND pin of the AOZ1213 to maintain
IN
steady input voltage and filter out the pulsing input
current. The voltage rating of input capacitor must be
greater than maximum input voltage plus ripple voltage.
The AOZ1213 has internal short circuit protection to
protect itself from catastrophic failure under output short
circuit conditions. The FB pin voltage is proportional to
the output voltage. Whenever FB pin voltage is below
0.3V, the short circuit protection is triggered. To prevent
current limit running away, when comp pin voltage is
higher than 2.1V, the short circuit protection is also
triggered. When the above conditions happen, PWM
turns off immediately, after about 1mS the converter
restarts via a soft start scheme. The short circuit
protection process repeats until the short circuit condition
disappears.
The input ripple voltage can be approximated by
equation below:
I
V
V
O
⎛
⎞
⎟
⎠
O
O
-----------------
--------
--------
ΔV
=
× 1 –
×
⎜
IN
V
f × C
V
⎝
IN
IN
IN
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
Power-On Reset (POR)
V
V
O
⎛
⎜
⎝
⎞
⎟
⎠
O
--------
--------
I
= I ×
1 –
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4.0V, the converter
starts operation. When input voltage falls below 3.7V,
the converter will stop switching.
CIN_RMS
O
V
V
IN
IN
if let m equal the conversion ratio:
V
O
--------
Linear Regulator
= m
V
IN
The AOZ1213 contains an error amplifier which can be
configured as a linear regulator controller. By adding an
external follower (NPN or NMOS) and divider resistors as
shown in Figure 1, the FB2 and LDRV pins can be
configured as a controller for a Low Dropout Regulator.
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2 on the next page. It can be seen that
when V is half of V , C is under the worst current
O
IN
IN
stress. The worst current stress on CIN is 0.5 x I .
O
The LDRV pin source capability come from LDO inside
which is capable more than 10mA of base current to the
external NPN transistor.
Rev. 1.3 November 2009
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Page 8 of 16
AOZ1213
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
0.5
0.4
0.3
0.2
0.1
0
ICIN_RMS(m)
IO
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
0
0.5
m
1
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Figure 2. ICIN vs. Voltage Conversion Ratio
For reliable operation and best performance, the input
capacitors must have current rating higher than I
CIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high ripple current rating. Depending on the
application circuits, other low ESR tantalum capacitor or
aluminum electrolytic capacitor may also be used. When
selecting ceramic capacitors, X5R or X7R type dielectric
ceramic capacitors are preferred for their better
temperature and voltage characteristics. Note that the
ripple current rating from capacitor manufactures is
based on certain amount of life time. Further de-rating
may be necessary for practical design requirement.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck con-
verter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
1
⎛
⎞
⎠
-------------------------
ΔV = ΔI × ESR
+
O
L
CO
⎝
8 × f × C
O
where;
CO is output capacitor value and
Inductor
ESRCO is the Equivalent Series Resistor of output capacitor.
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is,
When a low ESR ceramic capacitor is used as the output
capacitor, the impedance of the capacitor at the
switching frequency dominates. Output ripple is mainly
caused by capacitor value and inductor ripple current.
The output ripple voltage calculation can be simplified to:
V
V
O
⎛
⎞
⎟
⎠
O
----------
--------
ΔI
=
× 1 –
⎜
L
1
V
f × L
⎛
⎝
⎞
⎠
⎝
IN
-------------------------
ΔV = ΔI ×
O
L
8 × f × C
O
The peak inductor current is:
If the impedance of ESR at switching frequency
ΔI
L
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
--------
I
= I +
Lpeak
O
2
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss.
ΔV = ΔI × ESR
CO
O
L
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum capacitor or
aluminum electrolytic capacitor may also be used as
output capacitors.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor needs to be checked for
thermal and efficiency requirements.
Rev. 1.3 November 2009
www.aosmd.com
Page 9 of 16
AOZ1213
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It can
be calculated by:
The compensation design is actually to shape the
converter close loop transfer function to get desired gain
and phase. Several different types of compensation
network can be used for AOZ1213. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
ΔI
L
----------
12
I
=
CO_RMS
In the AOZ1213, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
G
EA
Schottky Diode Selection
------------------------------------------
f
=
P2
2π × C × G
The external freewheeling diode supplies the current to
the inductor when the high side NMOS switch is off.
To reduce the losses due to the forward voltage drop and
recovery of diode, Schottky diode is recommended to
use. The maximum reverse voltage rating of the chosen
Schottky diode should be greater than the maximum
input voltage and size for average forward current in
normal condition. Average forward current can be
calculated from:
C
VEA
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is the compensation capacitor
The zero given by the external compensation network,
capacitor C and resistor R , is located at:
I
O
C
C
--------
I
=
(V – V
)
OUT
D_AVE
IN
V
IN
1
-----------------------------------
=
f
Z2
2π × C × R
C
C
Loop Compensation
The AOZ1213 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
To design the compensation circuit, a target crossover
frequency f for close loop must be selected. The system
C
crossover frequency is where control loop has unity gain.
The crossover frequency is also called the converter
bandwidth. Generally a higher bandwidth means faster
response to load transient. However, the bandwidth
should not be too high due to system stability concern.
When designing the compensation loop, converter
stability under all line and load condition must be
considered.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
1
----------------------------------
f
=
p1
Usually, it is recommended to set the bandwidth to be
less than 1/10 of switching frequency. It is recommended
to choose a crossover frequency less than 30kHz.
2π × C × R
O
L
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
f
= 30kHz
C
1
------------------------------------------------
f
=
Z1
2π × C × ESR
O
CO
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
Rev. 1.3 November 2009
www.aosmd.com
Page 10 of 16
AOZ1213
The strategy for choosing R and C is to set the cross
External NPN Pass Transistor or MOSFET
C
C
over frequency with R and set the compensator zero
C
Both Transistor and MOSFET can be used as an
external follower. Some precautions must be followed:
with C . Using selected crossover frequency, f , to
C
C
calculate R :
C
1. The transistor and MOSFET should be able to supply
maximum operating current for the linear regulator
supply.
V
2π × C
O
O
---------- -----------------------------
R
= f ×
×
C
C
V
G
× G
EA CS
FB
2. DC current gain h must be large enough so that
FE
where;
the pass transistor and supply the maximum load
current with 30mA with base current. However, too
fC is desired crossover frequency,
VFB is 0.8V,
GEA is the error amplifier transconductance, which is 200x10-6
A/V, and
big of an h may cause the LDO to be sensitive to
FE
current noise, and as a compromise, a DC current
gain transistor should be selected.
3. The total power dissipation should not be higher than
the rated value.
GCS is the current sense circuit transconductance, which is
6.6 A/V
4. Compared to a transistor, a MOSFET has lower
The compensation capacitor C and resistor R together
C
C
dropout voltage which is R
multiplied by the
DS(ON)
make a zero. This zero is put somewhere close to the
dominate pole f but lower than 1/5 of selected cross-
output current. The minimum input voltage will
increase to V plus V while the transistor is V
O
p1
O
GS
over frequency. C can is selected by:
C
plus V
.
BE
1.5
----------------------------------
=
C
Linear Regulator Output Capacitor
C
2π × R × f
C
p1
The linear regulator requires using an output capacitor
as part of the frequency compensation network, which
affects the stability and high frequency response. The
regulator has a finite band width. For high frequency
transient loads, recovery from transient is determined by
both output capacitor and the bandwidth of the regulator.
A minimum output capacitor of 4.7µF is recommended to
prevent oscillations and provide good transient response.
The equation above can also be simplified to:
C × R
O
L
---------------------
C
=
C
R
C
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
The ESR value should be maintained in the range that
determines the loop stability. When small signal ringing
occurs with ceramics due to insufficient ESR in low
output voltage condition, adding ESR or increasing the
capacitor value improves the stability and reduces the
ringing. But too high an ESR is also not suggested, which
will cause the zero to be too big and the phase margin is
not satisfied. High ESR also brings in high voltage ripple.
The lower the output voltage is, the higher the ESR value
is needed. Basically, ESR between 0.02Ω and 3Ω can
make sure the circuit stable.
Linear Regulator Design
Adjustable Output Voltage
The output voltage can be set by feeding back the output
to FB2 pin with a resistor divider network. In the
application circuit shown in Figure1. The linear regulator
output voltage can be obtained using the following
equation:
R3
R4
⎛
= 0.8 × 1 +
⎝
⎞
⎠
-------
V
OUT2
Solid tantalum electrolytic, aluminum electrolytic, and
multilayer ceramic capacitors are all suitable, only if the
capacitance and ESR of them meet the requirements.
R4 should be 10kΩ or less to avoid bias current errors.
Rev. 1.3 November 2009
www.aosmd.com
Page 11 of 16
AOZ1213
Output Voltage Ripple
In the AOZ1213 buck regulator circuit, the three major
power dissipating components are the AOZ1213,
external diode and output inductor. The total power
dissipation of converter circuit can be measured by
input power minus output power.
The LDO is designed to provide low output voltage noise
while operating at any load. Because of the existence of
stray inductance and capacitance, sometimes there
could be a big ripple voltage in the output which is
unexpected. The following tips could decrease the ripple
voltage to a lower value:
P
= V × I – V × I
IN IN O O
total_loss
The power dissipation of the inductor can be
approximately calculated by output current and DCR of
the inductor.
1. Improve the PCB layout:
Signal grounds should connect to AGND to insure
the noise is small,
2
P
= I × R
× 1.1
inductor
inductor_loss
O
Low side divider resistor connects to AGND directly;.
The power dissipation of the diode is:
Keep sensitive signal trace such as FB2 pin, LDRV
pin as short as possible, and far away from noise
trace.
V
⎛
⎞
⎟
⎠
O
--------
P
= I × V × 1 –
⎜
⎝
diode_loss
O
F
V
IN
2. Adding a bypass capacitor from FB2 pin to AGND,
which will lower the bandwidth of the loop. The
impedance of the FB2 pin capacitor at the ripple
frequency should be less than the value of R3.
The actual AOZ1213 junction temperature can be
calculated with power dissipation in the AOZ1213 and
thermal impedance from junction to ambient.
3. Adding a resistor R between LDRV and the base of
G
the transistor (gate of MOSFET), which can structure
a RC filter with the capacitor of Base-Emitter to
T
= (P
–P
) × Θ
inductor_loss
JA
junction
total_loss
+
+ T
ambient
reduce the noise (Figure 2). As the increasing of R
value, the noise getting smaller. Considering the
G
The maximum junction temperature of AOZ1213 is
145°C, which limits the maximum load current capability.
power dispassion of the R , its value is often
G
between 10Ω and 100Ω.
The thermal performance of the AOZ1213 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC will
operate under the recommended environmental
conditions.
4. Increasing the capacitance of output capacitor or add
the ESR of the output capacitor.
5. Change the pass transistor to a lower h type
FE
(MOSFET to a lower g type), thus the loop gain
FS
can be smaller as a source follower. But the h
FE
and g should be large enough to meet the output
current requirement.
FS
Several layout tips are listed below for the best electric
and thermal performance. Figure 3 is the layout example.
1. Do not use thermal relief connection to the VIN and
the GND pin. Pour a maximized copper area to the
GND pin and the VIN pin to help thermal dissipation.
Thermal Management and Layout
Consideration
In the AOZ1213 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the
LX pins, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the GND pin of the
AOZ1213, to the LX pins of the AZO1213. Current flows
in the second loop when the low side diode is on.
2. Input capacitor should be connected as close as
possible to the VIN pin and the GND pin.
3. Make the current trace from LX pins to L to Co to the
GND as short as possible.
4. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
5. Keep sensitive signal traces such as the trace
connecting FB pin and COMP pin away from the
LX pins.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is recommended to connect input capacitor, output
capacitor, and GND pin of the AOZ1213.
Rev. 1.3 November 2009
www.aosmd.com
Page 12 of 16
AOZ1213
Layout Example of the AOZ1213
Figure 3a. Top Side
Figure 3b. Bottom Side
Rev. 1.3 November 2009
www.aosmd.com
Page 13 of 16
AOZ1213
Package Dimensions, DFN 4 x 3
A
Pin #1 IDA
e
L1
Chamfer 0.15
D/2
1
L
Index Area
(D/2 x E/2)
L3
L3
E/2
E1/2
E
E1
L2
D1
D2
TOP VIEW
BOTTOM VIEW
A3
A
Seating
Plane
A1
b
SIDE VIEW
Dimensions in millimeters
Dimensions in inches
RECOMMENDED LAND PATTERN
Symbols Min.
Nom. Max.
Symbols Min.
Nom. Max.
A
A1
A3
b
0.80
0.00
0.90
0.02
1.00
0.05
A
A1
A3
b
0.031 0.035 0.039
0.000 0.001 0.002
0.008 REF.
0.50
0.25
0.23
0.20 REF.
0.23
0.50
0.30
0.20
0.35
0.008 0.009 0.014
0.157 BSC
D
4.00 BSC
0.985
D
D1
D2
E
0.83
1.86
1.09
2.12
D1
D2
E
0.033 0.039 0.043
0.073 0.079 0.083
0.118 BSC
1.35
2.015
0.80
0.715
1.60
3.00 BSC
1.60
2.70
E1
e
1.45
1.70
E1
e
0.057 0.063 0.067
0.020 BSC
0.50 BSC
0.40
L
0.30
0.61
0.21
0.50
0.82
0.42
L
0.012 0.016 0.020
0.024 0.028 0.032
0.008 0.012 0.017
0.012 REF.
0.30
L1
L2
L3
aaa
bbb
ccc
ddd
0.715
L1
L2
L3
aaa
bbb
ccc
ddd
0.315
0.30 REF.
0.15
0.20 x 45°
1.035
0.315
2.065
0.006
Unit: mm
0.10
0.004
0.10
0.004
0.08
0.003
Notes:
1. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
2. The location of the terminal #1 identifier and terminal numbering conforms to JEDEC publication 95 SPP-002.
3. Dimension b applied to metallized terminal and is measured between 0.20mm and 0.35mm from the terminal tip. If the terminal
has the optional radius on the other end of the terminal, dimension b should not be measured in that radius area.
4. Coplanarity ddd applies to the terminals and all other bottom surface metallization.
Rev. 1.3 November 2009
www.aosmd.com
Page 14 of 16
AOZ1213
Tape and Reel Dimensions, DFN 4 x 3
Carrier Tape
P1
P2
D1
T
E1
E2
E
C
L
B0
K0
D0
A0
P0
Feeding Direction
UNIT: mm
Package
A0
B0
K0
D0
1.50
D1
1.50
E
E1
E2
P0
P1
P2
T
DFN 4 x 3
(12 mm)
3.40
0.10
4.40
0.10
1.10
12.0 1.75
0.3
5.50
0.05
8.00
0.10
4.00
0.10
2.00
0.10
0.30
0.05
0.10 Min. +0.10/-0.0
0.10
Reel
W1
S
N
K
M
V
R
H
W
UNIT: mm
Tape Size Reel Size
12mm ø330
M
N
W
W1
H
K
S
G
R
V
ø330.0 ø79.0
2.0
12.4
17.0
ø13.0
0.5
10.5
0.2
2.0
0.5
—
—
—
1.0 +2.0/-0 +2.6/-0
Leader / Trailer & Orientation
Components Tape
Orientation in Pocket
Leader Tape
500mm Min.
Trailer Tape
300mm Min.
125 Empty Pockets
75 Empty Pockets
Rev. 1.3 November 2009
www.aosmd.com
Page 15 of 16
AOZ1213
Package Marking
AOZ1213DI
(4 x 3 DFN-12)
Z1213DI
Part Number Code
FAYWLT
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Rev. 1.3 November 2009
www.aosmd.com
Page 16 of 16
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