AOZ1361DI [AOS]
28V Programmable Current-Limited Load Switch; 28V的可编程限流负载开关
| 型号： | AOZ1361DI |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | 28V Programmable Current-Limited Load Switch |
| 文件： | 总12页 (文件大小：828K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOZ1361DI
28V Programmable Current-Limited Load Switch
General Description
Features
The AOZ1361DI is a high-side load switch intended for
applications that require circuit protection. The device
operates from voltages between 4.5V and 28V. The
internal current limiting circuit protects the input supply
voltage from large load current. The current limit can be
set with an external resistor. The AOZ1361DI provides
thermal protection function that limits excessive power
dissipation. The device employs internal soft-start
circuitry to control inrush current due to highly capacitive
loads associated with hot-plug events. It features low
quiescent current of 220µA and the supply current
reduces to less than 1µA in shutdown.
z 35mΩ maximum on resistance
z Programmable current limit
z 4.5V to 28V operating input voltage
z Low quiescent current
z Under-voltage lockout
z Thermal shutdown protection
z Open-drain fault indicator with delay
z Small 4x4 DFN package
z 2.5kV ESD rating
Applications
The AOZ1361DI is available in a 10-pin 4x4 DFN
package and can operate over -40°C to +85°C
temperature range.
z Notebook PCs
z Hot swap supplies
Typical Application
VIN
VOUT
10
1
IN
OUT
C1
1µF
C2
0.1µF
9
2
6
4
3
IN
OUT
SET
SS
AOZ1361DI
7
5
8
EN
OFF ON
+5V
R1
74.5kΩ
R2
100kΩ
GND
FLTB
C4
1nF
TFLT
C3
1nF
Rev. 2.0 October 2010
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Page 1 of 12
AOZ1361DI
Ordering Information
Part Number
Feature
Package
Temperature Range
Environmental
AOZ1361DI-01
AOZ1361DI-02
Auto-restart
Latch-off
RoHS Compliant
Green Product
DFN 4x4 10
-40°C to +85°C
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
TOP VIEW
1
2
3
4
5
10
9
IN
IN
OUT
OUT
TFLT
SET
EN
OUT
8
FLTB
GND
SS
7
GND
6
DFN 4x4 10
Pin Description
Pin Number
Pin Name
Pin Function
1, 2
3
IN
P-channel MOSFET source. Connect a 1µF capacitor from IN to GND.
FLTB
Fault output pin. This is an open drain output that is internally pulled low to indicate a
fault condition. Connect to 5V or 3.3V through a pull up resistor.
4
5
6
7
GND
SS
Ground.
Soft-Start Pin. Connect a capacitor from SS to GND to set the soft-start time.
Enable Input.
EN
SET
Current Limit Set Pin. Connect a resistor between SET and GND to set the switch cur-
rent limit.
8
TFLT
OUT
Fault Delay pin. Connect a capacitor from TFLT to GND to set the Fault delay time.
P-channel MOSFET Drain. Connect a 0.1µF capacitor from OUT to GND.
9, 10
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Page 2 of 12
AOZ1361DI
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the
device.
Recommended Operating Conditions
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
Parameter
Rating
Parameter
Rating
63°C/W
IN to GND
-0.3V to +30V
-0.3V to VIN +0.3V
-0.3V to +6V
+150°C
Thermal Resistance (DFN 4x4)
EN, OUT to GND
FLTB, TFLT, SS, SET
Maximum Junction Temperature (TJ)
ESD Rating (HBM)
2.5kV
Electrical Characteristics
VIN = 12V, TA = 25°C unless otherwise stated.
Symbol
Parameter
Conditions
Min.
Typ.
Max
Units
VIN
Input Supply Voltage
4.5
28
V
V
VUVLO
Undervoltage Lockout
Threshold
IN rising
3.9
200
300
4.4
VUVHYS
Undervoltage Lockout
Hysteresis
mV
IIN_ON
IIN_OFF
ILEAK
Input Quiescent Current
Input Shutdown Current
Output Leakage Current
Switch On Resistance
EN = IN, no load
EN = GND, no load
EN = GND, no load
VIN= 12V
500
1
µA
µA
µA
1
RDS(ON)
22
33
35
43
3.4
0.8
mΩ
VIN = 4.5V
ILIM
Current Limit
RSET = 74.5kΩ
2
2.7
A
V
VEN_L
Enable Input Low Voltage
Enable Input High Voltage
Enable Input Hysteresis
Enable Input Bias Current
VEN_H
2.0
V
VEN_HYS
IEN_BIAS
Td_on
100
280
mV
µA
µs
1
Turn-On Delay Time
EN_50% to OUT_10%
RL=120Ω, CL = 1µF, SS = Floated.
Measure from 50% of EN voltage to
10% of OUT voltage
tON
Turn-On Rise Time
OUT_10% to 90%
RL=120Ω, CL = 1µF, SS = Floated.
Measure from 10% of OUT voltage
to 90% of OUT voltage
220
µs
µs
RL=120Ω, CL = 1µF, CSS = 1nF
360
280
tOFF
RDS(FLTB)
ILEAK_FLT
TFLT
Turn-Off Fall Time
RL=120Ω, CL = 1µF, SS = Floated
µs
Ω
On-Resistance at FLTB
FLT Output Leakage
Sink current = 4mA
100
1
µA
µs
°C
°C
FLT Delay Period
CTLT = 1nF
600
130
30
TSD
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
TSD_HYS
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Page 3 of 12
AOZ1361DI
Timing Diagram
VIH
VIL
EN
90%
TR
90%
10%
TD(ON)
OUT
TD(OFF)
Figure 1. AOZ1361DI Timing
Functional Block Diagram
OUT
SS
IN
C1
1μF
Gate Driver &
Slew Rate
Control
C4
1nF
3.9V
UVLO
SET
Current Limit
Comparator
5V
R1
74.5kΩ
EN
FLTB
R2
100
kΩ
Thermal
Shutdown
OC
OT
Fault Delay &
Latch
FLTG
AOZ1361DI
TFLT
C3
1nF
Figure 2. AOZ1361DI Functional Block Diagram
Rev. 2.0 October 2010
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Page 4 of 12
AOZ1361DI
Functional Characteristics
Turn-On
Turn-Off
(V = 12V, R = 5.6Ω, C4 = 0.01uF)
(V = 12V, R = 5.6Ω, C4 = 0.01uF)
IN L
IN
L
V
V
IN
2V/div
IN
2V/div
V
V
OUT
2V/div
OUT
2V/div
EN
EN
1V/div
1V/div
I
I
OUT
0.5A/div
OUT
0.5A/div
1ms/div
20μs/div
Current Limit Response Thermal Shutdown
Current Limit Response Thermal Shutdown
AOZ1361DI-01: Auto-Restart Version
AOZ1361DI-02: Latch-off Version
(V = 12V)
IN
(V = 12V)
IN
V
V
OUT
5V/div
OUT
5V/div
FLTB
FLTB
5V/div
5V/div
I
OUT
I
OUT
2A/div
2A/div
40ms/div
2ms/div
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Page 5 of 12
AOZ1361DI
Typical Operating Characteristics
Input Quiescent Current
Input Shutdown Current
450
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
350
300
250
200
150
85°C
25°C
-40°C
85°C
25°C
-40°C
5
10
15
20
25
30
5
10
15
20
25
30
Vin (V)
Vin (V)
UVLO Threshold vs Temperature
Output Leakage Current
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
4.0
3.95
3.9
Vin=12V
Vin=5.5V
Rising
Falling
3.85
3.8
3.75
3.7
3.65
3.6
0
-50
-60 -40 -20
0
20
40
60
80
100 120
-30
-10
10
30
50
70
90
Temperature (°C)
Temperature (°C)
Rds(on) vs Supply Voltage
Rds(on) vs Temperature
30
28
26
24
22
20
18
16
14
12
40
35
30
25
20
15
10
5
Vin=12V
Vin=5.5V
0
10
5
10
15
20
25
30
-60 -40 -20
0
20
40
60
80
100 120
Vin (V)
Temperature (°C)
Rev. 2.0 October 2010
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AOZ1361DI
Typical Operating Characteristics (Continued)
Enable Input Threshold (Rising) vs Temperature
1.8
Enable Input Threshold (Falling) vs. Temperature
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Vin=12V
Vin=5.5V
Vin=12V
Vin=5.5V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-60 -40 -20
0
20
40
60
80
100 120
-60 -40 -20
0
20
40
60
80
100 120
Temperature (°C)
Temperature (°C)
Current Derating Curve @ 6A, VIN = 12V
6.5
6
5.5
5
4.5
4
0
20
40
60
80
100
Ambient Temperature (°C)
Rev. 2.0 October 2010
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Page 7 of 12
AOZ1361DI
Detailed Description
Introduction
Thermal Shut-down Protection
The AOZ1361DI is a 35mΩ P-channel high-side load
switch with adjustable soft-start slew-rate control,
programmable current limit and thermal shutdown.
It operates with an input voltage range from 4.5V to 28V.
The thermal overload protection of AOZ1361DI is
engaged to protect the device from damage should the
die temperature exceeds safe margins due to a short
circuit, extreme loading or heating from external sources.
Enable
1. AOZ1361DI-01 (Auto-restart version): During current
limit or short circuit conditions, the PMOS resistance
is increased to clamp the load current. This increases
the power dissipation in the chip causing the die
temperature to rise. When the die temperature
reaches 130°C the thermal shutdown circuitry will
shutdown the device. There is a 30°C hysterisis. The
device will turn back on and go through soft start
after the temperature drops below +100°C . The
thermal shutdown will cycle repeatedly until the over
temperature condition disappears or the enable pin is
pulled LOW.
The EN pin is the ON/OFF control for the output switch.
The device is enabled when EN pin is high and VIN is
above UVLO. The EN pin must be driven to a logic high
or logic low state to guarantee operation. While disabled,
the AOZ1361DI only draws about 1µA supply current.
Under-Voltage Lockout (UVLO)
The under-voltage lockout (UVLO) circuit of AOZ1361DI
monitors the input voltage and prevents the output
MOSFET from turning on until VIN exceeds 3.9V.
Adjustable Soft-Start Slew-Rate Control
2. AOZ1361DI-02 (Latch-off version): Thermal
shut-down protection sets a fault latch and shuts off
the internal MOSFET and asserts the FLTB output if
the junction temperature exceeds +130°C. The
AOZ1361DI can be re-enabled by toggling EN pin
after the die temperature drops below +100°C.
When the EN pin is asserted high, the slew rate control
circuitry applies voltage on the gate of the PMOS switch
in a manner such that the output voltage and current is
ramped up linearly until it reaches the steady-state load
current level. The slew rate can be adjusted by an
external capacitor connected to the SS pin to ground.
The slew rate rise time, Ton, can be set using the
following equation:
FLTB
The FLTB pin is an open drain output that is asserted low
when either an over-current, short-circuit or over-
temperature condition occurs. To prevent false alarm, the
AOZ1361DI implements a fault delay time for over-
temperature, over-current and short-circuit fault
conditions. The FLTB pin becomes high impedance when
the fault conditions are removed. For AOZ1361DI-02, if
the temperature is higher than +130°C, the device will
latch off. After that, if temperature drops below +100°C,
the FLTB pin will pull high, which means the fault
condition has already been removed, although there is
no output voltage due to latch off function. A pull-up
resistor must be connected between FLTB to 5V or 3.3V
to provide a logic signal.
Css × V
IN
--------------------------
Ton =
30μA
Programmable Current Limit
The current limit is programmed by an external resistor
connected to the SET pin to ground. This sets a
reference voltage to the current limit error amplifier that
compares it to a sensed voltage that is generated by
passing a small portion of the load current through an
internal amplifier. When the sensed load current exceeds
the set current limit, the load current is then clamped at
the set limit and the Vout drop should be the result of
resistance increasing. The AOZ1361DI will stay in this
condition until the load current no longer exceeds the
current limit or if the thermal shutdown protection is
engaged. To set the current limit use Figure 3 on the
following page.
TFLT
TFLT is a fault delay pin, and its delay time is adjustable
by a capacitor connected from TFLT to GND. The delay
time can be calculated by:
C
(µs) = 600 µs / nF x C
(nF)
TFLT
TLT
Rev. 2.0 October 2010
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Page 8 of 12
AOZ1361DI
Applications Information
Input Capacitor Selection
Slew Rate Setting
The input capacitor prevents large voltage transients
from appearing at the input, and provides the
instantaneous current needed each time the switch turns
on and to limit input voltage drop. Also it is to prevent
high-frequency noise on the power line from passing
through the output of the power side. The choice of the
input capacitor is based on its ripple current and voltage
ratings rather than its capacitor value. The input capacitor
should be located as close to the VIN pin as possible. A
1µF ceramic cap is recommended. However, higher
capacitor values further reduce the voltage drop at the
input.
Slew rate is set by changing the capacitor value on the
SS pin of the device. A capacitor connected between this
SS pin and ground will reduce the output slew-rate. The
capacitive range is 0.001µF to 0.1µF. See Figure 4 for
Output Slew Rate Adjustment vs. Capacitance.
35
30
25
20
15
10
5
Output Capacitor Selection
The output capacitor acts in a similar way. A small 0.1µF
capacitor prevents high-frequency noise from going into
the system. Also, the output capacitor has to supply
enough current for a large load that it may encounter
during system transients. This bulk capacitor must be
large enough to supply fast transient load in order to
prevent the output from dropping.
0
0
0.02
0.04
0.06
0.08
0.1
Capacitance (μF)
Figure 4. Output Slew Rate Adjustment vs. Capacitance
Power Dissipation Calculation
Current Limit Setting
The current limit is program by using external resistor
connected to the SET pin. To set the current limit, use the
Figure 3 below.
Calculate the power dissipation for normal load condition
using the following equation:
2
P = R x (I )
OUT
D
ON
AOZ1361 RSET vs. ILIM
The worst case power dissipation occurs when the
load current hits the current limit due to over-current or
short circuit faults. The power dissipation under these
conditions can be calculated using the following
equation:
6.8
5.8
4.8
3.8
2.8
1.8
P = (V – V
) x I
LIMIT
D
IN
OUT
Layout Guidelines
Good PCB layout is important for improving the thermal
and overall performance of AOZ1361. To optimize the
switch response time to output short-circuit conditions
keep all traces as short as possible to reduce the effect of
unwanted parasitic inductance. Place the input and
output bypass capacitors as close as possible to the
IN and OUT pins. The input and output PCB traces
should be as wide as possible for the given PCB space.
Use a ground plane to enhance the power dissipation
capability of the device.
15
35
55
75
95
115
RSET (kΩ)
Figure 3. Current Limit vs. RSET (VIN = 12V)
Rev. 2.0 October 2010
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Page 9 of 12
AOZ1361DI
Package Dimensions, DFN 4x4
D
A
3
B
e
*
D/2
L3
10
INDEX AREA
(D/2xE/2)
6
L
2
E/2
*
*
E1/2
L4
L4
L1
E1
E
L2
Pin #1 IDA
Chamfer 0.20
1
5
Pin 1
D3
D4
D1
D2
TOP VIEW
6
BOTTOM VIEW
A3
A1
C
A
Seating
Plane
5
ddd
10x
4
b
eee
SIDE VIEW
Dimensions in millimeters
Dimensions in inches
Symbols Min. Nom. Max.
Symbols Min. Nom. Max.
A
A1
A3
b
0.70
0.00
0.75
0.02
0.80
0.05
A
A1
A3
b
0.028 0.030 0.031
0.000 0.001 0.002
0.008 REF
RECOMMENDED LAND PATTERN
0.203 REF
0.35
0.65 Typ.
0.35 TYP
0.30
3.95
1.58
1.22
0.40
4.05
1.78
1.42
0.012 0.014 0.016
0.156 0.157 0.159
0.062 0.066 0.070
0.048 0.052 0.056
0.012 REF
D
4.00
D
10
6
D1
D2
D3
D4
E
1.68
D1
D2
D3
D4
E
0.65 Typ.
1.32
0.3 REF
0.3 REF
4.00
0.012 REF
0.38
2.30
0.30
3.95
2.20
4.05
2.40
0.156 0.157 0.159
0.087 0.091 0.094
0.026 BSC
3.55
E1
e
2.30
E1
e
1.15
0.65 BSC
0.55
0.02
L
0.50
—
0.60
0.12
0.48
L
0.020 0.022 0.024
L1
L2
L3
L4
aaa
bbb
ccc
ddd
eee
0.02
L1
L2
L3
L4
aaa
bbb
ccc
ddd
eee
—
0.001 0.005
Pin #1 IDA
Chamfer 0.20
5
0.30
Unit: mm
1
0.28
0.38
0.011 0.015 0.019
0.033 REF
0.012 REF
0.006
0.85 REF
0.30 REF
0.15
1.78
1.42
0.10
0.004
0.10
0.004
Notes:
0.08
0.003
1. All dimensions are in millimeters.
2. The dimensions with * are just for reference.
0.05
0.002
3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SPP-002.
4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the
optional radius on the other end of the terminal, then dimension b should not be measured in that radius area.
5. Coplanarity applies to the terminals and all other bottom surface metallization.
6. Drawings shown are for illustration only.
Rev. 2.0 October 2010
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Page 10 of 12
AOZ1361DI
Tape and Reel Dimensions, DFN 4x4
Carrier Tape
P1
P2
D1
T
E1
E2
E
C
B0
L
K0
D0
A0
P0
Feeding Direction
UNIT: MM
Package
A0
B0
K0
1.10 1.50
0.10
D0
D1
1.50
E
E1
E2
P0
P1
P2
T
DFN 4x4
(12mm)
4.35
0.10
4.35
0.10
12.0
1.75
0.10
5.50
0.05
8.00
0.10
4.00
0.10
2.00
0.05
0.30
0.05
Min. +0.1/-0.0 0.3
Reel
W1
S
N
K
M
V
R
H
W
UNIT: MM
Tape Size
12 mm
M
N
W
W1
17.0
H
K
S
G
R
V
Reel Size
ø
330
ø
330.0
2.0
ø
79.0
1.0
12.4
ø
13.0
10.5
0.2
2.0
0.5
—
—
—
+2.0/-0.0 +2.6/-0.0
0.5
Leader/Trailer and Orientation
Trailer Tape
300mm min. or
75 empty pockets
Components Tape
Orientation in Pocket
Leader Tape
500mm min. or
125 empty pockets
Rev. 2.0 October 2010
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Page 11 of 12
AOZ1361DI
Part Marking
DFN 4x4
Option Code
Z1361DIX
ZA8R1B
Part Number Code
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Page 12 of 12
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